EVALUATION KIT AVAILABLE

Click here for production status of specific part numbers.

MAX1932 Digitally Controlled, 0.5% Accurate,

Safest APD Bias Supply

General Description Features

The MAX1932 generates a low-noise, high-voltage out- ●● Unique Architecture Delivers Excellent Accuracy for
put to bias avalanche photodiodes (APDs) in optical Improved System Performance
receivers. Very low output ripple and noise is achieved • 0.5% Accurate Output
by a constant-frequency, pulse-width modulated (PWM) • Low Ripple Output (< 1mV)
boost topology combined with a unique architecture that ●● Protection Features Guarantee Safe Operation
maintains regulation with an optional RC or LC post filter • Accurate High-Side Current Limit
inside its feedback loop. A precision reference and error • Avalanche Indicator Flag
amplifier maintain 0.5% output voltage accuracy.
●● Output-Voltage Flexibility Facilitates Multiple
The MAX1932 protects expensive APDs against adverse Applications and Design Approaches
operating conditions while providing optimal bias. • 4.5V to 90V Output
Traditional boost converters measure switch current for • Set Output Voltage via 8-Bit SPI-Compatible
protection, whereas the MAX1932 integrates accurate Internal DAC, External DAC, or External Resistors
high-side current limiting to protect APDs under ava-
●● Small Circuit Footprint Reduces Equipment Size
lanche conditions. A current-limit flag allows easy calibra-
• 12-Pin, 4mm x 4mm Thin QFN Package
tion of the APD operating point by indicating the precise
• Circuit Height < 2mm
point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to ●● Commonly Available 2.7V to 5.5V Input Voltage
provide safe APD operation without data loss. Range
The output voltage can be accurately set with either exter-
nal resistors, an internal 8-bit DAC, an external DAC, or
other voltage source. Output span and offset are inde-
pendently settable with external resistors. This optimizes Ordering Information
the utilization of DAC resolution for applications that may PART TEMP RANGE PIN-PACKAGE
require limited output voltage range, such as 4.5V to 15V,
4.5V to 45V, 20V to 60V, or 40V to 90V. MAX1932ETC -40°C to +85°C 12 Thin QFN

Applications
●● Optical Receivers and Modules
●● Fiber Optic Network Equipment Typical Application Circuit
●● Telecom Equipment
●● Laser Range Finders INPUT
2.7V TO 5.5V
●● PIN Diode Bias Supply

Pin Configuration
VIN

MAX1932 APD BIAS OUTPUT

4.5V TO 90V
GATE

COMP
VIN
CS

12 11 10 GATE

SCLK 1 9 GND
CS
CS+
DIN 2 8 COMP DAC INPUTS SCLK
MAX1932 CS-
DIN
CL 3 7 FB AVALANCHE
INDICATOR CL
4 5 6 FLAG FB
GND
DACOUT
DACOUT
CS+

CS-

19-2555; Rev 3; 10/19

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Absolute Maximum Ratings

VIN to GND..............................................................-0.3V to +6V Operating Temperature Range............................ -40°C to +85°C
DIN, SCLK, CS, FB to GND.....................................-0.3V to +6V Junction Temperature.......................................................+150°C
COMP, DACOUT, GATE, CL to GND...........-0.3V to (VIN +0.3V) Storage Temperature Range............................. -65°C to +150°C
CS+, CS- to GND................................................. -0.3V to +110V Lead Temperature (soldering 10s)...................................+300°C
Continuous Power Dissipation (TA = +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C).....1349mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL
Input Supply Range VIN 2.7 5.5 V
VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current IIN 0.5 1 mA
VIN Shutdown Supply Current ISHDN 00 hex loaded to DAC 25 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 1 2.0 MΩ
Current-Limit Threshold
1.80 2.00 2.20 V
for CS+/CS-
Common-Mode Rejection
CS+ = 3V to 100V ±0.005 %/V
of Current Threshold
Gate-Driver Resistance Gate high or low, IGATE = ±50mA 5 10 Ω
Input Bias Current -25 +25 nA
TA = +25°C 1.24375 1.2500 1.25625
FB Voltage VFB V
TA = 0°C to +85°C 1.24250 1.2500 1.25750
FB Voltage Temperature
TCVFB 0.0007 %/°C
Coefficient
FB to COMP Transconductance COMP = 1.5V 50 110 200 µS
COMP Pulldown Resistance
DAC code = 00 hex 100 Ω
in Shutdown
DACOUT to FB Voltage Difference DAC code = FF hex -3 +3 mV
DACOUT Differential Nonlinearity DAC Code = 01 to FF hex,
-1 +1 LSB
(Note 1) DAC guaranteed monotonic
DACOUT Voltage Temperature
TCVDACOUT 0.0007 %/µC
Coefficient
DAC code = 0F to FF hex, source or sink
DACOUT Load Regulation -1 +1 mV
50µA
Switching Frequency fOSC 250 300 340 kHz
GATE Maximum On-Time tON 3 µs

www.maximintegrated.com Maxim Integrated │ 2

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Electrical Characteristics (continued)

(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage 0.6 V
Input High Voltage 1.4 V
Input Hysteresis 200 mV
TA = +25°C -1 +1 µA
Input Leakage Current
TA = 0°C to +85°C 10 nA
Input Capacitance 5 pF
DIGITAL OUTPUT (CL)
Output Low Voltage ISINK = 1mA 0.1 V
Output High Voltage ISOURCE = 0.5mA VIN - 0.5 V
SPI TIMING (Figure 5)
SCLK Clock Frequency fSCLK 2 MHz
SCLK Low Period tCL 125 ns
SCLK High Period tCH 125 ns
Data Hold Time tDH 0 ns
Data Setup Time tDS 125 ns
CS Assertion to SCLK
tCSS0 200 ns
Rising Edge Setup Time
CS Deassertion to SCLK
tCSS1 200 ns
Rising Edge Setup Time
SCLK Rising Edge
tCSH1 200 ns
to CS Deassertion
SCLK Rising Edge
tCSH0 200 ns
to CS Assertion
CS High Period tCSW 300 ns

Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL
Input Supply Range VIN 2.7 5.5 V
VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current IIN 1 mA
VIN Shutdown Supply Current ISHDN 00 hex loaded to DAC 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 2 MΩ
Current-Limit Threshold
1.80 2.20 V
for CS+/CS-
Gate-Driver Resistance Gate high or low, IGATE = ±50mA 10 Ω
FB Input Bias Current -30 +30 nA

www.maximintegrated.com Maxim Integrated │ 3

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Electrical Characteristics (continued)

(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Voltage VFB 1.23875 1.26125 V
FB to COMP Transconductance COMP = 1.5V 50 200 µS
COMP Pulldown Resistance
DAC code = 00 hex 100 Ω
in Shutdown
DACOUT to FB Voltage Difference DAC code = FF hex -4 +4 mV
DACOUT Differential Nonlinearity DAC Code = 01 to FF hex, DAC
-1 +1 LSB
(Note 1) guaranteed monotonic
DAC code = 0F to FF hex, source or sink
DACOUT Load Regulation -1 +1 mV
50µA
Switching Frequency fOSC 240 360 kHz
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage 0.6 V
Input High Voltage 1.4 V
DIGITAL OUTPUT (CL)
Output Low Voltage ISINK = 1mA 0.1 V
Output High Voltage ISOURCE = 0.5mA VIN - 0.5 V
SPI TIMING (Figure 5)
SCLK Clock Frequency fSCLK 2 MHz
SCLK Low Period tCL 125 ns
SCLK High Period tCH 125 ns
Data Hold Time tDH 0 ns
Data Setup Time tDS 125 ns
CS Assertion to SCLK
tCSS0 200 ns
Rising Edge Setup Time
CS Deassertion to SCLK
tCSS1 200 ns
Rising Edge Setup Time
SCLK Rising Edge
tCSH1 200 ns
to CS Deassertion
SCLK Rising Edge
tCSH0 200 ns
to CS Assertion
CS High Period tCSW 300 ns
Note 1:DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2:Specifications to -40°C are guaranteed by design and not production tested.

www.maximintegrated.com Maxim Integrated │ 4

 MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Typical Operating Characteristics

(VIN = 5V, Circuit of Figure 2, TA =+25°C, unless otherwise noted)

SWITCHING WAVEFORMS SWITCHING WAVEFORM WITH LC FILTER STARTUP AND SHUTDOWN WAVEFORMS
MAX1932 toc01 MAX1932 toc02 MAX1932 toc03

VLX VLX
50V/div 50V/div

OUTPUT 50V/div
IL IL VOLTAGE
0.05A/div 0.05A/div

INPUT 50mA/div
VOUT RIPPLE (AC-COUPLED) VOUT RIPPLE (AC-COUPLED) CURRENT
0.002V/div 0.002V/div
VOUT = 90V VOUT = 90V, L = 300µH, C = 1µF, FIGURE 7

1µs/div 1µs/div 20ms/div

OUTPUT VOLTAGE vs. INPUT VOLTAGE VFB vs. TEMPERATURE OUTPUT VOLTAGE vs. LOAD CURRENT
92 1.2520 95
MAX1932 toc04

MAX1932 toc05

MAX1932 toc06
1.2515 90
CURRENT LIMIT
85
91 1.2510 ACTIVATED
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

80
1.2505
VFB (V)

75
90 1.2500
70
1.2495
65
89 1.2490 VCC = 5V, INDUCTOR = 100µH,
60
R1 = 806Ω
1.2485 55 FEEDBACK DIVIDER CURRENT AND CS-
CURRENT INCLUDED
88 1.2480 50
2.5 3.5 4.5 5.5 -60 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT VOLTAGE (V) TEMPERATURE (°C) LOAD CURRENT (mA)

OUTPUT VOLTAGE STEP-DOWN OUTPUT VOLTAGE STEP-UP OUTPUT VOLTAGE STEP

DUE TO DAC CHANGE DUE TO DAC CHANGE DUE TO DACOUT CHANGE
MAX1932 toc07 MAX1932 toc08 MAX1932 toc09

OFFSET = 62.962V = 88 hex OFFSET = 62.962V = 88 hex

STEP DOWN FROM 80 hex TO 88 hex STEP VALUE = 64.233 = 80 hex
20V/div

1V/div 1V/div
DACOUT EXTERNAL SOURCE

0.5V/div

10ms/div 10ms/div 20ms/div

www.maximintegrated.com Maxim Integrated │ 5

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Pin Description
PIN NAME FUNCTION
1 SCLK DAC Serial Clock Input
2 DIN DAC Serial Data Input
3 CL Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN.
Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential
4 CS+
threshold is 2V. CS+ has typically 1MΩ resistance to ground.
5 CS- Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground.
Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or
6 DACOUT
sink 50µA.
Feedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the
7 FB
output voltage. The feedback set point is 1.25V.
Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is
8 COMP
actively discharged to ground during shutdown or undervoltage conditions.
9 GND Ground
10 GATE Gate-Driver Output for External N-FET
11 VIN IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor.
12 CS DAC Chip-Select Input

Detailed Description span and offset are independently settable with external
resistors. See the Applications Information section for
Fixed Frequency PWM output control equations.
The MAX1932 uses a constant frequency, PWM, control-
ler architecture. This controller sets the switch ontime and SPI Interface/Shutdown
drives an external N-channel MOSFET (see Figure 1). As Use an SPI-compatible 3-wire serial interface with the
the load varies, the error amplifier sets the inductor peak MAX1932 to control the DAC output voltage and to shut
current necessary to supply the load and regulate the down the MAX1932. Figures 4 and 5 show timing dia-
output voltage. grams for the SPI protocol. The MAX1932 is a write-only
device and uses CS along with SCLK and DIN to com-
Output Current Limit municate. The serial port is always operational when the
The MAX1932 uses an external resistor at CS+ and CS- device is powered. To shut down the DC-DC converter
to sense the output current (see Figure 2). The typical portion only, update the DAC registers to 00 hex.
current-limit threshold is 2V. CL is designed to help find
the optimum APD bias point by going low to indicate when Applications Information
the APD reaches avalanche and that current limit has
been activated. To minimize noise, CL only changes state
Voltage Feedback Sense Point
on an internal oscillator edge. Feedback can be taken from in front of, or after, the current-
limit sense resistor. The current-limit sense resistor forms
Output Control DAC a lowpass filter with the output capacitor. Taking feed-
An internal digital-to-analog converter can be used to con- back after the current-limit sense resistor (see Figure 2),
trol the output voltage of the DC-DC converter (Figure 2). optimizes the output voltage accuracy, but requires
The DAC output is changed through an SPI™ serial overcompensation, which slows down the control loop
interface using an 8-bit control byte. On power-up, the response. For faster response, the feedback can be taken
DAC defaults to FF hex (1.25V), which corresponds to a from in front of the current-sense resistor (see Figure 3).
minimum boost converter output voltage. This configuration however, makes the output voltage
Alternately, the output voltage can be set with external more sensitive to load variation and degrades output
resistors, an external DAC, or a voltage source. Output accuracy by an amount equal to the load current times the
current-sense resistor value.

www.maximintegrated.com Maxim Integrated │ 6

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Output and DAC Adjustments Range The inductance value is given by:
Many biasing applications require an adjustable output
voltage, which is easily obtained using the MAX1932’s L=
(VIN) 2 × D 2 × T × η
DAC output (Figure 2). 2I OUT(MAX) × VOUT
The DAC output voltage is given by the following equation: where VIN is the input voltage, IOUT(MAX) is the maximum
output current delivered, VOUT is the output voltage, and
VDACOUT = (CODE + 1) x 1.25V/256 T is the switching period (3.3μs), η is the estimated power
conversion efficiency, and D is the maximum duty cycle:
On power-up, DACOUT defaults to FF hex or 1.25V,
which corresponds to the minimum VOUT output voltage. D < (VOUT - VIN)/VOUT up to a maximum of 0.9
The voltage generated at DACOUT is coupled to FB
through R6. DACOUT can sink only 50μA so: Since the L equation factors in efficiency, for inductor cal-
culation purposes, an η of 0.5 to 0.75 is usually suitable.
1.25V For example, with a maximum DC load current of 2.5mA,
R6 ≥ a 90V output, VIN = 5V, D = 0.9, T = 3.3μs, and η esti-
50µA
mated at 0.75, the above equation yields an L of 111μH,
so 100μH would be a suitable value.
Select the minimum output voltage (VOUTFF), and the
maximum output voltage (VOUT01) for the desired adjust- The peak inductor current is given by:
ment range. R5 sets the adjustment span using the fol- VIN × D × T
lowing equation: IPK =
L
R5 = (VOUT01 - VOUTFF) (R6/1.25V) These are typical calculations. For worst case, refer
R8 sets the minimum output of the adjustment range with to the article titled “Choosing the MAX1932 External
the following equation: Indicator, Diode, Current Sense Resistor, and Output
Filter Capacitor for Worst Case Conditions” located on
R8 = (1.25V x R5)/(VOUTFF) the Maxim website in the Application Notes section (visit
www.maximintegrated.com/an1805).
Setting the Output Voltage without
the DAC External Power-Transistor Selection
An N-FET power switch is required for the MAX1932. The
Adjust the output voltage by connecting a voltagedivider
N-FET switch should be selected to have adequate on-
from the output (VOUT) to FB (Figure 2 with R6 omitted).
resistance with the MOSFET VGS = VIN(MIN). The break-
Select R8 between 10kΩ to 50kΩ. Calculate R5 with the
down voltage of the N-FET must be greater than VOUT.
following equation:
For higher-current output applications (such as 5mA at
 VOUT  90V), SOT23 high-voltage low-gate-threshold N-FETs
=R5 R8  − 1 may not have adequate current capability. For example,
 1.25V 
with a 5V input, a 90V, 5mA output requires an inductor
peak of 240mA. For such cases it may be necessary to
Inductor Selection simply parallel two N-FETs to achieve the required current
Optimum inductor selection depends on input voltage, rating. With SOT23 devices this often results in smaller
output voltage, maximum output current, switching fre- and lower cost than using a larger N-FET device.
quency, and inductor size. Inductors are typically speci- Diode Selection
fied by their inductance (L), peak current (IPK), and
The output diode should be rated to handle the output
resistance (LR).
voltage and the peak switch current. Make sure that the
diode’s peak current rating is at least IPK and that its
breakdown voltage exceeds VOUT. Fast reverse recovery
time (trr < 10ns) and low junction capacitance (<10pF) are
recommended to minimize losses. A small-signal silicon
switching diode is suitable if efficiency is not critical.

www.maximintegrated.com Maxim Integrated │ 7

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Output Filter Capacitor Selection The DC open-loop gain is given by:

The output capacitors of the MAX1932 must have high AOL = K2 x Gm x REA
enough voltage rating to operate with the VOUT required. where REA = 310MΩ,
Output capacitor effective series resistance (ESR) deter-
mines the amplitude of the high-frequency ripple seen gM = 110μS,
on the output voltage. In the typical application circuit, a RLD is the parallel combination of feedback network and
second RC formed by R1 and C3 further reduces ripple. the load resistance.
Input Bypass Capacitor Selection K1 =
2 × VOUT -VIN
The input bypass capacitor reduces the peak currents VOUT -VIN
drawn from the voltage source and reduces noise caused
by the MAX1932’s switching action. The input source V (Volts) 2 × VIN
K2 =FB × ×
impedance determines the size of the capacitor required 0.75(Volts) 2 × VOUT -VIN
at the input (VIN). A low ESR capacitor is recommended.   V 
A 1μF ceramic capacitor is adequate for most applica-   OUT  R LD × T(second) 

tions. Place the bypass capacitor as close as possible to   VOUT -VIN  2 × L(Henries) 
 
the VIN and GND pins.
A properly compensated MAX1932 results in a gain vs.
Current-Sense Resistor Selection
frequency plot that crosses 0dB with a single pole slope
Current limit is used to set the maximum delivered out- (20dB per decade). See Figure 6.
put current. In the typical application circuit, MAX1932 is
designed to current limit at: Table 1 lists suggested component values for several
typical applications.
2V
R1 = Further Noise Reduction
ILIMIT
The current-limit sense resistor is typically used as part
Note that ILIMIT must include current drawn by the feed- of an output lowpass filter to reduce noise and ripple.
back divider (if sensing feedback after R1) and the input For further reduction of noise, an LC filter can be added
current of CS-. as shown in Figure 7. Output ripple and noise with and
without the LC filter are shown in the Typical Operating
Stability and Compensation Characteristics. If a post LC filter is used, it is best to
Component Selection use a coil with fairly large resistance (or a series resis-
Compensation components, R7 and C4, introduce a pole tor) so that ringing at the response peak of the LC filter is
and a zero necessary to stabilize the MAX1932 (see damped. For a 330μH and 1μF filter, 22Ω accomplishes
Figure 6). The dominant pole, POLE1, is formed by the this, but a resistor is not needed if the coil resistance is
output impedance of the error amplifier (REA) and C4. greater than 15Ω.
The R7/C4 zero, ZERO1, is selected to cancel the pole
formed by the output filter cap C3 and output load RLD, Output Accuracy and Feedback
POLE2. The additional pole of R1/C3, POLE3, should Resistor Selection
be at least a decade past the crossover frequency to not The MAX1932 features 0.5% feedback accuracy. The total
affect stability: voltage accuracy of a complete APD bias circuit is the sum
of the FB set-point accuracy, plus resistor ratio error and
POLE1 (dominant pole) = 1 / (2π x REA x C4)
temperature coefficient. If absolute accuracy is critical, the
ZERO1 (integrator zero) = 1 / (2π x R7 x C4) best resistor choice is an integrated network with specified
POLE2 (output load pole) = K1 / (2π x RLD x (C2 + C3)) ratio tolerance and temperature coefficient. If using discrete
resistors in high-accuracy applications, pay close attention
POLE3 (output filter pole) = 1 / (2π x R1 x C3)
to resistor tolerance and temperature coefficients.

www.maximintegrated.com Maxim Integrated │ 8

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Table 1. Compensation Components for Typical Circuits (Figure 2)

INDUCTOR L1 CSNS RSNS COUT RCOMP CCOMP
VIN, VOUT, IOUT(MAX)
(µH) C2 (µF) R1 (Ω) C3 (µF) R7 (kΩ) C4 (µF)
5VIN, 40-90VOUT at 2.5mA 100 0.047 806 0.1 20 0.22
5VIN, 20-60VOUT at 2.5mA 150 0.10 806 0.047 15 0.22
5VIN, 20-60VOUT at 5mA 82 0.22 392 0.10 10 0.47
3VIN, 40-90VOUT at 2.5mA 33 0.047 806 0.1 20 0.22
3VIN, 4.5-15VOUT at 2.5mA 220 0.47 806 0.01 7.5 0.47

Temperature Compensation PC Board Layout and Grounding

APDs exhibit a change in gain as a function of tem- Careful PC board layout is important for minimizing
perature. This gain change can be compensated with an ground bounce and noise. In addition, keep all connec-
appropriate adjustment in bias voltage. For this reason it tions to FB as a short as possible. In particular, locate
may be desirable to vary the MAX1932 output voltage as feedback resistors (R5, R6, and R8) as close to FB as
a function of temperature. This can be done in software possible. Use wide, short traces to interconnect large cur-
by the system through the on-chip DAC, but can also be rent paths for N1, D1, L1, C1, C2. Do not share these con-
accomplished in hardware using an external thermistor nections with other signal paths. Refer to the MAX1932
or IC temperature sensor. Figure 8 shows how an NTC EV kit for a PC board layout example.
thermistor can be connected to make the bias voltage
increase with temperature.

www.maximintegrated.com Maxim Integrated │ 9

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

COMP

REF UVLO VIN

1.25V

PWM CONTROL
FB GATE
AND GATE DRIVER
ERROR
AMPLIFIER

ERROR
COMPARATOR
RAMP
GND

OSC

987kΩ
CS+
CLIM CL
13kΩ

BUFFER
987kΩ
CS-

13kΩ

REF

SCLK
DACOUT
SPI 8
DIN SERIAL 8-BIT DAC
INTERFACE
CS

Figure 1. Functional Diagram

www.maximintegrated.com Maxim Integrated │ 10

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

C1 1µF
INPUT
2.7V TO 5.5V
VIN L1
CL 100µH
COMP D1 R1
100V 806Ω
R7 VOUT
20kΩ MAX1932 40V TO 90V
C2
C4 C3
GATE 0.047
0.22µF 0.1µF
N1
BSS123
CS CS+
CS-
SCLK
R5
DIN 1MΩ

GND FB
R6
DACOUT R8
24.9kΩ
32.4kΩ

Figure 2. Typical Operating Circuit

INSTRUCTION
EXECUTED

VOUT CS

GATE

FB 1 8
SCLK

MAX1932
DIN

CS+ D7 D6 D5 D4 D3 D2 D1 DO
CS-

Figure 3. Taking Feedback Ahead of Output Filter Figure 4. Serial Interface Timing Diagram

CS tCSW
tCSH0
tCSS0 tCSH1
tCH

SCLK

tDS tCL tCSS1

tDH

DIN

Figure 5. Detailed Serial Interface Timing Diagram

www.maximintegrated.com Maxim Integrated │ 11

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

120

100

90V, 90V,
1mA 2.5mA

80 POLE1 0.0023Hz 0.0023Hz

ZERO1 36Hz 36Hz

POLE2 36Hz 91Hz

POLE3 4.2kHz 4.2kHz

60
AOL 102dB 98dB
MAGNITUDE (dB)

40

36Hz

91Hz
20

0.01 0.1 1.0 10 100 1k 10k

FREQUENCY (Hz) 4.2k

Figure 6. Loop Response

www.maximintegrated.com Maxim Integrated │ 12

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

VIN

330µH
VOUT
0.1µF 1µF
GATE

FB

MAX1932

CS+
CS-

Figure 7. Adding a Post LC Filter

VIN

TO CS+ TO CS-
R1
VOUT

GATE
R5

MAX1932
FB

R8

R10
R9 NTC
THERMISTOR

Figure 8. Adding an NTC Thermistor for Hardware Temperature Compensation; Output Voltage Increases with Temperature Rise

www.maximintegrated.com Maxim Integrated │ 13

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Chip Information Package Information

TRANSISTOR COUNT: 1592 For the latest package outline information and land patterns
PROCESS: BICMOS (footprints), go to www.maximintegrated.com/packag-
es. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of
RoHS status.

PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.
12 TQFN T1244-4 21-0139 90-0068

www.maximintegrated.com Maxim Integrated │ 14

MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
2 5/15 Updated Benefits and Features section 1
Corrected R5 equation per JIRA ticket MXDS-110.
3 10/19 7
Simplified VDACOUT equation for clarity.

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2019 Maxim Integrated Products, Inc. │ 15