A TECHNICAL REPORT ON STUDENT INDUSTRIAL

WORK EXPERIENCE SCHEME (SIWES)

UNDERTAKEN AT
PLETHUDEEP HUB

ZONE B, BLOCK 15, SHOP 5, OAU CENTRAL MARKET,

ILE-IFE

by

IDOKO, IKENNA DANIEL

(CSC/2018/086)

SUBMITTED TO
THE DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
OBAFEMI AWOLOWO UNIVERSITY

IN PARTIAL FULFILMENT OF THE

REQUIREMENTS FOR THE AWARD OF BACHELOR OF SCIENCE IN
COMPUTER ENGINEERING

November 2023
 CERTIFICATION

This is to certify that this work was carried out by IDOKO, IKENNA DANIEL in partial
fulfilment of the requirements for the award of the degree of Bachelor of Science ([Link].),
in the Department of Computer Science and Engineering, Obafemi Awolowo University,
Ile-Ife, Nigeria.

————————————————
Engr. S.P. Olayiwola
Industry-based Supervisor

i
 DEDICATION

”Some folk we never forget

Some kind we never forgive

Haven’t seen the back of us yet

We’ll fight as long as we live

All eyes on the hidden door

To the Lonely Mountain borne

We’ll ride in the gathering storm

Until we get our long forgotten gold”

-Neil Finn

ii
 ACKNOWLEDGEMENTS

I express my deepest gratitude to the Almighty for His unwavering guidance and

grace throughout my SIWES journey. Special thanks to my SIWES supervisor, Engr.

Olayiwola, whose words of motivation and encouragement have been a guiding light. His

love for students and dedication to the progress of Nigeria are truly inspiring.

I am also immensely grateful to Innocent Emmanuel, whose mentorship in IC

design and engineering has been invaluable. His wisdom and support have shaped my

understanding and passion for the field. I am fortunate to have had such a dedicated

mentor.

To God, Engr. Olayiwola, and Innocent Emmanuel, thank you for being integral parts

of my SIWES experience, contributing to my growth and learning in profound ways.

iii
 Table of contents

List of Figures vi

List of Tables vii

List of Abbreviations viii

Abstract ix

Chapter 1: Introduction 1
1.1 Student Industrial Work Experience Scheme (SIWES) . . . . . . . . . . 1
1.2 Objectives of SIWES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 PlethuDeep Hub — Company Profile . . . . . . . . . . . . . . . . . . . . 4

Chapter 2: siwes activites 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Digital Signal Processing (DSP) . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Signal Processing Basics . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Generating Signals and Common Signal Operations . . . . . . . . 10
2.2.3 Estimating Power Spectral Density . . . . . . . . . . . . . . . . . 13
2.2.4 Improving the Power Spectral Density Estimate . . . . . . . . . . 16
2.2.5 Characterizing Digital Filters . . . . . . . . . . . . . . . . . . . . 17
2.2.6 Designing Digital Filters . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.7 Filter Design Algorithms . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.8 Streaming Signal Processing . . . . . . . . . . . . . . . . . . . . . 26
2.3 Analog IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.1 Design concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.2 The Design of the OTA . . . . . . . . . . . . . . . . . . . . . . . 30

iv
 2.3.3 Simulation and results of the OTA . . . . . . . . . . . . . . . . . 36

Chapter 3: SKILLS ACQUIRED AND EXPERIENCE GAINED 43

3.1 Skills Acquired . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Relevance to Course of Study (Computer Engineering) . . . . . . . . . . 45
3.3 Problems Encountered and Solutions . . . . . . . . . . . . . . . . . . . . 46

Chapter 4: Conclusion and Recommendations 47

4.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

References 49

v
 List of Figures

1.1 The organisation structure of PlethuDeep Hub . . . . . . . . . . . . . . . 6

2.1 Signals and Watermarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 PSD estimation techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Filter Design Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 The Folded cascode operational transconductance amplifier topology . . . 33
2.5 Transfer function of the OTA at open loop – Magnitude and phase plot . 42

vi
 List of Tables

2.1 A Few Signal Processing basics in MATLAB . . . . . . . . . . . . . . . . 9

2.2 FIR versus IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 FIR versus IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 FIR versus IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 Some DC parameter; hand-calculated values . . . . . . . . . . . . 39
2.6 Some DC parameter; .op simulation results . . . . . . . . . . . . . 40
2.7 Hand calculated values vs. simulation values of the input
common mode range and output swing . . . . . . . . . . . . . . . . 41

vii
 LIST OF ABBREVIATIONS

CMOS Complimentary Metal Oxide Semiconductor

FPGA Field Programmable Gate Array
IC Integrated Circuit
ITF Industrial Training Fund
OTA Operational Transconductance Amplifier
PICO Program for Integrated Circuit design Outreach
PDK Process Design Kit
PGA Programmable Gain Amplifier
SIWES Student Industrial Work Experience Scheme
SPICE Simulation Programming with Integrated Circuit Emphasis

viii
 ABSTRACT

This technical report encapsulates my enriching work experience at PlethuDeep Hub,

focusing on Digital Signal Processing (DSP) and Machine Learning utilizing Matlab,

alongside Analog Integrated Circuit (IC) design. The document provides a comprehensive

overview of the projects undertaken during this period, highlighting the integration of

DSP and Machine Learning techniques within the Matlab environment, as well as the

intricacies of Analog IC design. The report details the challenges faced, methodologies

employed, and the valuable insights gained from the intersection of these cutting-edge

technologies, contributing to my professional growth and expertise in the field.

ix
 CHAPTER ONE

INTRODUCTION

1.1 Student Industrial Work Experience Scheme (SI-

WES)

SIWES stands for the Students Industrial Work Experience Scheme. It is a program

designed to expose students in tertiary institutions in Nigeria to practical work experience

related to their field of study. SIWES is coordinated by the Industrial Training Fund

(ITF) in collaboration with various industries and educational institutions.

The history of SIWES in Nigeria dates back to 1971 when the program was established

by the Industrial Training Fund (ITF). The primary objective of SIWES is to bridge the

gap between theoretical knowledge acquired in the classroom and practical application in

the workplace. The program aims to provide students with the opportunity to gain hands-

on experience, develop practical skills, and understand the work environment within their

chosen field.

SIWES was established to address the concerns about the perceived lack of practical

skills among graduates and to enhance their employability.

1
 The Industrial Training Fund (ITF) was mandated to oversee the implementation

of SIWES. The ITF works in collaboration with tertiary institutions, industries, and

students to ensure the success of the program.

SIWES typically lasts for a period of three to six months, depending on the academic

program. During this time, students are required to undergo practical training in relevant

industries.

SIWES is usually a compulsory part of the curriculum for students in fields such

as engineering, science, technology, and other applied disciplines. It is seen as a

crucial component of the educational system to produce well-rounded and industry-ready

graduates.

The program offers several benefits, including exposure to real-world work environ-

ments, the opportunity to apply theoretical knowledge in practice, and the chance to

develop essential soft skills such as communication, teamwork, and problem-solving.

SIWES plays a vital role in preparing students for the workforce and ensuring that

they are equipped with the practical skills required by industries. It also serves as a

platform for industries to identify potential talent and contribute to the development of

a skilled and competent workforce in Nigeria.

2
1.2 Objectives of SIWES

• Integration of Theory and Practice: SIWES aims to bridge the gap between

theoretical knowledge acquired in the classroom and practical application in real-

world work environments. It provides students with the opportunity to integrate

what they have learned in their academic programs with hands-on experience.

• Exposure to Professional Work Environments: SIWES exposes students to

the actual working conditions and practices in industries related to their fields of

study. This exposure helps them gain a better understanding of industry operations,

standards, and professional ethics.

• Skill Development: The program is designed to enhance the practical skills and

competencies of students. By working in industries, students have the chance to

develop technical skills, problem-solving abilities, and other practical skills that are

essential for their chosen professions..

• Industry-Academia Collaboration: SIWES promotes collaboration between

educational institutions and industries. It fosters a mutually beneficial relationship

where academic institutions gain insights into industry trends, and industries

contribute to the development of a skilled and knowledgeable workforce.

• Identification of Career Paths: SIWES provides students with the opportunity

to explore different aspects of their chosen fields. This hands-on experience helps

them identify specific areas of interest within their disciplines, which can guide their

career choices after graduation.

3
 • Promotion of Self-Reliance: SIWES encourages self-reliance and independence

among students. It provides an opportunity for them to apply their knowledge in

real-world situations, fostering a sense of responsibility and self-confidence.

• Professional Networking: During SIWES, students have the chance to build

professional networks and connections within their industries. This networking can

be valuable for future career opportunities and mentorship.

In summary, SIWES plays a crucial role in preparing students for the workforce

by providing them with practical experience, enhancing their skills, and fostering

collaboration between academic institutions and industries.

1.3 PlethuDeep Hub — Company Profile

Plethudeep Hub is a technological hub established to incubate and accelerate student

projects to becoming viable products and services in the market. It was established 2018

but began operations 2020. Our Vision Statement Our vision is to bridge the gap between

training at school and the digital skills expected in the industrial world in order to provide

at scale future ready to fill job positions and create tech based startups Our Mission

Statement Our mission is as to provide a gamified platform that will drive engagement in

learning skills which re in tandem with the realities of the emerging digital market place

and that seamlessly integrates to their curriculum at school The various aspects of the

hub includes

• Artificial Intelligence

• Embedded systems development

4
 • Microelectronics

• Engineering idea incubation

The organogram of the company being a startup comprises the CEO who has the

Chief Technical Officer (CTO) working alongside with both the ideas incubation team

and design team

5
Figure 1.1: The organisation structure of PlethuDeep Hub

6
 CHAPTER TWO

SIWES ACTIVITES

2.1 Introduction

The focal point of my engagement at PlethuDeep Hub was the comprehensive exploration

of Digital Signal Processing (DSP), Machine Learning and Analog IC design. This chapter

exclusively delves into the intricacies of the design, simulation, and physical layout of a

programmable gain amplifier integrated circuit (IC), aligning with my specialization in

DSP and Analog IC design.

However, for the purpose of this chapter, the detailed discussion will revolve around my

involvement in DSP and Analog IC design, showcasing the skills and experiences gained

in these specific domains during my tenure at the Semiconductor Research Laboratory.

2.2 Digital Signal Processing (DSP)

This programmable gain amplifier project draws inspiration from the During my SIWES

internship, I gained hands-on experience in various aspects of digital signal processing.

I started by learning the basics of generating and manipulating digital signals. This

included techniques like resampling and modulation. After getting comfortable with

signal generation, I moved on to more advanced topics like spectral estimation and digital

7
filter design. A major part of my work involved processing streaming signals in real-

time. Throughout the internship, I applied DSP concepts to solve problems in condition

monitoring and digital watermarking.

2.2.1 Signal Processing Basics

I began by learning how to generate and visualize different types of digital signals

like sinusoids, chirps, impulses, and noise. Using MATLAB, I wrote programs to

generate sampled signals with specified sample rates and durations. I also learned basic

operations like shifting signals in time, changing amplitude, merging multiple signals, and

introducing noise. These skills allowed me to synthesize test signals for subsequent DSP

experiments.

8
 Table 2.1: A Few Signal Processing basics in MATLAB

Function Description Example

audioread Import audio [sig,fs] = audioread("[Link]")
pspectrum Display the power spectrum pspectrum(sig,fs)
Save the power spectrum [p,f] = pspectrum(sig,fs)
Display the spectrogram pspectrum(sig,fs,"spectrogram")
lowpass Display the filtered signal lowpass(sig,10,fs)
Save the filtered signal sigfilt = lowpass(sig,10,fs)

9
2.2.2 Generating Signals and Common Signal Operations

I generated sinusoidal, triangular, sawtooth and noise signals using functions like

sine, triange, sawtooth and randn in MATLAB. I specified parameters like amplitude,

frequency, phase, sample rate and duration to control the signal properties. By adding

multiple sinusoids, I generated more complex periodic signals.

To change the sample rate of a signal, I used functions like resample in MATLAB. This

allowed me to increase or decrease the sample rate by a factor while avoiding aliasing. For

frequency shifting without distortion, I multiplied the signal with a complex exponential

using the freqshift function. I also got familiar with time shifting and scaling operations

by introducing delays and modifying the timescale.

Digital Watermarking

I implemented a basic digital watermarking algorithm to hide information in audio signals.

The watermark was a pseudo-random binary sequence generated using a key. I embedded

the watermark into an audio signal by adding the scaled watermark to the signal. To

extract the watermark, I correlated the watermarked signal with the original watermark

pattern. This revealed the presence of the hidden information.

Resampling

When altering the sample rate of a signal, I was careful to apply anti-aliasing filters to

avoid artifacts. I wrote functions to upsample and downsample signals using polyphase

implementations. This approach provided an efficient way to change sample rates. There

10
are multiple ways to resample a signal to a higher or lower rate. Upsampling and

downsampling are the simplest methods.

11
 (a) Single tone watermark

(b) Chirp watermark

(c) Audio watermark

Figure 2.1: Signals and Watermarks

12
Modulation

I explored modulation techniques like AM and FM synthesis. Given a carrier and message

signal, I wrote functions to generate modulated outputs. Adjusting the modulation index

allowed me to vary the strength of the modulation. I also demodulated signals using

techniques like envelope detection.

2.2.3 Estimating Power Spectral Density

Spectral analysis allowed me to characterize the frequency content of signals. I calculated

periodograms using the Fast Fourier Transform. While straightforward to compute,

periodograms suffered from variance issues. To improve results, I implemented techniques

like:

• Zero-padding: Reduces leakage by interpolating additional samples

• Windowing: Reduces spectral leakage by attenuating discontinuities

• Welch’s method: Averages successive windowed periodograms to reduce noise

I wrote functions to apply each technique and analyzed the results. This gave me an

intuition for how each method improves the power spectral density estimate.

Discrete Fourier Transform

I estimated the frequency content of signals by computing the Discrete Fourier Transform

using the FFT. For real signals, I only looked at the positive frequencies due to symmetry.

The magnitude squared gave an estimate of the power at each frequency bin. The discrete

13
Fourier transform (DFT) is computed for each sample in x.

N
X −1
Xk = x[n].e−[Link]/N . (2.1)
k=0

For a discrete-time, finite-length signal, the discrete Fourier transform (DFT) can be used

to calculate the spectrum at particular frequencies. In MATLAB, you can calculate the

DFT by using the .fft function, which stands for fast Fourier transform.

Periodogram

The periodogram computes the power spectral density by taking the magnitude squared

of the DFT. I averaged multiple periodograms to reduce the variance of the estimate.

However, this came at the cost of reduced frequency resolution.

Zero Padding

To interpolate additional points, I padded the signal with zeros prior to taking the DFT.

This allowed me to increase the frequency resolution. However, zero-padding alone did

not reduce spectral leakage caused by discontinuities.

Windowing

I multiplied the signal by window functions like Kasier and Hamming windows prior

to taking the DFT. This attenuated discontinuities and reduced spectral leakage. The

smoothed spectrum enabled me to discern individual frequency components.

14
 (a) Periodogram

(b) Zero padding: In general, using a larger number of DFT

points will give your power spectrum a smoother appearance.

(c) Windowing: Rectangular windows are good in situations

where you want a narrow mainlobe width, or where there are
closely spaced tones. Here, there are two tones at 25 Hz and 26
Hz. You can see both peaks with the rectangular window, but
the mainlobes have merged together with the Kaiser window.

Figure 2.2: PSD estimation techniques

15
2.2.4 Improving the Power Spectral Density Estimate

For noisy, non-stationary signals, the standard periodogram was often insufficient. I

implemented more advanced techniques to improve the accuracy

Welch’s Method

I split the signal into overlapping segments, computed windowed periodograms of each

segment and averaged the results. This reduced noise by decreasing the variance across

segments. However, it decreased the frequency resolution. This is the implementation in

MATLAB

>> [p,f] = pwelch(sig,window,numoverlap,nfft,fs)

Where,

• p is the PSD estimate

• f is the Frequencies

• sig is the Input data

• window is the Window vector. If the size is less than sig, there is spectral averaging.

• numoverlap is the Number of samples to overlap. Must be less than the size of

window.

• nfft is the Number of DFT points

• fs is the Sample rate

16
Time-Frequency Analysis

For signals whose spectrum varies over time, I used time-frequency distributions.

The short-time Fourier transform (STFT) allowed me to analyze the spectral content

within sliding windows. For higher resolution, I implemented quadratic time-frequency

distributions.

Using MATLAB,

[s,f,t,ps] = spectrogram(sig,window,numoverlap,nfft,fs)

Parametric Methods

I modeled signals as auto-regressive (AR) processes. By estimating the AR coefficients, I

obtained a smooth power spectrum estimate. However, AR modeling required assuming

a specific model order which was not always easy to determine.

The experience helped me learn the trade-offs between different spectral estimation

methods. This enabled me to select appropriate techniques for different applications.

By exploring advanced spectral estimation methods, I gained knowledge on how to

improve resolution, reduce noise and handle non-stationary signals when estimating power

spectral densities.

2.2.5 Characterizing Digital Filters

I wrote programs to visualize filter responses in the time and frequency domains. This

helped build intuition on how filters transform signals.

17
 In the time domain, I analyzed the filter coefficients and impulse response. The

impulse response showed the output for a delta input and revealed properties like ringing

and delay.

For frequency-domain analysis, I computed amplitude and phase responses. Visualiz-

ing the magnitude response showed how the filter alters individual frequency components.

Group delay plots demonstrated constant, nonlinear or distorted phase.

Zeros and poles revealed stability and frequency selective properties. With this

comprehensive analysis, I was able to predict the impact of filters on signal characteristics.

Filter Coefficients

I specified FIR and IIR filters by directly entering the filter coefficients. Analyzing the

coefficients provided basic insights on filter behavior and stability.

Digital filters with finite-duration impulse response are called FIR filters, as opposed

to infinite-duration impulse response, which are called IIR filters. Each filter type has

advantages and disadvantages.

Filter Responses

I visualized the impulse and step response to analyze time-domain properties. The

impulse response characterized the output for an isolated input spike. Step response

showed the build-up and settling behavior.

18
Filter Delay

I quantified the delay introduced by a filter using the group delay plot. For linear phase

FIR filters, the delay was constant across frequencies. For IIR and nonlinear filters, the

delay varied with frequency.

Zeros and Poles

The position of zeros and poles indicated the stability of IIR filters. Filters with poles

outside the unit circle were unstable. The angle and distance of poles from the origin

determined the resonance and frequency selectivity.

By studying filter responses in the time and frequency domains, I developed an

intuitive understanding of how filters reshape signals. This helped me predict the impact

of filters and identify potential issues.

19
 Table 2.2: FIR versus IIR Filters

FIR Filters IIR Filters

Order / Delay Usually higher Usually lower, because of the filter’s feedback loops
Phase Can be linear Cannot be linear, except with zero-phase filtering (filtfilt)
Stability Always stable May be unstable, as poles may be outside the unit circle
Transient Finite Infinite

20
2.2.6 Designing Digital Filters

I designed digital filters to meet prescribed specifications:

FIR Filters

I designed finite impulse response (FIR) filters using the window, frequency sampling and

least squares methods. Windowing offered simplicity while frequency sampling allowed

arbitrary magnitude responses. I used least squares for equiripple designs.

IIR Filters

For infinite impulse response (IIR) filters, I applied the Butterworth and Chebyshev

approximations. I used higher order designs when sharp transitions were needed. Biquad

implementations enabled lower group delay.

Through hands-on design, I learned how parameters affect the frequency response,

stability and computational complexity of filters. This enabled me to make appropriate

design trade-offs.

2.2.7 Filter Design Algorithms

Using MATLAB toolboxes, I designed filters by specifying requirements like passband

edge, stopband attenuation and allowed ripples. This automated the design process

while allowing optimization of filters.

21
Arbitrary Filter Response

I designed custom FIR filters by specifying an ideal desired frequency response. MATLAB

functions like firls and firpm allowed me to implement filters with arbitrary, non-

standard magnitude responses.

By gaining experience in FIR and IIR filter design, I developed practical skills for

developing filters targeted for different applications. The combination of manual and

automated design enabled efficient prototyping and optimization.

22
(a) For example, here’s the magnitude response of
an IIR filter designed with the Butterworth method.

(b) Here’s the magnitude response of an IIR filter

designed with the elliptic method. The same
specifications were used.

(c) It is easier to compare the filters if you overlay

them on the same plot.

Figure 2.3: Filter Design Algorithms

23
 Table 2.3: FIR versus IIR Filters

Filter Type Lowpass Magnitude Response Description

Provides the best Taylor series approximation

to the ideal lowpass filter response at analog
frequencies Ω = 0 and Ω = ∞ for any
Butterworth order n. The magnitude squared response
filter has 2n - 1 zero derivatives (is maximally flat)
at these locations. Response is monotonic
overall, decreasing smoothly from Ω = 0 to
Ω=∞

24
Minimizes the absolute difference between
ideal and actual frequency response by using
Chebyshev an equal ripple in the passband. Stopband
Type I filter response is maximally flat. The transition
from passband to stopband is more rapid than
for the Butterworth filter.
 Table 2.4: FIR versus IIR Filters

Filter Type Lowpass Magnitude Response Description

Minimizes the absolute difference between
ideal and actual frequency response by using
an equal ripple in the stopband. Passband
response is maximally flat. The stopband does
Chebyshev
not approach zero as quickly as the type I filter
Type II filter
(and does not approach zero at all for even-
valued filter order n). The absence of ripple in
the passband, however, is often an important

25
advantage.

Minimizes the absolute difference between

ideal and actual frequency response using
equal ripples in both passband and stopband.
Generally meets filter requirements with the
Elliptic filter
lowest order of any supported filter type.
Given a filter order n, passband ripple,
and stopband ripple, elliptic filters minimize
transition width.
2.2.8 Streaming Signal Processing

Real-time streaming applications required processing sampled signals as they are

acquired:

I segmented the continuous input into chunks or frames using fixed length or adaptive

windows.

For each frame, I applied DSP operations like filtering, spectral analysis and feature

extraction.

The output was passed downstream for additional processing or decision making.

I implemented the frame processing in a loop to continuously handle new inputs. By

applying buffering and parallelization, I optimized the code to sustain real-time rates.

The streaming approach enabled online processing and analysis of live data. Through

hands-on development, I gained practical experience in implementing performant DSP

systems.

Create DSP System Objects

I created DSP system objects like filters, transforms, analyzers using MATLAB classes.

This encapsulated the signal processing operations for reuse.

Process Signals in a Loop

I processed the input frames inside a for/while loop. Each iteration handled the next

frame, applied DSP operations and passed the output. Buffering reduced data copies.

26
 By architecting DSP systems in a streaming manner, I learned real-time design

practices crucial for embedded signal processing applications. This experience helped

strengthen my skills.

2.3 Analog IC Design

The operational transconductance amplifier (OTA) stands as a cornerstone in analog

circuit design, facilitating the conversion of input voltage signals into corresponding

output currents. Among the various OTA architectures, the folded cascode configuration

has garnered significant attention for its robust performance and versatility in meeting

the demands of modern integrated circuits.

This design explores the intricacies of a folded cascode OTA, a configuration renowned

for its high gain, wide bandwidth, and enhanced linearity. As an essential component

in numerous analog and mixed-signal applications, the folded cascode OTA offers a

compelling solution for achieving optimal performance in demanding signal processing

tasks.

2.3.1 Design concepts

In this project, the level 1 square-law transistor model was utilized to size the transistors,

despite its limitations in accurately predicting the behavior of contemporary transistors.

This choice was made due to its convenience for manual calculations and its still

reasonable approximation of modern transistor behavior. While alternative models and

methodologies, such as the EKV model, gm/Id-based design approach, and the inversion

27
coefficient, yield results that align well with modern SPICE simulators, they were not

employed in this project. The EKV model and the inversion coefficient method are

impractical for manual calculations, and the gm/Id-based methodology, though suitable

for manual calculations, necessitates precompiled look-up charts. Unfortunately, time

constraints precluded the generation of these charts for the specific transistor technology

used in this project.

To align the design with actual transistor behavior, following the calculations using

the level-1 model, the design underwent simulation and optimization using the SPICE

model from the GF180 PDK.

The behavior of the MOS transistor devices for levels 1, 2, and 3 models is defined by

the following equations.

W
ID = µCox (VGS − VT n )2 (2.2)
2L

p p
VT n = VT o + γ 2ϕf − VSB − 2ϕf (2.3)

Where:

• ID is the drain current of the MOS transistor device

• VT n is the overall threshold voltage of the MOS device with backgate effect

• VT O is the threshold voltage of the MOS device without backgate effect

• γ is the backgate parameter

28
 • λ is the channel length modulation parameter

• VGS is the gate to source voltage

• VDS is the drain to source voltage

• Cox is the transconductance parameter of the device

• W
L
is the sizing of the transistor device

• ϕf is the potential of the substrate of the device

One of the common design parameters used in the level-1 model is the voltage overdrive

(Vov ). The overdrive voltage is defined by the following equations:

2ID
Vov = (2.4)
gm

Vovn = VGS − VT n (2.5)

Vovn = VSG − |VT n | (2.6)

Equations 2.5 and 2.6 are specific to NMOS and PMOS devices respectively. In

equation 2.4 gm is the transconductance of the transistor device either NMOS or PMOS.

In design one universally important parameter that needs to be determined is the

sizing ( W
L
) of the transistors. In levels 1-3 model design, the sizings of the transistors can

be determined with the following equations:

W gm 2
= (2.7)
L 2ID µn Cox

29
 W 2ID
= (2.8)
L µn Cox Vov 2

2.3.2 The Design of the OTA

The design process for all circuits and systems initiates with the specification phase.

Therefore, this particular design commenced with the specifications detailed at the

beginning of this chapter. To facilitate reference, the specifications are reiterated below:

• Gain Bandwidth GBW = 30MHz

• Load capacitance, CL = 5pF

• VDD = 3.3V

• Open loop Gain Av ≥ 1000V /V , 60dB

• Slew Rate, SR = 20V /µs

• P haseM argin ≥ 60

• Close Loop Gain Range = 0.25V/V, 0.5V/V, 1V/V, 2V/V, 4V/V, 8V/V

The CMOS technology employed in this design originates from the open-source

GlobalFoundry process design kit (PDK), specifically the GF180nm variant. While

the design process typically commences with specified requirements, it is prudent to

validate whether the chosen CMOS technology aligns with the intended specifications.

It’s essential to acknowledge that all specifications carry a degree of uncertainty, as certain

conditions may cause discrepancies, particularly when parameters are combined.

30
 For instance, the intrinsic gain of a transistor device is not uniform across all potential

output or input ranges. To address this, an initial simulation is often conducted using

the selected transistor technology to verify alignment with the desired output or input

range and gain. However, in the context of this design, an assumption was made that the

specifications are achievable with the chosen transistor technology. This assumption

is justified by the iterative nature of the design process, allowing for adjustments,

such as resizing device parameters, to meet specifications in subsequent iterations while

preserving other critical parameters.

The key parameters to be determined in this design include the sizing ratios ( W
L
) of

each transistor, the bias currents for each transistor, the bias voltages, and the output

voltage swing.

In Fig. 2.4(a), the fundamental folded cascode topology is depicted, biased by ideal

current sources I0 and IB . Within this topology, transistors M1 and M2 constitute the

input differential pair stage, while M3 and M4 function as the cascode transistors. The

pairs M1 − M3 and M2 − M4 form the folded cascode amplifier. To match the high output

resistance of the cascode pair, the current source load is implemented with a cascode

current mirror, involving transistors M5 to M8 . As the design adheres to an all-CMOS

configuration, the ideal current sources I0 and IB must also be realized with transistors.

In Fig. 2.4(b), the complete realization of the folded cascode amplifier is presented,

incorporating M0 and M9 to M10 as current sources. Further details regarding the design

of voltage references Vref , VB3 , VB5 , and VB9 will be addressed subsequently. Currently,

the focus will center on the design intricacies of the contributing transistors within the

Operational Transconductance Amplifier (OTA).

31
 The initial phase of this design involved determining the bias currents to meet the

specified slew rate requirement. The slew rate is defined by the equation:

I0
SR = (2.9)
CL

Where I0 is the bias current through M0 and CL is the load capacitance. From the SR

and CL specifications, and equation (2.9):

32
 (a) The folded cascode operational transconductance amplifier (OTA)
biased with ideal current sources I0 and IB .

(b) The folded cascode OTA with the ideal current sources replaced wiith
transistors M0 and M9,10 operating in their constant current region.

Figure 2.4: The Folded cascode operational transconductance amplifier topology

33
 I0 = SR · CL = 20
10−6
× 5 × 10−12 = 100µA

I0 100×10−6
This therefore means that ID1,2 = 2
= 2
= 50µA and the current through M3

I0
to M8 , ID3−8 = ID9,10 − 2
. Generally the design is done such that

ID9,10 ≥ I0 (2.10)

For this design, ID9,10 was chosen to be slightly greater than I0 . This was done to ensure

that M5-M8 are always on. So ID9,10 is assigned ID9,10 = 150µA and ID3−8 = ID9,10 − I20 =

(150 − 50)µA = 100µA . Therefore using equation (2.8)

W 2ID9,10 2 × 150 × 10−6

( ) = = = 25
L 9,10 µp Cox Vov9,10 2 48 × 10−6 × 0.52

W 2ID3,4 2 × 100 × 10−6

( ) = = = 66.67
L 3,4 µp Cox Vov3,4 2 48 × 10−6 × 0.252

W 2ID5−8 2 × 100 × 10−6

( ) = = = 6.93
L 5−8 µn Cox Vov3,4 2 180 × 10−6 × 0.42

Gain bandwidth (GBW), fGBW product is given by:

gm1,2
fGBW = (2.11)
2πCL

⇒ gm1,2 = 2π · fGBW · CL (2.12)

34
 Therefore gm1,2 = 2 × π30 × 106 × 5 × 10−12 = 942.5S Using equation (2.7), the sizing

of M1,2 was determined:

2 2
W gm1,2 (942.5 × 10−6 )
( )1,2 = = = 49.35
L 2ID1,2 µn Cox 2 × 50 × 10−6 × 180 × 10−6

Now to determine the voltage biases VB3 , VB5 , VB9 , and VB0 .

VB3 = VDD − Vov4 − Vov10 − |VT p | (2.13)

VB3 = 3.3 − 0.25 − 0.5 − | − 0.79| = 1.612V

VB5 = Vov6 + Vov8 + VT n (2.14)

VB5 = 0.4 + 0.4 + 0.65 = 1.45V

VB9 = VDD − Vov9 − |VT p | (2.15)

VB9 = 3.3 − 0.5 − | − 0.788| = 2.012V

VB0 = Vov0 + VT n (2.16)

VB0 = 0.5 − 0.711 = 1.211V

35
 Finally the input common mode range (Vcm ) and the output swing VOS , were

determined using the equations 2.9 and 2.10 respectively. But the overdrive voltage

of M1,2 was first determined. Equation 2.2 came in handy for this case.

2 · ID1,2 2 × 50 × 10−6
Vov1,2 = = = 108mV
gm1,2 924.5 × 10−6

Then the common mode input range:

Vov1,2 + Vov0 + VT n ≤ Vcm ≤ VDD − Vov9,10 + VT n

0.108 + 0.5 + 0.7 ≤ Vcm ≤ 3.3 − 0.5 + 0.7

1.3V ≤ Vcm ≤ 3.5V

The output swing:

V0v5,6 + Vov7,8 ≤ VOS ≤ VDD − Vov9,10 − Vov3,4

0.4 + 0.4 ≤ VOS ≤ 3.3 − 0.5 − 0.25

0.8V ≤ VOS ≤ 2.55V

2.55+0.8
This implies the optimum output voltage is 2
= 1.675V .

2.3.3 Simulation and results of the OTA

Following several SPICE simulation iterations, the chosen channel lengths (L) for each

transistor in the design are as follows:

36
 - LM 1,2 = 1µm - LM 3,4 = 1µm - LM 5−M 8 = 0.8µm - LM 9,10 = 0.8µm - LM 0 = 2µm

These lengths were selected based on simulation results that closely matched the

desired specifications. Additionally, the lengths were chosen to ensure that the calculated

W
sizing ratios L
of each transistor remained unchanged.

To validate the expected results, three simulations were conducted using Ngspice.

Both Bespice viewer and Ngspice viewer were utilized to visualize the simulation

waveforms. These simulations played a crucial role in verifying the performance and

compliance of the design with the specified requirements.

DC simulation

For the DC analysis, a .op analysis was executed to obtain the DC operating point of each

transistor. In Table 2.5, values of certain large signal variables were calculated manually,

while Table 2.6 presents the values of the same variables generated by the .op analysis.

Upon comparing the corresponding values in both tables, a notable agreement between

hand calculations and SPICE simulation results is observed. It is acknowledged that there

is room for further refinement. Table 2.7 juxtaposes the hand-calculated values with the

SPICE simulation results for the input common mode range and output swing.

This comparative analysis underscores the alignment between theoretical predictions

and practical simulation outcomes, laying the foundation for a robust validation of the

design’s performance characteristics.

37
AC simulation

In Figure 2.5, the AC transfer function of the Operational Transconductance Amplifier

(OTA) is depicted, showcasing both the magnitude and phase plots. Notably, the plot

illustrates that both the gain specification and the phase margin have been successfully

met. The visualization of the AC transfer function provides a comprehensive overview of

the amplifier’s behavior in the frequency domain, confirming its adherence to the desired

performance characteristics.

38
 Table 2.5: Some DC parameter; hand-calculated values

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M0
50µA 50µA 100µA 100µA 100µA 100µA 100µA 100µA 150µA 150µA 100µA

39
ID
VGS 0.9232V 0.9232V 1.0380V 1.0380V 1.111V 1.111V 1.111V 1.111V 1.288V 1.288V 1.211V
VDS,sat 0.106V 0.106V 0.25V 0.25V 0.4V 0.4V 0.4V 0.4V 0.5V 0.5V 0.5V
Gm 0.942mS 0.942mS 0.8mS 0.8mS 0.5mS 0.5mS 0.5mS 0.5mS 0.6mS 0.6mS 0.4mS
 Table 2.6: Some DC parameter; .op simulation results

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M0
ID 51.1µA 51.1µA 84.5µA 84.5µA 84.5µA 84.5µA 84.5µA 84.5µA 136µA 136µA 102µA

40
VGS 1.01V 1.01V 1.28V 1.28V 1.35V 1.35V 1.10V 1.10V 1.29V 1.29V 1.26V
VDS 1.68V 1.68V 1.56V 1.56V 0.377V 0.377V 0.727V 0.727V 0.632V 0.632V 0.990V
VDS,sat 0.102V 0.102V 0.255V 0.255V 0.398V 0.398V 0.370V 0.370V 0.489V 0.489V 0.487V
Gm 0.82mS 0.82mS 0.61mS 0.61mS 0.31mS 0.31‘mS 0.36mS 0.36mS 0.41mS 0.41mS 0.32mS
Table 2.7: Hand calculated values vs. simulation values of the input common
mode range and output swing

Parameter Hand Calculation Simulation

Output Range 0.8V ≤ V ≤ 2.55V 0.87 ≤ V ≤ 2.4V
Input Common Mode Range 1.3V ≤ V ≤ 3.5V —

41
Figure 2.5: Transfer function of the OTA at open loop – Magnitude and phase plot

42
 CHAPTER THREE

SKILLS ACQUIRED AND EXPERIENCE GAINED

During my SIWES, while working on both Digital Signal Processing (DSP) and Analog

IC design, I acquired a diverse set of technical and soft skills, contributing significantly

to my professional development.

My SIWES internship provided a great opportunity to apply concepts learned in key

computer engineering courses. Through hands-on projects in digital signal processing

and analog IC design, I honed critical skills that will serve me well in my career. This

report summarizes the major highlights.

3.1 Skills Acquired

Technical Skills

In DSP, I gained proficiency in generating and analyzing signals using MATLAB and

Python. Implementing techniques like filtering and spectral estimation from scratch gave

strong fundamentals.

Through circuit design using Xschem and ngspice, I developed skills in schematic

capture, simulation, and analog IC analysis. Exposure to the GF180 PDK provided

practical experience with real-world process design kits.

43
 • DSP Expertise: Developed proficiency in DSP techniques, including signal

processing, spectral analysis, and filter design, using tools such as MATLAB.

• Analog IC Design: Gained hands-on experience in designing an operational

transconductance amplifier (OTA) with the folded cascode topology using Xschem

and ngspice.

• Electronic Circuit Simulation: Enhanced skills in using simulation tools like

ngspice for accurate and efficient circuit analysis and verification.

• Programming Languages: Applied programming skills, particularly in MAT-

LAB for DSP applications and scripting languages for automation in circuit design.

Soft Skills

The internship enhanced vital soft skills like problem-solving, perseverance, and attention

to detail. For instance, debugging circuit stability issues and device mismatches required

meticulous simulation and troubleshooting.

Planning projects, tracking progress, and meeting deadlines improved my time

management abilities. Communicating results through reports and presentations polished

my technical writing skills.

• Team Collaboration: Worked collaboratively with interdisciplinary teams,

fostering effective communication and teamwork.

• Problem-Solving: Developed a systematic approach to problem-solving, essential

in addressing challenges encountered in both DSP and analog IC design.

44
 • Adaptability: Navigated through various tasks, demonstrating adaptability to

new tools, methodologies, and project requirements.

• Communication: Improved communication skills through regular reporting,

documentation, and presenting technical information to both technical and non-

technical stakeholders.

3.2 Relevance to Course of Study (Computer Engi-

neering)

The DSP projects reinforced concepts from Signals and Systems (EEE 309) and

Numerical Computation II (CSC 308) which covers MATLAB programming. Designing

circuits complemented Microelectronics Circuit (EEE 301/302) by allowing transistor-

level implementation.

• EEE 301/302 (Microelectronics Circuits): Applied analog IC design principles

and gained practical experience in designing circuits, aligning with the course’s

theoretical foundations.

• EEE 309 (Signals and Systems): Transferred DSP knowledge to real-world

applications, reinforcing the understanding of signal processing concepts and

techniques.

• CSC 308 (Numerical Computation II): Applied numerical computation skills

in circuit analysis and DSP algorithms, aligning with the course’s emphasis on

numerical methods.

45
 • CPE 316 (Introduction to Artificial Intelligence): Explored AI applications

in DSP and analog IC design, recognizing the relevance of AI in optimizing

algorithms and enhancing system intelligence.

3.3 Problems Encountered and Solutions

I encountered issues like high offset voltage due to device mismatches. By introducing

dummy devices, common-centroid layout techniques, and increasing transistor areas, I

was able to minimize mismatches and improve DC accuracy.

The circuit had stability issues and proneness to oscillations. I stabilized the design by

introducing compensation capacitors and improving phase margin. Careful AC analysis

was crucial to identify and resolve these issues.

Device parasitics limited the gain bandwidth product. I re-sized transistors and

optimized biasing to achieve the speed and gain targets.

In DSP projects, issues like noise and non-stationary signals required careful analysis

to select appropriate techniques.

The SIWES internship enabled me to complement classroom theory with practical

experience in DSP algorithm implementation and IC design. This will serve me well in

handling real-world engineering problems. The combination of technical and professional

skills will be invaluable as I start my career.

46
 CHAPTER FOUR

CONCLUSION AND RECOMMENDATIONS

4.1 Conclusion

The SIWES internship at PlethuDeep Hub provided invaluable hands-on experience and

complemented my undergraduate computer engineering coursework.

Through projects in digital signal processing and analog integrated circuit design,

I developed strong technical skills in areas like MATLAB, Python, schematic capture,

circuit simulation and frequency domain analysis.

The troubleshooting, analytical thinking and problem-solving abilities I gained will

serve me well in handling real-world engineering challenges. Communicating results

through reports and presentations enhanced my technical writing and presentation skills.

Adhering to deadlines and processes instilled professional work ethics like time

management, organization and attention to detail. Working alongside experienced

engineers allowed me to observe and learn industry best practices.

Overall, the SIWES internship enabled me to acquire engineering expertise, project

lifecycle exposure and key soft skills that will accelerate my career development.

47
4.2 Recommendations

Based on my experience, here are a few recommendations to improve the SIWES

internship:

• Increase focus on practical hands-on learning through lab sessions, live projects and

industry visits. This will enable students to better apply classroom theory.

• Provide opportunities to work on interdisciplinary projects spanning ECE domains

like power, communications, embedded systems etc. This will give a more holistic

perspective.

• Incorporate more training sessions on professional skills like technical writing, pre-

sentation delivery, project planning etc. These are vital for workplace effectiveness.

• Set up mentoring programs and progress reviews with faculty supervisors. This will

help better monitor student learning.

• Encourage students to document their work through project reports, code samples

etc. This will reinforce technical learning while improving documentation abilities.

By incorporating these suggestions, the SIWES program can provide even more

holistic development of technical talent ready for industry needs. I am grateful for the

experience which has enriched my engineering foundation.

48
 REFERENCES

Geiger, R. L., Allen, P. E., and Strader, N. R. (1985). VLSI design techniques for analog

and digital circuits. McGraw-Hill.

Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G. (2006). Analysis and design of

analog integrated circuits. Wiley.

Johns, D. and Martin, K. (2010). Analog integrated circuit design. Wiley.

Oppenheim, A. V., Schafer, R. W., and Buck, J. R. (1999). Discrete-time signal

processing. Prentice Hall.

Proakis, J. G. and Manolakis, D. K. (2007). Digital signal processing: principles,

algorithms, and applications. Pearson/Prentice Hall.

Sedra, A. S. and Smith, K. C. (2010). Microelectronic circuits. Oxford University Press.

Smith, S. W. (2010). Practical Signal Processing and its Applications With MATLAB

Programming. Newnes.

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