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22320 winter-2022 model answer paper

Digital technology (Government Polytechnic, Nagpur)

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MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

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WINTER – 2023 EXAMINATION

MODEL ANSWER
Subject: Digital Techniques Subject Code: 22320

Important Instructions to examiners:

1) The answers should be examined by key words and not as word-to-word as given
in the model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner
may try to assess the understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more
Importance (Not applicable for subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components
indicated in the figure. The figures drawn by candidate and model answer may
vary. The examiner may give credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the
assumed constant values may vary and there may be some difference in the
candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner
of relevant answer based on candidate’s understanding.
7) For programming language papers, credit may be given to any other program
based on equivalent concept.
8) As per the policy decision of Maharashtra State Government, teaching in
English/Marathi and Bilingual (English + Marathi) medium is introduced at first year
of AICTE diploma Programme from academic year 2021-2022. Hence if the
students in first year (first and second semesters) write answers in Marathi or
bilingual language (English +Marathi), the Examiner shall consider the same and
assess the answer based on matching of concepts with model answer.

Q. Sub Answer Marking

No Q.N. Scheme
1. Attempt any FIVE of the following: 10
a) Write radix of binary, octal, hexadecimal number system 2M
Ans. Number System Radix Correct
Binary 2 answer 2M
Octal 8
Hexadecimal 16
b) State necessity of demultiplexer. 2M
Ans. 1.De-multiplexers are used in applications where there is a necessity Any two
of connecting single source to several destinations. necessity
1M each
2. Used in memory decoding.
3. Data Routing
4. Serial to Parallel converter
5. Communication in TDM, FDM.

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Subject: Digital Techniques Subject Code: 22320

c) Draw symbol and write the truth table for T flip flop 2M
Clk T Qn+1 Remark
0 X Qn Last state
Ans. Symbol 1M
1 0 Qn Last state
Truth table
1 1 Qn' Toggle 1M

d) Compare between synchronous and asynchronous counter. 2M

Ans. SR SYNCHRONOUS ASYNCHRONOUS
NO COUNTER COUNTER
Any two
1. In synchronous counter, all In asynchronous counter, compariso
flip flops are triggered with different flip flops are ns 1M
same clock simultaneously. triggered with different clock, each
not simultaneously.
2. Synchronous Counter is Asynchronous Counter is
faster than asynchronous slower than synchronous
counter in operation. counter in operation.
3. Synchronous Counter is also Asynchronous Counter is also
called Parallel Counter. called Serial Counter.
4. Synchronous Counter Asynchronous Counter
designing as well designing as well as
implementation are complex implementation is very easy.
due to increasing the
number of states.
5. Synchronous Counter will Asynchronous Counter will
operate in any desired count operate only in fixed count
sequence. sequence (UP/DOWN).
6. In synchronous counter, In asynchronous counter,
propagation delay is less. there is high propagation
delay.
7. Synchronous Counter Asynchronous Counter
examples are: Ring examples are: Ripple UP
counter, Johnson counter. counter, Ripple DOWN
counter.

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Subject: Digital Techniques Subject Code: 22320

e) Write gray code to given number (11111)2 – (?)Gray 2M

Ans.
Step 1M
correct
answer 1M

f) State two features of ADC IC0809 2M

Ans. Features of ADC 0809 Any two
i. It operates on 0 to 5V input range with single 5V supply. features
1M each
ii. It does not require external 0 & full scale adjustment.
iii. It has low power consumption. It is 15m watt.
iv. Conversion time is 100μs.
v. It offers high speed of conversion.
vi. High accuracy over wide range minimum temperature
dependence.
vii. The output is TTL compatible.
viii. It is easy to interface with microprocessor.
g) Draw four variable K-map. 2M
Ans. Any one
diagram
with
correct cell
numbers
2M

OR

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Subject: Digital Techniques Subject Code: 22320

2. Attempt any THREE of the following: 12

a) Sketch the given Boolean expression; use one AND gate one OR 4M
gate only Y = AB + AC
Ans. Y=AB+AC Correct
Y = A (B+C) diagram
4M

b) Draw circuit diagram of BCD to seven segment decoder and 4M

write its truth table.
Ans. BCD to 7 segment decoder truth table for common cathode display Truth table
2M

Circuit
diagram
2M

Circuit diagram of BCD to 7 segment decoder

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Subject: Digital Techniques Subject Code: 22320

c) Draw the block diagram of programmable array logic 4M

Ans. Block Diagram of Programmable Array Logic Block
diagram
4M

d) Minimize following expression using K-map 4M

F(A,B,C,D) = Σm (1,5,6,7,11,12,13,15)

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Subject: Digital Techniques Subject Code: 22320

Ans. 2M for
K map

1M for
correct
grouping

1M for
correct
equation

3. Attempt any THREE of the following: 12

a) Realize the following logic operation using only NOR gates: AND, 4M
OR, NOT.

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Subject: Digital Techniques Subject Code: 22320

NOT gate
1M

AND gate
1.5M
Ans.
OR gate
1.5M

b) Describe the operation of 4bit serial in serial out shift register 4M

Ans. Diagram :(use SR or JK or D type flip flop)
Diagram
2M

Working
2M

Working:
The DATA leaves the shift register one bit at a time in a serial
pattern, hence the name Serial-in to Serial-Out Shift Register or
SISO.

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Subject: Digital Techniques Subject Code: 22320

The SISO shift register is one of the simplest of the four

configurations as it has only three connections, the serial input (SI)
which determines the input, the serial output (SO) which is the output
of the flip-flop and the sequencing clock signal (Clk). The logic
circuit diagram below shows a generalized serial-in serial-out shift
register, Output of FFA is Q4, FFB Q3, FFC Q2 and FFD is Q1.

c) Calculate the analog output of 4bit DAC if the digital input is 4M

1101.Assume VFS=5V
Ans.
Formula
1M

Calculatio
n 3M

d) Describe the working of SR flipflop with its truth table and logic 4M
diagram

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Subject: Digital Techniques Subject Code: 22320

Ans.
Diagram
1M

Truth table
1M

Working
2M

When clock = 0, the outputs of NAND gates 3 and 4 will be forced to

be 1 irrespective of the values of S and R. That means R’= S’ = 1.
Hence the outputs of basic SR i.e. No change Thus if clock = 0, then
there is no change in the output of the clocked SR flip-fl
Case I: S = R = 0, clock = 1: No change
If S=R=0 then outputs of NAND gate 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since R' and S' are the inputs
of the basic S – R flipflop using NAND gates. There will be no
change in the state of outputs.
Case II: S =1, R = 0, clock = 1: Set
Now S=0, R=1 and a positive going edge is applied to the clock
Output of NAND 3 i.e. R’ = 0 and output of NAND 4 i.e. S’ = 1.
Hence output of SR flip-flop is Q n+1 = 1 and Q’n+1 = 0. This is the
set condition.

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Case III: S =0, R = 1, clock = 1: Reset

Now S=0, R=1 and a positive edge is applied to the clock input. Since
S=0, output of NAND – 3 i.e. R´= 1. And as R’ = 1 and clock = 1 the
output of NAND-4 i.e. S´ = 0. Hence output of SR flip-flop is Q n+1
= 0 and Q’n+1= 1. This is the reset condition.
Case IV: S =1, R = 1, clock = 1: Undefined/ forbidden
As S=1, R=1 and clock = 1, the outputs of NAND gates 3 and 4 both
are 0 i.e. S' = R'=0. So both the outputs Q n+1 = 1 and Q’n+1. Hence
output is Undefined/ forbidden.
4. Attempt any THREE of the following: 12
a) Draw symbol ,Truth table and logical output equation of OR and 4M
Ex-OR gate
Ans. OR gate
Symbol &
Logical
Equation
1M

Truth
Table 1M

EX-OR
Symbol &
Logical
Equation
1M

Truth
Table 1M

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Subject: Digital Techniques Subject Code: 22320

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Subject: Digital Techniques Subject Code: 22320

b) Describe function of Full adder circuit with its truth table and 4M
Logical diagram
Ans. A full adder is a combinational logic circuit that performs addition
between three bits, the two input bits A and B, and carry C from the Full adder
previous bit. The output carry is designated as Cout and the normal 1M
output is designated as S which is SUM. Truth table
1M

Sum &
Carry
derivations
1M

Logical
diagram
1M

Based on the truth table, the Boolean functions for Sum (S) and Carry
(Cout) can be derived using K – Map.
For Sum S:

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Subject: Digital Techniques Subject Code: 22320

For Carry (COUT)

COUT=AB+ACin+BCin

Logical Diagram
(Note: Logic Diagram using basic or universal gate also can be
consider)

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Subject: Digital Techniques Subject Code: 22320

c) Design 16:1 multiplexer using 4:1 multiplexer 4M

Ans.
Correct
design 4M

d) Describe working of Master-slave JK flipflop with truth table and 4M

logic diagram
Ans.  The master slave JK flip flop is a combination of a clocked JK
latch and a clocked SR latch. The clocked JK latch acts as the
master and the clocked SR latch acts as the slave.
 Master is positive level triggered and due to the presence of an
inverter in the clock line, the slave is negative level edge triggered.
Hence when clock=1, the master is active and slave is inactive.
Vice versa happens when clock=0.

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Subject: Digital Techniques Subject Code: 22320

Working
1M

Diagram
2M

Truth table
1M

Case I: When clock is not given, both master and slave are inactive
and there will be no change in outputs.
Case II: For clock=1, master is active, slave inactive. As J=K=0,
output of master i.e. Q and Q' will not change. As soon as clock goes
to 0, slave becomes active, and master inactive. But since input to
slave S and R is same, output of slave will also remain same.
Case III: For clock=1, master is active and slave is inactive. When
J=0 and K=1, outputs of master will be Q=0, Q'=1, which will be
inputs to slave. When clock=0, slave becomes active and takes inputs
0, 1 to give output Q=0, Q'=1. This output will not change if clock is
again made 1and then 0. Hence we get a stable output from master
and slave.
Case IV: For clock=1, master is active and slave is inactive. When
J=1 and K=0, outputs of master will be Q=1, Q'=0, which will be
inputs to slave. When clock=0, slave becomes active and takes inputs
1, 0 to give output Q=1, Q'=0. This output will not change if clock is
again made 1 and then 0. Hence we get a stable output from master
and slave.
Case V: When clock =1, J=K=1, master output will toggle. So S and
R will invert. But slave remains inactive all this time since clock is 1.
As soon as clock becomes 0, slave becomes active and master
becomes inactive. So slave will also toggle. These changed outputs
are returned through feedback to the master, but master does not
respond to them because clock is now 0 and master is inactive. Thus,
in one clock period, master and slave both toggles only once, 1
avoiding race condition caused by multiple toggling.

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Subject: Digital Techniques Subject Code: 22320

Truth Table

e) Compare between R-2R Ladder DAC and weighted resistor DAC 4M

(Four points) Any four
relevant
points 1M
Ans. R-2R Ladder DAC Weighted resistor DAC each
It requires resistor of only It requires more than two
two values namely R and 2R. resistor values.
It can be easily expanded to It is not possible to extend.
handle more number of bits
by adding resistors.
It requires only one resistor It requires two resistors per
per bit. bit.
Accuracy and Stability is Accuracy and Stability
high. depends on the accuracy of
resistor used.

5. Attempt any TWO of the following: 12

a) Explain 3bit asynchronous counter with output waveforms 6M

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Subject: Digital Techniques Subject Code: 22320

Ans.

Circuit
Diagram
2M

Waveform
2M

Explanatio
n 1M
In an asynchronous counter, a clock pulse drives FF0. Output of FF0 Truth table
drives FF1 which then drives the FF2 flip flop. All J and K inputs are 1M
connected to Logic 1. Therefore, each flip flop will toggle with
negative transition at its clock input.
The 3 bit asynchronous counter consists of 3 JK flip flops. Initially all
flip flops are reset to produce 0. The output condition is Q2Q1Q0 =
000.
When the first clock pulse is applied, the FF0 changes state on its
negative edge. Therefore, Q2Q1Q0 = 001. On the negative edge of
the second clock pulse flip flop FF0 toggles. Its output changes from
1 to 0. This being a negative change, FF1 changes state. Therefore,
Q2Q1Q0 = 010. Similarly, the output of flipflop FF2 changes only
when there is negative transition at its input when the fourth clock
pulse is applied.

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Subject: Digital Techniques Subject Code: 22320

b) Compare following (Any three points) 6M

i) RAM with ROM memory.
ii) EPROM with EEPROM memory.
Ans. i) RAM and ROM memory
Parameter RAM ROM Any three
relevant
Definition RAM stands for Random ROM stands for Read points for
Access Memory. Only Memory. Compariso
n of RAM
& ROM
Data RAM data is volatile. Data ROM data is permanent. 3M
Retention is present till power Data remains even after
supply is present. power supply is not
present.

Data RAM data can be read, ROM data is read only.

Access erased or modified.

Usage RAM is used to store data ROM is used to store data

that the CPU needs for that is needed to bootstrap
current instruction the computer.
processing.

Speed RAM speed is quite high. ROM speed is slower than

RAM.

CPU The CPU can access data Data to be copied from

Access stored on RAM. ROM to RAM so that the
CPU can access its data.

Capacity RAM memory is large and ROM is generally small

high capacity. and of low capacity.

Usage RAM is used as CPU ROM is used as firmware

Cache, Primary Memory. by microcontrollers.

Cost RAM is costly. ROM is cheap.

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Subject: Digital Techniques Subject Code: 22320

ii) EPROM and EEPROM

Any three
Parameter EPROM EEPROM relevant
points for
Compariso
Techniques used Exposure to UV A voltage of 20 to 25 V is n of
for erasing light applied EPROM
and
Selective erasing Not possible . All Possible. A particular EEPROM
locations get location can be erased 3M
erased

Time required Long . 10 to 15 Short 10 msec

for erasing mins

Need to remove Necessary Not necessary

PROM from
circuit

Cost Less expensive Very expensive

c) Convert the following. 6M

i) (6AC)16 : ( ? )10
ii) (2003)10-: ( ? )16 2M for
iii) (228)10: ( ? )BCD each
conversion
Ans. i) (6AC ) 16 into () 10
= 6*16^2 + 10 *16^1 + 12 * 16^ 0
= 1536 + 160 + 12
= 1708
ii) (2003)10-: (?)16

Operation Quotient Remainder

2003/16 125 3
125/16 7 13
7/16 0 7
=7C3
iii) (228)10: (?)BCD
= 0010 0010 1000

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Subject: Digital Techniques Subject Code: 22320

6. Attempt any TWO of the following: 12

a) Give the block schematic of decade counter IC 7490 Design mod- 6M
7 counter using IC
Ans.
Block
schematic
2M

Mod
counter
1M

K-map 1M

Circuit
2M

Mod Counter
QD QC QB QA Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

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Subject: Digital Techniques Subject Code: 22320

Y= QAQBQC+QD

b) Design a four bit BCD adder using IC-7483 and NAND gate only. 6M
Ans. The 4-bit binary adder IC (7483) can be used to perform addition of
BCD numbers. Descriptio
n 1M
In this, if 4- bit sum output is not a valid BCD digit, or if carry C3 is
generated, then decimal 6 (0 1 1 0) is to be added to the sum to get
the correct result.

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Subject: Digital Techniques Subject Code: 22320

Truth table
1M

K-Map 1M

Diagram
3M

Y=S3S2+S3S1

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MODEL ANSWER
Subject: Digital Techniques Subject Code: 22320

c) Draw the circuit and explain the principle of TTL gate with totem 6M
pole output
Ans. Totem Pole means the addition of an active pull up circuit in the Principle
output of the Gate which results in a reduction of propagation delay. 1M
TTL NAND Gate
Diagram
3M

Explanati
on 2M

In the TTL NAND gate applying a logic '1' input voltage to both
emitter inputs of T1 reverse-biases both base-emitter junctions,
causing current to flow through R1 into the base of T2, which is
driven into saturation.
When T2 starts conducting, the stored base charge of T3 dissipates
through the T2 collector, driving T3 into cut-off.
On the other hand, current flows into the base of T4, causing it to
saturate and pull down the output voltage Vo to logic '0', or near
ground.
T3 is in cut-off, no current will flow from Vcc to the output, keeping
it at logic '0'.
T2 always provides complementary inputs to the bases of T3 and T4,
such that T3 and T4 always operate in opposite regions, except during
momentary transition between region S
On the other hand, applying a logic '0' input voltage to at least one
emitter input of T1 will forward-bias the corresponding base-emitter
junction, causing current to flow out of that emitter.

This causes the stored base charge of T2 to discharge through T1,

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Subject: Digital Techniques Subject Code: 22320

driving T2 into-cut-off.

T2 is in cut-off, current from Vcc will be diverted to the base of T3

through R3, causing T3 to saturate.
The base of T4 will be deprived of current, causing T4 to go into cut-
off. With T4 in cut-off and T3 in saturation, the output Vo is pulled
up to logic '1', or closer to Vcc.
Outputs of different TTL gates that employ the totem-pole
configuration must not be connected together since differences in
their output logic will cause large currents to flow from the logic '1'
output to the logic '0' output, destroying both output stages.

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