CSCI2510 Computer Organization

Lecture 10: Basic Processing

Unit

Ming-Chang YANG
mcyang@[Link]

Reading: Chap. 7.1~7.3 (5th Ed.)

Basic Functional Units of a Computer

Registers
Input

Arithmetic and
Memory
Logic Unit

Output
Control

I/O Processor / CPU

• Input: accepts coded information from human operators.
• Memory: stores the received information for later use.
• Processor: executes the instructions of a program stored in the memory.
• Output: sends back to the outside world.
• Control: coordinates all of these actions.
CSCI2510 Lec10: Basic Processing Unit 2
Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization

CSCI2510 Lec08: Cache Performance 3

Basic Processing Unit: Processor
• Executes machine-language instructions.
• Coordinates other units in a computer system.
• Often be called the central processing unit (CPU).
– The term “central” is no longer appropriate today.
– Today’s computers often include several processing units.
• E.g., multi-core processor, graphic processing unit (GPU), etc.

CSCI2510 Lec10: Basic Processing Unit 4

Main Components of a Processor

Register file: a
memory unit for the Control circuitry:
Control
processor’s general- Register Interpret or decode the
purpose registers circuitry fetched instruction
file
(GPRs)

IR: Hold the instruction

until its execution is
IR completed
(special purpose register)
Arithmetic and Logic Instruction
Unit (ALU): Perform address
ALU PC: Keep track of the
an arithmetic or logic generator address of the next
operation
instruction to be fetched
PC and executed
(special purpose register)

Processor–memory interface

Processor-memory interface: Allow the

communication between processor and memory

CSCI2510 Lec10: Basic Processing Unit 5

Processor Internal: Internal Bus (1/2)
• Internal Processor Bus: Internal processor
bus Control
– ALU, control circuitry, signals
…
PC
and all the registers are Instruction
Address
decoder
interconnected via a lines
&
MAR
single common bus. External control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 6

Processor Internal: Internal Bus (2/2)
• Internal Processor Bus: Internal processor
bus Control
– The common bus is signals
…
PC
internal to the processor. Instruction
Address
decoder
• i.e., only visible to the lines
&
MAR
processor. External control logic
memory
– Black parts: data path bus
MDR
Data
– Blue parts: control path lines
IR

Y R0
Constant 4 R1
• External Memory Bus: Select MUX R2

– Brown part: external Add

A B
R3
ALU

…
Sub
memory path (NOT control ALU
…

lines Carry Rn-1

internal processor bus!) XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 7

Processor Internal: External Bus (1/2)
• External Memory Bus: Internal processor
bus Control
– Processor-memory signals
…
PC
interface: External Instruction
Address
decoder
memory bus are lines
&
MAR
controlled through External output input control logic
memory
MAR and MDR. bus
MDR
Data IR
– MAR: Specify the lines
Y R0
requested memory Constant 4 R1
address
R2
• Input: Address is Select MUX
R3
specified by processor via Add
ALU A B

…
Sub
internal processor bus. control ALU
…

• Output: Address is send lines Carry Rn-1

XOR in
to the memory via
external memory bus. Z TEMP

CSCI2510 Lec10: Basic Processing Unit 8

Processor Internal: External Bus (2/2)
• External Memory Bus: Internal processor
bus Control
– MDR: Keep the content signals
…
PC
of the requested Instruction
Address
decoder
memory address lines
&
MAR
• There are two inputs and External control logic
memory two two
two outputs for MDR. bus outputs inputs
MDR
• Inputs: Data may be Data IR
lines
placed into MDR either
Y R0
– From the internal Constant 4 R1
processor bus or
R2
– From the external Select MUX
memory bus. R3
Add
ALU A B

…
• Outputs: Data stored in control
Sub
ALU
…

MDR may be loaded lines Carry Rn-1

XOR in
from either bus.
Z TEMP

CSCI2510 Lec10: Basic Processing Unit 9

Processor Internal: Register (1/2)
• General-Purpose Internal processor
bus Control
Registers: signals
…
PC
– R0 through Rn-1 Address
Instruction
decoder
• n varies from one lines
MAR &
processor to another. External control logic
memory
bus
• Special Registers:
MDR
Data IR
lines
– Program Counter Y R0
• Keep track of the address Constant 4 R1
of the next instruction to Select MUX R2
be fetched and executed. R3
Add
A B
– Instruction Register ALU

…
Sub
control ALU
…

Rn-1
• Hold the instruction until lines
XOR
Carry
in
the current execution is
Z TEMP
completed.
CSCI2510 Lec10: Basic Processing Unit 10
Processor Internal: Register
• Special Registers: Internal processor
bus Control
Y, Z, & TEMP signals
…
PC
– Transparent to the Address
Instruction
decoder
programmer. lines
MAR &
External control logic
– Used by the processor memory
bus
for temporary storage Data
MDR
IR
during execution of lines

some instructions. Y R0
Constant 4 R1
– Never used for storing R2
Select MUX
data generated by one R3
Add
instruction for later use ALU A B

…
Sub
control ALU
by another instruction.
…

lines Carry Rn-1

XOR in
– We will introduce their
Z TEMP
functionalities later.
CSCI2510 Lec10: Basic Processing Unit 11
Processor Internal: Control Circuitry
• Instruction decoder: Internal processor
bus Control
– Interpret the fetched signals
…
PC
instruction stored in the Instruction
Address
decoder
IR register. lines
&
MAR
External control logic
• Control logic: memory
bus
MDR
– Issue control signals to Data
lines
IR

control the all the units Y R0

inside the processor. Constant 4 R1

• E.g., ALU control lines, Select MUX R2

select signal for MUX, Add

R3
carry-in for ALU, etc. ALU A B

…
Sub
control ALU
…

– Interact with the lines

XOR
Carry Rn-1
in
external memory bus.
Z TEMP

CSCI2510 Lec10: Basic Processing Unit 12

Processor Internal: Internal Bus
• Arithmetic and Logic Internal processor
bus Control
Unit (ALU): signals
…
PC
– Perform arithmetic or Address
Instruction
decoder
logic operation lines
MAR &
External control logic
Z = A operator B memory
bus
• Two inputs A and B MDR
Data IR
• One output to register Z lines
Y R0

• Multiplexer (MUX): Constant 4 R1

R2
– The input A of ALU: Select MUX
R3
Add
Select (ctrl line) either ALU A B

…
Sub
• The output of register Y orcontrol ALU
…

lines Carry Rn-1

• A constant value 4 (for XOR in

incrementing PC). Z TEMP

CSCI2510 Lec10: Basic Processing Unit 13

Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization

CSCI2510 Lec08: Cache Performance 14

Recall: Register Transfer Notation
• Register Transfer Notation (RTN) describes the data
transfer from one location in computer to another.
– Possible locations: memory locations, processor registers.
• Locations can be identified symbolically with names (e.g. LOC).

Ex.
R2 ← [LOC]
– Transferring the contents of memory LOC into register R2.

 Contents of any location: denoted by placing

square brackets [ ] around its location name (e.g. [LOC]).
 Right-hand side of RTN: always denotes a value
 Left-hand side of RTN: the name of a location where the
value is to be placed (by overwriting the old contents)
CSCI2510 Lec04: Machine Instructions 15
Instruction Execution (1/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
MAR &
to by PC, and load into IR External control logic
memory
– PC  [PC]+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control
– Decode instruction in IR ALU
…

lines Carry Rn-1

XOR in
– Perform the operation(s)
Z TEMP

CSCI2510 Lec10: Basic Processing Unit 16

Instruction Execution (2/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
MAR &
to by PC, and load into IR External control logic
memory
– PC  [PC]+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control
– Decode instruction in IR ALU
…

lines Carry Rn-1

XOR in
– Perform the operation(s)
Z TEMP

CSCI2510 Lec10: Basic Processing Unit 17

Instruction Execution (3/3)
1) Fetch Phase Internal processor
bus Control
– IR  [[PC]] signals
…
PC
• Fetch the contents of the Instruction
Address
memory location pointed lines
decoder
MAR &
to by PC, and load into IR External control logic
memory
– PC  PC+4 bus
MDR
• Increment the contents of Data IR
lines
PC by 4.
Y R0
– Why 4? Instruction is 32 Constant 4 R1
bits (4B) and memory is
byte addressable. Select MUX R2
R3
2) Execute Phase ALU
Add
A B

…
Sub
control
– Decode instruction in IR ALU
…

lines Carry Rn-1

XOR in
– Perform the operation(s)
Z TEMP

CSCI2510 Lec10: Basic Processing Unit 18

Instruction Execution: Execute Phase
• An instruction can be executed by performing one or
more of the following operation(s):
1) Transfer data from a register to another register
or to the ALU
2) Perform arithmetic (or logic) operations and
store the result into the special register Z
3) Load content of a memory location to a register
4) Store content of a register to a memory location

• Sequence of Control Steps: Describes how these

operations are performed in processor step by step.

CSCI2510 Lec10: Basic Processing Unit 19

1) Register Transfer
• Input and output of Internal processor
bus Control
register Ri are controlled signals
…
PC
by switches ( ): Address
Instruction
decoder
– Ri-in: Allow data to be lines
MAR &
External control logic
transferred into Ri memory
bus
MDR
Data IR
Ri-in lines
Y R0
Ri Constant 4 R1

Select MUX R2
Ri-out R3
Add
ALU A B

…
Sub
– Ri-out: Allow data to be control ALU
…

lines Carry Rn-1

transferred out from Ri XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 20

1) Register Transfer (Cont’d)
• Ex: R3  [R1] Internal processor
bus Control
 Clock 1: R1-out, R3-in signals
…
PC
• Set R1-out to 1 Instruction
Address
decoder
• Set R3-in to 1 lines
&
MAR
• Set all others to 0 External control logic
memory
 Clock 2: bus
MDR
Data IR
• Reset R1-out to 0 lines
• Reset R3-in to 0 Y R0
Constant 4 R1
Sequence of Steps: R2
Select MUX
 R1-out, R3-in Add
R3
ALU A B

…
Sub
Note: Only state “sets” for short. control ALU
…

lines Rn-1
• Recall: Clock Cycle XOR
Carry
in

Z TEMP

Clock
CSCI2510 Lec10: Basic Processing Unit 21
 Student ID: Date:
Class Exercise 10.1 Name:

• What is the sequence Internal processor

bus Control
of steps for the signals
…
PC
following operation? Address
Instruction
decoder
R1  [R3] External
lines
MAR &
control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 22

2) Arithmetic or Logic Operation
• ALU: A circuit without Internal processor
bus Control
storage to manipulate data. signals
…
PC
– Two inputs: from A & B Address
Instruction
decoder
• A: #4 or register Y lines
MAR &
External control logic
• B: Any other register memory
– ALU: Perform operation bus
Data
MDR
IR
– One output: to register Z lines
Y R0
• Ex: R3  [R1] + [R2] Constant 4 R1
R2
Sequence of Steps: Select MUX
R3
 R1-out, Y-in
Add
ALU A B

…
Sub
control ALU
…

 Select-Y, R2-out, lines

XOR
Carry
in
Rn-1

B-in, Add, Z-in Z TEMP

 Lec10:
CSCI2510 Z-out, R3-in Unit
Basic Processing 24
2) Arithmetic or Logic Operation (Cont’d)
• Ex: R3  [R1] + [R2]

 R1-out, Y-in  Select-Y  Z-out, R3-in

R2-out, B-in,
CSCI2510 Lec10: Basic Processing Unit Add, Z-in 25
Class Exercise 10.2
• What is the sequence Internal processor
bus Control
of steps for the signals
…
PC
following operation? Address
Instruction
decoder
R6  [R4] – [R5] External
lines
MAR &
control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 26

Recall: Processor-Memory Interface
• Data transferring takes place through MAR and MDR.
– MAR: Memory Address Register
– MDR: Memory Data Register
k-bit
Processor address bus Memory
(byte-addressable)
MAR Up to 2k addressable
memory locations
n-bit
data bus (unit: word)
MDR Word length =n bits

Control lines
( R / W , MFC, etc.)
*MFC (Memory Function Completed): Indicating the
requested operation has been completed.
CSCI2510 Lec06: Memory Hierarchy 28
Recall: Assembly-Language Notation
• Assembly-Language Notation is used to represent
machine instructions and programs.
– An instruction must specify an operation to be performed
and the operands involved.
– Ex. The instruction that causes the transfer from memory
location LOC to register R2:
Load R2, LOC
Some machines may put
Load: operation; destination last:
LOC: source operand; operation src, dest
R2: destination operand.

– Sometimes operations are defined by using mnemonics.

• Mnemonics: abbreviations of the words describing operations
• E.g. Load can be written as LD, Store can be written as STR or ST.
CSCI2510 Lec04: Machine Instructions 29
3) Loading Word from Memory
• MAR: Memory Address
Register MAR-in
– Uni-directional bus () MAR
– Connect to the address
lines directly
External
memory bus
(address lines)

• MDR: Memory Data MDR-outE MDR-out

Register
– Bi-directional bus () MDR

– MDR connections to
buses are all controlled MDR-inE MDR-in
External
by switches ( ). memory bus
Internal
processor bus
(data lines)
CSCI2510 Lec10: Basic Processing Unit 30
3) Loading Word from Memory (Cont’d)
• Ex: Mov R2, (R1) Internal processor
bus Control
signals
Sequence of Steps: PC
…
R/W
 R1-out, MFC
(Control lines) Instruction
decoder
External &
MAR-in, memory Addr
MAR
control logic
bus lines
Read (start to load a MDR
word from memory) Data
lines
IR

Y R0
 MDR-inE, Constant 4 R1

WaitMFC (wait until the Select MUX R2

R3
loading is completed) Add
A B
ALU

…
Sub
control ALU
…

Rn-1
 MDR-out, lines
XOR
Carry
in

R2-in Z TEMP

CSCI2510 Lec10: Basic Processing Unit 31

3) Loading Word from Memory (Cont’d)
• Timing Sequence: Step 1 2 3
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
 R1-out (not shown), Clock

MAR-in, MARin

Read (start to read

Address bits appear on Address Bus (MAR content)
a word from memory) Address
=== assume memory Read

read takes 3 cycles === Memory

 MDR-inE, Read
(MR)
MDRinE
WaitMFC (wait
until the loading is Data Data bits

completed)
MFC

 MDR-out,
MDR out
R2-in (not shown)
CSCI2510 Lec10: Basic Processing Unit 32
Class Exercise 10.3
• What is the sequence Internal processor
bus Control
of steps for the signals
…
PC
following operation? Address
Instruction
decoder
lines
Mov R4, (R3) External
MAR &
control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 33

4) Storing Word to Memory
• This operation is similar Internal processor
bus Control
to the previous one. PC signals
…
• Ex: Mov (R1), R2 R/W
MFC
(Control lines) Instruction
decoder
External &
Sequence of Steps: memory Addr
MAR
control logic
bus lines
 R1-out, MDR
Data IR
MAR-in lines
Y R0

 R2-out, MDR-in, Constant 4 R1

R2
Write (start to store a Select MUX
R3
word into memory) ALU
Add
A B

…
Sub
control ALU
…

Rn-1
 MDR-outE, lines
XOR
Carry
in

WaitMFC (wait until the Z TEMP

storing is completed)
CSCI2510 Lec10: Basic Processing Unit 35
Class Exercise 10.4
• What is the sequence Internal processor
bus Control
of steps for the signals
…
PC
following operation? Address
Instruction
decoder
lines
Mov (R3), R4 External
MAR &
control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 36

Loading Word vs Storing Word
• Loading Word • Storing Word
• Ex: Mov R2, (R1) • Ex: Mov (R1), R2
 R1-out,  R1-out,
MAR-in, MAR-in
Read

 MDR-inE,  R2-out,
WaitMFC MDR-in,
Write

 MDR-out,  MDR-outE,
R2-in WaitMFC

CSCI2510 Lec10: Basic Processing Unit 38

Revisit: Fetch Phase
• Fetch Phase: The first phase of Internal processor
bus Control
machine instruction execution signals
…
PC
– IR  [[PC]] Address
Instruction
decoder
• Fetch the instruction lines
MAR &
from the memory External control logic
memory
location pointed to by PC, bus
MDR
and load it into IR Data IR
lines
– PC  [PC]+4 Y R0
• Increment the contents Constant 4 R1
of PC by 4 Select R2
MUX

• What is the sequences Add

A B
R3
ALU

…
Sub
of steps for the fetch control ALU
…

lines Carry Rn-1

phase with the highest XOR in

parallelism? Z TEMP

CSCI2510 Lec10: Basic Processing Unit 39

Fetch Phase (1/3)
• Ex: Fetch Phase Internal processor
bus Control
signals
Sequence of Steps: PC
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External &
Select-4, B-in, memory Addr
MAR
control logic
bus lines
Z-in, Add MDR
– Fetch the instruction IR

– Increment PC in parallel Y R0
Constant 4 R1
 MDR-inE, WaitMFC Select MUX R2
Z-out, PC-in, Y-in Add
R3
ALU A B

…
– Y-in is for branch control
Sub
ALU
…

lines Rn-1
(discuss later). XOR
Carry
in

 MDR-out, IR-in Z TEMP

CSCI2510 Lec10: Basic Processing Unit 40

Fetch Phase (2/3)
• Ex: Fetch Phase Internal processor
bus Control
signals
Sequence of Steps: PC
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External &
Select-4, B-in, memory Addr
MAR
control logic
bus lines
Z-in, Add MDR
– Fetch the instruction IR

– Increment PC in parallel. Y R0
Constant 4 R1
 MDR-inE, WaitMFC Select MUX R2
Z-out, PC-in, Y-in Add
R3
ALU A B

…
– Y-in is for branch control
Sub
ALU
…

lines Rn-1
(discuss later). XOR
Carry
in

 MDR-out, IR-in Z TEMP

CSCI2510 Lec10: Basic Processing Unit 41

Fetch Phase (3/3)
• Ex: Fetch Phase Internal processor
bus Control
signals
Sequence of Steps: PC
…
R/W
 PC-out, MAR-in, Read MFC
(Control lines) Instruction
decoder
External &
Select-4, B-in, memory Addr
MAR
control logic
bus lines
Z-in, Add MDR
– Fetch the instruction IR

– Increment PC in parallel. Y R0
Constant 4 R1
 MDR-inE, WaitMFC Select MUX R2
Z-out, PC-in, Y-in Add
R3
ALU A B

…
– Y-in is for branch control
Sub
ALU
…

lines Rn-1
(discuss later). XOR
Carry
in

 MDR-out, IR-in Z TEMP

CSCI2510 Lec10: Basic Processing Unit 42

Observations and Insights
• The internal processor bus and the external memory
bus can be operated independently (concurrently).
– Since the separation provided by MAR and MDR.

• Independent operations imply the possibility of

performing some steps in parallel.
– E.g., memory access and PC increment, instruction
decoding and reading source register

• During memory access, processor waits for MFC.

– There is NOTHING TO DO BUT WAIT for few cycles.
– Question: Any way to improve this situation?

CSCI2510 Lec10: Basic Processing Unit 43

Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization

CSCI2510 Lec08: Cache Performance 44

Example 1) ADD R1, (R3) (1/3)
• Instruction Execution: Fetch Phase & Execute Phase
Sequence of Steps:
1) Fetch the instruction  PC-out, MAR-in, Read
Select-4, B-in, Z-in, Add
 MDR-inE, WaitMFC
Z-out, PC-in, Y-in
 MDR-out, IR-in
2) Decode the instruction  DecodeInstruction
3) Load the operand [R3]  R3-out, MAR-in, Read
from memory  R1-out, Y-in, MDR-inE,
WaitMFC
4) Perform the addition  MDR-out, SelectY, Add, Z-in,
B-in
5) Store
CSCI2510 Lec10:result to R1Unit
Basic Processing  Z-out, R1-in 45
Example 1) ADD R1, (R3) (2/3)
Sequence of Steps: Internal processor
bus Control
 PC-out, MAR-in, Read PC signals
…
Select-4, B-in, Z-in, Add R/W
(Control lines) Instruction
MFC decoder
 MDR-inE, WaitMFC External
MAR &
memory Addr control logic
Z-out, PC-in, Y-in bus lines
 MDR-out, IR-in MDR
IR
 DecodeInstruction
Y R0
 R3-out, MAR-in, Read Constant 4 R1
 R1-out, Y-in, MDR-inE, Select MUX R2

WaitMFC Add
R3
ALU A B

…
 MDR-out, SelectY, Add,
Sub
control ALU
…

lines Carry Rn-1

Z-in, B-in XOR in

 Z-out, R1-in Z TEMP

CSCI2510 Lec10: Basic Processing Unit 46

Example 1) ADD R1, (R3) (3/3)
• Detailed Explanation for Sequence of Steps:
 PC loaded into MAR, read request to memory,
MUX selects 4, added to PC (B-in) in ALU, store sum in Z
 Z moved to PC (and Y) while waiting for memory
 Word fetched from memory and loaded into IR
 Instruction Decoding: Figure out what the instruction
should do and set control circuitry for steps 4 – 7
 R3 transferred to MAR, read request to memory
 Content of R1 moved to Y while waiting for memory
 Read operation completed, the loaded word is already in
MDR and copied to B-in of ALU, SelectY as second input
of ALU, add performed
 Result is transferred to R1
CSCI2510 Lec10: Basic Processing Unit 47
Example 2) Branch Instruction (1/2)
• Instruction Execution: Fetch Phase & Execute Phase
Sequence of Steps:
1) Fetch the instruction  PC-out, MAR-in, Read
Select-4, B-in, Z-in, Add
 MDR-inE, WaitMFC
Z-out, PC-in, Y-in
 MDR-out, IR-in
2) Decode the instruction  DecodeInstruction
3) Add the offset specified  Offset-field-of-IR-out,
in the instruction (Offset- SelectY, Add, Z-in, B-in
field-of-IR) to the PC
4) Update the PC  Z-out, PC-in
CSCI2510 Lec10: Basic Processing Unit 48
Example 2) Branch Instruction (2/2)
Sequence of Steps: Internal processor
bus Control
 PC-out, MAR-in, Read PC signals
…
Select-4, B-in, Z-in, R/W
(Control lines) Instruction
MFC decoder
Add External
memory MAR &
Addr control logic
 MDR-inE, WaitMFC bus lines

Z-out, PC-in, Y-in MDR

IR offset

 MDR-out, IR-in Y R0

 DecodeInstruction Constant 4 R1
R2
 Offset-field-of-IR-out,
Select MUX
R3
Add
SelectY, Add, Z-in, B-in ALU A B

…
Sub
control ALU
 Z-out, PC-in
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 49

 Student ID: Date:
Class Exercise 10.5 Name:

• What is the sequence Internal processor

bus Control
of steps for the signals
…
PC
following operation? Address
Instruction
decoder
R6  [R4] + [R5] External
lines
MAR &
control logic
memory
bus
MDR
Data IR
lines
Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 50

Class Exercise 10.6
• What are the purposes Internal processor
bus Control
or functionalities of the PC signals
…
special registers Y, Z, R/W
(Control lines) Instruction
MFC decoder
and TEMP? External
memory MAR &
Addr control logic
bus lines
MDR
IR

Y R0
Constant 4 R1

Select MUX R2
R3
Add
ALU A B

…
Sub
control ALU
…

lines Carry Rn-1

XOR in

Z TEMP

CSCI2510 Lec10: Basic Processing Unit 52

Outline
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization

CSCI2510 Lec08: Cache Performance 54

Multiple Internal Buses (1/2)
• Disadvantage of single bus:
Bus A Bus B Bus C

Incrementer

Only one data item can be PC

transferred internally at a time.

• Solution: Multiple Internal Buses
Register
file

– All registers combined into a Constant 4

register file with 3 ports

MUX
A

• TWO out-ports and ONE in-port (Why ALU R

B
3? Instruction format!).
– Buses A and B allow simultaneous Instruction
decoder

transfer of the two operands for

IR
the ALU.
MDR
– Bus C can transfer data into a third
register during the same clock MAR

cycle. Memory b us Address

data lines lines
CSCI2510 Lec10: Basic Processing Unit 55
Multiple Internal Buses (2/2)
• Solution: Multiple Internal Buses
Bus A Bus B Bus C

Incrementer

– ALU is able to just pass one of its PC

operands to output R
• E.g. R=A or R=B Register
file

Constant 4

– Employ an additional “Incrementer”

MUX
A
unit to compute [PC]+4 (IncPC) ALU R

• ALU is not used for incrementing PC. B

• ALU still has a Constant 4 input for Instruction

decoder
other instructions (e.g., post-increment:
[SP]++ for stack push). IR

MDR

MAR

Memory b us Address
data lines lines
CSCI2510 Lec10: Basic Processing Unit 56
Class Exercise 10.7
• Can you tell what does the
Bus A Bus B Bus C

Incrementer

following execution do? PC

 PC-out, MAR-in, Read, R=B

Register

 MDR-inE, WaitMFC, IncPC file


Constant 4
MDR-out, IR-in, R=B


MUX
DecodeInstruction A

ALU R

 R4-outA, R5-outB, SelectA, B

Add, R6-in Instruction

decoder

IR

MDR

MAR

Memory b us Address
data lines lines
CSCI2510 Lec10: Basic Processing Unit 57
Summary
• Processor Internal Structure
• Instruction Execution
– Fetch Phase
– Execute Phase

• Execution of A Complete Instruction

• Multiple-Bus Organization

CSCI2510 Lec08: Cache Performance 59