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Birla Institute of Technology and Science – Pilani, Hyderabad Campus, First Semester 2018-19
CS/EEE/ECE/INSTR: F215 Digital Design Comprehensive Examination –Part B
Time: 9:00AM-12:00PM Date: 11th December 2018 Max. Marks: 40
Instructions: For Evaluators Use:
Answer in the space provided for each question. Question No Marks Obtained
Use Supplementary sheet for ROUGH Work
1
2
3
Total
1. A serial decrementer block with a 4-bit shift register is shown in the figure below. 4-bit shift register is
initially loaded with a binary value (say M). Design the serial decrementer circuit (as Mealy sequential
Circuit) using only one JK Flip-flop (which has both Q and Q’ outputs) and one logic gate, such that
after 4 clock cycles the shift register contains binary value equal to M-1. (e.g. If shift register contains 1101
initially then after 4 clock cycles the shift register should contain 1100)
State Diagram (Label the initial State) [3M]
State Table [3M] Circuit Diagram [4M]
Present I/p Next O/p J K
State State
(Q) (Q+)
State Equations (2M)
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2. A 1-bit comparator is shown in the figure. This circuit compares two one bit inputs (Ai, Bi) and generates
two outputs, Li indicating Ai is less than Bi and Ei indicating Ai is equal to Bi. If Ai<Bi, then Li is logic 1
and Ei is logic 0; If Ai=Bi, then Li is logic 0 and Ei is logic 1; If Ai>Bi, then both Li and Ei are logic 0. Both
Li and Ei will never be equal to logic 1 at the same time.
Now a 2-bit comparator, which compares two 2-bit inputs A (A1A0) and B (B1B0) is to be designed using
two 1-bit comparators and 2:1 multiplexers without using K-map. The 2-bit comparator has two outputs L
(indicating A<B, i.e. (A1A0) < (B1B0)) and E (indicating A=B, i.e. (A1A0) = (B1B0)).
(i) Write the truth table which shows the relation between 1-bit comparator outputs (E1, L1, E0, L0) and
final outputs (E, L).
(ii) Analyze this truth table and design a 2-bit comparator using two 1-bit comparator blocks and two
2:1 multiplexers only (No other blocks\gates should be used).
Truth Table [7M] :
L1 E1 L0 E0 L E
(A1<B1) (A1=B1) (A0<B0) (A0=B0) (A<B) (A=B)
Circuit Diagram with two 1-bit comparators and two 2:1 Multiplexers (clearly label all inputs and outputs)[6M]
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3. Booth’s Multiplication algorithm using 2-bit encoding is to be implemented in hardware using modular
approach. The circuit should start multiplication when the Start signal is given. The completion of
multiplication should be indicated by a Ready signal. Assume that the datapath has registers, shift registers,
adder-subtractor and a counter. For this Booth’s Multiplier
(i) List the different inputs and outputs for the control unit.
(ii) Develop the complete ASM chart for the control unit.
Mark Inputs/outputs for Control Unit [5M]
Control Unit
ASM Chart [10M]
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(Additional Space)
