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Verilog Lab 5

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22 views21 pages

Verilog Lab 5

Uploaded by

khoihchtb
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

1

FINITE STATE
MACHINE

ĐTH
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
2

1. Moore & Mealy Machine


OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
3

1. Moore & Mealy Machine


OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
4

1. Moore & Mealy Machine


OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
5

1. Moore & Mealy Machine


OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
6

1. Moore & Mealy Machine


OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
7

always @(w, tt_ht)


case (tt_ht)
A: if (w) tt_kt = B;
else tt_kt = A;
B: if (w) tt_kt = C;
else tt_kt = A;
C: if (w) tt_kt = C;
else tt_kt = A;
default: tt_kt = 2’bxx;
endcase
module simple (Clock, Resetn,
w, z); always @(negedge Resetn, posedge Clock)
input Clock, Resetn, w; if (Resetn == 0)
output z; tt_ht < = A;
reg [2:1] tt_ht, tt_kt; else tt_ht < = tt_kt;
parameter [2:1] A = 2’b00, B = assign z = (tt_ht == C);
2’b01, C = 2’b10; endmodule
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
8

if (reset)
tt_ht <=S0;
else tt_ht <= tt_kt;
always @*
case (tt_ht)
SO: if(a) if(b) tt_kt =S2;
else tt_kt =Sl;
else tt_kt =S0;
Sl: if(a) tt_kt =S0;
else tt_kt =S1;
module fsm-eg-mult-seg S2: tt_kt =S0;
(input wire clk , reset , default: tt_kt =S0;
input wire a , b , endcase
output wire yo, yl ); //Moore outputlogic
localparam [1:0] S0 = 2’b00, S1 = assign yl=(tt_ht ==S0)||(tt_ht ==Sl);
2'b01 , S2=2'b10;
reg [1:0] tt_ht, tt_kt;
//Mealy outputlogic
always @ (posedge clk ,posedge assign y0=(tt_ht ==SO)&a&b;
reset) endmodule
9

BÀI 1: Cho MTT có sơ đồ trạng thái như


hình, Reset thấp, CLK lên.
a) Viết RTL code mô tả MTT trên
b) Viết testbench với tín hiệu ngõ ra là
trạng thái hiện tại và z.
c) Thực thi trên board với tần số 1 Hz
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
10

1. RTL CODE
always @(w, tt_ht)
case (tt_ht)
A: if (w) tt_kt = B;
else tt_kt = A;
B: if (w) tt_kt = C;
else tt_kt = A;
C: if (w) tt_kt = A;
else tt_kt = C;
default: tt_kt = 2'bxx;
module Mtt_moore(
input Clock, Resetn, w, endcase
output z, always @(negedge Resetn, posedge Clock)
output reg [1:0] tt_ht); if (Resetn == 0) tt_ht <= A;
reg [2:1] tt_kt = 0; else tt_ht <= tt_kt;
parameter [2:1] A = 2'b00, // Define output assign z = (tt_ht == B);
B = 2'b01, C = 2'b10; endmodule
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
11

2. TB
initial begin
Clock = 0;
Resetn = 0; w = 0; #10;
Resetn=1; w=1; #40; w=0; #20; w=1; #20;
end //***************************
always begin
#10; Clock=~Clock;
end
//***************************
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
12

3. RTL CODE

module Chiaxung_1hz module Board_test_1Hz(


#(parameter N= 26) input clk_50m, reset, w,
output z, clk_1hz,
( input wire clk, output wire q ); output [1:0] tt_ht );
// signal declaration wire clk_i; Chiaxung_1hz
reg [N-1:0] r_reg; IC1(clk_50m, clk_i); Mtt_moore
wire [N-1:0] r_next; IC2(clk_i, reset, w, z, tt_ht);
// body, register assign clk_1hz = clk_i;
endmodule
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
13

[Link]
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ; NET "clk_50m"
CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "w" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "z" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "clk_1hz" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET “tt_ht<0>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET “tt_ht<1>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
14

BÀI 2: Cho MTT có sơ đồ trạng thái như


hình, Reset cao, CLK lên.
a) Viết RTL code mô tả MTT trên
b) Viết testbench với tín hiệu ngõ ra là
trạng thái hiện tại và z.
c) Thực thi trên board với tần số 1 Hz
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
15

1. RTL CODE

reg [1 : 0] tt_kt = 0 ;
always @ (posedge clk ,posedge reset)
if (reset) tt_ht<=S0;
else tt_ht<=tt_kt;
//next_state logic
always @*
case (tt_ht)
S0: if(a) if(b) tt_kt=S2;
else tt_kt=S1;
else tt_kt=S0;
module MTT_moore_mealy ( input S1: if(a) tt_kt=S1; else tt_kt=S0;
wire clk , reset , input wire a S2: tt_kt=S0;
, b , default: tt_kt=S0;
output wire yl,y0, endcase
output reg [1:0] tt_ht ); //Moore outputlogic assign yl=(tt_ht==S0);
localparam [1:0] S0 = 2'b00, S1 //Mealy outputlogic assign y0=(tt_ht==S0)&a&b;
= 2'b01 , S2=2'b10; endmodule
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
16

2. TB initial begin
clk = 0;
reset = 1; a = 1; b = 1; #10;
//****************************
reset = 1; a = 0; b = 0; #20;
reset = 0; a=0; #20; a=1; b=1; #20;
a=1; b=1; #20; a=1; b=0; #20; a=1; #20;
a=0; #20; end
always begin #10; clk=~clk; end
//***************************
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
17

3. RTL CODE

module Chiaxung_1hz Module Board_test_1Hz_moore_mealy(


input clk_50m, reset, a, b,
#(parameter N= 26) output y1, y0, clk_1hz,
( input wire clk, output wire q ); output [1:0] tt_ht );
wire clk_i;
// signal declaration Chiaxung_1hz IC1(clk_50m, clk_i);
reg [N-1:0] r_reg; MTT_moore_mealy IC2(clk_i, reset, a, b, y1,
y0, tt_ht);
wire [N-1:0] r_next; assign clk_1hz = clk_i; endmodule
// body, register
always @(posedge clk)
r_reg<=r_next;
// next state logic
assign r_next = r_reg + 1;
// output logic
assign q=r_reg[25];
endmodule
OVERVIEW BLOCK DIG RTL CODE TESTBENCH IMPLEMENT
18

[Link]
NET "clk_50m" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "clk_50m" CLOCK_DEDICATED_ROUTE = FALSE;
NET "reset" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "a" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "b" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk_1hz" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "y1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "y0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET “tt_ht<1>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET “tt_ht<0>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
19

BÀI 3: Làm lại bài 1 nhưng ngõ ra có


thêm TTKT.
20

BÀI 4: Làm lại bài 2 nhưng có thêm


TTKT. 0

1
21

BÀI 5: Làm lại bài 2 nhưng có thêm


TTKT.

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