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PrimeTime RC Delay Calculator

Troubleshooting Guidelines

Version 1.1

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TABLE OF CONTENTS
1 INTRODUCTION 4

2 DIFFERENCES WITH TRANSISTOR-LEVEL SIMULATION 5

2.1 DISCREPANCIES DUE TO SETTINGS IN SPICE AND PRIMETIME 5
2.2 CELL TIMING DISCREPANCY 6
2.2.1 Is the RC network unit definition the same in both PrimeTime and the SPICE simulation? 6
2.2.2 Are C-total and C-effective inside the library table boundaries? 6
2.2.3 Is input transition time inside the boundaries of the library table? 6
2.2.4 Is the characterization waveform applied on the input pin in SPICE simulation? 6
2.2.5 Do PrimeTime and the SPICE simulation results match for the same input transition time at C-total or
C-effective? 7
2.2.6 Do the simulations of the PrimeTime driver model and the transistor-level driver agree for C-total and C-
effective? 7
[Link] Background: 7
[Link] Comparison: 9
2.3 RC-NETWORK TIMING DISCREPANCY 10
2.3.1 Is the driver cell timing discrepancy small? 10
2.3.2 Is the RC-network definition the same in both PrimeTime and the SPICE simulation? 10
2.3.3 Do PrimeTime and the SPICE simulation use the same driver arc? 10
2.4 PATH TIMING DISCREPANCY 11
2.4.1 Does the path begin with a port? 11
2.4.2 Are the side inputs the same in PrimeTime and the SPICE simulation? 11
2.5 TIMING OPTIMISM 11
2.5.1 Was a realistic characterization waveform used to create the library? 11
3 RC DELAY CALCULATOR ERROR AND WARNING MESSAGES 12
3.1 MESSAGES DURING THE ‘READ_PARASITICS’ COMMAND 12
3.1.1 Discrepancies between a logical netlist and its associated parasitic data. 12
[Link] PARA-006 - Error: Driver/Load pin 'xx' is missing in the RC annotation for net 'xxx'. Ignoring the
incomplete RC annotation. 13
[Link] PARA-007- Warning: Unconnected hierarchy pin 'xx' is missing in the RC annotation for net 'xxx’ 13
3.1.2 Multi-driven net (DES-023) 13
3.2 WARNING MESSAGES DURING A TIMING UPDATE 14
3.2.1 Missing thresholds (DES-021) 14
3.3 CELL ARC WARNINGS 14
3.3.1 Calculation Failure -RC-004: 14
[Link] Non-positive drive-resistance 15
[Link] Inconsistency with a linear driver-model. 15
[Link] C-total less than or equal to zero 16
[Link] Invalid reduced-order model 16
[Link] Invalid pole-residue model 16
[Link] Unconnected from-pin 17
3.3.2 Rd override -RC-009: 17
[Link] First condition: Rd << Znet 17
[Link] Second condition- Net Delay > driver slew 18
[Link] Quality of parasitic extraction 18
[Link] What to do next? 18
3.4 NET ARC WARNINGS 19
3.4.1 RC-005 Warning: Calculation Failure 19

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[Link] Unsupported multi-drive condition 19

[Link] No timing arcs 19
[Link] Under-driven network 19
[Link] Slew propagation 19
[Link] Incompatible Voltage Swings 20
3.5 MULTI-DRIVE WARNINGS 20
3.5.1 Incomplete driver coverage (RC-002) 20
3.5.2 Degenerate driver coverage (RC-003) 21
3.5.3 Calculation failure (RC-007) 22
3.6 MIN/MAX BOUNDS WARNING (RC-008) 22
4 CONCLUSION 22

5 RECOMMENDED READING 23

APPENDIX A: EXAMPLE OF HOW TO DEBUG RC-004 WARNING TYPE DESCRIBED IN

SECTION [Link] 24

APPENDIX B: PARALLEL DRIVER REDUCTION 29

APPENDIX C: SYNOPSYS LIBERTY SCREENER 31

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1 Introduction
PrimeTime is a chip-level static timing analysis (STA) tool for complex multi-million gate system-on-a-chip
(SoC) designs. PrimeTime’s powerful and accurate delay calculation engine allows users to perform analysis
using detailed parasitic data in SPEF or DSPF format. Library, tool, and flow qualification may include
calibration of the results from PrimeTime’s delay calculator with detailed parasitic annotation against
transistor-level simulation. In flows where users have access to SPICE sub-circuits and device models, users
may choose to perform SPICE simulation on critical paths identified by PrimeTime.

During the correlation process, users may encounter the following issues:

• Mismatching PrimeTime and SPICE results

• RC delay calculation error or warning messages from PrimeTime
The purpose of this application note is to help users understand and solve these issues. The first part presents
guidelines on how to efficiently investigate and resolve the source of unexpected discrepancies. The second
part explains how to interpret and identify possible causes for RC delay calculation warnings and error
messages.

This application note is intended for users who have access to library characterization methods and data,
including SPICE subcircuits and device models. It is also useful for end users who want to achieve a better
understanding of delay calculation for interaction with the library provider. Prior to reading and applying the
techniques in this application note, it is highly recommended that you become familiar with the background
application notes listed in the “Recommended Reading” section.

Please note that the debugging techniques described in this application note are applicable to libraries using
nonlinear delay models (NLDMs). The techniques are not applicable to generic CMOS models. The part
related to driver_model is not applicable to CCS timing models either.

The information in this application note is related to versions 2004.06 and later.

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2 Differences with Transistor-Level Simulation

In order to compare PrimeTime results to those of a transistor-level simulator such as SPICE, one must
correctly set the simulator accuracy settings and path conditions such as input transition time and output
loading. This section describes how to investigate differences between PrimeTime and transistor-level
simulation results in the absence of delay calculation warnings or errors from PrimeTime. For designs that
generate PrimeTime delay calculation warnings or errors, please refer to the next section, “RC delay
calculation warning Messages”.

Please note that in order to simplify the wording in this application note, transistor-level simulation will be
referred to as SPICE simulation.

Initially, we must find out if the source of the discrepancies is global due to SPICE simulation settings or
inconsistent setup between SPICE and PrimeTime.

Next, we consider the following specific situations in which discrepancies may occur:

• Cell timing discrepancies

• Network timing discrepancies
• Path timing discrepancies, including the overall trend in the discrepancies. For example, we need to
examine whether SPICE delays are longer than in PrimeTime and investigate possible causes of this
timing optimism.

2.1 Discrepancies Due to Settings in SPICE and PrimeTime

Following are the first things to check when investigating discrepancies in settings between SPICE and
PrimeTime.
2.1.1 Are high-accuracy settings used in SPICE simulation?
Berkeley SPICE and its derivatives are not typically set to the highest accuracy level by default. When
invoking SPICE simulation for library characterization and for comparison against PrimeTime, make sure
that SPICE is set in its most accurate mode of analysis. Please refer to the specific SPICE simulation manual
for details. Also, make sure that the simulation step size or granularity of waveform data is appropriate for
the given process. As a practical rule, the simulation step size should be set to 1% of the minimum cell delay.
For example, a good estimation of that minimum cell delay can be obtained by looking at the inverter with the
largest drive driving the smallest possible load.

2.1.2 Do PrimeTime and SPICE simulation use the same trip-points?

Both PrimeTime and the SPICE simulation must use the same delay and transition time trip-points. The trip-
points determine the points on the waveform from which the delay and transition time are measured. For
example, transition time trip-points may be at 30%-70% of Vdd, and delay trip-point may be at 50% Vdd. If
different trip-points are used between PrimeTime and SPICE simulation, then the comparison is not valid.

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Please note that in libraries where transition times are specified at 0%-100% of Vdd, library slew derating is
required for PrimeTime RC delay calculation. Please refer to the man page for the shell variable
rc_slew_derate_from_library.

Assuming that the previous checks have been done, what are some of the other causes of discrepancies
between PrimeTime and SPICE?

2.2 Cell Timing Discrepancy

Cell delay is defined as the delay between a logic transition on an input of a gate and the logic transition on
the output of a gate. When the cell delay in PrimeTime and SPICE do not match, it is called a cell timing
discrepancy. This section describes several possible causes.
2.2.1 Is the RC network unit definition the same in both PrimeTime and the SPICE
simulation?
It is possible that the units, such as for resistor and capacitor values, are not specified correctly either in the
parasitic file (SPEF or DSPF) or in the SPICE simulation file. Please also check to make sure that the process,
voltage, and temperature in SPICE simulation match the operating conditions being used in PrimeTime.

2.2.2 Are C-total and C-effective inside the library table boundaries?
Verify that the lumped capacitance (C-total) and effective capacitance (C-effective) are inside the boundaries
of the library table. These values are given by the PrimeTime command:

pt_shell > report_delay_calculation –from Cell/Input –to Cell/Output

If C-total and C-effective are not inside the boundaries of the library table, the discrepancy may be due to
library data extrapolation. Whenever C-total and C-effective are not inside the library table, the cell delay and
output transition time must be calculated by using extrapolation techniques. In this case, one option is to
modify the design if the output capacitance value violates a design rule. This can be easily verified with:

pt_shell > report_constraint –all_violators

Other option is to re-characterize the library to so that the actual output capacitance is inside the boundaries of
the lookup table.

2.2.3 Is input transition time inside the boundaries of the library table?
If the input transition time is not inside the library table, the discrepancy may also be due to library
extrapolation. Similar to C-total and C-effective, the design must be modified to meet design rule
specifications or the library must be re-characterized. In short, the cells must be used so that their operating
conditions are inside the characterization tables.
2.2.4 Is the characterization waveform applied on the input pin in SPICE simulation?
In deep sub-micron technologies, during the characterization process, a real waveform is applied on the input
of the cell to be characterized. When you do a comparison with a SPICE simulation, you must apply that
characterization waveform in the SPICE simulation, not an ideal waveform, even if the ideal waveform has
the same transition time. Otherwise, the ideal waveform could cause some significant differences in
calculated delay.

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Ideal

100%
70%

50%
Real

30%
0%

Time

Figure 1: Apply to the real circuit the characterization waveform.

2.2.5 Do PrimeTime and the SPICE simulation results match for the same input transition
time at C-total or C-effective?
For a given input transition time, the user should run SPICE simulations with the output capacitance set to C-
total and C-effective. The cell delays in PrimeTime and SPICE simulation should match within about -/+1%.
This max error will allow the user to have a +/-5% max error for the sum of cell delay and interconnect delay
in PrimeTime.
If the cell delays do not match, this indicates a potential library data interpolation problem. One of the reasons
is that an insufficient number of indices have been used for characterization in the fast (nonlinear) region of
the library table. To minimize interpolation errors, the cell should be re-characterized with more table points
in the particular region of interest.

2.2.6 Do the simulations of the PrimeTime driver model and the transistor-level driver agree
for C-total and C-effective?

[Link] Background:
After back-annotation of the extracted parasitics from the layout, the PrimeTime delay calculator replaces the
instantiated driving cell with a driver model called SDM (Synopsys Driver Model). This model is a Thevenin
voltage source with a driving resistance. The parameters of this model are calculated so that the resulting
waveform (cell delay and slew) matches, as closely as possible, the actual cell output waveform when C-
effective is the load applied to that cell. For more information on this process, please refer to the PrimeTime
Delay Calculator white paper mentioned in the recommended reading paragraph.

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Ceff
Cell Output Transition
Actual Driving cell Cell Input Transition
Volt

Delay trip point

Rd
0
0 tz tz + Dt Time
Ceff

Thevenin Source
Simplified Driver

Figure 2: Simplified Driver Model

See paragraph 2.2.2 for information about the Ceff Ctotal values.
The resulting calculated model parameters rd, tz, and Dt can be obtained by the PrimeTime command:

pt_shell> report_driver_model –rise_slew <input_trans> -fall_slew <input-trans> \

-capacitance <Ceff or Ctotal> -lib_cell <driving cell> -from_pin <input pin> \
-to_pin <output pin>
which gives

****************************************
Report : driver_model
Driver : xxx/yy:B-->Z
Version: 2002.03
Date : Mon Mar 18 [Link] 2002
****************************************
Accuracy Settings: Rise Fall
slew_lower_threshold = 35% 35%
slew_upper_threshold = 65% 65%
input_threshold = 50% 50%
output_threshold = 50% 50%
slew_derate_from_library = 0.3
driver_model_max_error = 16%
lib_thresholds_per_lib = true
Library Inputs: (in library units)
Rising input slew = 0.370370
Falling input slew = 0.370370
Output load capacitance = 0.001881
Driver model for sense 'positive-unate':
(max) Rise Fall
--------------------------------------------------
load = 0.001881 0.001881 (pF)
delay = 0.263882 0.260043 (ns)
slew = 0.029534 0.025686 (ns without derate)

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d-load = 1.88e-05 1.88e-05 (pF)

d-delay = 7.25e-05 7.20e-05 (ns)
d-slew = 5.06e-05 3.57e-05 (ns without derate)
rd = 22.67360 19.72783 (kohm)
tz = 0.192315 0.197800 (ns)
dt = 0.073450 0.063882 (ns)
error = 0.791158 0.743590 (%)
check = pass pass

(min) Rise Fall

--------------------------------------------------
load = 0.001881 0.001881 (pF)
delay = 0.263882 0.260043 (ns)
slew = 0.029534 0.025686 (ns without derate)
d-load = 1.88e-05 1.88e-05 (pF)
d-delay = 7.25e-05 7.20e-05 (ns)
d-slew = 5.06e-05 3.57e-05 (ns without derate)
rd = 22.67360 19.72783 (kohm)
tz = 0.192315 0.197800 (ns)
dt = 0.073450 0.063882 (ns)
error = 0.791158 0.743590 (%)
check = pass pass

You can read in bold the four calculated values for rd, tz and dt for a max and min analysis and for a rising
and falling edge.
Another way to have this information in a more compact but less readable format is:

pt_shell> get_attribute [get_pins <driving pin>] ceff_params_max

gives
get_att [get_pins xxx/Z] ceff_params_max
{ A {rd 2.416740e+01 2.154167e+01} {t0 2.344839e-01 2.338319e-01} {delta_t
7.828199e-02 6.975447e-02} {ceff 1.880544e-03 1.880544e-03}} { B {rd 2.267359e+01
1.972783e+01} {t0 1.92315e-01 1.97800e-01} {delta_t 7.343002e-02 6.388229e-02} {ceff
1.880544e-03 1.880544e-03}} and

pt_shell> get_attribute [get_pins <driving pin>] ceff_params_min

gives

get_att [get_pins xxx/Z] ceff_params_min

{ A {rd 2.26730e+01 2.154167e+01} {t0 2.344839e-01 2.338319e-01} {delta_t 7.828199e-
02 6.975447e-02} {ceff 1.880544e-03 1.880544e-03}} { B {rd 2.267359e+01
1.972783e+01} {t0 1.92315e-01 0.1978500e-01} {delta_t 7.345002e-02 6.3882e-02} {ceff
1.880544e-03 1.880544e-03}}

The slight value differences that one might get between these two different commands are due to the fact that
in report_driver_model, we specify in the command line the input slew. So this is a round-off value. When
looking at the ceff_params_max/min attribute, the input transition is the one from the design, so the
accuracy is slightly higher.

[Link] Comparison:
After you get these parameters from PrimeTime, you can simulate in SPICE the actual driving cell loaded by
the lumped capacitance and the effective capacitance; and the driver model (voltage source with a serial Rd
resistance) loaded by the lumped capacitance and the effective capacitance. At this stage, the resulting
waveforms should really match, especially in the region between the trip points. User can take advantage of
PrimeTime SI command write_spice_deck for this task.

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2.3 RC-Network Timing Discrepancy

RC network delay is defined as the delay between a logic transition on the driving output pin to a logic
transition on an input load pin. When the RC network delay or the driver and load transition time between
PrimeTime and SPICE simulation do not match, it is called an RC network timing discrepancy. This section
describes several possible causes.
2.3.1 Is the driver cell timing discrepancy small?
If the driver cell timing between PrimeTime and SPICE simulation does not match within reasonable
expectations, this should be investigated first. Please refer to the previous section for more information.

2.3.2 Is the RC-network definition the same in both PrimeTime and the SPICE simulation?
It is possible that the units, such as for resistor and capacitor values, are not specified correctly either in the
parasitic file (SPEF or DSPF) or in the SPICE simulation file. The SPICE deck must contain the same
resistors and capacitors as the ones in the SPEF/DSPF file used by PrimeTime. The units must be also the
same in the .db file. A useful command in PrimeTime to check the units is report_units.
Units
---------------------------------------------
Capacitive_load_unit : 1e-12 Farad
Current_unit : 0.001 Amp
Resistance_unit : 1000 Ohm
Time_unit : 1e-09 Second
Voltage_unit : 1 Volt

This can be checked against the SPEF file header:

*T_UNIT 1 NS
*C_UNIT 1 FF
*R_UNIT 1 OHM
*L_UNIT 1 HENRY
These units are the values used in Spice language.

2.3.3 Do PrimeTime and the SPICE simulation use the same driver arc?
In order for the comparison to be valid, PrimeTime and the SPICE simulation must use the same driver arc. If
the network driver has a fan-in of one, such as for an inverter or buffer, both the cell delay and output
transition are derived from the same arc. If the network driver has a fan-in of greater than one, such as for a
multi-input gate with multiple arcs, PrimeTime propagates only one of the arcs according to whether min or
max analysis is active and according to the slew propagation mode. Depending on the setting of the variable
timing_slew_propagation_mode , this can be worst slew propagation mode or worst arrival propagation
mode. For the worst slew mode, the worst input slew of multi-input gates is always propagated, i.e. this worst
input transition is used for the delay and slew calculation for that cell. For the worst arrival mode, the slew of

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the latest-arrival input is used for delay and slew calculation for that cell. A SPICE simulation, on the other
hand, always uses the actual input slew of that cell.
So, once it has been verified that the cell timing matches with the SPICE simulation, the RC-network timing
must be verified using the same arc that was propagated by PrimeTime. One way to ensure this is by setting
the same side-inputs in both PrimeTime and the SPICE simulation. For more information, see the man pages
for the report_delay_calculation command and the timing_slew_propagation_mode variable.
This is done automatically if the user uses write_spice_deck utility in primetime.

2.4 Path Timing Discrepancy

This section describes how to troubleshoot differences in path delay between PrimeTime and a SPICE
simulation. A timing path is a path that starts with an input port or a clock pin of a flip-flop and ends with an
output port of a D pin of a flip-flop. It may consist of several cells. Before attempting to troubleshoot path
timing discrepancies, it is assumed that any cell timing discrepancies and R-C network discrepancies have
been resolved. Please refer to the previous sections on how to resolve these types of discrepancies.
2.4.1 Does the path begin with a port?
A comparison should begin with an input pin on a leaf cell, and the characterization waveform should be
applied to this pin in the SPICE simulation in order to make the comparison consistent. Be sure to use the
set_annotated_transition command to annotate the same input transition time on the pin in PrimeTime as
the time used or measured in the SPICE simulation.
2.4.2 Are the side inputs the same in PrimeTime and the SPICE simulation?
All side inputs along the path must be specified equivalently for the comparison to be valid. A side
input is an input that doesn’t belong to the path but contributes to that path. For example, if the path goes
through the pin A from a NAND gate, input B of this NAND gate will be seen as a side input.

IN
A
CLOCK
B

Side Input

Figure 3: Side inputs

2.5 Timing Optimism

For the purpose of delay correlation, we define timing optimism as the case where the cell delay or RC
network delay determined by PrimeTime is shorter in maximum analysis, or longer in minimum analysis,
than determined by SPICE simulation.

2.5.1 Was a realistic characterization waveform used to create the library?

Different waveform shapes can have the same slew measurement but induce significant differences in
downstream cell delays. Ideally, a waveform shape that induces maximum delays should be used for
characterizing libraries for max analysis, and a waveform shape that induces minimum delays should be used
for characterizing libraries for min analysis. If only one characterization waveform shape is used, some

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timing optimism will be unavoidable in those cases. For example, if the actual waveform in setup analysis is
slower than the one used during characterization, the PrimeTime delay will be underestimated.

100%
70%
50%

30%
0%

time
Transition Time

Fastest waveform
Typical waveform
Slowest waveform
Figure 4: Characterization waveform

Some libraries are characterized with a pre-driver cell. For better correlation results this pre-driver cell must
be used as well in the design.

3 RC Delay Calculator Error and Warning

Messages
In this section, we will describe guidelines for investigating RC-related messages (DES-XXX, RC-XXX) in
PrimeTime. Please refer to the man page for each warning message for additional information.

3.1 Messages During the ‘read_parasitics’ Command

3.1.1 Discrepancies between a logical netlist and its associated parasitic data.
The logical netlist describes the connectivity of the leaf cells and hierarchical cells in design and is typically
in the form of a Verilog netlist. The parasitic data represents the physical characteristics (resistance,
capacitance, inductance) of the nets described in the logical netlist. This data is extracted from the physical
database and is typically in the form of a SPEF file.

There are valid sources of discrepancies between these two representations of the nets in the design, but these
discrepancies should be investigated. Encountering either of the following messages warrants a detailed
examination of the parasitic extraction flow/data to verify that these conditions are to be expected an not an
indication of a serious problem with the parasitic annotation data.

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[Link] PARA-006 - Error: Driver/Load pin 'xx' is missing in the RC annotation for net 'xxx'.
Ignoring the incomplete RC annotation.
This is an error because a leaf or connected hierarchy pin is missing in the annotation file. PARA-006 causes
a wire load model to be used instead of the parasitic annotation for all net arcs driven by that cell.
The error PARA-006 indicates that PrimeTime has encountered a connection to a leaf cell pin that does not
have a corresponding complete network description in the SPEF file. There are two ways of resolving this
type of inconsistency. One is to complete the network using the either the -complete_with option to
read_parasitics or the complete_parasitics command. If you choose not to complete the parasitic network,
any SPEF annotation that exists for that net is discarded and the parasitic data for that net is retrieved from the
appropriate wire load model.

[Link] PARA-007- Warning: Unconnected hierarchy pin 'xx' is missing in the RC annotation for
net 'xxx’
The warning PARA-007 indicates that PrimeTime has encountered a connection to a hierarchical pin in the
logical netlist that does not have a corresponding network description in the SPEF file.
In this case, the assumption is that this segment does contribute to the parasitic effects of that net. The
contribution to the parasitics is derived from the appropriate wire load model, or as specified by the
complete_parasitics command or the -complete_with option to read_parasitics.

Unconnected
hierarchical Pin

PARA-007 Warning

PARA-006 Error
No Warning
BLOCK A
Figure 5: PARA-006/7 situations

3.1.2 Multi-driven net (DES-023)

Warning: Net 'IA1' is multi-driven. (DES-023)
The purpose of this message is to make the user aware that there are multi-driven nets. Be sure you really
intend to have this net multi-driven. This warning is informational and occurs only if the PrimeTime delay
calculator is used. Please be aware that only some types of multi-drive conditions are supported, such as a
configuration where the input pins of the multi-drive cells are connected together. See section [Link] for
details on this subject.
A parallel driver reduction methodology is available to improve the run time. For more information on this
feature see Appendix B of this document.

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3.2 Warning Messages during a Timing Update

When using update_timing, report-timing or report_delay_calculation, the following types of messages
can occur
3.2.1 Missing thresholds (DES-021)

DES-021 (warning) These environment variables need to be set for accurate RC

delay calculation:
Variable name Default
------------------------------------------------------
rc_slew_lower_threshold_pct_rise 20
rc_slew_lower_threshold_pct_fall 20
rc_slew_upper_threshold_pct_rise 80
rc_slew_upper_threshold_pct_fall 80
rc_input_threshold_pct_rise 50
rc_input_threshold_pct_fall 50
rc_output_threshold_pct_rise 50
rc_output_threshold_pct_fall 50

Thresholds for rise/fall transition times and delay must be defined in the libraries. They can also be specified
with shell variables. However, in order to use several libraries defined with different set of trip points, it is far
better if they are defined in the library.
The rc_*_threshold_* variables specify the trip-points used for computing transition times and delays.
If this information is not in the library and you cannot find it anywhere, you need to get the information from
the library provider.

PrimeTime gets the threshold information using the following order of priority:
• Default case (when lib_thresholds_per_lib is true)
• Variables from the library containing the pin
• rc_*_ threshold_* variables if they are set
• main library (first library in the link path)
• Default values (20%/80% slew, 50% delay, 1 as slew-derate)

• lib_thresholds_per_lib is false
• rc_*_threshold_* variables if they are set
• main library (first library in the link path)
• Default values (20%/80% slew, 50% delay, 1 as slew-derate)

See the man page and section [Link] for more information on the lib_threshold_per_lib variable.

3.3 Cell arc warnings

These warnings are related to the calculation of the Synopsys Driver Model when using NLDM libraries.
3.3.1 Calculation Failure -RC-004:
This serious warning implies that the delay calculator was unable to calculate the effective capacitance. In
that case, for a conservative analysis, C-total is used in max analysis mode and C-zero is used in min analysis
mode. C-total is the sum of all the capacitance values of the network, and in hold analysis, PrimeTime
assumes a load equal to 0. The RC-004 warning means that the Ceff calculation failed. But the detailed
warning message gives information on the reason for this failure.

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In addition, the RC delay calculation is not applied to a transition going to or from Z. So the RC-004 warning
never shows up for a disable or enable timing arc.

[Link] Non-positive drive-resistance

Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because the library data indicates a non-positive drive
resistance. [r/f inp_slew = 0.028226/0.028226, out_cap = 0.003015 (lib units)]
(RC-004)

This message indicates that the library cell delay or output slew does not increase with increasing load
capacitance. The library issues must be resolved. You can use the report_driver_model command to test the
capacitance-sensitivity of the library data. It calculates the impact of an increase of the loading capacitance by
1% on the delay. The delay and the slew must increase in this case.
This problem can be caused by a library extrapolation, an incorrect value for the transition time trip-points, or
not enough significant digits in the NLDM tables.
Example:

pt_shell > report_driver_model –rise_slew 0.028226 –fall_slew 0.028226 –capacitance 0.003015 \

–lib_cell xx/yy –from_pin A –to_pin Z
gives:

Driver model for sense 'positive-unate':

(max) Rise Fall
--------------------------------------------------
load = 0.003014 0.003014 (pF)
delay = 0.054132 0.081334 (ns)
slew = 0.044777 0.039348 (ns without derate)
d-load = 3.01e-05 3.01e-05 (pF)
d-delay = -3.35e-05 6.91e-05 (ns)
d-slew = 0.000150 7.13e-05 (ns without derate)
rd = 0.000000 5.171246 (kohm)
tz = 0.000000 0.057792 (ns)
dt = 0.000000 0.022714 (ns)
error = -NaN 1.041177 (%)
check = FAIL pass

The warning is issued because d-delay (increase of delay with respect to increase in load) is negative. A
methodology to analyze this issue is available in Appendix A. It is also recommended that the library be
analyzed with the Synopsys Liberty Screener. This tool screens the library with criteria such as non-
monotonic behavior, number of significant digits, min/max capacitance values, and min/max transitions
values. For more information on this tool, see Appendix C.

[Link] Inconsistency with a linear driver-model.

Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because the library data is inconsistent with a linear-
driver model[r/f inp_slew = 0.028226/0.028226, out_cap = 0.003015 (lib units)]
(RC-004)

PrimeTime could not find driver-model parameters that effectively match the library delay, slew, and
sensitivity to capacitance. Usually this is because the trip-points are not set correctly or the library data is
inaccurate, with not enough precision when the library was characterized. If that case, you can increase the
value of the shell variable rc_ceff_delay_min_diff_ps from 0.25 to 0.5 or 1.0 until the library can be fixed.
This variable specifies the tolerance used by PrimeTime for determining the effective capacitance by looking
at the driver cell delay.
If doubling or quadrupling this value does not stop the RC-004 warnings, it is more likely that the problem is
due to incorrect trip point setting. Note that increasing the tolerance setting helps prevent calculation failures,

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but also adversely impacts the accuracy of those calculations that previously did not fail. See the man page on
the variable for more information.

[Link] C-total less than or equal to zero

Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because C-total is less than or equal to zero[r/f
inp_slew = 0.028226/0.028226, out_cap = 0.0 (lib units)] (RC-004)

This can only happen if the read_parasitics command was incorrectly used with the ‘-pin_cap_included’
option. Obviously, if PrimeTime incorrectly subtracts the pin capacitance from the network, Ctotal can be
negative, which prevents the delay calculator from calculating Ceff.

[Link] Invalid reduced-order model

Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because the RC network has an invalid reduced-order
model[r/f inp_slew = 0.028226/0.028226, out_cap = 0.003015 (lib units)] (RC-
004)

This can only happen if the connectivity of the annotated parasitics does not match that of the design. Check
to see if there was an accompanying PARA-006/PARA-007 message (missing pin in the parasitics) or LNK
message (unconnected pin in the design) for the net.
[Link] Invalid pole-residue model
Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because the RC network has an invalid pole-residue
model[r/f inp_slew = 0.028226/0.028226, out_cap = 0.003015 (lib units)] (RC-
004)
This message indicates that the RC data is represented in terms of pi models R/C/R with additional poles and
residues. This model is used to compute the slew at the driver pin. This can only happen with wrong pi-model
data imported from RSPF or SPEF RNETs.

Example of Reduced SPEF syntax:

Figure 6: Reduced Pi Model

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[Link] Unconnected from-pin

Warning: Failed to compute C-effective for the timing arc (xx/yyy) i1/A-->Z
(rising positive-unate) because from-pin is unconnected[r/f inp_slew =
0.028226/0.028226, out_cap = 0.003015 (lib units)] (RC-004)

This can only happen if one of the drivers on a multi-driven net has an unconnected from-pin. In that case,
there is also a LNK-22 warning for the unconnected input and an RC-007 because of the multi-drive
structure.

3.3.2 Rd override -RC-009:

Warning: The drive-resistance for the timing arc (xxx/yy) buf3/A-->Z (falling
positive-unate) is much less than the network impedance to ground; PrimeTime has
adjusted the drive-resistance to improve accuracy. (RC-009)

As previously mentioned, the driver model consists of a voltage ramp in series with a resistor. The resistor
helps smooth out the voltage ramp so that the resulting driver waveform has similar curvature to that of an
actual transistor driver. An Rd adjustment takes place when the two following conditions are verified:

[Link] First condition: Rd << Znet

U1 U2

PrimeTime detects that Znet is greater

than Rd and adjusts the driver model to
Waveforms improve accuracy.
at net
input
SDM

Rd=small U2

V(t)
Thevenin
Source

Figure 7: RC-009 case: first condition

When the drive resistor is much less than the impedance of the network to ground, the smoothing effect is
reduced, causing RC delay calculation to be potentially inaccurate. This condition can occur when a very
strong driver is connected to a very resistive network. When the library-derived drive resistance is much less
than the network’s dynamic impedance to ground, PrimeTime overrides Rd to improve accuracy.

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By default, PrimeTime obtains extra pessimism in min analysis mode by not using slew-degradation.

[Link] Second condition- Net Delay > driver slew

Net input waveform

t70

t50

Net output waveform

t30

Network delay

Driver transition
time
Figure 8: RC-009 case: second condition

By default, this adjustment and the warning only take place when in addition to the first condition; the net
delay is greater than the driver slew, because it is in this case that the loss of accuracy occurs. Indeed this is
expected because the network delay depends upon the driver waveform near and beyond the later slew trip-
point. This is precisely the aspect of the waveform most affected by the drive resistance.
This is controlled with the shell variable rc_filter_rd_less_than_rnet.. See man page for more information
on that variable.

[Link] Quality of parasitic extraction

Finally, users should be very aware that Znet is greatly affected by the quality of parasitic extraction. The
default behavior assumes a well-distributed RC network. However, thousands of RC-009 messages may
appear when very resistive nets have been extracted with a relatively small number of RC segments. In this
case, Znet increases as the number of RC segments is reduced for a given network. PrimeTime can perform
more and more accurate calculation if the parasitic network is extracted with greater and greater detail (i.e. it
is more distributed). A more distributed network (i.e. increased number of RC segments) can typically be
extracted by decreasing the value of the maximum line segment length parameter. Eliminating the use of
reduction algorithms in the extraction tool can also lead to a more distributed network. With a more
distributed and detailed parasitic network, Znet will decrease, leading to fewer RC-009 messages and more
accurate results from PrimeTime.

The RC-009 mechanism is controlled by a threshold parameter value that assumes high-resolution RC
extraction (i.e. many RC segments for very resistive nets). If low-resolution RC is used, then be sure to set
rc_filter_rd_less_than_rnet true to avoid too many RC-009 messages.

[Link] What to do next?

This condition does not arise out of a problem with library data. When this condition occurs, PrimeTime
adjusts the drive resistance to improve accuracy. However, note that even with this adjustment, the resulting
accuracy might be insufficient.

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For users who are concerned with extremely high accuracy and wish to calculate the difference between
PrimeTime's driver and network timing results compared to transistor simulation (SPICE), these messages
can be used to pinpoint areas to investigate to determine the accuracy of the empirical driver models.
Notice usage of CCS models gets rid of this accuracy issue.

Otherwise, the RC-009 messages can be safely suppressed. Use the command 'suppress_message RC-009'.

3.4 Net arc warnings

The PrimeTime delay calculator uses a Reduced Order Model to model the behavior of the network. The
following warnings are related to some failure in the network calculation.
3.4.1 RC-005 Warning: Calculation Failure
Warning: Failed to compute the RC network delay
from the pin 'xxx/yy'
to the pin 'zzz/x'
in the network 'xx'. (RC-005)

Depending on which other warnings are produced by the delay calculator, you can find the reason why this
warning is showing up.

[Link] Unsupported multi-drive condition

In this case, there is also an RC-002 warning. See section 3.5.1 for more details.
PrimeTime only supports multi-drive conditions where the drivers are all wired in parallel. If this warning
occurs, either apply case analysis to disable unsupported arcs, modify the design to use the supported
topology, or annotate delays and slews on the unsupported arcs. The delays and slews can be measured in a
SPICE simulation and can be annotated with the set_annotated_delay and set_annotated_transition
commands in PrimeTime. See man pages for more information on these commands.

[Link] No timing arcs

Dead-end nets (i.e. those with only drivers or only loads) can be created; reporting to or from pins on such
nets can cause this message. You can ignore these messages.

[Link] Under-driven network

Extremely under-driven nets (e.g. one clock buffer connected to hundreds of clock pins) may not converge to
one of the waveform trip-points. This sometimes occurs before layout for nets (for example, clock trees)
when buffer insertion has not yet been performed. You can annotate delays and slews on nets to be replaced
with post-layout clock buffer trees.

[Link] Slew propagation

The worst_arrival slew propagation mode only analyzes constrained paths. If reporting is performed on an
unconstrained path, the RC-005 message is issued. Use the report_delay_calculation command or disable
worst-arrival slew propagation with the shell variable timing_slew_propagation_mode.

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[Link] Incompatible Voltage Swings

The PrimeTime delay calculator can handle a network between two cells belonging to libraries with different
trip-points. If the PrimeTime delay calculator fails to calculate the network in this situation, it may be due to
an incorrect setup of the rc_xxx variables (trip points) or power rail. If the correct values were not specified in
the source of the library, Library Compiler uses a set of default values, possibly resulting in the calculation
failure. Notice that the default power rail will be 5.00 if nom_voltage is not specified like this:

nom_process: 1.5;
nom_voltage : 1.62;
nom_temperature : 105.
Use:

pt_shell> report_delay_calculation –from <driving cell/output> -to <load/input> -threshold

From pin: xxx/yy

To pin: zzz/x
Main Library Units: 1ns 1pF 1kOhm

arc sense: unate

arc type: net

Library Rise Rise Fall Fall Slew Rail

Thresholds: Delay Slew Delay Slew Derate Voltage
----------------------------------------------------------------
from-pin 40 10->90 50 90->10 1.000 1.550
to-pin 50 20->80 50 80->20 1.000 5.000
Warning: Failed to compute the RC network delay
from the pin 'xxx/yy'
to the pin 'zzz/x'
in the network 'div_0/fsm_inst/lowphase'. (RC-005)
Warning: The type of RC delay calculation problems that
has just occured prevents the max results from bounding
the correct values. (RC-008)
Using lump net delay because the calculation with detailed RC failed.
Balanced case tree
RC delay: (r_wire/load_count) * (c_pin + c_wire/load_count)
rise: (0.0422141 / 1) * (0.0072 + (0.035859 / 1))
fall: (0.0422141 / 1) * (0.0072 + (0.035859 / 1))

Rise delay = 0.0018177

Fall delay = 0.0018177

In this example, we can obviously see that the Rail Voltage of the second library is erroneous.
You have to correct the library or use the main library set of trip-points by setting the variable:
lib_thresholds_per_lib to false (see man page for more information).

This appears as the most common condition for RC-005: the lib_thresholds_per_lib variable is true
and the driver voltage swing does not cover all the trip-points of a load pin.

Another common cause of this problem is using a library without a default operating condition. When this
occurs, you can either fix the library or use the set_operating_conditions command on the affected cells.

3.5 Multi-Drive Warnings

3.5.1 Incomplete driver coverage (RC-002)
Warning: The net 'A1' controls only a subset of the drivers of

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the multi-driven net 'IA1', so detailed RC delay calculation cannot be used. (RC-
002)

This RC-002 message indicates that net A1 is controlling the switching activity of only a subset of the drivers
of a multi-driven net. The switching activity of the remaining drivers is uncertain, so detailed RC delay
calculation cannot be used. A from-net (A1 in this case) does not cover all of the drivers on a multi-driven
net. This multi-drive condition is unsupported by PrimeTime. Instead, the load is assumed to be the total
capacitance of the multi-driven net divided by the number of drivers. Ensure all drivers are switched by each
from-net (i.e. that they are wired in parallel), or annotate delays and transition times if you seek greater
accuracy than the lumped fallback analysis can provide.
You may have RC-005 warning as well, as described in section [Link]. However, unsupported multi-drive
conditions will fail cell-arc delay calculation, but a valid driver-model is built for the fallback data at
Ctotal/zero and is used to drive the net. The RC-005 message is for problems specific to net delay calculation
only.
There can be an RC-008 message as well: see section 3.6 for more information.

Non supported: Warning DES-023,

RC-002, RC-005

Supported: Warning DES-023

Figure 9: Unsupported/Supported Examples

3.5.2 Degenerate driver coverage (RC-003)

Warning: The net 'A1' connects to more than one pin on a driver
of the multi-driven net 'Z', so detailed RC delay calculation cannot be
used. (RC-003)

This message indicates that a net connects to more than one pin on a driver of the multi-driven net. Therefore,
detailed RC delay calculation cannot be used. Instead, the load is assumed to be the total capacitance of the
multi-driven net divided by the number of drivers.

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Figure 10: Unsupported RC-003 and Unsupported RC-002 Examples

3.5.3 Calculation failure (RC-007)

Warning: Failed to compute C-effective for the multi-driven net 'xxx/yy' driven
by cell arcs controlled by the from-net 'xxx/y' (RC-007)
This message indicates that multiple drivers are switching faster than the library delay at zero output
capacitance. This is a limitation of the current PrimeTime driver model. In max analysis mode, the C-zero
fallback is used, but in min analysis mode, there is no valid fallback. For accurate analysis, annotate the
delays and slew. See man page for more information.

3.6 Min/Max Bounds Warning (RC-008)

Warning: The type of RC delay calculation problems that
has just occured prevents the max results from bounding
the correct values. (RC-008)

In case of one of the previously described failures, a fallback calculation has been selected to guarantee a
conservative analysis: C-total is used in max analysis mode and C-zero min analysis mode. However if
PrimeTime cannot determine that these fallback values are pessimistic, then it issues an RC-008 message. So
this is a supplemental warning that may be due for example to a multi-driven network switching faster than
the min delay for this cell or in case of a library extrapolation problem that would return a negative slew.
Users should fix the problems associated with the earlier delay calculation warnings, or fix the library or use
annotated delay and slew information obtained by circuit simulation.

4 Conclusion
This document can help you efficiently analyze, understand, and debug the most frequent issues encountered
in PrimeTime analysis with back-annotated detailed parasitics. All the errors and warnings described here can
result in the loss of accuracy and pessimism in the analysis, so it is important to carefully examine them. If

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the existing data structure is unsupported and unavoidable, it is recommended that you use annotated delay
and slew information obtained by circuit simulation.

5 Recommended Reading
The following documents are recommended for a deeper understanding of PrimeTime’s RC Delay Calculator.
Please contact your Synopsys Applications Consultant for a copy.

[1] “Understanding Delay Calculation with Detailed Parasitics in PrimeTime”, PrimeTime white paper
from Synopsys, Inc.
[2] “Library Qualification Guidelines for PrimeTime”, PrimeTime Application Note, Synopsys, Inc.

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Appendix A: Example of how to debug RC-004

warning type described in section [Link]

If the PrimeTime delay calculator gives an RC-004 failure calculation message as described in step 1, you can
analyze the potential issues for the cell:
• Is this cell used within the boundaries of the library table (as required in section 2.2.3)?
• Does the cell have monotonic behavior (as required in section [Link])?

Step 1:
Look at one of the RC-004 messages from the log file:

Warning: Failed to compute C-effective for the timing arc

(custom_arrays/dual_64x64_ram_con0)
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1
/p1_clk-->p1_rd_data[29] (rising falling)
because the library data indicates a non-positive drive resistance.
[r/f inp_slew = 0/0, out_cap = 0.0784132 (lib units)] (RC-004)

Step 2:
pt_shell> remove_annotated_parasitics

This will remove the detailed parasitics

Step 3:
pt_shell> set_annotated_transition -rise 0.0 ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_clk
pt_shell> set_annotated_transition -fall 0.0 ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_clk

We annotate the transition time that shows up in the warning message

Step 4:
pt_shell> set_load -subtract_pin_load 0.0784132 [get_nets -of_object \
[get_pins ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]]]

We annotate the load that shows up in the warning message. We subtract the pin loads because PrimeTime
adds them automatically.

Step 5:
pt_shell> report_delay_calculation -from_rise 0.0 -from_fall 0.0 –from \
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_clk –to \
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]

Step 6:
set_load -subtract_pin_load [expr 0.0784132*1.01] [get_nets -of_object \
[get_pins ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]]]

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We increase the load by 1%.

Step7:
report_delay_calculation -from_rise 0.0 -from_fall 0.0 –from \
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_clk –to \
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]

We look at the impact of this load increase on the cell delay.

Step8:
Look at the reports from the delay calculations:

Reports from Step 5:

Report : delay_calculation
Design : np
Version: 2002.03
Date : Wed Apr 4 [Link] 2002

From pin: ivq/ivq_comp_fi_fo0/ivq_comp_fifo_ml/pl_clk

To pin: ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]
Main Library Units: 1ns 1pF 1kOhm
Library: ‘custom_arrays’
Library Units: 1ns 1pF 1kOhm

Library Cell: ‘dual_64x64_ram_con0’

arc sense: falling_edge
arc type: cell
Units: 1ns 1pF 1kOhm

Rise Delay

cell delay = 1.2892

Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0784132
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 1.3290 (Z) 1.3530
(Y) 0.1320 (Z) 1.3530 (Z) 1.4850

Z = A + B*X + C*Y + D*X*Y

A = 1.3890 B = -0.9333
C = -1.2727 D = 18.1818

Z = 1.2892
scaling result for operating conditions
multiplying by 1 gives 1.2892

Fall Delay

cell delay = 1.2892

Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0784132
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 1.3290 (Z) 1.3530
(Y) 0.1320 (Z) 1.3530 (Z) 1.4850

Z = A + B*X + C*Y + D*X*Y

A = 1.3890 B = -0.9333

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C = -1.2727 D = 18.1818

Z = 1.2892
scaling result for operating conditions
multiplying by 1 gives 1.2892

Cell Delay
rise: 1.2892
fall: 1.2892

Rise delay = 1.2892

Fall delay = 1.2892

Units: 1ns 1pF 1kOhm

Transition rise
transition = 0.0834543
Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0784132
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 0.0730 (Z) 0.0680
(Y) 0.1320 (Z) 0.1030 (Z) 0.0990

Z = A + B*X + C*Y + D*X*Y

A = 0.0490 B = -0.0667
C = 0.4394 D = 0.1683

Z = 0.0834543
scaling result for operating conditions
multiplying by 1 gives 0.0834543

Transition fall
transition = 0.0834543
Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0784132
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 0.0730 (Z) 0.0680
(Y) 0.1320 (Z) 0.1030 (Z) 0.0990

Z = A + B*X + C*Y + D*X*Y

A = 0.0490 B = -0.0667
C = 0.4394 D = 0.1683

Z = 0.0834543
scaling result for operating conditions
multiplying by 1 gives 0.0834543

Rise transition = 0.0834543

Fall transition = 0.0834543
Annotated max rise absolute transition: 0 pin transition: 0
Annotated max fall absolute transition: 0 pin transition: 0

Report from Step 7:

Report : delay_calculation
Design : np
Version: 2002.03
Date: Wed Apr 4 [Link] 2002

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>From pin: ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_clk

To pin:
ivg/ivg_comp_fifo0/ivg_comp_fifo_m1/p1_rd_data[29]
Main Library Units: 1ns 1pF 1kOhm

Library: ‘custom_arrays’
Library Units: 1ns 1pF 1kOhm
Library Cell: ‘dual_64x64_ram_con0’
arc sense: falling_edge
arc type: cell
Units: 1ns 1pF 1kOhm

Rise Delay

cell delay = 1.2882

Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0791973
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 1.3290 (Z) 1.3530
(Y) 0.1320 (Z) 1.3530 (Z) 1.4850

Z = A + B*X + C*Y + D*X*Y

A = 1.3890 B = -0.9333
C = -1.2727 D = 18.1818

Z = 1.2882
scaling result for operating conditions
multiplying by 1 gives 1.2882

Fall Delay

cell delay = 1.2882

Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0791973
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 1.3290 (Z) 1.3530
(Y) 0.1320 (Z) 1.3530 (Z) 1.4850

Z = A + B*X + C*Y + D*X*Y

A = 1.3890 B = -0.9333
C = -1.2727 D = 18.1818

Z = 1.2882
scaling result for operating conditions
multiplying by 1 gives 1.2882

Cell Delay
rise: 1.2882
fall: 1.2882

Rise delay = 1.2882

Fall delay = 1.2882

Units: 1ns 1pF 1kOhm

Transition rise
transition = 0.0837988
Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0791973

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Relevant portion of lookup table:

(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 0.0730 (Z) 0.0680
(Y) 0.1320 (Z) 0.1030 (Z) 0.0990

Z = A + B*X + C*Y + D*X*Y

A = 0.0490 B = -0.0667
C = 0.4394 D = 0.1683

Z = 0.0837988
scaling result for operating conditions
multiplying by 1 gives 0.0837988

Transition fall
transition = 0.0837988
Table is indexed by
(X) input_pin_transition = 0
(Y) output_net_total_cap = 0.0791973
Relevant portion of lookup table:
(X) 0.0900 (X) 0.1800
(Y) 0.0660 (Z) 0.0730 (Z) 0.0680
(Y) 0.1320 (Z) 0.1030 (Z) 0.0990

Z = A + B*X + C*Y + D*X*Y

A = 0.0490 B = -0.0667
C = 0.4394 D = 0.1683

Z = 0.0837988
scaling result for operating conditions
multiplying by 1 gives 0.0837988

Rise transition = 0.0837988

Fall transition = 0.0837988
Annotated max rise absolute transition: 0 pin transition: 0
Annotated max fall absolute transition: 0 pin transition: 0

Step 9: Analysis and Conclusion

From the above two reports, we observe that with a 1% increase of load (0.0784132*1.01), rise/fall delay
decreased (from 1.2892 to 1.2882), which is wrong. The behavior of this cell is non-monotonic, which means
that the delay doesn’t increase (decreases or stays the same) with increasing load. Therefore, the PrimeTime
delay calculator cannot find a correct driver model since the resulting Rd is negative. See section [Link] for
more information on the driver model.

Furthermore, from the report you will also notice the following portion of the lookup table:

(X) 0.0900 (X) 0.1800

(Y) 0.0660 (Z) 1.3290 (Z) 1.3530
(Y) 0.1320 (Z) 1.3530 (Z) 1.4850

which says that (X), meaning the input pin transition, started from 0.0900, whereas in our case (look at the
RC-004 message) it is 0.0, which is outside of the above table. So the cell is not used in its characterization
range, and some extrapolation inaccuracy is expected. A cell must always been used in its characterization
range. See section 2.2.2 for more information on the characterization range.
These issues can also been analyzed by the Liberty Screener: see Appendix C for more information.

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Appendix B: Parallel Driver Reduction

Because clock signals must typically drive a large number of loads, clocks are often buffered to provide the
drive strength necessary to reduce clock skew to an acceptable level. A large clock network might use a large
number of drivers operating in parallel. These drivers can be organized in a “mesh” or “spine” pattern to
distribute the signal throughout the chip. If a design has 1,000 drivers in parallel driving 1,000 loads,
PrimeTime must keep track of one million different timing arcs between the drivers and loads. Timing
analysis of such a network can consume a large amount of CPU and memory resources.
For better performance, PrimeTime can reduce the number of timing arcs that must be analyzed. When the
reduction feature is enabled, PrimeTime selects one driver in a parallel network and analyzes the timing arcs
through that driver only.

Invoking Parallel Driver Reduction

Parallel driver reduction is controlled by the following variables:

• timing_reduce_multi_drive_net_arcs
• timing_reduce_multi_drive_net_arcs_threshold

The first of these two variables can be set to true or false to enable or disable parallel driver reduction. By
default, it is set to false and no reduction is done. When it is set to true, during design linking,
PrimeTime checks for the presence of nets with multiple drivers. If it finds a net with driver-load
combinations exceeding the threshold specified by the threshold variable, it reduces the number of timing arcs
associated with the drivers of that net.
The threshold variable specifies the minimum number of timing arcs that must be present in order to trigger a
reduction. By default, it is set to 10,000, which means that PrimeTime reduces the timing arcs of a net if the
number of drivers multiplied by the number of loads on the net is more than 10,000. In typical designs, this
large number only occurs in clock networks.
PrimeTime performs driver reduction for a net when all of the following conditions are true:

• The number of driver-load combinations is more than the variable-specified threshold (10,000 by default).
• The driver cells are nonsequential library cells (not flip-flops or latches and not hierarchical).
• All drivers of the net are instances of the same library cell.
• All the drivers are connected to the same input and output nets.

To expand a collapsed network to its original form or to perform driver

reduction with a different threshold, you must relink the design.

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Working With Collapsed Drivers

After layout is complete and detailed parasitic information becomes available, it is not possible to annotate
this information on a reduced network. To get accurate results, you can use an external simulator such as
SPICE to get detailed delay information for the network.
Then you can annotate the clock latency values and transition times on the individual clock pins of the
sequential cells, while still allowing PrimeTime to treat the reduced network as ideal, with zero delay.
This technique provides reasonably accurate results, while being very efficient because the clock network
timing only needs to be analyzed once, even for multiple PrimeTime analysis runs.
If you back-annotate the design with the read_sdf command, any annotations on the reduced timing arcs are
ignored. PrimeTime issues a PTE-048 informational message when this happens. You can suppress these
messages with the following command:

pt_shell> suppress_message PTE-048

If you write out SDF with the write_sdf command, no interconnect delays are generated for the reduced
network.
Reducing parallel drivers only affects the timing arcs analyzed by PrimeTime, not the netlist. Therefore, it
does not affect the output of the write_changes command.

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Appendix C: Synopsys Liberty Screener

The Liberty Screener is a utility available to check libraries. You must have access to the library source in
order to use this tool. Please note that the settings in the Liberty Screener should be adjusted to adapt to your
particular technology.

Please contact your Synopsys Applications Consultant for information on how to obtain the Liberty Screener.

Table1: Liberty Screener Features

Monotonically • Screen non-monotonic delay/slew arcs in library
increasing values • Plot delay/slew vs. load for all non-monotonic arcs
• Output PrimeTime test cases for all non-monotonic
delay/slew arcs

Accuracy of library • Links to .lib for all reported arcs

• Interpolate values in tables. Users have to compare the interpolation
results against SPICE simulations and check for interpolation error.

Number of significant • Check whether table values have enough significant digits
digits

Range of indices • Screen potential table extrapolations

• Check table size
• Check the minimum input slew

Usage:

libscr <options> -lib lib_file

Options for screening:

-check_mono : screen non monotonic delay arcs
-check_minc : screen bad min capacitance design rules
-check_maxc : screen bad max capacitance design rules
-check_maxt : screen bad max transition design rules
-check_tsize : screen delay tables with less than recommended size (7x7)
-check_sd : screen delay table values with less than recommended (5)
number of significant digits
-check_sip : screen delay tables whose starting index point is more
than recommended (0.0, 0.0)
If none of the -check_* option is given, then by default all checks are performed.

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Example:

libscr -lib [Link] -out [Link]

[Link]
Non Monotonic Delay Arcs
[Link]: GENLIB (3 cells)
# .lib Line# Cell Arc Input Slope
1 301 AN2 A -> Z, combinational, cell_rise 2.3
WARNING: Found 1 Non Monotonic Arcs
Bad Design Rules
[Link]: GENLIB (3 cells)
# .lib Line# Cell Arc Load Range Slope Range
Max Cap Max Trans
Delay Table Sizes
[Link]: GENLIB (3 cells)
# .lib Line# Table Name Table Size Recommended
1 213 table_1 4x4 7x7
2 219 table_10 3 7
(…)

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