HT24LC04

4K 2-Wire CMOS Serial EEPROM

Features
• Operating voltage: 2.4V~5.5V • Patial page write allowed
• Low power consumption • 8-byte Page write modes
– Operation: 5mA max. • Write operation with built-in timer
– Standby: 5µA max. • Hardware controlled write protection
• Internal organization • 40-year data retention
– 4K (HT24LC04): 512×8 • 106 erase/write cycles per word
• 2-wire serial interface • 8-pin DIP/SOP/TSSOP package
• Write cycle time: 5ms max. • Commerical temperature range
• Automatic erase-before-write operation (0°C to +70°C)

General Description
The HT24LC04 is a 4K-bit serial read/write low power and low voltage operation are essen-
non-volatile memory device using the CMOS tial. Up to four HT24LC04 devices may be con-
floating gate process. Its 4096 bits of memory nected to the same two-wire bus. The
are organized into 512 words and each word is HT24LC04 is guaranteed for 1M erase/write
8 bits. The device is optimized for use in many cycles and 40-year data retention.
industrial and commercial applications where

Block Diagram Pin Assignment

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Pin Description
Pin No. Pin Name I/O Description
1~3 A0~A2 I Address inputs
4 VSS — Negative power supply
5 SDA I/O Serial data inputs/output
6 SCL I Serial clock data input
7 WP I Write protect
8 VCC I Positive power supply

Absolute Maximum Ratings

Operating Temperature (Commercial) ................................................................................. 0°C to 70°C
Storage Temperature ....................................................................................................... –50°C to 125°C
Applied VCC Voltage with Respect to VSS ........................................................................ –0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS .................................................................. –0.3V to VCC+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-
mum Ratings” may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.

D.C. Characteristics Ta=0°C to 70°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage — — 2.4 — 5.5 V
ICC1 Operating Current 5V Read at 100kHz — — 2 mA
ICC2 Operating Current 5V Write at 100kHz — — 5 mA
VIL Input Low Voltage — — –1 — 0.3VCC V
VIH Input High Voltage — — 0.7VCC — VCC+0.5 V
VOL Output Low Voltage 2.4V IOL=2.1mA — — 0.4 V
ILI Input Leakage Current 5V VIN=0 or VCC — — 1 µA
ILO Output Leakage Current 5V VOUT=0 or VCC — — 1 µA
ISTB1 Standby Current 5V VIN=0 or VCC — — 5 µA
ISTB2 Standby Current 2.4V VIN=0 or VCC — — 4 µA
CIN Input Capacitance (See Note) — f=1MHz 25°C — — 6 pF
COUT Output Capacitance (See Note) — f=1MHz 25°C — — 8 pF

Note: These parameters are periodically sampled but not 100% tested

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A.C. Characteristics Ta=0°C to 70°C

Standard Mode* VCC=5V±10%

Symbol Parameter Remark Unit
Min. Max. Min. Max.
fSK Clock Frequency — 100 — 400 kHz
tHIGH Clock High Time 4000 — 600 — ns
tLOW Clock Low Time 4700 — 1200 — ns
tR SDA and SCL Rise Time Note — 1000 — 300 ns
tF SDA and SCL Fall Time Note — 300 — 300 ns
After this period
START Condition Hold
tHD:STA the first clock pulse 4000 — 600 — ns
Time
is generated
Only relevant for
START Condition
tSU:STA repeated START 4000 — 600 — ns
Setup Time
condition
tHD:DAT Data Input Hold Time 0 — 0 — ns
tSU:DAT Data Input Setup Time 200 — 100 — ns
STOP Condition Setup
tSU:STO 4000 — 600 — ns
Time
Output Valid from
tAA — 3500 — 900 ns
Clock
Time in which the
bus must be free
tBUF Bus Free Time before a new 4700 — 1200 — ns
transmission can
start
Input Filter Time
Noise suppression
tSP Constant (SDA and SCL — 100 — 50 ns
time
Pins)
tWR Write Cycle Time — 5 — 5 ms

Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means V CC=2.4V to 5.5V
For relative timing, refer to timing diagrams

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Functional Description
• Serial clock (SCL) line is high. Changes in data line while the
The SCL input is used for positive edge clock clock line is high will be interpreted as a
data into each EEPROM device and negative START or STOP condition.
edge clock data out of each device. • Start condition
• Serial data (SDA) A high-to-low transition of SDA with SCL high
The SDA pin is bidirectional for serial data is a start condition which must precede any
transfer. The pin is open-drain driven and other command (refer to Start and Stop Defi-
may be wired-OR with any number of other nition Timing diagram).
open-drain or open collector devices. • Stop condition
• A0, A1, A2 A low-to-high transition of SDA with SCL high
The HT24LC04 uses the A2 and A1 inputs for is a stop condition. After a read sequence, the
hard wire addressing and a total of four 4K stop command will place the EEPROM in a
devices may be addressed on a single bus standby power mode (refer to Start and Stop
system. The A0 pin is not connected. (The Definition Timing Diagram).
device addressing is discussed in detail under • Acknowledge
the Device Addressing section).
All addresses and data words are serially
• Write protect (WP) transmitted to and from the EEPROM in 8-bit
The HT24LC04 has a write protect pin that words. The EEPROM sends a zero to acknow-
provides hardware data protection. The write ledge that it has received each word. This
protect pin allows normal read/write opera- happens during the ninth clock cycle.
tions when connected to the VSS. When the
write protect pin is connected to Vcc, the write
protection feature is enabled and operates as
shown in the following table.
WP Pin Protect Array
Status HT24LC04
At VCC Full Array (4K)
At VSS Normal Read/Write Operations
Device addressing
Memory organization
The 4K EEPROM devices require an 8-bit de-
• HT24LC04, 4K Serial EEPROM vice address word following a start condition to
Internally organized with 512 8-bit words, enable the chip for a read or write operation.
random word addressing requires a 9-bit data The device address word consist of a mandatory
word address. one, zero sequence for the first four most signifi-
cant bits (refer to diagram showing the Device
Device operations Address). This is common to all the EEPROM
device.
• Clock and data transition
The next three bits are the A2, A1 and A0 device
Data transfer may be initiated only when the
address bits for the 1K/2K EEPROM. These
bus is not busy. During data transfer, the data
three bits must compare to their corresponding
line must remain stable whenever the clock
hard-wired input pins.

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The 4K EEPROM only use the A2 and A1 device • Page write

address bits with the third bit as a memory The 4K device is capable of 16-byte page writes.
page address bit. The two device address bits
A page write is initiated the same as byte
must compare to their corresponding hardwired
write, but the microcontroller does not send a
input pins. The A0 pin is not connected.
stop condition after the first data word is
The 8th bit of device address is the read/write clocked in. Instead, after the EEPROM ac-
operation select bit. A read operation is initi- knowledges the receipt of the first data word,
ated if this bit is high and a write operation is the microcontroller can transmit up to fifteen
initiated if this bit is low. more data words. The EEPROM will respond
If the comparison of the device address succeed the with a zero after each data word received. The
EEPROM will output a zero at ACK bit. If not, the microcontroller must terminate the page
chip will return to a standby state. write sequence with a stop condition.
The data word address lower four bits are
internally incremented following the receipt
of each data word. The higher data word ad-
dress bits are not incremented, retaining the
Write operations memory page row location (refer to Page write
timing).
• Byte write
• Acknowledge polling
A write operation requires an 8-bit data word
address following the device address word Since the device will not acknowledge during
and acknowledgment. Upon receipt of this ad- a write cycle, this can be used to determine
dress, the EEPROM will again respond with a when the cycle is complete (this feature can be
zero and then clock in the first 8-bit data used to maximize bus throughput). Once the
word. After receiving the 8-bit data word, the stop condition for a write command has been
EEPROM will output a zero and the address- issued from the master, the device initiates
ing device, such as a microcontroller, must the internally timed write cycle. ACK polling
terminate the write sequence with a stop con- can be initiated immediately. This involves
dition. At this time the EEPROM enters an the master sending a start condition followed
internally-timed write cycle to the non-vola- by the control byte for a write command
tile memory. All inputs are disabled during (R/W=0). If the device is still busy with the
this write cycle and EEPROM will not re- write cycle, then no ACK will be returned. If
spond until the write is completed (refer to the cycle is completed, then the device will
Byte write timing). return the ACK and the master can then pro-
ceed with the next read or write command.

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• Write protect

The HT24LC04 can be used as a serial ROM

when the WP pin is connected to VCC. Pro-
gramming will be inhibited and the entire
memory will be write-protected.
• Read operations
Read operations are initiated the same way as
write operations with the exception that the
read/write select bit in the device address
word is set to one. There are three read opera-
tions: current address read, random address
read and sequential read.
• Current address read
The internal data word address counter main-
tains the last address accessed during the last
read or write operation, incremented by one.
Acknowledge polling flow
This address stays valid between operations
as long as the chip power is maintained. The
• Random read
address roll over during read from the last
byte of the last memory page to the first byte A random read requires a dummy byte write
of the first page. The address roll over during sequence to load in the data word address
write from the last byte of the current page to which is then clocked in and acknowledged by
the first byte of the same page. Once the de- the EEPROM. The microcontroller must then
vice address with the read/write select bit set generate another start condition. The micro-
to one is clocked in and acknowledged by the controller now initiates a current address
EEPROM, the current address data word is read by sending a device address with the
serially clocked out. The microcontroller does read/write select bit high. The EEPROM ac-
not respond with an input zero but generates knowledges the device address and serially
a following stop condition (refer to Current clocks out the data word. The microcontroller
read timing). does not respond with a zero but does gener-
ates a following stop condition (refer to Ran-
dom read timing).

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• Sequential read words. When the memory address limit is

Sequential reads are initiated by either a cur- reached, the data word address will roll over
rent address read or a random address read. and the sequential read continues. The se-
After the microcontroller receives a data word, quential read operation is terminated when
it responds with an acknowledgment. As long as the microcontroller does not respond with a
the EEPROM receives an acknowledgment, it zero but generates a following stop condition
will continue to increment the data word ad- (refer to Sequential read timing).
dress and serially clock out sequential data

Timing Diagrams

Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end
of the valid start condition of sequential command.

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Holtek Semiconductor Inc. (Headquarters)

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Copyright © 1999 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present
a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at [Link]

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