Date: 10-07-2019

From
Mrs. P. Merlin Viji,
Course Coordinator & Asst. Professor of Dept. of Electronics and Communication Engineering,
Vins Christian College of Engineering,
Chunkankadai.
To

The Principal,
Vins Christian College of Engineering,
Chunkankadai.
Sub: Requesting approval to conduct the value-added course –reg

Respected Sir,
It is brought to your kind notice that, we have planned to conduct a value-added course for our B.E –
ELECTRONICS AND COMMUNICATION ENGINEERING students of the current academic year- 2019-2020
(ODD Semester). The Value-added course details are below.
Academic year : 2019-2020
Year / Sem : II / 03, III / 05 & IV / 07
Course Code/ Course Name : DPAECE– DSP PROCESSORS AND ITS APPLICATIONS
Duration : 08.07.2019 to 13.07.2019
Total Number of Hours : 33 Periods
Course Coordinators : Mrs. P. Merlin Viji (9629065) Mrs. S. Abija Sherin (9629049)
Assistant Professor, Assistant Professor,
Dept. of Electrical and Dept. of Electrical and
Electronics Engineering. Electronics Engineering.
We enclosed the proposal of course details with course contend for your reference. We seek your kind
permission to conduct this value-added course for the betterment of students.
Thank You
Yours Truly,

(Mrs. P. Merlin Viji)

Course Coordinator
Approval / Remarks
Forwarded / NOT Recommended / NOT Approved / NOT

Head of the Department IQAC – Coordinator Principal

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
PROPOSAL OF VALUE ADDED COURSE

1. Course Code / Title : DPAECE– DSP PROCESSORS AND ITS APPLICATIONS

The course is designed to introduce architectural features of

2. Objective of the course : programmable DSP Processors of TI - Analog Devices and to
develop the programming knowledge using Instruction set of
DSP Processors.

Basic Knowledge about analog devices and to

3. Prerequisite :
programming

4. Beneficiary : 03rd, 05th & 7th Semester ECE Students

5. Date & Duration of the course :

08.07.2019 to 13.07.2019

6 No. of hours required : 33 Hours

7 Proposed timings : 9.30 AM TO 4.00 PM

1. Mrs. P. Merlin Viji, Assistant Professor / ECE

8. Internal Resources :
2. Mrs. S. Abija Sherin, Assistant Professor / ECE

9. Internal Assessment : Objective Type Test

10. Course Registration fee : NIL
11. Contents of the course : Enclosed separately
Those who have 75% attendance and scored 50%marks
12. Credits / Certification :
will be eligible for certification.
13. Venue : ECE Department – MM Laboratory

COURSE COORDINATOR HEAD OF THE DEPARTMENT

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SYLLABUS
DPAECE DSP PROCESSORS AND ITS APPLICATIONS L T P
1 0 1
Goal:
To clarify or standardize digital signals, but it can also perform various other tasks, such as filtering,
compression and modulation.
Course Objective: The course should enable the students to:
To introduce architectural features of programmable DSP Processors of TI and Analog Devices.
To recall digital transform techniques.
To give practical examples of DSP Processor architectures for better understanding.
Course Outcome: The students should be able to:
To distinguish between the architectural features of general purpose processors and DSP processors
Understand the architectures of TMS 320C54XX and ADSP2100 DSP devices
Able to write assembly language programs using instruction set of TMS320C54XX

Module – Introduction to Digital Signal Processing 6 Hours

Introduction, A Digital signal-processing system, The sampling process, Discrete time sequences. Discrete Fourier
Transform (DFT) and Fast Fourier Transform (FFT), Linear time- invariant systems, Digital filters, Decimation and
interpolation.
Module – II Architectures for Programmable DSP Devices 6 Hours
Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing
Capabilities, Address Generation UNIT, Programmability and Program Execution, Speed Issues, Features for
External interfacing.
Module – III Programmable Digital Signal Processors 6 Hours
Commercial Digital signal-processing Devices, Data Addressing modes of TMS320C54XX DSPs, Data Addressing
modes of TMS320C54XX Processors, Memory space of TMS320C54XX Processors, Program Control,
TMS320C54XX instructions and Programming, On-Chip Peripherals, Interrupts of TMS320C54XX processors,
Pipeline operation of TMS320C54XX Processors.
Module – IV Analog Devices Family of DSP Devices 6 Hours
Analog Devices Family of DSP Devices – ALU and MAC block diagram, Shifter Instruction, Base Architecture of
ADSP 2100, ADSP-2181 high performance Processor.
Module – V Interfacing Memory and I/O Peripherals to Programmable DSP Devices 6 Hours
Memory space organization, External bus interfacing signals, Memory interface, Parallel I/Ointerface, Programmed
I/O, Interrupts and I/O, Direct memory access (DMA).

Course Assessment Test for 100 Marks – 3 Hours

Website / URL References
A Practical Approach to Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran, Ananthi. S,
1
New Age International, 2006/2009
Digital Signal Processors, Architecture, Programming and Applications – B. Venkataramani and M.
2
Bhaskar, 2002, TMH.

COURSE COORDINATOR HEAD OF THE DEPARTMENT

[Link]: VCCE/ECE/2019-2020/VAC/071501 Date: 15-07-2019

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 CIRCULAR
The students from Department of ELECTRONICS AND COMMUNICATION ENGINEERING (III, V & VII
Semester) are hereby informed to enroll their names for Value added course “DPAECE– DSP
PROCESSORS AND ITS APPLICATIONS” on or before 19-07-2019.

COURSE DETAILS:
Course Duration : 33 Hours
Beneficiary : II, III & IV - Year Students of Electronics and Communication Engg.
Certificate : YES
Venue : ECE Department - Simulation Laboratory
Schedule : 22.07.2019 to 27.07.2019

Timings : 9.30 AM to 4.00 PM

HOD / ECE
Enclosed: Brochure
Copy Submitted to the Chairman, The Secretary and IQAC Cell
Copy to:
1. The Principal
2. Department Notice Board
3. All ECE Staff members
4. III, V & VII Semester EEE Students

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

RESOURCE PERSON PROFILE

Name: MERLIN VIJI P
 Courses Completed NPTEL Courses in Digital Signal Processing

Attended FDP&Workshop conducted by Various Universities,

Training programs
AICTE etc.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE PLAN
1 .Mrs. P. Merlin Viji,
DPAECE–DSP
Course Code & Name of the Assistant Professor / ECE
PROCESSORS AND ITS
Title: Faculty(s): 2 . Mrs. S. Abija Sherin ,
APPLICATIONS
Assistant Professor / ECE
Course Objective
To introduce architectural features of programmable DSP Processors of TI and Analog Devices.
To recall digital transform techniques.
To give practical examples of DSP Processor architectures for better understanding.
Course Outcome
To distinguish between the architectural features of general purpose processors and DSP processors
Understand the architectures of TMS 320C54XX and ADSP2100 DSP devices
Able to write assembly language programs using instruction set of TMS320C54XX
Lesson Plan for VAC
Ses T / R*
Sl. Period Mode of
Date sio Topic Book
No. No’s Teaching
n
1. Introduction 1 1 PPT/BB
2. A Digital signal-processing system 1 2 PPT/BB
FN
The sampling process, Discrete time
3. 1 3 PPT/BB
sequences
22 July ‘19
nd
Discrete Fourier Transform (DFT) and Fast
4. 1 4 PPT/BB
Fourier Transform (FFT)
5. AN Linear time- invariant systems 1 5 PPT/BB
6. Digital filters, Decimation and interpolation. 1 6 PPT/BB
7. 23rd July ‘19 FN Basic Architectural features 1 7 PPT/BB
 8. DSP Computational Building Blocks 1 9 PPT/BB
Address Generation UNIT, Programmability
9. 1 10 PPT/BB
AN and Program Execution
10. Speed Issues, Features for External
1 12 PPT/BB
interfacing.
11. Commercial Digital signal-processing Devices
1 13 PPT/BB
12. Data Addressing modes of TMS320C54XX
FN 1 15 PPT/BB
DSPs.
24 July ‘19
th
Data Addressing modes of TMS320C54XX
13.
17 PPT/BB
Processors
14. AN Memory space of TMS320C54XX Processors, 1 18 PPT/BB
Program Control

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE PLAN

Sl. Period Mode of

Date Session Topic T /R*
No. No’s Teaching
TMS320C54XX instructions and
15. 1 19 PPT/BB
Programming,
24 July ‘19
th
AN
On-Chip Peripherals, Interrupts of
16. 1 20 PPT/BB
TMS320C54XX processors
Analog Devices Family of DSP Devices –
17. 1 21 PPT/BB
ALU and MAC block diagram,
FN
25th July ‘19 Shifter Instruction, Base Architecture of
18. 1 22 PPT/BB
ADSP 2100
19. AN ADSP-2181 high performance Processor 1 24 PPT/BB
20. Memory space organization 1 26 PPT/BB
FN
21. External bus interfacing signals 1 27 PPT/BB
26th July ‘19 Memory interface, Parallel I/O interface,
22. 1 28 PPT/BB
Programmed I/O
AN
Interrupts and I/O, Direct memory access
23. 1 30 PPT/BB
(DMA).
27th July ‘19 FN Assessment I for 100 Marks 33
Website / URL References
A Practical Approach to Digital Signal Processing - K Padmanabhan, R. Vijayarajeswaran, Ananthi. S,
1
New Age International, 2006/2009
Digital Signal Processors, Architecture, Programming and Applications – B. Venkataramani and M.
2
Bhaskar, 2002, TMH.

Name & Sign of Faculty In-charge:

 Mrs. P. Merlin Viji Mrs. S. Abija Sherin,
Assistant Professor / ECE Assistant Professor / ECE

COURSE COORDINATOR HEAD OF THE DEPARTMENT

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

STUDENTS REGISTRATION LIST
Course Code &Title: DPAECE– DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07

[Link] Name of the Student Register Number Signature

1. MOHAMMED RASVI M R 962918106003

2. CATHERINE BIMLA J 962917106002

3. GIPSON D 962917106003

4. JAROM T 962917106004

5. JASPER JENO J 962917106005

6. KARTHICK T 962917106006

7. RAVID R V 962917106007

8. SANCHIEV K R 962917106008

9. ANUSHA J 962917106301

10. SARATH S 962918106501

11. AJI ENBA BEL S J 962916106001

12. AJISH S 962916106002

13. AJITH M 962916106003

14. ANAND BABU V 962916106004

15. ARUL SHIYA A P 962916106005

[Link] Name of the Student Register Number Signature

16. ARUL STEFFI A P 962916106006

17. ASHENA FARVIN M 962916106007

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
STUDENTS REGISTRATION LIST
Course Code &Title: DPAECE– DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07

[Link] Name of the Student Register Number Signature

18. DANIYA R 962916106008

19. JINI D 962916106009

20. KARTHICK R 962916106010

21. KAYATHIRI S 962916106011

22. LAVISHA V 962916106012

23. MONISHA D 962916106014

24. NITHIN JOSE J 962916106015

25. RAJ MOHAN S S 962916106016

26. RENU M NAIR 962916106017

27. RINCY Y 962916106018

28. RINSHA Y 962916106019

29. SOWMIYA LITTLE FLOWER J 962916106021

30. SUBIN KUMAR S 962916106022

31. VISHNU A 962916106023

32. JINO SELVA KUMAR P E 962916106501

COURSE COORDINATOR HEAD OF THE DEPARTMENT

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ATTENDANCE SHEET
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07
ATTENDANCE SHEET (FN Session – 3 Hours & AN Session– 3 Hours)
[Link]. Name of the Register
Student Number 09-07-18 10-07-18 11-07-18 12-07-18 13-07-18 14-07-18
FN AN FN AN FN AN FN AN FN AN FN
MOHAMMED RASVI M P
1. R
962918106003 P P P P P P P P P P

2. CATHERINE BIMLA J 962917106002 P P P P P P P P P A P

3. GIPSON D 962917106003 P P P P P P A A P P P

4. JAROM T 962917106004 P P P P P A P A P P P

5. JASPER JENO J 962917106005 P P P P P P P P P P P

6. KARTHICK T 962917106006 P P P P P P P P P P P

7. RAVID R V 962917106007 P P P P P P P P P A P

8. SANCHIEV K R 962917106008 P P P P P P A A P P P

9. ANUSHA J 962917106301 P P P P P A P A P P P

10. SARATH S 962918106501 P P P P P P P P P P P

11. AJI ENBA BEL S J 962916106001 P P P P P P P P P P P

12. AJISH S 962916106002 P P P P P P P P P P P

13. AJITH M 962916106003 P P P P P P A A P P P

14. ANAND BABU V 962916106004 P P P P P A P A P P P

15. ARUL SHIYA A P 962916106005 P P P P P P P P P P P

16. ARUL STEFFI A P 962916106006 P P P P P P P P P P P

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ATTENDANCE SHEET
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07
ATTENDANCE SHEET (FN Session – 3 Hours & AN Session– 3 Hours)
[Link]. Name of the Register
Student Number 09-07-18 10-07-18 11-07-18 12-07-18 13-07-18 14-07-18
FN AN FN AN FN AN FN AN FN AN FN

17. ASHENA FARVIN M 962916106007 P P P P P P P P P P P

18. DANIYA R 962916106008 P P P P P P P P P A P

19. JINI D 962916106009 P P P P P P A A P P P

20. KARTHICK R 962916106010 P P P P P A P A P P P

21. KAYATHIRI S 962916106011 P P P P P P P P P P P

22. LAVISHA V 962916106012 P P P P P P P P P P P

23. MONISHA D 962916106014 P P P P P P P P P P P

24. NITHIN JOSE J 962916106015 P P P P P P P P P P P

25. RAJ MOHAN S S 962916106016 P P P P P P P P P A P

26. RENU M NAIR 962916106017 P P P P P P A A P P P

27. RINCY Y 962916106018 P P P P P A P A P P P

28. RINSHA Y 962916106019 P P P P P P P P P P P

SOWMIYA LITTLE
29.
FLOWER J
962916106021 P P P P P P P P P P P

30. SUBIN KUMAR S 962916106022 P P P P P P P P P P P

31. VISHNU A 962916106023 P P P P P P A A P P P

JINO SELVA KUMAR
32.
PE
962916106501 P P P P P A P A P P P

COURSE COORDINATOR HEAD OF THE DEPARTMENT

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Course Code & Title: DPAECE–BASICS OF DSP PROCESSORS AND ITS
APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07
ASSESSMENT TEST QUESTIONS

1. The analog signals are categorized into ________

a. One
b. Two (ANSWER)
c. Three
d. Four
2. If discrete-time signal passes through an analog to digital converter we get ______
a. Binary sequence (ANSWER)
b. Decimal sequence
c. Hexadecimal sequence
d. None of the above
3. The technique where processing is done on an analog signal is nothing but ______
a. Analog signal processing (ANSWER)
b. Digital signal processing
c. Mixed-signal processing
d. None of the above

4. The most convenient and accurate signal processing technique is _____

a. Analog signal processing
b. Digital signal processing (ANSWER)
c. Mixed-signal processing
d. None of the above

5. The advantages of digital signal processing are _____

a. Flexible in operation
b. It is a stable system
c. Low cost
d. All of the above (ANSWER)
6. The impulse response of FIR filter is ______
a. Finite (ANSWER)
b. Zero
c. One
d. Infinite

7. ______ are the major applications of FIR filter

a. Data transmission
b. Speech processing
c. Correlation processing and interpolation
d. All of the above (ANSWER)
8. The non-recursive FIR filters are always ______
a. Stable (ANSWER)
b. Unstable

9. The advantages of FIR filters are _________

a. Stable
b. Realized in recursive
c. Realized in non-recursive
d. All of the above (ANSWER)

10. How many types of signals are there?

a. One
b. Two (ANSWER)
c. Three
d. Four

11. Analog signals converts into digital signal using _______

a. Sampling
b. Quantization
c. Both a and b (ANSWER)
d. None of the above

12. The signal processing is performed to ____________ the signal

a. Analyze
b. Modify
c. Synthesize
d. All of the above (ANSWER)

13. How many types of signal processing are there?

a. One
b. Two
 c. Three (ANSWER)
d. Four

14. The digital signal processing can be used in _______

a. Speech and audio processing
b. Image and video processing
c. Military and space applications
d. All of the above (ANSWER)

15. The disadvantages of FIR filter are _________

a. Complex
b. Requires more filter coefficient
c. Simple
d. Both a and b (ANSWER)

16. The number of complex addition in the direct computation of DFT is equal to _____
a. N(N-1) (ANSWER)
b. N(N+1)
c. N(N*1)
d. N(1/N)

17. The formula for percentage saving of addition in FFT is __________

a. 100-(number of addition in FFT/ number of addition in DFT)*100 (ANSWER)
b. 100-(number of addition in DFT/ number of addition in FFT)*100
c. 100-(number of addition in FFT/ number of addition in FFT)*100
d. None of the above

18. The formula for percentage saving of multiplication in FFT is __________

a. 100-(number of multiplication in FFT/ number of multiplication in DFT)*100 (ANSWER)
b. 100-(number of multiplication in DFT/ number of multiplication in FFT)*100
c. 100-(number of multiplication in FFT/ number of multiplication in FFT)*100
d. None of the above

19. ________ is the disadvantage of digital signal processing

a. Flexible in operation
b. Speed of operation is limited (ANSWER)
c. Speed of operation is unlimited
d. None of the above
20. If the processing is on a digital signal then the signal processing is called as _________
a. Analog
b. Digital (ANSWER)
c. Mixed
d. None of the above

21. The zero state response also called as ______ response

a. Free
b. Forced (ANSWER)
c. Natural
d. None of the above

22. The scaling operation also called as __________

a. Up-sampling
b. Down-sampling (ANSWER)
c. Both a and b
d. None of the above

23. _____ parameters are required to calculate correlation between X(n) and Y(n) signals?
a. Noise signal
b. Time delay
c. Attenuation factor
d. All of the above (ANSWER)

24. The zero input response also called as ______ response

a. Free
b. Natural (ANSWER)
c. Free or natural
d. None of the above

25. The function of the autocorrelation is ______

a. Even (ANSWER)
b. Odd
c. Both a and b
d. None of the above

26. The difference between quantized and unquantized is called quantization _______
a. Error (ANSWER)
b. Coefficient
c. Ratio
d. None of the above
27. Depending upon the number of independent variables the signals are categorized into ________
a. One
 b. Two
c. Three (ANSWER)
d. Four

28. __________ are the examples of random signals

a. EEG signal
b. ECG signal
c. Speech signal
d. All of the above (ANSWER)
29. The signals are categorized into ________ based on repetition nature
a. One
b. Two (ANSWER)
c. Three
d. Four

30. The signals are categorized into ________ based on reflection

a. One
b. Two (ANSWER)
c. Three
d. Four
31. _________ are the main elements of digital signal processing system
a. Quantizer, Sampler
b. Digital signal processor
c. Decoder
d. All of the above (ANSWER)
32. The speech signals are _______
a. One dimensional (ANSWER)
b. Two dimensional
c. Three dimensional
d. Multidimensional

33. The kinds of sounds are of ___________

a. One
b. Two (ANSWER)
c. Three
d. Four

34. _________ is an application of speech coding

a. Military communication (ANSWER)
b. Voice alarms
c. Information retrieval systems
d. All of the above
35. ______ are the parameters of speech
a. Pitch
b. Loudness
c. Quality
d. All of the above (ANSWER)

36. ____________ is an application of speech recognition

a. Information retrieval systems (ANSWER)
b. Source coding
c. Narrowband cellular radio
d. None of the above

37. __________ are the common methods of speech analysis

a. Harmonorphic filtering
b. Linear prediction
c. Short-time Fourier analysis
d. All of the above (ANSWER)

38. The parameters of speech coding are ________

a. Bitrate
b. Quality, delay
c. Complexity
d. All of the above (ANSWER)

39. _____________ is a type of waveform coding

a. Frequency domain coding (ANSWER)
b. Vector quantization
c. Pitch excited coder
d. None of the above

40. __________ is a type of narrow-band coding

a. Frequency domain coding
b. Linear predictive coding
c. Pitch excited coder (ANSWER)
d. None of the above

41. How many types of redundancies are there?

a. One
b. Two
c. Three (ANSWER)
d. Four

42. _________ are the common techniques based on the redundancy detection method
 a. Transformation method
b. Direct data compression method
c. Parametric extraction method
d. All of the above (ANSWER)

43. The discrete-time signals are categorized into __________

a. One
b. Two
c. Three (ANSWER)
d. Four

44. There are _________ types of infinite length sequences are there
a. One
b. Two
c. Three (ANSWER)
d. Four

45. The discrete-time systems are categorized into ________

a. One
b. Two
c. Four
d. Six (ANSWER)

46. What are the limitations of digital signal processing?

a. Bandwidth restrictions
b. Finite word length problems
c. Speed limitations
d. All of the above (ANSWER)

47. The signal ___________ are the uses of filters

a. Signal separation
b. Signal restoration
c. Both a and b (ANSWER)
d. None of the above

48. How many types of digital filters are there?

a. One
b. Two (ANSWER)
c. Four
 d. Six

49. _____ is a 16-bit fixed-point arithmetic DSP processor

a. TMS320C1X (ANSWER)
b. TMS320C3X
c. TMS320C4X
d. None of the above

50. _____ is a 32-bit fixed-point arithmetic DSP processor

a. TMS320C3X (ANSWER)
b. TMS320C5X
c. TMS320C8X
d. None of the above

COURSE COORDINATOR HEAD OF THE DEPARTMENT

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ASSESMENT MARK STATEMENT
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07
ATTENDANCE
MARKS OUT
Si .No. Name of the Student REGISTER NO IN
OF 100
PERCENTAGE
1. MOHAMMED RASVI M R 962918106003 92 100

2. CATHERINE BIMLA J 962917106002 96 97

3. GIPSON D 962917106003 96 94

4. JAROM T 962917106004 92 94

5. JASPER JENO J 962917106005 90 100

6. KARTHICK T 962917106006 90 100

7. RAVID R V 962917106007 92 97
 8. SANCHIEV K R 962917106008 92 94

9. ANUSHA J 962917106301 96 94

10. SARATH S 962918106501 96 100

11. AJI ENBA BEL S J 962916106001 100 100

12. AJISH S 962916106002 100 100

13. AJITH M 962916106003 96 94

14. ANAND BABU V 962916106004 96 94

15. ARUL SHIYA A P 962916106005 92 100

16. ARUL STEFFI A P 962916106006 90 100

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ASSESMENT MARK STATEMENT
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07
ATTENDANCE
MARKS OUT
Si .No. Name of the Student REGISTER NO IN
OF 100
PERCENTAGE
17. ASHENA FARVIN M 962916106007 92 100

18. DANIYA R 962916106008 96 97

19. JINI D 962916106009 90 94

20. KARTHICK R 962916106010 90 94

21. KAYATHIRI S 962916106011 96 100

22. LAVISHA V 962916106012 96 100

23. MONISHA D 962916106014 92 100

 24. NITHIN JOSE J 962916106015 92 100

25. RAJ MOHAN S S 962916106016 96 97

26. RENU M NAIR 962916106017 90 94

27. RINCY Y 962916106018 90 94

28. RINSHA Y 962916106019 96 100

29. SOWMIYA LITTLE FLOWER J 962916106021 96 100

30. SUBIN KUMAR S 962916106022 92 100

31. VISHNU A 962916106023 92 97

32. JINO SELVA KUMAR P E 962916106501 96 94

COURSE COORDINATOR HEAD OF THE DEPARTMENT

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

FEEDBACK FORM
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07

Please complete the following evaluation for the Add on Course you attended. Your feedback will help us
evaluate the effectiveness of this program and allow us to make improvements in the future program. Your
feedback is important for planning future programming and services we offer.
Thank you.
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Circle your response

1. The course met my expectations. 4 3 2 1
2. The content was helpful. 4 3 2 1
3. The level of the course was appropriate. 4 3 2 1
4. The speaker had a good understanding of the topics. 4 3 2 1
5. The handouts were helpful. 4 3 2 1
 6. The course was worth my time. 4 3 2 1
7. The length of the course was appropriate. 4 3 2 1
8. I recommend that the course be repeated for other Students 4 3 2 1
9. What were the most useful aspects of the course?
10. What changes should be made to enhance / improve the game?
Additional comments:

Name of the participant: Signature:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SUMMARY REPORT WITH COURSE OUTCOME
Course Code & Title: DPAECE–DSP PROCESSORS AND ITS APPLICATIONS
Academic Year: 2019- 2020 Duration: 22nd July ’19 – 27th July ’19 Year/Sem: II / 03, III / 05 & IV / 07

Name of Activity organized : Value Added Course

Title of the activity : DPAECE–DSP PROCESSORS AND ITS
APPLICATIONS
Coordinators : 1. Mrs. P. Merlin Viji,
Assistant Professor / EEE
2. Mrs. S. Abija Sherin,
Assistant Professor / EEE

Place of the activity : VCCE - Chunkankadai

No. of participants : 32

No of participants completed : 32

No. of participants qualified : 32

Name of the sponsored organization : NIL

 Able to distinguish between the
architectural features of general-purpose
processors and DSP processors

Outcome of the activity Understood the architectures of TMS

: 320C54XX and ADSP2100 DSP devices

Able to write assembly language programs

using instruction set of TMS320C54XX

COURSE COORDINATOR HEAD OF THE DEPARTMENT