Sequential Logic Circuits

Module 4 Part B

Faculty in Charge: Jagadeesh Kumar P

 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling

There are two kinds of abstract behaviors in the Verilog HDL. ( initial and
always)

Behavior declared by the keyword initial is called single-pass behavior and

specifies a single statement or a block statement (i.e., a list of statements
enclosed by either a begin . . , end or a fork . . . join keyword pair).

A single-pass behavior expires after the associated statement executes.

In practice, designers use single-pass behavior primarily to prescribe stimulus

signals in a test bench-never to model the behavior of a circuit-because
synthesis tools do not accept descriptions that use the initial statement.
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 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling

The always keyword declares a cyclic behavior:

Both types of behaviors begin executing when the simulator launches at time t = 0.

The initial behavior expires after its statement executes;

the always behavior executes and re executes indefinitely, until the simulation is stopped.

A module may contain an arbitrary number of initial or always behavioral statements.

They execute concurrently with respect to each other starting at time 0 and may interact
through common variables.

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 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling

A word description of how an always statement works for a simple model of

a D flip-flop:

Whenever the rising edge of the clock occurs, if the reset input is asserted,
the output Q gets 0; otherwise the output Q gets the value of the input D.

The execution of statements triggered by the clock is repeated until the

simulation ends.

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 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling

An initial behavioral statement executes only once.

It begins its execution at the start of simulation and expires after all of its statements have completed
execution.

As mentioned the initial statement is useful for generating input signals to simulate a design.

In simulating a sequential circuit, it is necessary to generate a clock source for triggering the flip-flops.

The following are two possible ways to provide a free-running clock that operates for a specified number of
cycles:

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 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling

The following are two possible ways to provide a

free-running clock that operates for a specified number
of cycles:

In the first version, the initial block contains two

statements enclosed within the begin and end keywords.

The first statement sets clock to 0 at time = 0.

The second statement specifies a loop that re executes 30

times to wait 10 time units and then complement the value
of clock.

This produces 15 clock cycles, each with a cycle time of

20 time units.

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 Synthesizable HDL Models of Sequential Circuits
Behavioral Modeling - The following are two possible ways to
provide a free-running clock that operates for a specified
number of cycles:

In the second version, the first initial behavior has a single

statement that sets clock to 0 at time = 0, and it then expires
(causes no further simulation activity).

The second single-pass behavior declares a stopwatch for the

simulation. The system task finish causes the simulation to
terminate unconditionally after 300 time units have elapsed.

Because this behavior has only one statement associated with it,
there is no need to write the begin . . . end keyword pair.

After 10 time units, the always statement repeatedly complements

clock , providing a clock generator having a cycle time of 20 time
units.
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 Synthesizable HDL Models of Sequential Circuits
Here is another way to describe a free-running clock:

initial begin clock = 0; forever #10 clock = ~clock; end

This version, with two statements on one line, initializes the clock and then
executes an indefinite loop (forever) in which the clock is complemented after a
delay of 10 time steps.

Note that the single-pass behavior never finishes executing and so does not
expire.

Another behavior would have to terminate the simulation.

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 Synthesizable HDL Models of Sequential Circuits
Time delays specified with the # delay control operator are commonly used in single-pass
behaviors.

The delay control operator suspends execution of statements until a specified time has elapsed.

Another operator is called the event control operator and is used to suspend activity until an event
occurs.

An event can be an unconditional change in a signal value (e.g., @ A) or a specified transition of

a signal value (e.g., @ (posedge clock)).

The general form of this type of statement is

always @ (event control expression) begin

// Procedural assignment statements that execute when the condition is met

end
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 Synthesizable HDL Models of Sequential Circuits
The statement

always @ (A or B or C)

will initiate execution of the procedural statements in the associated always

block if a change occurs in A, B , or C.

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 Synthesizable HDL Models of Sequential Circuits
In synchronous sequential circuits, changes in flip-flops occur only in response to a transition of a
clock pulse.

The transition may be either a positive edge or a negative edge of the clock, but not both.

Verilog HDL takes care of these conditions by providing two keywords: posedge and negedge.

For example, the expression

always @(posedge clock or negedge reset) // Verilog 1995

The 2001 and 2005 revisions to the Verilog language allow a comma- separated list for the event
control expression (or sensitivity list):

always @(posedge clock, negedge reset) II Verilog 2001, 2005

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 Synthesizable HDL Models of Sequential Circuits
A procedural assignment is an assignment of a logic value to a variable
within an initial or always statement.

This is in contrast to a continuous assignment discussed in Section 4.12

with dataflow modeling, A continuous assignment has an implicit
level-sensitive sensitivity list consisting of all of the variables on the
right-hand side of its assignment statement.

The updating of a continuous assignment is triggered whenever an event

occurs in a variable listed on the right-hand side of its expression.

In contrast, a procedural assignment is made only when an assignment

statement is executed within a behavioral statement.

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 Synthesizable HDL Models of Sequential Circuits
For example, the clock signal in the preceding example was complemented
only when the statement clock = ~clock executed;

the statement did not execute until 10 time units after the simulation began.

It is important to remember that a variable having type reg remains

unchanged until a procedural assignment is made to give it a new value.

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 Synthesizable HDL Models of Sequential Circuits
There are two kinds of procedural assignments: blocking and nonblocking.

The two are distinguished by the symbols that they use.

Blocking assignments use the symbol ( = ) as the assignment operator, and

Nonblocking assignments use (<= ) as the operator.

Blocking assignment statements are executed sequentially in the order

they are listed in a block of statements.

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 Synthesizable HDL Models of Sequential Circuits
There are two kinds of procedural assignments: blocking and nonblocking.

Nonblocking assignments are executed concurrently by evaluating the set

of expressions on the right-hand side of the list of statements;

they do not make assignments to their left-hand sides until all of the
expressions are evaluated.

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 Synthesizable HDL Models of Sequential Circuits
Consider these two procedural blocking assignments:

B=A

C=B+1

The first statement transfers A into B.

The second statement increments the value of B and transfers the new value
to C.

At the completion of the assignments, C contains the value of A + 1.

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 Synthesizable HDL Models of Sequential Circuits
Consider the two statements as nonblocking assignments:

B <= A

C <= B + 1

When the statements are executed, the expressions on the right-hand side are
evaluated and stored in a temporary location.

The value of A is kept in one storage location and the value of B + 1 in another.

After all the expressions in the block are evaluated and stored, the assignment
to the targets on the left-hand side is made.

In this case, C will contain the original value of B , plus 1

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 Synthesizable HDL Models of Sequential Circuits
A general rule is to use blocking assignments when sequential ordering is
imperative and in cyclic behavior that is level sensitive (i.e., in
combinational logic).

Use nonblocking assignments when modeling concurrent execution (e.g.,

edge-sensitive behavior such as synchronous, concurrent register transfers)
and when modeling latched behavior.

Nonblocking assignments are imperative in dealing with register transfer level

design.

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 Flip-Flops and Latches
The D latch is transparent and
responds to a change in data input
with a change in output, as long as
the enable input is asserted.

The module description of a D

latch is shown in HDL Example 5.1

It has two inputs, D and enable ,

and one output Q.

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 Flip-Flops and Latches
Since Q is evaluated in a procedural
statement, it must be declared as reg
type.

Latches respond to input signal

levels, so the two inputs are listed
without edge qualifiers in the event
enable expression following the @
symbol in the always statement.

Specifies the transfer of input D to

output Q if enable is true (logic 1).

This statement is executed every time

there is a change in D if enable is 1.

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 Flip-Flops and Latches
A D-type flip-flop is the simplest
example of a sequential machine.

HDL Example 5.2 describes two

positive-edge D flip-flops in two
modules.

The first responds only to the

clock;

The second includes an

asynchronous reset input.

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 Flip-Flops and Latches
Output Q must be declared as a reg data
type in addition to being listed as an
output.

This is because it is a target output in a

procedural assignment statement.

The keyword posedge ensures that the

transfer of input D into Q is synchronized
by the positive-edge transition of Clk.

A change in D at any other time does not

change Q.
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 Flip-Flops and Latches
There are two edge events in the second
module of HDL Example 5.2.

The negedge rst (reset) event is

asynchronous, since it matches the if
(~rst) statement.

As long as rst is 0, Q is cleared to 0.

If Clk has a positive transition, its effect is

blocked.

Only if rst = 1 can the posedge clock event

synchronously transfer D into Q .
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T ( Toggle ) Flip-Flop

The first module, TFF, describes a T flip-flop by

instantiating DFF.

The declared wire, DT, is assigned the exclusive-OR of Q

and T , as is required for building a T flip-flop with a D
flip-flop.

The instantiation with the value of DT replacing D in

module DFF produces the required T flip-flop.
JK Flip-Flop
JK Flip-Flop