超大型積體電路設計導論 Fall 2023 期中考試題範例
Total score:
Part I. 解釋名詞 (每題 3 分)
A. Ohmic contact
Additional p+ diffusion in P substrate (or n+ diffusion in N well) to lower the resistance of the
substrate (well) contact
B. Transistor aspect ratio
The ratio of transistor width over length W/L
C. (pSelect) (Active) (nWell) (NOT [poly]) = ?
Source/drain of a pMOS transtor
Part II. 簡答題 (每題 4 分，共 19 分)
A. Vertical 與 horizontal layout style 的差異 (4)
Vertical layout style: source and drain run vertically
Horizontal layout style: source and drain run horizontally
B. 如何區別 well/substrate contact 和 source/drain contact (4)
if the diffusion and the substrate/well are of the same type substrate/well contact, otherwise
source/drain contact
Part III. 設計題
Q1. (8pts) Please draw a CMOS schematic circuit that implements F a b c
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Q2. (10pts) Consider a process that has tox = 9.5nm, n = 540cm2/V-sec, p = 220cm2/V-sec. An nFET
and a pFET are made, both with W=12m, L=0.35m. Both have VG=3.3.V, while VTn=0.65V and
VTp=-0.74V.
a) find the values of Rn and Rp for the two transistors
b) keep the nFET same size but increase the width of the pFET so that Rp=Rn,
find the required width of the pFET
(a)
(b) let Rp=Rn=56.1
1
56.1
p (3.3 0.74)
W
p 6.963 103 k p'
0.35
W 30.47 m
Vdd
Q3. (12pts) 針對下列邏輯電路
D
a) 針對下列電路圖，其輸出 Boolean function Y 為何？ (3) C
Y AB C ( D E ) E
b) 下列何者為 P-block 與 N-block 共通之 Euler path？(3) A B
1. CABDE 2. CDEBA c) EDCAB d) Y
A C
ABCDE
EDCAB B D E
A C D
C
E
B D E
A B
N-Graph P-Graph
c) 請根據 b)中正確之 Euler path 所決定之輸入順序(由左至右)，假設 N-well 1P1M process，
畫出 layout 對應之 stick diagram (請以彩色筆作答) (6)
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E D C A B
Q4. 針對下列 layout(布局圖)
a) 請劃出對應的 MOS schematic 電路圖
b) 請劃出 active area 的光罩
c) 請指出 rule 1 ~ 4 分別對應哪一個 layout design rule
Rule 1: B3, rule 2: B2, rule 3: D4, rule 4: E4
d) 根據 layout design rule，請算出 PMOS 電晶體的 source diffusion layout 所需的最小寬度為
多少? E2 + E1 + E4 = 6
Rule 2
Rule 1
Rule 3
Rule 4
A. N-well A.1 minimum size 10 D. P+/N+ D.1 Min. overlap of active 2
layer A.2 minimum spacing 6 D.2 Minimum size 7
B.1 Minimum size 3 D.3 Min. overlap of active 1
in abutting contact
B.2 minimum spacing 3 D.4 spacing of P+/N+ to 3
B. Active N+/P+ gate
area B.3 N-well overlap of 5 E. contact E.1 minimum size 2
P-diffusion
B.4 N-well overlap of 3 E.2 min. spacing (poly) 2
N-diffusion
B.5 N-well space to 5 E.3 min. spacing (active) 2
N-diffusion
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B.6 N-well space to 3 E.4 min. overlap of active 2
P-diffusion
C. Poly C.1 Minimum size 2 E.5 min. overlap of poly 2
C.2 Minimum spacing 2 E.6 min. overlap of metal 1
C.3 Spacing to active 1 E.7 min spacing to gate 2
C.4 Gate extension 2 F. Metal F.1 minimum size 3
F.2 Minimum spacing 3
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