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Vlsi Assignment1

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Srujana Reddy N.V.
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14 views3 pages

Vlsi Assignment1

Uploaded by

Srujana Reddy N.V.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

// Code your design here

module fourbit_add_sub(a,b,aluc_2,out);
input [31:0]a;
input [31:0]b;
input aluc_2;
output [31:0]out;
reg [31:0]out;
always@(a or b)
if(~aluc_2)
out=a+b;
else
out=a+(~b)+1;
endmodule

// Code your design here


module barrelshifter(a,b,aluc_2,aluc_3,out);
input [4:0]a;
input [31:0]b;
input aluc_2;
input aluc_3;
output [31:0]out;
reg [31:0]out;
always@(a or b)
if({aluc_3,aluc_2}==2'b00)
out=b<<a;
else if({aluc_3,aluc_2}==2'b01)
out=b>>a;
else if({aluc_3,aluc_2}==2'b10)
begin
reg signed_bit = $signed(b);
out=b<<a;
out={out,{a'{signed_bit}}};
end
out=b>>a;

endmodule

// Code your testbench here


// or browse Examples
module test;
reg [31:0]a;
reg [31:0]b;
reg [3:0]aluc;
wire [31:0]adder_out;
fourbit_add_sub DUT1(.a(a), .b(b), .aluc_2(aluc[2]),.out(adder_out));
initial begin
a=4'b0000;
b=4'b0000;
carry=1;
#5
a=4'b1100;
b=4'b0010;
carry=0;
#5
a=4'b0100;
b=4'b0011;
carry=1;
#5
$finish();
end
initial begin $dumpfile("full_tb.vcd");$dumpvars(); end
endmodule

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