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Verilog Code For Structural Module

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75 views4 pages

Verilog Code For Structural Module

Uploaded by

sudeepsudeepsr054
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Verilog code for Structural module

// Code your design here

module LogicGates(a, b, c, d, e);

input a, b, c;

output d, e;

wire w1;

and (w1, a, b);

not (e, c);

or (d, w1, c);

endmodule

module TestModule;

reg a, b, c;

wire d, e;

LogicGates uut (.a(a),.b(b),.c(c),.d(d),.e(e) );

initial begin

$dumpfile("dump.vcd");

$dumpvars(1);

// Initialize inputs

a = 0; b = 0; c = 0;

#5 a = 0; b = 0; c = 1;

#5 a = 0; b = 1; c = 0;

#5 a = 0; b = 1; c = 1;

#5 a = 1; b = 0; c = 0;

#5 a = 1; b = 0; c = 1;

#5 a = 1; b = 1; c = 0;

#5 a = 1; b = 1; c = 1;

#5 $finish;

End

endmodule
module halfadder(x,y,sum,carry);

input x,y;

output sum,carry;

assign sum((!x)&y)||(x&e(!y);

assign carry=(x&&);

endmodule

module TestModule

reg x,y;

wire sum,carry;

halfadder uut (.x(x),.y(y),.sum(sum),.carry(carry));

initial begin

$dumpfile(“dump.vcd”);

$dumpvars(1);

End

Initial begin

x=0;y=0;

#5 x=0;y=1;

#5 x=1;y=0;

#5 x=1;y=1;
$finish

end

endmodule

module mux_2to1_behavioral(Y,A,B,S);

output y;

input A,B,S;

reg Y;

always@(A,B,S)

begin

if(S==0)

Y=A;

else

Y=B;

End

Endmodule

Module mux_2to1_behavioral;

Reg S,A,B;

Wire Y;

mux_2to1_

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