USOO5747955A

United States Patent (19) 11 Patent Number: 5,747,955

Rotunda et al. 45 Date of Patent: May 5, 1998

54 CURRENT SENSING MODULE FOR A 4,481,457 11/1984 Zach et al..

WARIABLE SPEED AC MOTOR DRIVE FOR 4,525,658 61985 Yanagida.
USE WITH A TREADMLL 4,604,563 8/1986 Min.
4,628.235 12/1986 Goings ................................ 318/434 X
75) Inventors: John T. Rotunda, Bothell; Lester A. 3. Eir
Hass, El; Victor Pipinich, Seattle, 4,656572 4/1937 Caputo et al.,
all of Wash. 4,658,692 4/1987 Bagus.
4,691,694 9/1987 Boyd et al. .
73) Assignee: Quinton Instrument Company. 4,749,181 6/1988 Pittaway et al. .
Bothell, Wash. 4,759.540 7/1988 Yu et al. .
4,792,134 12/1988 Chen.
(21) Appl. No.: 934,044 4,842,266 6/1989
Sweeney, Sr. et al. .
4,910,450 3/1990
Parker et al. .
22 Filed: Sep. 19, 1997 4,922,161 5/1990 Gilliland et al..
4,928.956 5/1990 Chen.
Related U.S. Application Data 4,944,713 7/1990 Salerno.
4,964.841 10/1990 Takayama et al. .
63 doned.
Continuation of Ser. No. 414,400, Mar. 31, 1995, aban- 4.999556 3/1991 Masters
5,021,726 6/1991 Reinhardt et al. .
6 5,047,704 9/1991 Yamauchi et al. ...................... 318/801
51) int. C. ................................................. H02P 7/00 5,053,688 10/1991 Rees.
(52) U.S. Cl. ............................. 318/434; 361/31; 361/96; 5,059.875 10/1991 De Salme
318/432; 482/54 5,088,297 2/1992 Maruyama et al. .
(58) Field of Search ..................................... 318/432, 434, 2: 3:3: in
318/798-815; 388/903, 904,930; 361/23, a ww.y g
30, 31, 42-50, 51, 87, 93, 919, t (List continued on next page.)
Primary Examiner-Jonathan Wysocki
56 References Cited Attorney, Agent, or Firm-Montgomery W. Smith; Richard
D. Allison
U.S. PATENT DOCUMENTS
1,607.002 11/1926 Keller. 57) ABSTRACT
3,392,316 7/1968 Salihi. A current sensing module for use with a variable speed AC
E. E. E. motor control drive system for use with devices such as
3704,403 11/1972 3. -- treadmills and including a module to sense the current of
3711812 1/1973 Cherry pulse width modulated signals provided to an AC motor
3.737,163 6/1973 sumrin. wherein the current sensing module includes a fast sense
3,819,992 6/1974 Opal et al.. circuit to sense excessive current conditions in the pulse
3,832,613 8/1974 Bernstein et al. . width modulated signals and a slow sense circuit to sense
3,919,891. 11/1975 Stuhlmuller et al. . average current values in excess of desired values over a
3,954,018 5/1976 O’Berto. predetermined period of time to protect the AC motor from
3,984,744 10/1976 Moody. damage caused by the increased frictional resistance to the
: E. i.e.,i 36/28 rotation of the walk belt on the treadmill deck as the walk
4280082 7/1981. Acharya et al. . belt and treadmill deck wear out.
4,384,244 5/1983 Matsumoto.
4,426,075 1/1984 Otte. 21 Claims, 14 Drawing Sheets

s f 78
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POWER SPY
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POWER SUPPY
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 5,747,955
Page 2

U.S. PATENT DOCUMENTS 5,270,631 12/1993 Takahashi et al. .

8/1992 Rowan et al.
5,361,022 11/1994 Brown ..................................... 38/375
5,140,248 5,386, 183 1/1995 Cronvich et al. ... 318/434
5,141,479 8/1992 Wanjani et al. . 5,448.442 9/1995 Farag ......................... ... 361/24
5,162,709 11/1992 Oh.
5,168,439 12/1992 Kumar et al. . 5,463,294 10/1995 Waldivia et al. ........... ... 38,432
5,220.264 6/1993 Yamada. 5,488,279 1/1996 Kawamoto et al. ................... 38/801
U.S. Patent May 5, 1998 Sheet 1 of 14 5,747,955

ICROPROCESSOR
U.S. Patent May 5, 1998 Sheet 2 of 14 5,747,955

TORQUE

SPEED

FIGURE 2

FIGURE 3
U.S. Patent May 5, 1998 Sheet 3 of 14 5,747,955

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U.S. Patent May 5, 1998 Sheet 4 of 14 5,747,955

64 66

62 COMMUNICATIONS VSD LED 68

INTERFACE INDICATOR

60
RESET GRADE
MONITOR INTERFACE

76 VSD SOFTWARE
PROCESS

Intifice
INTERFACE INTERFACE

PWM CONTROL DRIVER FAULT 7O

INTERFACE INTERFACE

74 72

FIGURE 6
U.S. Patent May 5, 1998 Sheet S of 14 5,747,955

PHASE (A) PHASE (B) PHASE (A)

PHASE
COMPA
S. PHASE SE)
COMPARE
PHASE (C)
COMPARE
TIMER TIMER TIMER
f OO
SB f O2
CALCULATE CALCULATE CALCULATE
PWM-TIME BUILD
CLOCK PHASE (A)
PS ()
COMPARE
PS) YBUILD
COMPARE
PS(O)
PHASE (C)V COMPARE
VALUE VALUE VALUE
REAL-TIME 78 1 OB
CLOCK

WAVE FORM (A) WAVE FORM (B)

DATA BASE
WAVE FORM (C)
DATA BASE
UPDATE SPEED STEP TIMER DATA BASE

SPEED 80US TIMER BO

106
PWMSPEED CHECK 94. 110
WAVE FORM
BUILDING
PERFORM SPEED PARAMETERS
ERROR CHECK
96

ABS
PEEDTIMER CHECK BLE EAEER 36
ABS filter VBUS
A CURRENT SPEED ABS
SPEED CHECK PWMBUILDER
PARAMETER 1 TO A TO D
TIMER BUILDER (- TARGE SPEED CHANNEL
D VSD STATUS f
BUILD NEW
SPEED STEP VALUE

84 92 90 BB

FICURE 6
U.S. Patent May 5, 1998 Sheet 6 of 14 5,747,955

f 18 128

EPA5 OUTFSET OUTPUT

W. B. SE COMPARE MODULE
1so Ps. vie
REG. PHASE DIR
f32
SEESS f32
EPA5
AWAVEFORM APTR COMPARE MODULE
AWAVEFORM BPR PHANTOMF SET
AWAVEFORM CPTR SR CONTROLLER

BWAVEFORM APTR PWM SR RUN8OuS PWM

BWAVEFORM BPR
BWAVEFORM CPTR PROCESS
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PAO PHASEA
coupé MODULE PWM OUTPUT
f22
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WAVEFORM B
WAWEFORM C

SPEED MERCHECK
CURRENTSPEED
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1REAL TIME.EXECUTIVE) L1,w SPEED CONTRO

N- PROCESS-1 N-PROCESS TARGET SPEED
WSD STATUS AND
CSS,
( aw SPEED click

82 1 26

FIGURE 7
U.S. Patent May 5, 1998 Sheet 7 of 14 5,747,955

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U.S. Patent May 5, 1998 Sheet 13 of 14 5,747,955

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U.S. Patent May 5, 1998 Sheet 14 of 14 5,747,955

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 5,747,955
1. 2
CURRENT SENSING MODULE FOR A the maintenance of a constant magnetic flux density in the
WARIABLE SPEED AC MOTOR DRIVE FOR windings of the AC drive motor.
USE WITH A TREADMLL Some currently available AC drive motors receive power
through a pulse width modulated (PWM) DC signal. By
This application is a continuation of application Ser. No. 5 controlling the duty cycles of the pulses in the PWM signals,
08/414,400, filed Mar. 31, 1995, now abandoned. signals are produced that, when applied to the AC motor, act
like AC signals of any desired frequency. This allows the AC
BACKGROUND OF THE INVENTION drive motor to operate at a desired speed by setting the duty
cycle of the PWM signals to produce AC signals at a
1. Field of the Invention O frequency determined to produce the desired speed of the
The invention relates to a system for controlling and AC motor.
sensing the operation of an AC induction drive motor and A prior art system for producing a PWM signal to drive
more specifically to a system for sensing the current of the an AC drive motor is disclosed in U.S. Pat. No. 5,140,248
pulse width modulated (PWM) signal that powers an AC granted to Rowan et al. In this system, the motor control or
induction drive motor in a treadmill to detect the occurrence s drive includes a power section that receives power at a line
of fast and slow fault conditions. frequency of 60 Hz from a three phase AC power source.
2. Description of Related Art The three phases of the power source are connected to an
AC-DC power converter in the power section of the drive.
Many treadmills have walk belts powered by AC drive The AC-DC power converter passes the AC signal through
motors. These AC drive motors rotate pulleys and walk belts a full-bridge rectifier system that converts the AC signal into
at speeds that depend on the frequency of the AC power 20
a near DC signal on a DC bus that connects to power inputs
provided to the motor. on a pulse width modulation voltage inverter which com
When a person walks or runs on a treadmill the impact of pletes the power section of the drive. The PWM inverter
the person's foot on the walk belt pushes the walk belt into includes a group of switching elements which are turned on
frictional contact with the treadmill deck of the treadmill. 25 and off to convert the DC voltage to pulses of constant
This frictional contact between the walk belt and the tread magnitude.
mill deck resists the smooth movement of the walk belt and The pulse train pattern from the PWM inverter is char
creates an increased resistance to the rotation of the pulleys acterized by a first set of positive going pulses of constant
and motor. A number of solutions have been proposed to magnitude but of varying pulse width and by a second set of
reduce the amount of friction between the walk belt and negative going pulses of constant magnitude but of varying
treadmill deck. One commonly used approach involves pulse width. The RMS value of the pulse train pattern
coating the treadmill deck and/or walk belt with a wax or approximates one cycle of a sinusoidal signal which is
lubricous coating. A difficulty with this approach is that the characteristic of an AC wave form. The pattern is repeated
wax or lubricous coating has a tendency to wear off after to generate additional cycles of the AC wave form.
extended use. The amount of frictional resistance to the 35 To control the frequency and, magnitude of the resultant
movement of the walk belt on the treadmill deck also varies AC power signals to the motor, AC inverter phase control
greatly between users and is a function of the person's stride, signals are applied to the PWM inverter. The PWM voltage
weight and various other factors. inverter receives three balanced AC inverter phase control
We have found that when a person is walking or running signals which vary in phase by 120 degrees, and the mag
on the treadmill at a relatively continuous pace, the amount nitude and the frequency of these signals determines the
of frictional resistance to the rotation of the walk belt is pulse widths and the number of pulses in the pulse trains
nearly sinusoidal in nature. The frictional resistance is at its which are applied to the terminals of the motor. The inverter
maximum when the person is planting his foot and is at its phase control signals are produced as a result of a 2 phase
minimum or near zero when the person is pushing off the to 3 phase conversion which is accomplished with a 2 to 3
walk belt surface with his foot. This periodic increase in 45 phase converter.
frictional resistance to the movement of the walk belt U.S. Pat. No. 5,140,248 granted to Rowan et al., also
translates into a variable load applied to the AC drive motor discloses a motor controller system which attempts to main
of the treadmill. Because the frictional resistance of a person tain current constant for a fixed load by limiting the current
walking or running on the walk belt at a relatively constant provided to the motor. As shown in FIG. 1, a
speed is nearly sinusoidal in nature, the load placed on the 50 microprocessor-based PWM generator produces PWM sig
AC drive motor by the person walking or running on the nals that control switches passing or not passing DC power
walkbelt is also nearly sinusoidal in nature. The adjustment to the AC motor in response to the PWM signals from the
to the application of a variable load to the AC drive motor PWM generator. The current at each of the switches is
is important in maintaining the speed of treadmills relatively sensed, passed through an A-to-D converter and presented to
constant and is particularly noticeable when aheavier person 55 the microprocessor. As the current at the switches drops
plants his foot on the walk belt and the speed of the walk belt below an acceptable level, the microprocessor causes the
is at a minimum or lower speed. PWM signals to that switch to have a longer duty cycle so
The increased load on the AC drive motor caused by the that the input signal is adjusted to regulate the current to the
user walking on the walk belt causes a drop in the high motor.
voltage DC supply across the filter capacitor. This reduction As described above, various PWM controller systems for
in the high voltage DC supply reduces the available voltage AC motors are generally known. Some of these systems
to power the motor which causes the performance and sense the PWM signal as it is presented to the drive motor.
torque produced by the electronic drive to deteriorate. These systems pass information about the sensed condition
It is highly desirable for the AC drive motor to maintain of the PWM signal to the PWM generator to modify the
a constant speed at a given AC power frequency despite the 65 PWM signal. However, these systems do not sense the
varying loads placed on the drive motor during use of the condition of the bus voltage and do not vary the PWM signal
treadmill. The constant speed of the AC drive motor requires directly to account for the variation in the bus voltage.
 5,747,955
3 4
When the AC drive motor has a load applied to it, the DC provides the bus voltage to switches controlled by a pulse
bus voltage drops. Unless the PWM signal is modified, there width modulated signal generator. The PWM signal genera
is insufficient energy provided to the drive motor to maintain tor modulates the DC power to produce three phase PWM
a constant speed. Consequently, it is desirable to create a drive signals. The PWM drive signals are passed to the AC
system that senses the load placed on the AC drive motor drive motor. The PWM drive signals appear to the AC drive
and adjusts the PWM signal accordingly to produce a near motor as sine waves of a predetermined frequency.
constant drive motor speed and a corresponding constant The adaptive bus scaling (ABS) system senses the DC
treadmill belt speed for treadmills despite varying loads. voltage of the bus providing power to the PWM switches. As
described above, changes will occur in the DC bus voltage
One approach to solving this problem is to use line 10 for various reasons, including as a result of a user walking
voltage to determine the voltage supplied to the AC drive on the treadmill and because of fluctuations in the line
motor through the PWM signal. The difficulty with this voltage used to produce the DC bus voltage. The ABS
approach is that the line voltage varies considerably from system senses the voltage changes as they occur in the DC
place to place and even from time to time at the same place. bus voltage and passes the sensed bus voltage to the three
In the U.S. the line voltage typically varies from about 100 phase PWM signal generator.
volts to about 130 volts, a 30% variation or between about 5 The PWM signal generator then manipulates the duty
99 V to 132 V for a 33% variation. In the PWM system cycle of the PWM control signals to maintain a constant
described above, this variation in line voltage produces a magnetic flux density in the windings of the AC drive motor,
variation in the bus voltage supplied to the PWM drives of When the DC bus voltage drops, the PWM signal generator
about 280 volts for a 99-volt line to about 368 volts, less increases the duty cycle of the PWM control signals so that
bridge drops and bus sag, for a 130-volt line or 373 volts for 20 the total power provided to the windings of the AC drive
a 132 volt line. The bus voltage is used to determine the motor remains constant. Likewise, when the DC bus voltage
amplitude of the PWM signal. To maintain a constant increases, the PWM signal generator decreases the duty
magnetic flux density in the windings of the AC drive motor cycle of the PWM control signals so that the total power
despite the load placed on the AC drive motor by a person provided to the windings of the AC drive motor remain
walking or running on the treadmill belt, the PWM signal 25 constant despite fluctuations in line voltage or in the load
applied to the motor.
corresponding to the 99-volt line must be different from the A further feature of the preferred embodiment of the
PWM signal corresponding to a line voltage of about 115 present invention relates to the use of a current sensing
volts. module which continuously monitors the high side current to
Although it may be possible to pass a rectified and filtered 30 each of the three motor phases. This module senses each
signal through a voltage regulator to provide a non-varying phase current to provide protection in the event of a single
voltage to the PWM drivers and subsequently to the AC fault condition as well as to provide redundancy and com
drive motor, the cost and the complexity of such a system monality for the operation of each phase. The preferred
renders this type of approach impractical for large scale embodiment of this invention includes two current sense
manufacture or for use in relatively inexpensive applica circuits to provide protection in the event that either of two
tions. For example, in treadmills, a current of 10 amps is 35 types of faults occur.
It is an object of the invention to provide an AC drive
frequently drawn by the AC drive motor. Even at the low motor
voltage of 99-volt AC described above, a maximum of about profile controller
to the AC
system that provides a constant torque
drive motor despite variations in the line
2000 watts of electrical power is used by the AC drive motor. voltage that drives the system and motor.
Voltage regulators capable of handling 2000 watts are It is another object of the invention to provide an AC drive
expensive and typically require a large number of motor controller system that provides a constant torque
components, any one of which may fail or disable the profile to the AC drive motor despite variations in the load
voltage regulator during use. placed on the AC drive motor.
It is, therefore, an object of the invention to provide a It is another object of the invention to provide an AC drive
method and device for maintaining the flux density of a drive 45 motor controller system that adjusts the torque profile to the
motor constant through drive voltage PWM generators that AC drive motor in response to variations in the line voltage
are inexpensive to manufacture and reliable. that drives the system and in response to variations in the
It is a further object of the invention to provide a device load placed on the motor.
It is yet another object of the invention to provide an AC
for monitoring or regulating the flux density of a drive motor drive motor controller system that readily adapts to varying
with a PWM driver that is reliable. 50
line frequencies.
SUMMARY OF THE INVENTON It is yet another object of the invention to provide an AC
drive motor controller system that protects against both short
One basic consideration of an AC motor constructed in term and long term over current situations to prevent dam
accordance with the present invention is that the speed age to the motor and the control system.
regulation of the AC motor is approximately determined by 55 It is a further object of the invention to provide an AC
the relation: drive motor controller system that is inexpensive to manu
Voltage/Frequency=Constant Flux Density facture and is reliable in use.
Thus, by varying the frequency while keeping the flux These and other objects of the invention will be clear from
constant and changing the PWM drive voltage, the speed of the description of the invention given herein and more
the motor is controlled. An additional benefit to this system particularly with reference to the following detailed descrip
is that by keeping the flux constant, a near constant torque tion of the invention and with reference to the accompanying
profile on the drive motor is produced despite the varied drawings. Throughout the description, like reference num
speed of rotation. bers refer to like elements.
An embodiment of the present invention includes an AC BRIEF DESCRIPTION OF THE DRAWINGS
drive motor control system having an adaptive bus scaling 65
(ABS) system. The motor control system of the present FIG. 1 is a schematic drawing of a prior art pulse width
invention converts line AC power to DC power which modulated powered AC drive motor system;
 5,747,955
5 6
FIG. 2 is illustrative of the preferred form of the torque vs voltage levels. As a result of the regulated and controlled
speed profile of the present invention; frequency and voltage levels, the rotation of the motor shaft
FIG. 3 is illustrative of the PWM logic functional timing and therefore, the speed of rotation of the walk belt is
of the present invention; controlled. Although the majority of the circuitry on the
variable speed drive supports the AC drive motor function,
FIG. 4 is a schematic drawing of the preferred form of the other sections control the grade system and provide for
PCBA architecture for the variable speed drive system of the communication with a remote controller as briefly described
present invention; below.
FIG. 5 is a data flow drawing of the software configura FIG. 2 is illustrative of the preferred torque profile of the
tion of the peripheral signal interface of the variable speed 10 present invention at various speeds. As shown, for any given
drive system of the present invention; speed of the treadmill, the torque profile to the AC drive
FIG. 6 is a data flow drawing of the software configura motor is constant despite varying loads placed on the motor.
tion of the pulse width modulated speed control system of For example, locationXrepresents the speed of the treadmill
the present invention; when the torque applied to the motor is low, such as when
FIG. 7 is a functional drawing of the software configu 15 the user is in between strides or as they are pushing off of the
ration of the pulse width modulated speed control system of treadmill deck. Location Y is illustrative of the situation
the present invention; when the user first plants their foot on the treadmill deck to
FIG. 8 is a schematic drawing of the microprocessor cause a footfall as described above. As shown, the present
module of the present invention; invention maintains the speed of the treadmill constant
during the normal range of operating speeds and resistance
FIG. 9 is a schematic drawing of the optocoupler system as shown by locations X and Y which are illustrative of the
of the present invention; generally perpendicular torque profile of the present inven
FIG. 10 is a block diagram of the adaptive bus scaling tion.
system of the present invention; FIG. 3 is illustrative of the PWM logic functional timing
FIG. 11 is a schematic drawing of the buss recovery 25 with the microprocessor module 20 of the present invention.
system module of the present invention; The signals shown in FIG.3 are representative of the signals
FIG. 12 is a schematic drawing of the predriver module of shown in FIGS. 4 and 8. The Fset signal is preferably a 7
the present invention; microsecond pulse that marks the beginning of a 80 micro
FIG. 13 is a schematic drawing of the driver module of the second PWM cycle as described in more detail below. When
present invention; the Fiset signal is active, all of the low side H bridge
transistors are turned on. When the Fset signal is inactive.
FIG. 14 is a schematic drawing of the power supply the PhaseA, PhaseB and Phasec PWM signals are enabled
module of the present invention; and by the gating logic described below. When the Fset signal is
FIG. 15 is a schematic drawing of the current sense reasserted, the software of the microprocessor module 20
module of the present invention; 35 loads the other event processor array (EPA) compare logic
DETALED DESCRIPTION OF THE for that period. The Ao, Bo and Co signals originate from the
INVENTION EPA which is an internal logic block that is based on
programmable timers. The EPA is configured by the soft
FIG. 1 shows the prior art circuit diagram of the system ware to operate in a high speed PWM mode so that each
disclosed in U.S. Pat. No. 5,140,248 granted to Rowan et al. PWM channel is modified in real time to satisfy the current
As shown in FIG. 1 and described above, the prior art system requirements of the variable speed drive system.
includes a phase current regulator which is an analog circuit. As shown in the system diagram of FIG. 4, the variable
Further embodiments of the prior art system include an AC speed drive system 10 of the present invention includes a
or DC power supply regulators which are carried out in an grade module 12. The grade module 12 contains the elec
electronic regulator circuit. In the device disclosed in the 45 tronics for switching and rectifying the voltage used in
Rowan et al patent, the current of each phase is measured driving a DC grade motor 14. The grade motor 14 increases
and the output current is kept constant to the motor accom or decreases the angle or slope of the treadmill deck accord
modate fixed loads. ing to the signals received from the grade module 12. The
FIGS. 2 to 15 show the currently preferred embodiment of grade electronics provide either a positive or negative volt
a treadmill AC drive motor system for use with the present 50 age to the grade motor 14 with each polarity causing the
invention. Although the present invention is described below motor to turn in an opposite direction. Feedback for deter
with respect to the preferred use of the present invention in mining the slope of the treadmill deck is provided by a
combination with a treadmill, it is anticipated that the potentiometer mounted to a rack gear (not shown). As the
present invention may be used with various drive motor treadmill deck moves up and down, the grade pot 16 turns
systems where it is desirable to provide a constant torque 55 with it. A voltage is applied across the grade pot 16 and the
profile to the AC motor despite variable loads and line voltage at a tappoint on the potentiometer is measured and
voltage. received by the microprocessor module 20 as a tap signal 18.
The variable speed drive of the present invention is The grade of the treadmill deck is proportional to the voltage
preferably a microprocessor based, three phase, AC motor measured at the tap point and the microprocessor module 20
controller. The main function of the variable speed drive is sends up or down PWM signals to the grade module 12 in
to drive an AC motor that in the preferred embodiment response to the tap signal 18 to turn the grade motor 14 in
drives the walk belt of the treadmill. As described in more the appropriate direction.
detail below, the present invention generally utilizes sine The variable speed drive system 10 of the present inven
wave outputs which are synthesized by a variable speed tion also includes the microprocessor module 20 having a
drive using pulse width modulators and high current tran 65 microprocessor 22 and software. As shown generally in FIG.
sistor switches. The pulse width modulation signals vary in 4 and in more detail in FIG. 8. the microprocessor 22
duty cycle to effectively change the sine wave frequency and communicates with the external treadmill controller module
 5,747,955
7 8
24, sends pulse width modulated signals to the predriver module 40 which is in communication with a plurality of
module 26 and monitors various system parameters as bleeder resistors 42. The BRS module 40 is shown in more
described more fully below. In the preferred form of the detail in FIG. 11 and provides protection for the drive
present invention, the microprocessor 22 includes a com circuitry when the treadmill is at a grade which exceeds a
munications link to the treadmill controller module 24 which predetermined level such as 15%. In this situation, the user
preferably includes an RS422 serial link in the preferred may begin to "drive” the walk belt which in turn drives the
form of the present invention. As described more fully drive motor 38. This may occur because, as the drive motor
below, the microprocessor module 20 receives a signal. 38 is driven by the user, the drive motor 38 may act like a
shown as ABS in FIG. 4, from the adaptive bus scaling generator and build up excess energy. If this were to occur
system module 28 of the present invention. This signal is 10 and the 300 V bus exceeded the maximum voltage
preferably between about 0 to 5 volts DC and is proportional requirement, the controller module 24 would shut down the
to the bus voltage as described more fully below. The microprocessor module 20 otherwise, the components in the
microprocessor module 20 also receives fault signals from drive circuitry would be exposed to voltages in excess of
the predriver module 26 which indicate that a fault has their maximum ratings. To prevent this from occurring, the
occurred in the driver module 30 or the predriver module 26. 15 BRS module 40 includes the bleeder resistors 42 which are
As will be described more fully below, the fault signals designed to bleed off the excess energy from the 300 V bus
referred to herein include cross conduction errors, various so that the excess energy is dissipated prior to causing any
short circuits and overloads. damage in the microprocessor module 20.
As shown generally in FIG. 4 and in more detail in FIG. As shown generally in FIG. 4 and in more detail in FIG.
12, the predriver module 26 receives the pulse width modu 20 14, the power supply module 44 of the preferred form of the
lated signals from the microprocessor module 20. These present invention includes two switching regulators, 50 and
signals are shown as PHA, PHB and PHC in FIGS. 3 and 4. 51, to generate low voltage supplies of +12V, isolated, and
As described more fully below, the predriver module 26 +24 V, non-isolated, respectively. The +12 V supply pro
converts the PWM signals into high and low gate drive vides power for the ABS module 28 and the controller
signals for the power insulated gate bipolar transistors 25 module 24. Additionally, a linear regulator generates an
(IGBT) 32 in the predrivermodule 26. The predriver module isolated low voltage of +5 VDC from the +12 V supply to
26 also receives over current signals for each phase from the provide operating power for the microprocessor control
current sense module 34. These signals are shown as IMAH circuitry. The +24 V supply is used to provide non-isolated
for phase A, IMBH for phase B and IMCH for phase C in input for six linear regulators. Four of these regulators
FIG. 4. The predriver module 26 sends high and low gate 30 supply +15 V for the IGBT drivers. One 15 V regulator
drive signals to the driver module 30. These signals are supplies all three low side drivers (15 W power supply). Each
shown as AOUTH and AOUTL for phase A, BOUTH and high-side driver has its own 15 V regulator (+15 V, non
BOUTL for phase B and COUTH and COUTL for phase C isolated, flying power supply) since the ground reference for
in FIG. 4. each circuit "flies" to the buss voltage independently. The
The ABS system module 28 of the present invention is 35 other two linear regulators provide non-isolated +5 V
shown generally in FIG. 4 and in more detail in FIG. 10. As (5PHPWR) for the predriver module 26 (deadtime generator
described more fully below, the ABS system module 28 circuit) and (5 V 7800) for the ABS module 28. The 300
generates an isolated low voltage signal which is propor VDC is supplied as a high voltage, high current supply for
tional to the 300 volt bus. This signal is shown in FIG. 4 as the driver module 30 which is then supplied to the drive
ABS and is passed to the microprocessor module 20 for motor 38 and monitored by the ABS module 28 and the
digitization and monitoring as described more fully below, bleeder resistors 42.
The driver module 30 of the present invention is shown FIG. 5 is illustrative of the peripheral interfaces to the
generally in FIG. 4 and in more detail in FIG. 13. The driver variable speed drive software module 60 of a preferred form
module 30 preferably includes IGBT drivers which include of the present invention. The following is intended to
six insulated gate bipolar transistors (IGBT) which are 45 provide an illustrative description of the general operating
configured as 3 "H" bridges. The driver module 30 is environment of the preferred form of the present invention
preferably self contained and includes transistors and pro without limiting the present invention to the specific
tection diodes mounted and potted together. The driver embodiment described herein. As shown in FIG. 5, one of
module 30 receives the high and low gate drive signals from the interfaces is a reset monitor 62. The reset monitor 62 is
the predriver module 24 to turn the IGBT switches on and preferably an external reset monitor device (not shown)
off. which provides the variable speed drive software module 60
As shown in FIGS. 4 and 15, the current sense module 34 with an external reset signal. When a reset signal is detected,
of the present invention monitors the current of each of the a self test process is performed. If an error is detected, a self
three phase wires on their way to the drive motor 38. These test error detect message is sent to an error handling process
signals are shown in FIG. 4 as UA, U B and UC and 55 in the software module 60. If no errors are found in the self
represent the high current three phase motor signals between test, an initialize variable speed drive message is sent to the
the driver module 30 and the drive motor 38. As described initialization process of the software module 60 and the
more fully below, if a threshold is reached by the high variable speed drive is initialized for normal operation. If no
current three phase motor signals, a fault is sent back to the errors are found during initialization, a start up variable
predriver module 26 to shut down the appropriate IGBT for speed drive message is sent to the background control
the rest of that cycle and to the microprocessor module 20 process where it starts up the real time executive for real
and the controller module 24. If further over current faults time processing. If a time out occurs in any process, a reset
are generated by the current sense module 34, the micro message is sent to the self test process where the system is
processor module 20 will shut the variable speed drive reset and initialized. The background control process con
system 10 down. 65 trols and sequences all non-time critical tasks while the real
As shown in FIG. 4, the microprocessor module 20 also time executive controls and sequences all time critical tasks.
sends a BRS signal to the bus recovery system (BRS) Control is passed between the background and real time
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control processes via two messaging paths with the real time interface 70 to gain access to a filtered representation of the
task message having the highest absolute priority. Control is buss voltage. The A to D process converts a 0 to 5 b
returned to the background control process via a background 57475246,001 volt analog input into an 8 bit integer where
task message when all real time tasks are completed. it is then filtered. The result is then placed into an adaptive
The next interface shown in FIG. 5 is the communications buss voltage register for use by the pulse width modulation
interface 64. The control flows originate from an external control interface 74 and buss recovery system interface 70.
communications interface module such as an external The microprocessor module 20 operates in part according
RS-422 module and provide the software module 60 with to a software controlled state machine. FIG. 6 shows the
transmit and receive capabilities. The purpose of the com state machine and illustrates the pulse width modulation
munications interface is to allow a host controller, such as O speed control process. FIG. 7 illustrates the overall PWM
the controller module 24 shown in FIG. 4, to send command control process in further detail. A real-time clock 78 is
packets and receive status and control information from the connected to 80 usecond timer 80. The 80 second timer 80
software module 60. sends an interrupt every 80 seconds to a real-time executive
Another interface shown in FIG. 5 is a variable speed 82. The interrupt “wakes up" real-time executive 82 and
drive LED indicator 66. The data flow path of the LED 15 directs real-time executive 82 to initiate the software module
indicator 66 provides self test flash codes and provides an called pulse width modulation (PWM) parameter builder 84.
indication of a start enabled condition for service personnel. The PWM parameter builder 84 constantly senses param
After a self test is completed and an error is located that eters of the treadmill belt system through sensors 86, 88 and
indicates that communications cannot be established, the
20
90. The sensors 86, 88 and 90 measure the speed and status
LED will flash. If no errors are found and communications parameters of the system of interest in determining the pulse
are able to be established, the LED will remain off. width modulation signal sent to the drive motor 38. The
Another interface shown in FIG. 5 is the grade interface sensors 86.88 and 90 are connected to PWM parameter
68. The grade interface 68 allows the software module 60 to builder 84 through an A-to-D converter 92. As a result of the
interface with the elevation system of the treadmill which interrupt generated by 80 usecond timer 80, the PWM
controls the grade or angle of the deck of the treadmill. The parameter builder 84 samples and stores the parameters of
grade and feedback control signal is sampled and filtered by the system of interest every 80 seconds.
an Ato D control process as described more fully below. The The parameters of the system of interest in determining
Ato D process samples the grade feedback voltage and then the PWM signal sent to the drive motor 40 are preferably the
filters and grades the result. Once ready, the new feedback current speed of the treadmill belt, the target speed of the
level is stored in a buffer. The background control process is treadmill belt and the variable speed drive status. The
responsible for generating all control and pulse width modu sensors 86.88 and 90 sense the current speed of the treadmill
lation responses necessary for proper grade operation by belt, the target speed of the walk belt and the variable speed
using both current and target grade parameters to determine drive status, respectively.
when a grade change is necessary. 35 The wave form building parameter module 94 is a soft
Another interface shown in FIG. 5 is the buss recovery ware module which retrieves the system parameters from
signal (BRS) interface 70. The buss recovery signal interface PWM parameter builder 84 and the adaptive buss signal
70 is used to switch a power resistor on when the buss voltage register 96. The wave form building parameter
voltage exceeds a predetermined level. The background module 94 then passes these values to the three PWM signal
control process periodically sends a check message to the constructing modules phaseA PWM constructing module
buss signal interface 70 for the buss signal interface 70 to 98, phaseB PWM constructing module 100 and phasec
sample the adaptive buss scaling voltage and if the voltage PWM constructing module 102. The phaseA PWM con
exceeds a predetermined level the power resistor is turned structing module 98, phaseBPWM constructing module 100
on and the voltage is switched to the bleeder resistors 42 and phasec PWM constructing module 102 are each con
until the voltage decreases to a safe level. 45 nected to a PWM frequency reference generator or event
Another interface shown in FIG. 5 is the drive fault processor array (EPA) 132 as shown in FIG.7. The EPA 132
interface 72. The driver fault interface 72 is responsible for provides the reference signal that determines the frequency
detecting and responding to driver fault event signals. In the of the individual pulses of the PWM signal. In the preferred
event of a valid over current situation, the fault status embodiment, the PWM cycle time can range from about 80
checking process of the driver default interface 72 signals 50 usecond to 500 usecond but is preferably set for a cycle time
the software module 60 to stop the pulse width modulation of approximately 80 useconds.
process to disable all pulse width modulation signaling and Each PWM constructing module 98, 100 and 102 is
sends a message to the LED indicator module 66 and the connected to the wave formA data base 106, wave forms
host remote control unit. database 108 and wave formC database 110. Each database
Another interface shown in FIG. S is the pulse width 55 contains sine, saturated and supersaturated wave form infor
modulation control interface 74. The pulse width modula mation. The term "Saturated" as used herein is intended to
tion control interface provides the software module 60 with mean that the absolute value of the amplitudes of the
pulse width modulation, timing and output control signals waveform is larger than the corresponding absolute value of
and is shown in more detail in FIG.7. This process monitors the amplitudes for a sine wave. The term "Supersaturated"
current and requested speed and updates all pulse width as used herein is intended to mean that the absolute value of
modulation control parameters. the amplitudes of the waveform is larger than the corre
Another interface shown in FIG. 5 is the adaptive buss sponding absolute value of the amplitudes for a "saturated"
scaling interface 76. The adaptive buss scaling module 28 is sine wave. The wave form databases 106, 108 and 110 are
shown in more detail in FIG. 10. The adaptive buss scaling preferably memory registers containing "words" that digi
interface 76 provides the variable speed drive system 10 65 tally represent different shaped waveforms. In the preferred
with the adaptive buss scaling voltage that allows the pulse embodiment, the wave formA data base 106 contains the
width modulation control interface 74 and the buss recovery data to produce a wave form for Phase A. The wave formb
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data base 108 contains the data to produce a wave form for up to read all of the registers and produce three PWM signals
Phase B. The wave formC data base 110 contains the data every 80 useconds. In the present invention, a double
that produces a wave form for Phase C. buffered system is preferably used to call either the A or B
The PWM constructing modules 98, 100 and 102 use the buffers of data at the request of the real time executive 82 to
system parameters presented the from wave form building enable the PWM ISR process 120 to build the next point of
parameter 94 and the data contained in the wave form data the three waveforms. With a double buffered system, one set
bases 106, 108 and 110 along with the timing signal from of buffers is updated while the PWM ISR process 120 is
EPA 132, to produce three PWM signals. reviewing the other set of buffers. When the PWM speed
The PhaseA PWM constructing module 98 provides the control process 126 (as shown in FIG. 6) is updated, all of
10 the buffers are updated with a switch called the wave buffer
PWM Output signals that drive coil(A) of the three-phase select 128. The PWM speed control process 126 is called by
AC drive motor 30 based on the following equation: the real time executive process 80 and has the ability to
select its own call back rate so that as speed is increased or
PWM Phase(A)=(Wnt/ABS)xSinwri decreased, the call back rate of the PWM speed control
5 process 126 may be increased or decreased. This allows the
where Vm is buss voltage. treadmill to use what are called "soft" starts where the speed
The PhaseB PWM constructing module 100 provides the of the walk belt is gradually increased irrespective of the
PWM Output signal that drives coil(B) of the three-phase initial speed selected by the controller module 24. Otherwise
AC drive motor 38 based on the following equation: the walk belt may start abruptly at the speed selected by the
user or controller module 24 without a gradual increase in
speed. This abrupt type of speed change may potentially
PWM Phase(B)=(Vn/ABS)xSinwf-120°. startle or injure the user. Similarly, as the speed of the walk
Where the phrase "wt-120” means that the varying sine belt is decreased, the speed change is preferably gradual
wave sin(wt) that varies with time is phase shifted by 120°. rather than an immediate speed change unless an emergency
25 stop or serious fault condition exists where it is desirable to
The Phasec PWM constructing module 102 provides the stop the walk belt as quickly as possible.
PWM Output signal that drives coil(C) of the three-phase The phase index register 118 is essentially an index into
AC drive motor 38 based on the following equation: the wave form data channel to determine the phase position
of the three waveforms. Additionally, a phase step register
30 130 is also used to determine the sampling rate or speed at
PWM Phase(C)=(Wnt/ABS)xSinwr-240.
which the wave form is updated so that at slower speeds a
Where the phrase "wt-240” means that the varying sine smaller increment is used and, at faster speeds, a larger
wave sin(wt) that varies with time is phase shifted by 240°. increment is used by the PWM ISR process 120. The event
As a result of the output from the phase constructing processor arrays (EPAs) 132 are configured as pulse width
modules 98, 100 and 102, three PWM signals are produced 35 modulated channels and are designed to receive the PWM
that differ from each other only in the phase of the PWM data from the PWM ISR processor 120.
signal. FIG. 8 is a schematic drawing of the modular architecture
FIG. 7 shows a high level data flow diagram for the of the microprocessor module 20. As described above, the
software operation of the PWM Control Process that is microprocessor module 20 generally includes a microcon
carried out in the microprocessor module 20. The micro troller 22 and software where the microcontroller 22 com
processor module 20 contains a number of registers. Three municates with the controller module 24, sends pulse width
of these registers are called WaveformA, Waveformb and modulated signals to the predriver module 26 and monitors
WaveformC registers identified as 112, 114 and 116, respec various system parameters.
tively. The microcontroller 22 preferably includes a high inte
Another register is called the Phase Index register 118. 45 gration internal controller having a 16 bit central processing
The Phase Index register 118 contains information about the unit as a basic core component. A register RAM, an 8
phase position of the waveforms contained in registers channel A to D converter, a serial I/O port, timers and an
Waveform A. Waveform B and WaveformC. event processing array (EPA) surround the CPU and are used
The PWM interrupt service routine (ISR) Process 120 to generate the pulse width modulated signals as described
controls the PWM drivers 122. The PWM ISR Process 120 50 above.
produces pulses having a width determined according to the As shown in FIG. 8, the microprocessor module 20
following equations: receives a signal from the predriver module 26 shown as
Fault. This signal is optically isolated and buffered so that
the software of the microprocessor module 20 reacts to the
Phase A width=Fset time"0.58-96Flux(Wspeed)"Vbuss/ABS 55 receipt of the Fault signal in different ways depending on the
voltage'satsine(wt). current state of the system. The microprocessor module 20
Phase A width=Fset time"0.58-%Flux(Wspeed)"IVbuss/ABS also receives a reset signal from the voltage monitor and
voltage'satsine(wt-120). reset integrated circuit 134 to return the internal logic of the
Phase A width=Fset timeO.58-9Flux(Wspeed)*Vbuss/ABS -
microprocessor 22 to a known state upon receipt of the
voltage'satsine(wt-240). signal. The microprocessor module 20 also receives an RXD
signal which consists of a serial bit input stream through a
The resulting PWM signals produce synthetic sine waves suppression circuit 138 and buffer 140 from the controller
having frequencies ranging from 0 to 120 Hz. module 24. The signals shown as AD0-AD15 consist of a
As shown in FIG. 7, the PWM control process is essen micro data buss where data is read from and written to
tially a data base of wave forms so that the phase index 65 peripherals such as the waferscale microprocessor periph
register 118 is used by the PWM ISR process 120 every 80 eral 136. The waferscale peripheral 136 contains fixed
microseconds through an 80 second timer 80 which is set programmemory and static RAM for the microprocessor 22.
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These two memories share the same address and data port such as a HCPL 7800 manufactured by Hewlett Packard is
out of the device and are selected by internal decoding logic. used to send the raw data across the optical isolation
The signals shown as RD and WR are low level signals that boundary 152. Once the data is on the microprocessor side
indicate the microcontroller 22 is reading or writing data of the isolation boundary 152, the differential voltage is
from or to the waferscale peripheral 136. The signal shown filtered and scaled by a differential optical amplifier 154 to
as ALE is an address latch enable signal which is used by the provide the appropriate signal level required by the micro
peripheral 136 to latch the address from the A/D buss during processor module 20.
the appropriate part of the cycle. As shown in FIG. 10, the input to the ABS module 28 is
The PWM gating logic 142 is the logic which supports the the drive buss (Vbuss). The preferred range of measurement
microprocessor event processor array channels 144 shown for the ABS module 28 is between about 0 VDC to 600
as EPA0, EPA1. EPA2 and EPA3. Preferably the three EPA VDC. The resistors 156 provide the proper scaling for the
channels, EPA1-EPA3, generate a raw PWM signal and the isolation amplifier 150. The preferred resistors have a maxi
EPA0 channel generates an Fset signal as shown in the mum voltage rating of 200 V and therefore... three resistors
drawings. As shown in FIGS. 3 and 8, and described above, which are preferably of equal value are used to step the
the Fset signal marks the beginning of the PWM cycle and 15 voltage down to the isolation amplifier level.
is gated with all three PWM signals. The enable signal from As described more fully below, the drive buss includes
the microprocessor 22 to the gating logic 142 enables the two frequency ranges of concern. The first frequency of
PWM signals to transition when active. When the signal is concern is known as the rectification frequency or twice the
inactive, the PWM signals all go to a high state. Because all line frequency. In the preferred form of the present
of the I/O pins of the processor go to high impedance during invention, the rectification frequency is preferably a mini
reset, a pull down resistor is added to this signal so that the mum value of approximately 100 Hz due to the existence of
signal stays inactive during reset. European and Japanese line frequencies of 50 Hz and
As described above, the Fset signal is preferably a 7 includes the value of approximately 120 Hz for line fre
microsecond pulse that marks the beginning of the 80 quencies in the United States.
microsecond PWM cycle. When the Fset is active, all low 25 The other frequency of concern is at approximately 3 Hz.
side transistors are on. When the Fset signal goes inactive for This frequency is caused by the footfalls of a user on the
the remainder of the cycle, Phase A, B, and Care enabled by treadmill deck. The ABS module 28 is designed to attenuate
the PWM gating logic 142. During the period that the Fset the 100 Hz rectification ripple with an input filter 158 prior
signal is asserted, the software loads the other EPA compare to the isolation amplifier 150 which provides a 3 dB fre
logic module 132 (FIG. 7) with the PWM information for 30 quency of approximately 470 Hz and an output filter 160 at
that period. The signals shown in FIGS. 3, 4 and 8 as A0, B0 the output of the differential optical amplifier 154 as
and C0 originate from the microprocessor event processor described below. The ABS module 28 also passes the 3 Hz
array which is an internal logic block that is based on footfall frequency to an ABS software module which pro
programmable timers and is configured by the software to wides a stabilization filter as needed.
operate in a high speed PWM mode. Each PWM channel is 35 The isolation boundary 152 of the isolation amplifier 150
modified in real time to satisfy the current requirements of provides electrical isolation between the drive buss and the
the system. microprocessor module 20. The input to the isolation ampli
FIG. 9 is illustrative of the optical coupler system 146 of fier 150 is converted to a digital value using a conventional
the present invention between the microprocessor module 20 A to D converter. The digital value is then serially encoded
and the predriver module 26. The coupler system 146 and optically transmitted across the isolation boundary 152.
provides isolation between the phase input signals and the Once the data is across the isolation boundary 152, the data
output phase drive signals and include an interface for the is given a fixed gain and decoded and converted into a
phase input signals shown in FIG. 4 as PHA, PHB and PHC. differential analog voltage by the isolation amplifier 150.
These phase input signals are derived from the microcon The differential amplifier 154 referred to in FIG. 10 as
troller 22 and are decided through phase decoding logic. The 45 LM358 provides the gain to reach the desired levels. The
phase input signals feed optocoupler input lines on the differential optical amplifier 154 preferably has a +12 V
isolated side of the system 146 and require drive levels of power supply to allow it to have a full 0 V to 5 V swing.
approximately +5 V CMOS. The +5 volt isolated input bias The output filter 160 preferably receives the output of the
power is converted to light energy via an LED emitter 148 differential optical amplifier 154 and attenuates the 100 Hz
in order to cross the isolation boundary. The output signals 50 minimum rectification frequency of the buss voltage. The
feed a crossover delay phase splitter system and are prefer preferred form of the output filter 160 is a single pole filter
ably non-inverted versions of the phase input signals. The which preferably is a combination of a 10K Ohm resistor
variable speed drive system 10 also includes the fault signal 162 and a 1 microfarad capacitor 164. The output filter 160
between predriver module 26 and the microprocessor mod provides a -3 dB frequency of approximately 16 Hz.
ule 20 as shown in FIG. 4. The fault input signal is derived 55 Therefore, when the output filter 160 and the input filter 158
from the predriver module 26 and feeds an optical coupler are combined, the attenuation of the 100 Hz minimum
input line (not shown) on the non-isolated side. The output rectification frequency is approximately -16.5 dB and the
signal feeds the cross over delay phase splitter system and is attenuation of 120 Hz would be approximately -18 dB. The
a non-inverted version of the input signal. The isolated input preferred specifications of the ABS module 28 include again
bias power is converted to light energy through an LED of approximately 0.0078833+/-6% for 0 V</=Vbuss</=600
emitter (not shown) in order to cross the isolation boundary. V and more preferably between about 200 V and 600 V to
FIG. 10 is a schematic diagram of the adaptive buss provide a buss voltage of approximately 2.49 V per proces
scaling module (ABS) 28 of the present invention. As sorbit and a frequency response where the 3 Hz frequency
described briefly above, the ABS module 28 provides the is attenuated less than 0.25 dB and the 100 Hz frequency is
microprocessor module 20 with an analog voltage signal 65 attenuated more than 15 dB.
which is proportional to the voltage of the drive buss. The As shown in FIGS. 4 and 11, the buss recovery module 40
drive buss is typically 300 volts. An isolation amplifier 150, includes an optocoupler 166, an input LED bias resistor 168,
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an opto output resistor 170, a gate drive transistor 172, a also has a charge pump circuit to generate a negative voltage
transistor switch 174 and the bleeder resistors 42. As as a gate drive off signal.
described above, the BRS module 40 protects the variable The first chipset receives two drive signals from the
speed drive system 10 from excess voltage conditions by deadtime generator 176, one for each of the upper and lower
bleeding off the excess voltage through the bleeder resistors IGBTs. The signal for the upper IGBT is passed from the
42. In the preferred embodiment of the present invention, the first chipset to the second chipset. The signals between the
BRS module 40 is activated when the ABS module 28 first and second chipsets are provided by pulse transformers
indicates that the buss voltage is generally in excess of about to maintain isolation. The drive signal is transmitted from
400 V and more preferably about 412 V and will be the first chipset to the second chipset and the fault signals for
inactivated when the buss voltage is about 375 V and more 10 the upper IGBTs are ORed and transmitted from the upper
preferably about 407 V. IGBT to the lower IGBT and then back to the microproces
As shown in FIGS. 4 and 12. The predriver module 26 sor module 20. The fault signal includes an indication of the
includes a deadtime generator 176, a pair of chipsets in each overcurrent of an IGBT and under voltage on both the
IGBT driver for each phase, 178, 180 and 182 and various positive supply and the negative charge pump generated
peripheral components. The predriver module 26 receives supply. Both chipsets include internal negative charge
15
signals from the microprocessor module 20, injects a dead pumps to provide negative gate off drive signals for the
time and generates gate drive output signals for the low and IGBTs. The charge pumps also provide a negative power
high side half bridge switches in the insulated gate bipolar supply regulated at 20 volts below the positive supply rail
driver module. In the preferred form of this embodiment, such that if a supply voltage is at +15 volts, the local driver
there is preferably a single deadtime generator 176 which 20 ground will be -5 volts. The overcurrent circuit is used in a
receives three inputs from the microprocessor module 20 desaturation detection mode by measuring the voltage across
and provides three sets of outputs. The outputs are shown in one resistor in a resistor divider across the power transistor
FIG. 4 as three sets of two signals, with one set of three in the "on" state. Because the collector-emitter voltage is
signals for each of the three pairs of chipsets and the approximately one half the buss voltage (or 150 V, typical)
switches in the respective IGBT driver 178, 180 and 182. 25 during a cross-conduction condition (i.e., upper and lower
The first chipset of each driver preferably controls the transistors of a H-bridge are "on" simultaneously), sensing
second chipset of the driver which then generates signals for this voltage using the resistor divider network described
the high side half bridge switches in the driver module 30. above can provide effective protection against this condi
As shown in FIG. 12 for the Phase A signal, the current sense tion. Although cross-conduction causes exceedingly high
module 34 also interfaces between each of the high side 30 currents to flow through the drive transistors, this circuit is
switches and the IGBTs of the respective driver module 178, actually sensing "on" state collector-emitter voltage. This
180 or 182 to provide a similar function to the low side voltage, after attenuation by the resistor divider network,
function described below. The deadtime generator 176 passes to an "M" pin (not shown) which is referenced to a
receives three electrically isolated signals though the opto KG pin (KG AL of FIG. 12) that is preferably a Kelvin
couplers of the microprocessor module 20 for the A, B and 35 ground which is intended to be connected to the kelvin
C phases. The deadtime generator 176 has an internal state source of the power device for accurate low-voltage mea
machine (not shown) that works with either an internal surements in the presence of inductive transients on the
crystal oscillator, such as a parallel resonant oscillator, or an power device source terminal.
external clock to provide precise signal timing. In the The second chipset preferably has generally the same
preferred form of the present invention, a parallel resonant functions as the first chipset except that it is designed for use
oscillator with two capacitors and a resistor are used. When with the high side IGBT. The drive signal is transmitted from
a phase level change is input to the deadtime generator 176, the first chipset to the second chipset through one winding
it is first synchronized with the oscillator. The on input is pair of a pulse transformer to provide isolation for the
then switched off for a deadtime of eight clock periods and second chipset. Another winding pair of the pulse trans
then a complimentary output is switched on. The clock 45 former transmits fault signals from the second chipset to the
periods are preferably set using an external 16 MHz oscil first chipset for transmission to the microprocessor module
lator with a deadtime of approximately 500 nanoseconds. 20. Although the preferred form of the first chipset includes
The three sets of outputs generated by the deadtime genera only one single desaturation overcurrent, the second chipset
tor 176 go to each of the pairs of the chipsets. The deadtime has a second overcurrent circuit ORed to the same IM pin or
generator 176 also includes a reset pin to keep the outputs in 50 input.
the off condition during start up. A current sense resistor is preferably in series with the
The chipsets are designed to work as a set to drive the motor winding of the drive motor 38 and a differential
upper and lower IGBTs which are connected in the half amplifier monitors the current. Excessive current, such as
bridge configuration. As shown in FIG. 4, the deadtime 11.5 amps peak, over a period of time will cause a com
generator 176 transmits two outputs per phase and both 55 parator to go high back to the IM pin which will set the
outputs are received by the low side chipset. A pair of small overcurrent fault. The current sense resistor is preferably
pulse transformers preferably provide isolation and commu designed to monitor relatively long term excessive current
nication between the edge triggered receivers of the lower due to the wearing of the deck and walk belt as described
side drive and the upper side drive. In this embodiment, the below. The logic ground for the second chipset is preferably
lower side drive sends the necessary gate drive control a floating ground which is tied to the emitter of the top
signals to the high side driver provided that both the low and IGBT. When the IGBT is turned on, the emitter and therefore
high side drivers are not required to be on at the same time. the logic ground are pulled up to the 300W buss. The power
The high side driver is preferably referenced to a floating for the second chipset during this period is provided by a
ground which is tied to the emitter of the high side driver. large capacitor which is charged when the bottom IGBT is
The present embodiment also preferably includes shut down 65 on. The charging diode is reverse biased when the top IGBT
protection circuitry to protect the power devices from the is on and the circuit is supplied by energy from the capacitor.
existence of an overcurrent situation. Each chipset device Because the supply voltage for the second chipset has the
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charging diode drop, and the bottom IGBT Vce (on) in tary over current conditions, such as those encountered with
series, the first chipset's power supply is not adequate. The the footfalls of a user, must be filtered to provide an accurate
supply voltage for the second chipset is regulated down from average current value and then when the average value
the 24 V to 15 V by a three terminal regulator. exceeds the preselected motor current rating the variable
F.G. 13 is illustrative of the driver module 30 of the speed drive system 10 is shut down to protect the drive
present invention and includes a plurality of power IGBTs motor 38 before damage actually occurs.
36. As shown in FIG. 13, the driver module 30 is generally Due to the low level voltages generated by the current
self contained and preferably includes six transistors and sense resistor and the electrically noisy environment of the
diodes which are mounted and potted together. FIG. 13 also high side switching, a differential input stage 190 (FIG. 15)
illustrates the motor windings and general location of the O consisting of an operational amplifier 194 and the resistors
inputs for motor signals to the drive motor 38. which are shown as R2-R5 in FIG. 15 are used to provide
FIG. 14 is schematic of the preferred form of the power a typical voltage gain of -18.33. The diodes 192, which are
supply 44 of the present invention and is provided to shown as D1-4 in FIG. 15, rectify the output of the opera
illustrate the various power requirements of the modules and tional amplifier 194 so that only the motor voltages which
components of the preferred form of the present invention. 5 are less than the insulated gate bipolar transistor output
FIG. 15 is a schematic drawing of the current sense voltages have a non zero gain and the IGBT out signals are
module 34 described briefly above. In the preferred form of approximately equal to the logic ground voltages of the high
the present invention, the current sense module 34 consists side predriver (such as 4411 LG shown in FIG. 15) that
of three separate modules which continually monitor the provide the ground reference for the high side predriver
high side current (U. A., U B and U C) to each of the three 20 circuits. The rectification of the output of the resistors 190
motor phases. Each module is preferably identical to each provide a signal which, assuming the input voltage is
other and the sensing for each phase current is performed to sinusoidal, has an average value of 0.3183 times the peak of
provide protection in the event of a single fault condition as the sinusoid, or 0.45 times the RMS of the sinusoid. When
well as to provide redundancy and commonality for the this is combined with the input stage gain. an overall gain of
operation of each phase. 25 5.8355 times the average value of the sinusoid or 8.25 times
The current to each motor phase is preferably sent through the RMS value of the sinusoid is achieved.
a resistor 184 (FIG. 13) such as a 0.02 Ohm, 4 lead resistor The resistor 196 shown as R7 and the capacitor 198
to create a voltage level which is sensed by the current sense shown as C3 then filter the rectified signal from diodes 192.
module. The 4 lead resistor is used to eliminate the effect of With a typical time constant of 2.2 seconds and -3dB point
the high current causing voltage drops in the lead impedance 30 of 0.0722 Hz, the filter (196 and 198) is used to provide both
of the resistor such that the sense leads do not carry the high an average value after the rectification but also to filter out
current and are internally routed from the 0.02Ohm resistive the effect of current surges due to footfalls by the user. After
element. filtering by 196 and 198, the voltage is then compared to a
Each module includes two sense circuits to provide pro 1.235 V level generated by the precision rectifier 200 shown
tection in the event of two separate types of faults which are 35 in FIG. 15 as U2 and a resistor 202 shown in FIG. 15 as R8.
referred to herein and shown in FIG. 15 as a slow sense The comparison is performed by an operational amplifier
circuit 186 and a fast sense circuit 188. In the event of an 220 and when the filtered voltage exceeds 1.235 V, the
over current condition being sensed in either the slow or fast output of the operational amplifier 220 goes high. In a
circuits, 186 or 188, the line known as the IM line of the high normal mode which is not over current, the output is
side driver is driven high to cause the high side predriver of approximately equal to the signal represented as Vee or -6
the predriver module 26 to turn off the high side transistor V with respect to the logic ground of the high side predriver
immediately and report the fault condition to the micropro module 26. When an over current occurs, the output of the
cessor module 20. operational amplifier 220 changes to approximately a signal
The slow sense circuit 186 is useful to detect changes in represented as Vdd or +15 V with respect to the logic ground
the requirements of the variable speed drive system 10 45 of the high side predriver. When the output exceeds the
which may occur over a relatively long period of time. For signal shown as IGBTKG by the diode drop of one of the
example, as the walk belt and deck gradually wear out, the diodes 204 shown as D2-3, it is scaled by a factor of
power required for the motor to perform to the load speci approximately 0.45 by resistors 206 shown in FIG. 15 as R9
fications of the treadmill will be exceeded by the drive motor and R1 and routed to the line shown as IM input. When this
38 because of the increased frictional resistance of the walk 50 input exceeds 0.24 VDC to 0.45 VDC the respective IGBT
belt on the deck. If this condition is allowed to continue, the driver 178, 180 or 182 turns off the high side transistor and
drive motor 38 will eventually exceed the manufacturer's sends a fault indication signal to the microprocessor module
specifications for the drive motor 38 and possibly overheat. 20.
If this occurs, the windings may short circuit and destroy the The circuitry of the variable speed drive system 10 can
drive motor 38. Because this type of motor damage requires 55 survive direct short circuits for only short periods of time
a relatively significant length of time before damage actually exceeding 10 microseconds. As described above, the slow
occurs (tens of seconds or minutes), the slow sense circuit sense circuit 186 responds in the range of seconds to protect
186 will shut down when the magnitude of the overload is the drive motor 38. Therefore, a fast current sense circuit
relatively small. Additionally, because the heating of the 188 is also provided to protect the variable speed drive
motor windings occurs as a result of the average current used system 10. The fast current sense circuit 188 is designed to
by the drive motor 38, a safe thermal equilibrium may be rapidly sense large high side currents such as currents in
obtained while the current swings above and below the excess of 20 A. When a fault is sensed by the fast current
steady state maximum as long as the average current value sense circuit 188, the high side transistor is turned off and a
is at or below a predetermined maximum value. The prede fault indication signal is sent to the microprocessor module
termined maximum value is preferably chosen based on the 65 20.
specifications or rating of the drive motor 38. Therefore, in The fast current sense circuit 188 includes a differential
order to sense legitimate over current conditions, momen amplifier at the input stage. As shown in FIG. 15, the
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19 20
resistors 210 shown as R10-R13 and operational amplifier IGBTKG. When the IGBT driver 178, 180 or 182 sends out
212 shown as U1-B provide a differential gain of approxi the signal to turn on the high side drive transistor, it releases
mately -2.93 typical. The resistor 214 shown as R14 and the the line shown as IM to the signal represented as IGBTKG
capacitor 216 shown as C2 form a network which is a high to short and allows the IM line to be driven externally. As
frequency filter which attenuates noise. The resistor 218 described above, if the voltage reaches 0.3 V typical, the
shown as R15 provides a small amount of hysteresis to the high side transistor is turned off and a fault indication is sent
operational amplifier around 200 mV so that the circuit does to the microprocessor module 20. Two 280K Ohm resistors
not repeatedly turn on and off if the voltage input fluctuates (not shown) are connected in series from the collector of the
near the threshold level. When the voltage input to the high side drive transistor to the IM line. The IGBTKG line
operational amplifier 212 (U1-A) exceeds 1.235 V typical, O is connected to the emitter of the high side drive transistor.
the output of the operational amplifier 212 (U1-A) goes This circuit is designed to turn off the transistor if a cross
conduction situation occurs so that approximately one half
high. In a normal mode without an over current situation, the of the full buss voltage will be dropped across the collectorf
output of the operational amplifier 212 is approximately emitter of both of the high and low side transistors. When the
equal to the signal represented as Vee or -6 V with respect high side transistor is off, the approximately 300 V which
to the logic ground of the IGBT driver 178, 180 or 182. 15 pass across the collector/emitter of the high side drive
When an over current situation occurs, the output of the transistor would generate a voltage of 10.6 V at the IM line
operational amplifier 212 changes to a value approximately if it was not shorted to the IGBTKG line by the internal
equal to the signal represented as Vdd or +15 V with respect controller of the IGBT driver 178, 180 or 182. When the
to the logic ground of the IGBT driver 178, 180 or 182. transmitterfemitter is on, the collectorfemitter voltage drops
When the output exceeds the signal represented by IGBTKG 20 to less than 4 V. This represents a voltage of 0.14 V at the
by the diode drop of diodes 204, the output is scaled by a IM line which is significantly below the 0.25 V which is the
factor of approximately 0.9 by the resistor 222 shown as R16 minimum fault level.
and the resistor 206 shown as R1 and routed to the IGBT The capacitor 224 shown as C10 provides the delay
driver 178, 180 or 182 shown as IM input. When this input Because necessary to allow the high side transistor to be turned on.
exceeds 0.24 VDC to 0.45 VDC (0.30 VDC typical) the 25 178, 180there is a finite time between when the IGBT driver
IGBT driver 178, 180 or 182 turns off the high side transistor releases the shortsends
or 182 the signal to turn on the transistor,
and sends a fault indication to the microprocessor module when the transistoris fully on,thetheIMcapacitor
between line and IGBTKG and
224 provides the
20.
The current sense module 34 also includes several other delay necessary to prevent an accidental fault voltage at the
components which are not specifically required to meet the 30 IM line. The capacitor 224 is sized to ensure that the
requirements of the current sense modules described above. presenttransistor's collectorfemitter voltage during turn on does not
The first component is a pull up resistor shown as R17. In conditions a fault voltage at the IM line even during high line
normal operation, the 0.02 Ohm sense resistor is between 100 V across while ensuring that a cross conduct condition of
"Motor" and "IGBEout". To ease in-circuit testing of the nated as rapidlytheascollector/emitter when fully on is termi
possible and within 10 microseconds or
module, a removable jumper (not shown) is placed between 35 less.
the 0.02 Ohm resistor and "IGBTout". This allows the
"IGBTout" signal to be driven positive with respect to the What is claimed is:
"Motor" signal without having to drive the 0.02 Ohm 1. An AC drive motor system for a treadmill having a
impedance of the sense resistor. If the jumper is not in place, microprocessor module, predriver module and driver mod
the sense circuitry's proper operation cannot be assured. In ule therein to provide pulse width modulated signals to a
this situation, the pullup resistor causes the "IGBTout" drive motor and a current sensing circuit therein, the circuit
signal to be approximately equal to the signal represented as including;
Vdd or +15 V with respect to the logic ground of the IGBT a fast sense circuit for detecting the occurrence of a first
driver 178, 180 or 182 and both the slow and fast current current in excess of a predetermined value for an AC
sense circuits, 186 and 188, will go into a fault mode to 45 drive motor system to prevent rapid damage to said AC
prevent treadmill operation. When the jumperis in place, the drive motor system wherein said fast sense circuit
"IGBTout" will have the same potential as the signal rep senses the current of pulse width modulated signals
resented as IGBTKG and which is approximately equal to between the drivermodule and the drive motor wherein
the logic ground of the IGBT driver 178, 180 or 182. said signals have controlled cycles and when said
The current sense module 34 also includes Vee generator 50 current of said sensed signal is greater than a prede
components that are required for the operation of the IGBT termined threshold, said fast sense circuit sends a fault
driver 178, 180 or 182. Various capacitors and diodes (not signal to said predriver module to close a switch for the
shown) are also required as external components for the remainder of said cycle of said sensed signal; and
operation of the internal controller of the IGBT driver 178, a slow sense circuit to detect the occurrence of a second
180 or 182. When the Vee generator is combined with the 55 current in excess of a predetermined value which is
IGBT driver 178, 180 or 182, a voltage of approximately 21 caused by a gradual fault condition wherein said fault
V less than the signal represented as Vdd voltage is gener condition results from the increased frictional resis
ated and the signal represented as Vee voltage is typically tance to the rotation of the walk belt of a treadmill on
about -6 V with respect to the logic ground of the IGBT a treadmill deck.
driver 178, 180 or 182. 2. The current sensing circuit of claim 1 wherein the slow
The current sense module 34 also includes a member sense circuit monitors the average current value of the
described as the IM termination component. The IM termi current supplied to an AC motor over a predetermined time
nation component consists of a resistor, such as resistor 206 period such that when the average current value exceeds a
in parallel with a capacitor 224, such as C10, to provide preselected motor current rating for said AC motor, the
further cross conduction protection. When the high side 65 sensing circuit shuts down said AC drive motor system to
drive transistor is off, the IGBT driver 178, 180 or 182 shorts prevent damage to said AC motor by sending a fault signal
the line shown as the IM line to the signal represented as to the microprocessor.
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21 22
3.The current sensing circuit of claim2 wherein said slow 13. The AC drive motor system of claim 10 wherein said
sense circuit filters out transient current values which exceed slow sense circuit senses is triggered by current values in
said preselected motor current rating and which do not excess of 7.5 A.
trigger the fast sense circuit to prevent the inadvertent shut 14. The AC drive motor system of claim 10 wherein said
down of said AC drive motor system. fast sense circuit includes a differential amplifier.
4. The current sensing circuit of claim 1 wherein said slow 15. The AC drive motor system of claim 10 wherein said
sense circuit and said fast sense circuit monitor the current slow sense circuit responds in the range of seconds and the
of pulse width modulated signals supplied to said AC motor response of said fast sense circuit is less than one second.
by the driver module. 16. The current sensing circuit of claim 10 wherein said
5. The current sensing circuit of claim 4 wherein said 10
slow sense circuit and said fast sense circuit monitor the
pulse width modulated signals are formed by a pulse width current of said pulse width modulated signals between said
modulated signal generator. driver module of said AC drive motor system and said AC
6. The current sensing circuit of claim.5 wherein said slow motor to determine if said sensed currents as sensed by said
sense circuit and said fast sense circuits monitor three phases slow sense circuit and said fast sense circuit are above
of pulse width modulated signals to said AC motor. 15
7. The current sensing circuit of claim 1 wherein said slow certain different predetermined thresholds.
sense circuit and said fast sense circuit generate signals 17. The current sensing circuit of claim 10 further includ
which are received by a microprocessor module as a fault ing a filter of approximately 3 Hz thereinto remove the noise
signal to cause the shut down of said AC drive motor system caused by footfalls of a user.
until said AC drive motor system is reset if further faults are 18. A method of detecting the presence of potentially
received. damaging over current situations with an AC motor having
8. The current sensing circuit of claim 1 wherein said slow a variable speed drive motor controller system comprising
sense circuit and said fast sense circuit generate further the steps of:
signals which are received by a controller module as a fault providing a DC current to the system;
signal to notify the user of the shut down of said AC drive 25
pulse width modulating the DC current to produce a drive
motor system. signal which appears to an AC motor as an alternating
9. The current sensing circuit of claim 1 wherein said slow current signal of a predetermined frequency and volt
sense circuit and said fast sense circuit generate signals age;
which are in addition to a voltage dissipation circuit having
voltage dissipation circuitry to dissipate excess bus voltage sensing the current of the drive signal with a slow sense
in said AC drive motor system. circuit and a fast sense circuit wherein the slow sense
10, An AC drive motor system for a treadmill having a circuit monitors the average current value over a pre
current sensing circuit therein, the circuit including determined period of time and the fast sense circuit
a fast sense circuit for detecting the occurrence of a first monitors the non-averaged value of the current sup
current of a pulse width modulated signal in excess of 35 plied to the AC motor and the fast sense circuit sends
the predetermined value for an AC drive motor system a first fault signal to a first portion of the system to
to prevent damage to said AC drive motor system discontinue the remainder of the cycle of the sensed
wherein said fast sense circuit sends a fault signal to a signal and wherein a further fault signal is sent to
predriver module to shut down a switchfor the remain another portion of the system by the fast sense circuit
der of the cycle of said sensed first current of said pulse to shut down the AC motor when multiple fault signals
width modulated signal; and are generated by the fast sense circuit.
a slow sense circuit which monitors the average current 19. The method of claim 18 wherein a fault signal is
value between a driver module and the AC motor of generated by the slow sense circuit when the average current
said AC drive motor system to detect the occurrence of 45
value exceeds a predetermined value over a predetermined
a gradual fault condition where the average current period of time and the fault signal generated by the slow
exceeds a predetermined value over a predetermined sense circuit causes the system to shut down the AC motor.
period of time and wherein said average current value 20. The method of claim 19 wherein the fast sense circuit
is less than said predetermined value for said fast sense generates said fault signals in response to the sensing of a
circuit.
50
current in excess of a predetermined current value which is
11. The AC drive motor system of claim 10 wherein said greater than the average current value which generates a
slow sense current senses the increase in operating current fault signal from the slow sense circuit.
required by said AC motor as a result of increased frictional 21. The method of claim 20 wherein the fault signals
resistance to the rotation of the walk belt of the treadmill generated by the fast sense circuit and the slow sense circuits
over the treadmill deck.
55
are received by a predriver module and a microprocessor
12. The AC drive motor system of claim 10 wherein said module.
fast sense circuit senses is triggered by current values in
excess of 20 A.