UCIE: Fuelling the Chiplet Revolution in High-

Performance Computing
Introduction
The demand for high-performance computing (HPC) is ever-increasing, driven
by advancements in artificial intelligence, machine learning, and data
analytics. Traditional monolithic chips are struggling to keep pace with this
demand, facing limitations in size, yield, and cost. Chiplets, smaller
integrated circuits that can be combined to form larger, more complex
systems, offer a promising solution. Building larger high computing system
using chiplet beats the performance need without compromising on yield.
However, efficient communication between these chiplets is crucial for
realizing their full potential. This is where the Universal Chiplet Interconnect
Express (UCIe) standard steps in, revolutionizing the landscape of HPC.
UCIe: The Foundation of Chiplet-Based Systems
UCIe is an open industry standard that defines the interconnect between
chiplets within a package. It provides a standardized way for chiplets from
different vendors to communicate seamlessly, fostering interoperability and
innovation in the semiconductor industry. UCIe leverages existing protocols
like PCIe and CXL, building upon their proven performance and reliability.
The Rapid Evolution of UCIe
The UCIe consortium, comprising over 180 members including industry
giants like Intel, AMD, Arm, and TSMC, has been instrumental in driving the
rapid development of the standard. In just two years, UCIe has gone through
several iterations:
 UCIe 1.0 (UCIe_S): Released in June 2022, this initial specification
focused on planar package technologies (2D and 2.5D), laying the
groundwork for chiplet interconnectivity.
 UCIe 1.1 (UCIe_A): Launched in August 2023, UCIe 1.1 maintained
backward compatibility with UCIe 1.0 while introducing enhancements
and optimizations.
 UCIe 2.0 (UCIe_3D): Released in August 2024, UCIe 2.0 extended the
standard to 3D package technologies, unlocking a new era of
performance and efficiency.
This rapid progress demonstrates the industry's commitment to UCIe and its
potential to transform HPC.
Technical Deep Dive into UCIe Specifications
UCIe specifications encompass various aspects of chiplet interconnect,
ensuring seamless integration and operation:
 Layered Architecture: UCIe adopts a layered approach, comprising the
physical layer, adapter layer, and protocol layer. This modularity allows
for flexibility and innovation, with different vendors contributing to
each layer.
 Well-Defined Interfaces: The specifications define clear interfaces
between each layer, ensuring interoperability and consistent
functionality across different implementations.
 Comprehensive Coverage: UCIe addresses various aspects, including
form factor, management, compliance, interoperability, and more,
providing a robust framework for chiplet-based systems.
UCIe Package Requirements:
 UCIe 1.0/1.1 (UCIe_S and UCIe_A): These specifications utilize planar
package technologies, including:
o 2D Packaging: Employs a package substrate for connecting
chiplets, offering lower cost but higher power consumption
compared to 2.5D.
o 2.5D Packaging: Utilizes a package substrate and a silicon bridge
(e.g., Intel EMIB, TSMC CoWoS) for improved performance and
lower power.
 UCIe 2.0 (UCIe_3D): This specification leverages 3D package
technologies, such as hybrid bonding, enabling significantly higher
bump density and reduced interconnect distances.
Advantages of UCIe in HPC
UCIe offers numerous benefits that make it ideal for HPC systems:
 Breaking the reticle Limit: Chiplets enable larger and more complex
designs, overcoming the limitations of monolithic dies and enabling
higher performance.
 Improved Yield and Cost: Smaller chiplets have higher yields, reducing
manufacturing costs. Additionally, reusing IP from older process nodes
further optimizes cost-effectiveness.
 Enhanced Performance: On-package memory facilitated by UCIe
reduces data access latency, leading to significant performance gains.
  Faster Time-to-Market: Reusing existing IP and leveraging a
standardized interconnect accelerates development cycles, enabling
faster time-to-market.
UCIe 3D: Ushering in a New Era of Performance
UCIe 3D, with its support for 3D packaging, represents a major advancement
in chiplet interconnect technology. It offers unparalleled advantages:
 Unmatched Bandwidth and Latency: UCIe 3D can achieve data rates
comparable to on-chip frequencies, exceeding 32G and potentially
reaching 4G nominal bandwidth, resulting in extremely high bandwidth
and ultra-low latency.
 Exceptional Power Efficiency: Simplified analog circuits, reduced
parasitic effects, and the elimination of complex components like ESD
structures contribute to significantly lower power consumption,
achieving up to 25 times better power efficiency than UCIe_A and 50
times better than UCIe_S.
 Ultra-High Bump Density: 3D packaging enables bump pitch reduction
from 25 microns to as low as 1 micron, resulting in a 625X increase in
bump density and exponentially higher bandwidth for the same area
compared to planar UCIe.
 Simplified PHY Implementation: No complex transmitter, receiver, or
clocking circuits are required in UCIe_3D PHY, leading to simpler
inverter-based circuits and lower power operation.
DFX Challenges and Improvements in UCIe 2.0
While UCIe 1.0/1.1 focused on interconnect-level DFX coverage (margin,
interop, loopback, compliance, sideband, fault reporting), UCIe 2.0 addresses
the challenges at the chiplet and package levels.
 Cluster-Level Repair: UCIe 2.0 introduces cluster-level repair
mechanisms to address potential faults in multiple pins within a
cluster, improving testability and repairability in high-density 3D
packages.
 Holistic Test and Repair: UCIe 2.0 emphasizes a holistic approach to
test and repair, covering all levels from die sort to package bond and
beyond, aiming for a plug-and-play experience.
Industry Adoption and the Future of UCIe
UCIe has witnessed rapid adoption in the industry, with several companies
announcing products with UCIe IP and successful silicon demonstrations. The
collaboration between Intel and Synopsys, showcasing interoperability
between Intel's 3nm test chip and Synopsys' UCIe PHY on TSMC's 3E process,
highlights the technology's maturity and cross-vendor compatibility.
The future of UCIe is bright, with ongoing development and refinement of the
standard. As the chiplet ecosystem expands, UCIe is poised to become the
cornerstone of next-generation HPC systems, enabling greater performance,
scalability, and efficiency.
Conclusion
UCIe is a game-changing technology that is driving the chiplet revolution in
HPC. Its open and interoperable nature, rapid evolution, and comprehensive
specifications make it a critical enabler for the future of computing. By
breaking down the limitations of monolithic chips and fostering collaboration
across the industry, UCIe is paving the way for a new era of innovation and
progress in HPC.

Disclaimer: The information presented in this blog is intended for general

knowledge and informational purposes only, and does not constitute
professional advice. The content is based on publicly available information
and the author's understanding of the topic. While the author has made
every effort to ensure the accuracy and completeness of the information, no
guarantee is made as to its correctness or suitability for any specific
purpose. Readers are advised to consult with qualified professionals for
specific guidance.