Model Question Paper with effect from 2023-24 (CBCS

2022 Scheme)
Third Semester B.E. Degree Examination
Subject Title: COMPUTER ORGANISATION
& ARCHITECTURE
Time :03 Hours Max Marks:100
Note: Answer any FIVE full questions, choosing at least ONE question
from each MODULE.

Q1a. With a neat diagram, describe the functional units of a computer.

Solution:

A computer consists of five functionally independent main parts input, memory, arithmetic
logic unit (ALU), output and control unit.

Input unit: -
The source program/high level language program/coded information/simply data is fed to a computer
through input devices keyboard is a most common type. Whenever a key is pressed, one corresponding
word or number is translated into its equivalent binary code over a cable & fed either to memory or
processor.
Joysticks, trackballs, mouse, scanners etc are other input devices.
Memory:
1. Primary memory: - Is the one exclusively associated with the processor and operates at the
electronics speeds programs must be stored in this memory while they are being executed.Memory in
which any location can be reached in a short and fixed amount of time after specifying its address is
called random- access memory (RAM).
Memory which is only readable by the user and contents of which can’t be altered is called read only
memory (ROM) it contains operating system.
Arithmetic logic unit (ALU):-
Most of the computer operators are executed in ALU of the processor like addition, subtraction,
division, multiplication, etc. the operands are brought into the ALU from memory and stored in high
speed storage elements called register. Then according to the instructions the operation is performed in
the required sequence.
The control and the ALU are may times faster than other devices connected to a computer system. This
enables a single processor to control a number of external devices such as key boards, displays,
magnetic and optical disks, sensors and other mechanical controllers.

Output unit:-
These actually are the counterparts of input unit. Its basic function is to send the processed results to
the outside world.
Examples:- Printer, speakers, monitor etc.
Control unit:-
It effectively is the nerve center that sends signals to other units and senses their states. The actual
timing signals that govern the transfer of data between input unit, processor, memory and output unit
are generated by the control unit.

1c. With a neat diagram, discuss the operation concepts in a computer highlighting the role of
PC, MAR, MDR & IR.
Solution:

• The IR holds the instruction that is currently being executed.

• The control-unit generates the timing-signals that determine when a given action is to take place.
• The PC contains the memory-address of the next-instruction to be fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next instruction.
• The MAR holds the address of the memory-location to be accessed.
• The MDR contains the data to be written into or read out of the addressed location.
• MAR and MDR facilitates the communication with memory. (IR Instruction-Register, PC
Program Counter)

(MAR Memory Address Register, MDR Memory Data Register)

The instruction register (IR):- Holds the instructions that are currently being executed. Its output is
available for the control circuits which generates the timing signals that control the various processing
elements in one execution of instruction.
The program counter PC:-
This is another specialized register that keeps track of execution of a program. It contains the memory
address of the next instruction to be fetched and executed.
Besides IR and PC, there are n-general purpose registers R0 through Rn-1.
The other two registers which facilitate communication with memory are: -

2a. Explain the IEEE standard used for single & double precision floating point number
representation with examples.

Solution:

There are three binary floating-point basic formats (encoded with 32, 64 or 128 bits) and two
decimal floating-point basic formats (encoded with 64 or 128 bits). The binary32 and binary64 formats
are the single and double formats of IEEE 754-1985 respectively.

According to IEEE standard, floating-point number is represented in two ways:

Precision Base Sign Exponent Significand

Single precision 2 1 8 23+1

Double precision 2 1 11 52+1

Single Precision: Single Precision is a format proposed by IEEE for the representation of floating-
point numbers. It occupies 32 bits in computer memory.

Double Precision: Double Precision is also a format given by IEEE for the representation of the
floating-point number. It occupies 64 bits in computer memory.
 SKIP

Difference between Single and Double Precision:

SINGLE PRECISION DOUBLE PRECISION

In single precision, 32 bits are used to represent In double precision, 64 bits are used to represent
floating-point number. floating-point number.

This format, also known as FP32, is suitable for This format, often known as FP64, is suitable to
calculations that won’t be adversely affected by represent values that need a wider range or more exact
some approximation. computations.

It uses 8 bits for exponent. It uses 11 bits for exponent.

In single precision, 23 bits are used for mantissa. In double precision, 52 bits are used for mantissa.

Bias number is 127. Bias number is 1023.

Range of numbers in single precision : 2^(- Range of numbers in double precision : 2^(-
126) to 2^(+127) 1022) to 2^(+1023)

This is used where precision matters less. This is used where precision matters more.

It is used for wide representation. It is used for minimization of approximation.

It is used in complex programs like scientific

It is used in simple programs like games.
calculator.

This is called binary32. This is called binary64.

It provides more accurate results but at the cost of

It requires fewer resources as compared to double
greater computational power, memory space, and data
precision.
transfer.
 SINGLE PRECISION DOUBLE PRECISION

The cost incurred using this format does not always

It is less expensive.
justify its use for every computation .

2c. Discuss the following with an example

i) Three-address instruction
ii) Two-address instruction
iii) One-address instruction

3a. Describe the following addressing modes with an example i) Register ii) Direct iii) Indirect iv)
Index

Solution:

Register Mode
• The operand is the contents of a register.
• The name (or address) of the register is given in the instruction.
 • Registers are used as temporary storage locations where the data in a register are accessed.
• For example, the instruction
Move R1, R2 ;Copy content of register R1 into register R2.

Direct addressing Mode

Direct addressing is a scheme in which the address specifies which memory word or register contains
the operand.
For example:
1) LOAD R1, 100 Load the content of memory address 100 to register R1.
2) LOAD R1, R2 Load the content of register R2 to register R1.

Indirect Mode
• The EA of the operand is the contents of a register(or memory-location).
• The register (or memory-location) that contains the address of an operand is called a Pointer.
• We denote the indirection by
→ name of the register or
→ new address given in the instruction.
E. g: Add (R1),R0 ;The operand is in memory. Register R1 gives the effective-
address (B) of the operand. The data is read from location B and
added to contents of register R0.

• To execute the Add instruction in fig 2.11 (a), the processor uses the value which is in register
R1, as the EA of the operand.
• It requests a read operation from the memory to read the contents of location B. The value
read is the desired operand, which the processor adds to the contents of register R0.
• Indirect addressing through a memory-location is also possible as shown in fig 2.11(b). In
this case, the processor first reads the contents of memory-location A, then requests a second
read operation using the value B as an address to obtain the operand.

Index mode
• The operation is indicated as X(Ri)
where X=the constant value which defines an offset(also called a displacement).
Ri=the name of the index register which contains address of a new location.
• The effective-address of the operand is given by EA=X+[Ri]
 • The contents of the index-register are not changed in the process of generating the
effective- address.
• The constant X may be given either
→ as an explicit number or
→ as a symbolic-name representing a numerical value.

• Fig(a) illustrates two ways of using the Index mode. In fig(a), the index register, R1, contains
the address of a memory-location, and the value X defines an offset(also called a displacement)
from this address to the location where the operand is found.

3b. Define Stack, Explain push & pop operations on stack with neat diagram and examples

Solution:
STACKS
• A stack is a special type of data structure where elements are inserted from one end and
elements are deleted from the same end. This end is called the top of the stack (Figure:
2.14).
• The various operations performed on stack:
1) Insert: An element is inserted from top end. Insertion operation is called push operation.
2) Delete: An element is deleted from top end. Deletion operation is called pop operation.
• A processor-register is used to keep track of the address of the element of the stack that is at
the top at any given time. This register is called the Stack Pointer (SP).

• If we assume a byte-addressable memory with a 32-bit word length,

1) The push operation can be implemented as
Subtract #4,
SP Move NEWITEM, (SP)
2) The pop operation can be implemented as
Move (SP),
ITEM Add #4, SP
4b. Define subroutine. With a program segment illustrate parameter passing using registers

Solution:

SUBROUTINES
• A subtask consisting of a set of instructions which is executed many times is called a Subroutine.
• A Call instruction causes a branch to the subroutine (Figure: 2.16).
• At the end of the subroutine, a return instruction is executed
• Program resumes execution at the instruction immediately following the subroutine call
• The way in which a computer makes it possible to call and return from subroutines is
referred to as its Subroutine Linkage method.
• The simplest subroutine linkage method is to save the return-address in a specific
location, which may be a register dedicated to this function. Such a register is called the
Link Register.
PARAMETER PASSING
• The exchange of information between a calling-program and a subroutine is referred to as
Parameter Passing (Figure: 2.25).
• The parameters may be placed in registers or in memory-location, where they can be
accessed by the subroutine.
• Alternatively, parameters may be placed on the processor-stack used for saving the return-address.
• Following is a program for adding a list of numbers using subroutine with the
parameters passed through registers.
4c. Explain memory operations with examples

Solution:

MEMORY OPERATIONS
• Two memory operations are:
1) Load (Read/Fetch) &
2) Store (Write).
• The Load operation transfers a copy of the contents of a specific memory-location to the processor.
The memory contents remain unchanged.
• Steps for Load operation:
1) Processor sends the address of the desired location to the memory.
2) Processor issues „read‟ signal to memory to fetch the data.
3) Memory reads the data stored at that address.
4) Memory sends the read data to the processor.
• The Store operation transfers the information from the register to the specified memory-location.
This will destroy the original contents of that memory-location.
• Steps for Store operation are:
1) Processor sends the address of the memory-location where it wants to store data.
2) Processor issues „write‟ signal to memory to store the data.
3) Content of register(MDR) is written into the specified memory-location.
5a. Define interrupt. Point out & explain the various ways of enabling & disabling interrupts
Solution:

 An interrupt is an event which suspends the execution of one program and begins the
execution of another program.

 In program controlled I/O, a program should continuously check whether the I/O device is
free. By this continuous checking the processor execution time is wasted. It can be
avoided by I/O device sending an ‘interrupt’ to the processor, when I/O device is free.

 The interrupt invokes a subroutine called Interrupt Service Routine (ISR), which
resolves the cause of interrupt.

 The occurrence of interrupt causes the processor to transfer the execution control from
user program to ISR.

ENABLING AND DISABLING THE INTERRUPTS

The arrival of interrupt request from external devices or from within a process, causes the
suspension of on-going execution and start the execution of another program.

 Interrupt arrives at any time and it alters the sequence of execution. Hence the
interrupt to be executed must be selected carefully.
 All computers can enable and disable interruptions as desired.
 When an interrupt is under execution, other interrupts should not be invoked. This is
performed in a system in different ways.
 The problem of infinite loop occurs due to successive interruptions of active INTR signals.
 There are 3 mechanisms to solve problem of infinite loop:
1) Processor should ignore the interrupts until execution of first instruction of the ISR.

2) Processor should automatically disable interrupts before starting the execution of the
ISR.
3) Processor has a special INTR line for which the interrupt-handling circuit.

Interrupt-circuit responds only to leading edge of signal. Such line is called

edge- triggered.
• Sequence of events involved in handling an interrupt-request:

1) The device raises an interrupt-request.

2) The processor interrupts the program currently being executed.

3) Interrupts are disabled by changing the control bits in the processor status register
(PS).
 4) The device is informed that its request has been recognized.

In response, the device deactivates the interrupt-request signal.

5) The action requested by the interrupt is performed by the interrupt-service routine.
Interrupts are enabled and execution of the interrupted program is resume.

5b. Explain operation of DMA with neat diagram.

 Direct Memory Access is the process of transferring the block of data at high speed in
between main memory and external device (I/O devices) without continuous intervention of
CPU.
 This operation is performed by the control circuit, called as DMA controller.
 DMA controller is a part of the I/O interface.
 The data transfer operation in DMA is processed by the help of DMA controller.
 To initiate Directed data transfer between main memory and external devices DMA controller
needs parameters from the CPU.
 These 3 Parameters are:

1) Starting address of the memory block.

2) No of words to be transferred.
3) Type of operation (Read or Write).
After receiving these 3 parameters from CPU, DMA controller establishes directed data transfer
operation between main memory and external devices without the involvement of CPU. Hence
the processor is free to execute other programs.

 In the sample architecture shown above, the DMA controller connects two external devices
namely disk 1 and disk 2 to system bus.
 The DMA controller also interconnects high speed network devices to system bus as shown in the
above fig.
  Let us consider direct data transfer operation by means of DMA controller without the
involvement of CPU in between main memory and disk 1.
To establish direct data transfer operation between main memory and disk 1.

 After receiving these 3 parameters from processor, DMA controller directly transfers block of data
between main memory and external devices (disk 1) depending on the operation.
 This information is informed to CPU by setting respective bits in the status and controller
register of DMA controller.
These are 2 types of request with respect to system bus
1). CPU request.
2). DMA request.
Highest priority will be given to DMA request.

5c. Write a explanatory note on interrupt hardware

Solution: INTERRUPT HARDWARE

 The external device (I/O device) sends interrupt request to the processor by activating a
bus line and called as interrupt request line.
 All I/O device uses the same single interrupt-request line.
 One end of this interrupt request line is connected to input power supply by means of a
register.
 The another end of interrupt request line is connected to INTR (Interrupt request)
signal of processor as shown in the fig.

 The I/O device is connected to interrupt request line by means of switch, which is
grounded as shown in the fig.
 When all the switches are open the voltage drop on interrupt request line is equal to the
VDD and INTR value at process is 0.
  This state is called as in-active state of the interrupt request line.

The I/O device interrupts the processor by closing its switch.

 When switch is closed the voltage drop on the interrupt request line is found to be zero, as the
switch is grounded, hence INTR=0 and INTR=1.
The signal on the interrupt request line is logical OR of requests from the several I/O devices.
Therefore, INTR=INTR1 + INTR2 + ........................... + INTRn
6a. Illustrate interrupt priority scheme with neat diagram
Solution:
A priority interrupt is a system which decides the priority at which various devices,
which generates the interrupt signal at the same time, will be serviced by the CPU. The
system has authority to decide which conditions are allowed to interrupt the CPU, while
some other interrupt is being serviced.
• A multiple-priority scheme is implemented by using separate INTR & INTA lines for
each device
• Each INTR line is assigned a different priority-level as shown in Figure.

• Priority-level of processor is the priority of program that is currently being executed.

• Processor accepts interrupts only from devices that have higher-priority than its own.
• At the time of execution of ISR for some device, priority of processor is raised to that
of the device.
• Thus, interrupts from devices at the same level of priority or lower are disabled.
Privileged Instruction
• Processor's priority is encoded in a few bits of PS word. (PS = Processor-Status).
• Encoded-bits can be changed by Privileged Instructions that write into PS.
• Privileged-instructions can be executed only while processor is running in Supervisor
Mode.
• Processor is in supervisor-mode only when executing operating-system routines.
6b. Distinguish between memory mapped I/O and standard I/O write a program
segment to read a line of text from keyboard & display it.

Solution:

1. Memory mapped I/O:

 In this technique, both memory and I/O devices can share the common memory to
store the data, the I/O instructions are mapped to any memory location.
All memory related instructions are used for data transfer between I/O and processor.
2. I/O Mapped I/O:
 In this technique, a separate address space is allocated for I/O devices.
Address space for program and I/O devices are different.
 Hence two sets of instruction are used for data transfer.
 One set for memory operations and another set for I/O operations.
 Whole address space is available for the program.
 Eg – IN AL, DX

 For example the DATA IN is the address of input buffer associated with
the keyboard instruction.

operation can be implemented as,

MOVE DATAIN ,R0

This instruction reads the data from location DATAIN to register R0.
  Similarly output can be implemented as,

MOVE R0, DATAOUT

The data is written from R0 to DATAOUT location (address of output buffer)

6c. Explain the concept of Vectored Interrupt

Solution:

VECTORED INTERRUPT
• A device requesting an interrupt identifies itself by sending a special-code to
processor over bus.
• Then, the processor starts executing the ISR.

• The special-code indicates starting-address of ISR.

• The special-code length ranges from 4 to 8 bits.

• The location pointed to by the interrupting-device is used to store the staring address
to ISR.
• The staring address to ISR is called the interrupt vector.

• Processor

→ loads interrupt-vector into PC &

→ executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA line.

• Then, I/O-device responds by sending its interrupt-vector code & turning off the
INTR signal.
• The interrupt vector also includes a new value for the Processor Status Register

7a. With a neat diagram, explain the principal of working of magnetic disk
Soultion:
MAGNETIC DISK
• Magnetic Disk system consists of one or more disk mounted on a common spindle.
• A thin magnetic film is deposited on each disk (Figure 8.27).
• Disk is placed in a rotary-drive so that magnetized surfaces move in close proximity to
R/W heads.
• Each R/W head consists of 1) Magnetic Yoke & 2) Magnetizing-Coil.
• Digital information is stored on magnetic film by applying current pulse to the magnetizing-
coil.
• Only changes in the magnetic field under the head can be sensed during the Read-operation.
• Therefore, if the binary states 0 & 1 are represented by two opposite states,
then a voltage is induced in the head only at 0-1 and at 1-0 transition in the bit stream.
• A consecutive of 0‟s & 1‟s are determined by using the clock.
• Manchester Encoding technique is used to combine the clocking information with data.

• R/W heads are maintained at small distance from disk-surfaces in order to achieve high bit
densities.
• When disk is moving at their steady state, the air pressure develops b/w disk-surfaces &
head.
This air pressure forces the head away from the surface.
• The flexible spring connection between head and its arm mounting permits the head to fly at
the
desired distance away from the surface.
Winchester Technology
• Read/Write heads are placed in a sealed, air–filtered enclosure called the Winchester
Technology.
• The read/write heads can operate closure to magnetic track surfaces because
the dust particles which are a problem in unsealed assemblies are absent.
Advantages
• It has a larger capacity for a given physical size.
• The data intensity is high because
the storage medium is not exposed to contaminating elements.
• The read/write heads of a disk system are movable.
• The disk system has 3 parts:
1) Disk Platter (Usually called Disk)
2) Disk-drive (spins the disk & moves Read/write heads)
3) Disk Controller (controls the operation of the system. )
7b. Explain the internal organization of 2M x 8 DRAM chip with neat diagram

Solution:

The 4 bit cells in each row are divided into 512 groups of 8 (Figure 5.7).
• 21 bit address is needed to access a byte in the memory. 21 bit is divided as follows:
1) 12 address bits are needed to select a row.
i.e. A8-0 → specifies row-address of a byte.
2) 9 bits are needed to specify a group of 8 bits in the selected row.

i. e. A20-9 → specifies column-address of a byte.

During Read/Write-operation,
→ row-address is applied first.
→ row-address is loaded into row-latch in response to a signal pulse on RAS’ input of chip.
(RAS = Row-address Strobe CAS = Column-address Strobe)
• When a Read-operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row-address is loaded, the column-address is
→ applied to the address pins &
→ loaded into CAS’.
• The information in the latch is decoded.
• The appropriate group of 8 Sense/Write circuits is selected.
R/W’=1(read-operation) Output values of selected circuits are transferred to data-lines D0-
D7.
R/W’=0(write-operation) Information on D0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they change from
high
to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed
periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that govern
the timing.
• The processor must take into account the delay in the response of the memory.

Fast Page Mode

Transferring the bytes in sequential order is achieved by applying the consecutive sequence
of column-address under the control of successive CAS‟ signals.
This scheme allows transferring a block of data at a faster rate.
The block of transfer capability is called as fast page mode.

8a. Illustrate Internal structure of static memory

Solution:
STATIC RAM (OR MEMORY)
• Memories consist of circuits capable of retaining their state as long as power is applied are
known.

• Two inverters are cross connected to form a latch (Figure 8.4).

• The latch is connected to 2-bit-lines by transistors T1 and T2.
• The transistors act as switches that can be opened/closed under the control of the word-line.
• When the word-line is at ground level, the transistors are turned off and the latch retain its
state.
Read Operation
• To read the state of the cell, the word-line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line b‟ is low.
• Thus, b and b‟ are complement of each other.
• Sense/Write circuit
→ monitors the state of b & b‟ and
→ sets the output accordingly.
Write Operation
• The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b‟ and
→ then activating the word-line. This forces the cell into the corresponding state.
• The required signal on the bit-lines is generated by Sense/Write circuit.
CMOS Cell
• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 8.5).
• In state 1, the voltage at point X is high by having T5, T6 ON and T4, T5 are OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low signals
respectively.

Advantages:
1) It has low power consumption „.‟ the current flows in the cell only when the cell is active.
2) Static RAM‟s can be accessed quickly. It access time is few nanoseconds.
Disadvantage: SRAMs are said to be volatile memories „.‟ their contents are lost when
power
is interrupted.

8b. With a neat diagram, explain virtual memory organization.

Solution:VIRTUAL MEMORY
• It refers to a technique that automatically move program/data blocks into the main-memory
when
they are required for execution (Figure 8.24).
• The address generated by the processor is referred to as a virtual/logical address.
• The virtual-address is translated into physical-address by MMU (Memory Management
Unit).
• During every memory-cycle, MMU determines whether the addressed-word is in the
memory.
If the word is in memory.
Then, the word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Using DMA scheme, transfer of data between disk and memory is performed.
VIRTUAL MEMORY ADDRESS TRANSLATION
• All programs and data are composed of fixed length units called Pages (Figure 8.25).
The Page consists of a block-of-words. The words occupy contiguous locations in the
memory.
The pages are commonly range from 2K to 16K bytes in length.
• Cache Bridge speed-up the gap between main-memory and secondary-storage.
• Each virtual-address contains
1) Virtual Page number (Low order bit) and
2) Offset (High order bit).
Virtual Page number + Offset specifies the location of a particular word within a page.
• Page-table: It contains the information about
→ memory-address where the page is stored &
→ current status of the page.
• Page-frame: An area in the main-memory that holds one page.
• Page-table Base Register: It contains the starting address of the page-table.
• Virtual Page Number + Page-table Base register Gives the starting address of the page if
that page
currently resides in memory.
• Control-bits in Page-table: The Control-bits is used to
1) Specify the status of the page while it is in memory.
2) Indicate the validity of the page.
3) Indicate whether the page has been modified during its stay in the memory
9a. Explain Single bus organization of the datapath inside a processor with neat diagram

Solution: SINGLE BUS ORGANIZATION

• ALU and all the registers are interconnected via a Single Common Bus (Figure 7.1).
• Data & address lines of the external memory-bus is connected to the internal processor-bus
via MDR
& MAR respectively. (MDR Memory Data Register, MAR Memory Address Register).
• MDR has 2 inputs and 2 outputs. Data may be loaded
→ into MDR either from memory-bus (external) or
→ from processor-bus (internal).
• MAR‟s input is connected to internal-bus;
MAR‟s output is connected to external
bus.
• Instruction Decoder & Control Unit is responsible for
→ issuing the control-signals to all the units inside the processor.
→ implementing the actions specified by the instruction (loaded in the IR).
• Register R0 through R(n-1) are the Processor Registers.
The programmer can access these registers for general-purpose use.
• Only processor can access 3 registers Y, Z & Temp for temporary storage during program-
execution.
The programmer cannot access these 3 registers.
• In ALU,
1) „A‟ input gets the operand from the output of the multiplexer (MUX).
2) „B‟ input gets the operand directly from the processor-bus.
• There are 2 options provided for „A‟ input of the ALU.
• MUX is used to select one of the 2 inputs.
• MUX selects either
→ output of Y or
→ constant-value 4( which is used to increment PC content).

• An instruction is executed by performing one or more of the following operations:

1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.
• Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.
Solution: Provide multiple internal-paths. Multiple paths allow several data-transfers to take
place in
parallel.

9b.Develop the complete control sequence for the execution of instruction Add (R3), R1

Solution:

EXECUTION OF A COMPLETE INSTRUCTION

• Consider the instruction Add (R3),R1 which adds the contents of a memory-location pointed
by R3 to
register R1. Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand.
3) Perform the addition &
4) Load the result into R1.

• Instruction execution proceeds as follows:

Step1--> The instruction-fetch operation is initiated by
→ loading contents of PC into MAR &
→ sending a Read request to memory.
The Select signal is set to Select4, which causes the Mux to select constant 4. This value
is added to operand at input B (PC‟s content), and the result is stored in Z.
Step2--> Updated value in Z is moved to PC. This completes the PC increment operation and
PC will now point to next instruction.
Step3--> Fetched instruction is moved into MDR and then to IR.
The step 1 through 3 constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR. This
enables the control circuitry to activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
Step4--> Contents of R3 are loaded into MAR & a memory read signal is issued.
Step5--> Contents of R1 are transferred to Y to prepare for addition.
Step6--> When Read operation is completed, memory-operand is available in MDR, and the
addition is performed.
Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a new instruction
fetch cycle to begin by returning to step1.

10a. Describe Three-bus organization of the datapath with a neat diagram.

Solution: THREE BUS ORGANIZATION

• Disadvantage of Single-bus organization: Only one data-word can be transferred over the
bus in
a clock cycle. This increases the steps required to complete the execution of the instruction
Solution: To reduce the number of steps, most processors provide multiple internal-paths.
Multiple
paths enable several transfers to take place in parallel.
• As shown in fig 7.8, three buses can be used to connect registers and the ALU of the
processor.
• All general-purpose registers are grouped into a single block called the Register File.
• Register-file has 3 ports:
1) Two output-ports allow the contents of 2 different registers to be simultaneously placed on
buses A & B.
2) Third input-port allows data on bus C to be loaded into a third register during the same
clock-cycle.
• Buses A and B are used to transfer source-operands to A & B inputs of ALU.
• The result is transferred to destination over bus C.
• Incrementer Unit is used to increment PC by 4.

Instruction execution proceeds as follows:

Step 1--> Contents of PC are
→ passed through ALU using R=B control-signal &
→ loaded into MAR to start memory Read operation. At the same time, PC is incremented by
4.
Step2--> Processor waits for MFC signal from memory.
Step3--> Processor loads requested-data into MDR, and then transfers them to IR.
Step4--> The instruction is decoded and add operation takes place in a single step.

10b. Discuss Hardwired control unit organization with relevant diagram

HARDWIRED CONTROL
• Hardwired control is a method of control unit design (Figure 7.11).
• The control-signals are generated by using logic circuits such as gates, flip-flops, decoders
etc.
• Decoder/Encoder Block is a combinational-circuit that generates required control-outputs
depending on state of all its inputs.
• Instruction Decoder
It decodes the instruction loaded in the IR.
If IR is an 8 bit register, then instruction decoder generates 28 (256 lines); one for each
instruction.
It consists of a separate output-lines INS1 through INSm for each machine instruction.
According to code in the IR, one of the output-lines INS1 through INSm is set to 1, and all
other lines are set to 0.
• Step-Decoder provides a separate signal line for each step in the control sequence.
• Encoder
It gets the input from instruction decoder, step decoder, external inputs and condition codes.
It uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so
on.
For example (Figure 7.12), Zin=T1+T6.ADD+T4.BR
;This signal is asserted during time-slot T1 for all instructions.
during T6 for an Add instruction.
during T4 for unconditional branch instruction
• When RUN=1, counter is incremented by 1 at the end of every clock cycle.
When RUN=0, counter stops counting.
• After execution of each instruction, end signal is generated. End signal resets step counter.
• Sequence of operations carried out by this machine is determined by wiring of logic circuits,
hence
the name “hardwired”.
• Advantage: Can operate at high speed.
• Disadvantages:
1) Since no. of instructions/control-lines is often in hundreds, the complexity of control unit is
very high.
2) It is costly and difficult to design.
3) The control unit is inflexible because it is difficult to change the design
1b. Explain little Endian and big Endian byte address assignment with a neat diagram.
Show how the number 34761395 is stored using these methods.

Solution:
BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS
• There are two ways in which byte-addresses are arranged (Figure 2.3).
1) Big-Endian: Lower byte-addresses are used for the more significant bytes of
the word.
2) Little-Endian: Lower byte-addresses are used for the less significant bytes of
the word
• In both cases, byte-addresses 0, 4, 8................ are taken as the addresses of successive
words in the
memory.
3c. Consider a register R1 to size 16-bits with initial data 5876d. With neat diagram,
depict the output in each case after performing the following operations
i) LshiftL #2,R1 ii)AshiftR #1,R1 iii) RotateR #1,R1
4a. Consider a database of marks scored by students in 3 tests stored in memory starting
at address LIST. Each student record consists of student ID followed by marks in 3 tests.
Assume each of there to be 4 bytes in size. There are 50 students in the class & this value
is stored at location NUM
i) Sketch the memory map showing all details
ii) Develop an ALP using indexed addressing mode to compute
the sum of scores by all the students in Test 2 and store the
results in location SUM. Write appropriate comments
2b. Perform the subtraction on the following pairs of numbers using 5-bit signed 2’s
complement format. Determine about overflow in each case
i) +12 and +9 ii) -15 and -9 iii) +10 and -8