Basic Concepts of DFThttps://youtu.
be/1OoJG8CeFns
Scan Design Flowhttps://youtu.be/7fGJto2F8JU
Power Analysis using OpenSTAhttps://youtu.be/ZHk9e0KpHUY
Automatic Test Pattern Generation (ATPG)https://youtu.be/oOVaTWGkVy8
Built-in Self Test (BIST)https://youtu.be/iT_lXRDUdZI
1] Which of the following is NOT the purpose of employing a fault model in design for test (DFT) tasks?
It allows us to analyze the impact of a defect using logic or circuit analysis techniques.
It helps us reduce the number of defects during integrated circuit fabrication.
It allows us to derive test patterns algorithmically for detecting a given fault.
It helps us transform the problem of defect detection into the problem of fault detection.
2] From the perspective of design for test (DFT), which of the following statements best describes a test vector:
Any input pattern, or sequence of input patterns, that produces a 1 for a faulty circuit and a fault-free circuit
Any input pattern, or sequence of input patterns, that produces a 0 for a faulty circuit and a fault-free circuit
Any input pattern, or sequence of input patterns, that produces a matching output response for a faulty circuit and a fault-free circuit
Any input pattern, or sequence of input patterns, that produces a different output response for a faulty circuit and a fault-free
ircuit
c
3] In scan-based testing methodology, we replace a D flip-flop with a scan cell. What is the motivation for this:
It decreases the delay and area of the circuit.
It increases the manufacturability of the circuit.
It increases the controllability and observability of a circuit.
It increases the performance and reliability of a circuit.
4] In scan-based testing methodology, what is the correct value at the SE (scan enable) port for the shift and capture mode, respectively?
Shift SE=0, Capture SE=0
Shift SE=0, Capture SE=1
Shift SE=1, Capture SE=0
Shift SE=1, Capture SE=1
5] The non-controlling value of a two-input XOR gate is:
0
1
Both 0 and 1
Neither 0 nor 1
6] For the circuit shown below, the test pattern to detect SA1 at G3/X1 is:
A=1 B=1 C=0 D=1
A=0 B=0 C=0 D=1
A=1 B=1 C=0 D=0
A=0 B=1 C=0 D=1
7] Which of the following components is typicallyNOTa part of Built-inSelf-test (BIST) infrastructure?
Random Test Pattern Generator
Test Response Analyzer
JPEG Encoder
BIST controller
8] The patterns obtained using Linear Feedback Shift Register (LFSR) are:
Finite, repeatable, and pseudo-random
Infinite, repeatable, and truly random
Finite, non-repeatable, and truly random
Infinite, non-repeatable, and pseudo-random
9] What is aliasing in signature analysis from the perspective of Built-in Self-test (BIST)
Matching of signature of “good” circuit and “faulty” circuit
Matching of signature of the designer and the signature of the engineer who is fabricating
Overlapping of frequency components in automatic test equipment
Distortion in the outline of the image of the chip taken during testing
