Transmission Gate Logic Design
Gaurav Sharma (T23212), Chandan Singh (T23219)
School of Computing and Electrical Engineering,
IIT Mandi, Himachal Pradesh, India.
{t23212, t23219}@students.iitmandi.ac.in
AIM: Explore the design and characteristics of Transmis- A. TGL Nand Gate
sion Gate (TG) logic gates (2:1 Mux, NAND, AND, NOR,
XOR) and compare them with other logic implementations.
Abstract—This report presents the design, simulation, and
characteristics analysis of Transmission Gate (TG) logic gates
using TSMC 28nm node technology in Cadence Virtuoso. Special A
emphasis is placed on the unique advantages of TG logic,
including rail-to-rail switching and fast transitions. Simulation Bbar
results are examined to verify these characteristics and compare
TG logic gates with other logic families.
Abar OUT
I. I NTRODUCTION
A. Why Transmission Gate Logic?
Transmission Gate (TG) logic presents a compelling alter-
native to traditional logic families, offering unique advantages
that address specific challenges. One notable feature is the A
ability to achieve rail-to-rail switching, ensuring that the output
voltage can reach both power supply rails (VDD and VSS ). Fig. 1. TGL Nand circuit
This characteristic is particularly advantageous in scenarios
where the full swing of logic levels is crucial for reliable
circuit operation.
B. Rail-to-Rail Switching advantage:
In TG logic, the concurrent operation of both PMOS and
NMOS transistors during the charging or discharging process
enables rail-to-rail switching. Unlike some other logic families,
TG logic ensures that the output voltage can reach the power
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supply rails (VDD and VSS ), providing a full and reliable logic
NAND Y
swing. 0.54
0.36
C. Application in 2:1 Mux and Logic Gates:
0.18
These advantages make TG logic well-suited for various
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digital circuit applications. In the design of a 2:1 Mux and
logic gates (NAND, AND, NOR, XOR), the rail-to-rail switch- 0.66
B
ing and fast transition features play a key role in achieving 0.33
efficient and high-performance circuitry.
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D. Simulation Verification: 0.99
To practically verify these characteristics, Cadence Virtuoso 0.66
simulation with TSMC 28nm node technology is employed.
A
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By analyzing the simulation results, which include power
consumption, delay, and area utilization, we can gain valuable 0.00
insights into the superior performance of TG logic in achieving 0.0 200.0p 400.0p 600.0p 800.0p
Time(sec)
rail-to-rail switching and rapid transitions.
II. S IMULATION
Fig. 2. TGL NAND Simulation
The simulation of the designed gates with their circuits are
shown below:
B. TGL AND Gate C. Nor Gate
A
0
A Abar
B
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Bbar
A
Fig. 5. TGL Nor circuit
Fig. 3. TGL And circuit
0.8
0.6
NOR Y
0.4
0.2
0.99
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A
B
B 0.33
0.00
0.99
Abar OUT
0.66
A
0.33
0.00
0.0 200.0p 400.0p 600.0p 800.0p
A Time (sec)
Fig. 4. TGL NAND Simulation Fig. 6. TGL NOR Simulation
D. Xor Gate E. 2:1 Mux using TG
A
Bbar
Abar OUT
Fig. 7. TGL Xor circuit
Fig. 9. TG Multiplexer
0.76
0.76
0.57
Y
0.57
XOR Y
0.38
0.38
0.19
0.19 0.99
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S0
0.99
0.33
0.66
0.00
B
0.99
0.33
0.66
B
0.00
0.33
0.99
0.00
0.99
0.66
A
0.66
A
0.33
0.33
0.00
0.00
0.0 200.0p 400.0p 600.0p 800.0p 0.0 200.0p 400.0p 600.0p 800.0p
Time (Sec) TIme(sec)
Fig. 8. TGL XOR Simulation Fig. 10. TGL MUX Simulation
III. R ESULTS AND C ONCLUSION IV. R EFERENCES
[1] Weste, Neil HE, and David Harris. CMOS VLSI design:
A. Results
a circuits and systems perspective. Pearson Education India,
The key parameters for TGL-nand gate are as follows: 2015.
[2] Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje
Nikoli´ c. Digital integrated circuits: a design perspective. Vol.
Results Schematic Value
7. Upper Saddle River, NJ: Pearson education, 2003.
TPHL 1.51p s
TPLH 1.92p s
Avg. Power 2.98mW
The key parameters for TGL-and gate are as follows:
Results Schematic Value
TPHL 5.509p s
TPLH 1.78p s
Avg. Power 2.09mW
The key parameters for TGL-nor gate are as follows:
Results Schematic Value
TPHL 1.49p s
TPLH 1.88p s
Avg. Power 2.99mW
The key parameters for TGL-Xor gate are as follows:
Results Schematic Value
TPHL 4.73p s
TPLH 1.88p s
Avg. Power 2.47mW
B. Key Findings
The simulation results confirm the unique advantages of
Transmission Gate (TG) logic, showcasing its ability to
achieve rail-to-rail switching and fast transitions. These fea-
tures position TG logic as a promising choice in applications
where full swing and high-speed operation are crucial.
C. Comparison with Other Logics
In comparison to other logic families, TG logic stands out
in terms of its rail-to-rail capabilities. The reduced propagation
delay contributes to its suitability for high-speed applications,
making it a compelling alternative to traditional logic imple-
mentations.
D. Considerations for Adoption
While TG logic presents clear advantages, designers should
carefully assess its suitability based on specific application
requirements. Factors such as power consumption, area utiliza-
tion, and sensitivity to process variations should be considered
for optimal circuit performance.
