IRFB11N50A

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Vishay Siliconix
Power MOSFET
D
FEATURES
• Low gate charge Qg results in simple drive
TO-220AB
requirement Available

• Improved gate, avalanche, and dynamic dV/dt

Available
ruggedness
G
• Fully characterized capacitance and avalanche voltage
and current
S • Material categorization: for definitions of compliance
D please see www.vishay.com/doc?99912
G S
Note
N-Channel MOSFET
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
PRODUCT SUMMARY Please see the information / tables in this datasheet for details
VDS (V) 500
APPLICATIONS
RDS(on) (Ω) VGS = 10 V 0.52
• Switch mode power supply (SMPS)
Qg max. (nC) 52
• Uninterruptible power supply
Qgs (nC) 13
• High speed power switching
Qgd (nC) 18
Configuration Single APPLICABLE OFF LINE SMPS TOPOLOGIES
• Two transistor forward
• Half and full bridge
• Power factor correction boost

ORDERING INFORMATION
Package TO-220
Lead (Pb)-free IRFB11N50APbF
Lead (Pb)-free and halogen-free IRFB11N50APbF-BE3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 500
V
Gate-source voltage VGS ± 30
TC = 25 °C 11
Continuous drain current VGS at 10 V ID
TC = 100 °C 7.0 A
Pulsed drain current a IDM 44
Linear derating factor 1.3 W/°C
Single pulse avalanche energy b EAS 275 mJ
Repetitive avalanche current a IAR 11 A
Repetitive avalanche energy a EAR 17 mJ
Maximum power dissipation TC = 25 °C PD 170 W
Peak diode recovery dV/dt c dV/dt 6.9 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +150
°C
Soldering recommendations (peak temperature) d For 10 s 300
10 lbf · in
Mounting torque 6-32 or M3 screw
1.1 N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = 11 A (see fig. 12)
c. ISD ≤ 11 A, dI/dt ≤ 140 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case

S21-0867-Rev. C, 16-Aug-2021 1 Document Number: 91094

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THERMAL RESISTANCE
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient RthJA - 62
Case-to-sink, flat, greased surface RthCS 0.50 - °C/W
Maximum junction-to-case (drain) RthJC - 0.75

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 500 - - V
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 30 V - - ± 100 nA
VDS = 500 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS μA
VDS = 400 V, VGS = 0 V, TJ = 150 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 6.6 A b - - 0.52 Ω
Forward transconductance gfs VDS = 50 V, ID = 6.6 A 6.1 - - S
Dynamic
Input capacitance Ciss VGS = 0 V, - 1423 -
Output capacitance Coss VDS = 25 V, - 208 -
Reverse transfer capacitance Crss f = 1.0 MHz, see fig. 5 - 8.1 -
pF
VDS = 1.0 V, f = 1.0 MHz - 2000 -
Output capacitance Coss
VGS = 0 V VDS = 400 V, f = 1.0 MHz - 55 -
Effective output capacitance Coss eff. VDS = 0 V to 400 V - 97 -
Total gate charge Qg - - 52
ID = 11 A, VDS = 400 V
Gate-source charge Qgs VGS = 10 V - - 13 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 18
Turn-on delay time td(on) - 14 -
Rise time tr VDD = 250 V, ID = 11 A - 35 -
ns
Turn-off delay time td(off) RG = 9.1 Ω, RD = 22 Ω, see fig. 10 b - 32 -
Fall time tf - 28 -
Gate input resistance Rg f = 1 MHz, open drain 0.5 - 3.2 Ω
Drain-Source Body Diode Characteristics

Continuous source-drain diode current IS MOSFET symbol D

- - 11
showing the
A
integral reverse G

Pulsed diode forward current a ISM p - n junction diode S

- - 44

Body diode voltage VSD TJ = 25 °C, IS = 11 A, VGS = 0 V b - - 1.5 V

Body diode reverse recovery time trr - 510 770 ns
TJ = 25 °C, IF = 11 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 3.4 5.1 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss effective is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS

S21-0867-Rev. C, 16-Aug-2021 2 Document Number: 91094

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

RDS(on), Drain-to-Source On Resistance

102 3.0
VGS 20 µs Pulse Width ID = 11 A
Top 15 V TJ = 25 °C VGS = 10 V
ID, Drain-to-Source Current (A)

10 V 2.5
8.0 V
7.0 V
10 2.0

(Normalized)
6.0 V
5.5 V
5.0 V 1.5
Bottom 4.5 V

1 1.0

4.5 V 0.5

0.1 0.0
0.1 1 10 102 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160

91094_01 VDS, Drain-to-Source Voltage (V) 91094_04 TJ, Junction Temperature (°C)

Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature

102 2400
VGS 20 µs Pulse Width VGS = 0 V, f = 1 MHz
Top 15 V TJ = 150 °C Ciss = Cgs + Cgd, Cds Shorted
ID, Drain-to-Source Current (A)

10 V 2000 Crss = Cgd

8.0 V Coss = Cds + Cgd
C, Capacitance (pF)

7.0 V
1600 Ciss
6.0 V
5.5 V
10 5.0 V 1200
Bottom 4.5 V

800
Coss
Crss
400
4.5 V

1 0
1 10 102 1 10 102 103

91094_02 VDS, Drain-to-Source Voltage (V) 91094_05 VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

102 20
ID = 11 A
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)

VDS = 400 V
16
VDS = 250 V
10 TJ = 150 °C
12
VDS = 100 V
TJ = 25 °C
8
1

4
20 µs Pulse Width For test circuit
VDS = 50 V see figure 13
0.1 0
4.0 5.0 6.0 7.0 8.0 9.0 0 10 20 30 40 50

91094_03 VGS, Gate-to-Source Voltage (V) 91094_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

S21-0867-Rev. C, 16-Aug-2021 3 Document Number: 91094

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

RD
102 VDS
ISD, Reverse Drain Current (A)

VGS
D.U.T.
RG
10 +
TJ = 150 °C - VDD

10V
TJ = 25 °C
Pulse Width ≤ 1 µs
1 Duty Factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

VGS = 0 V
0.1 VDS
0.0 0.4 0.8 1.2 1.6
90 %
91094_07 VSD, Source-to-Drain Voltage (V)

Fig. 7 - Typical Source-Drain Diode Forward Voltage

10 %
103 VGS
Operation in this area limited
by RDS(on) t d(on) tr t d(off) t f

Fig. 10b - Switching Time Waveforms

102
ID, Drain Current (A)

10 µs
10
100 µs

1 ms
1
TC = 25 °C 10 ms
TJ = 150 °C
Single Pulse
0.1
10 102 103 104

91094_08 VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

12

10
ID, Drain Current (A)

0
25 50 75 100 125 150

91094_09 TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

S21-0867-Rev. C, 16-Aug-2021 4 Document Number: 91094

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1
Thermal Response (ZthJC)

D = 0.50

0.20
0.1 PDM
0.10

0.05 t1
Single Pulse t2
0.02 (Thermal Response) Notes:
0.01 1. Duty Factor, D = t1/t2
2. Peak TJ = PDM x ZthJC + TC
10-2
10-5 10-4 10-3 10-2 0.1 1

91094_11 t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

EAS, Single Pulse Avalanche Energy (mJ)

600
ID
15 V Top 4.9 A
500 7.0 A
Bottom 11 A

Driver 400
VDS L

300
RG D.U.T. +
- VDD
A
200
IAS A
20 V
tp 0.01 Ω
100

Fig. 12a - Unclamped Inductive Test Circuit

0
25 50 75 100 125 150

V DS 91094_12c Starting TJ, Junction Temperature (°C)

tp Fig. 12c - Maximum Avalanche Energy vs. Drain Current

660
VDSav, Avalanche Voltage (V)

640

I AS
620
Fig. 12b - Unclamped Inductive Waveforms

600

580
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

91094_12d Iav, Avalanche Current (A)

Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche

Current

S21-0867-Rev. C, 16-Aug-2021 5 Document Number: 91094

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRFB11N50A
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Vishay Siliconix

Current regulator
Same type as D.U.T.

QG 50 kΩ

12 V 0.2 µF
10 V 0.3 µF
QGS Q GD
+
V
D.U.T. - DS
VG
VGS

3 mA
Charge
IG ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

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Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
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S21-0867-Rev. C, 16-Aug-2021 6 Document Number: 91094

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Revision: 01-Jul-2024 1 Document Number: 91000

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