Unit 3, Module 3

Flip-Flops Conversion and Flip Flop ICs

Instructor
Dr. R. S. Khule,
Department of Information Technology,
Matoshri College of Engineering and Research Centre,
Nashik.
 Recap

• We have seen the logic diagram, operation and truth table of

JK, Master-Slave JK, D ,T Flip- flops.
• We have also seen the procedure to derive excitation table for
SR, D, JK and T Flip-Flop.
 Contents

• Conversion of one Flip Flop to another.

• Flip- Flop ICs.
 Module Objectives

• Understand the procedure of conversion of one Flip-Flop

to another.
• Study the 7474 and 7476 Flip Flop ICs.
 Module Outcomes

• Convert the given Flip Flop to the specified Flip Flop

• Know the 7474 and 7476 Flip Flop ICs

 Flip Flop Conversion
• The conversion from one type of flip flop to the other
needs design of conversion logic which is done using the
excitation tables and K map simplifications.

Q
Flip-flop

{
Flip-flop
Data
Conversion
logic
(Combinational
circuit)
Given
flip-
flop
_
Q}
Outputs
inputs

Required Flip-
Flop
General model used to convert one type of FF to the other
 Truth Table of Conversion Logic

• The truth table of the conversion logic has data inputs and Q
and Q outputs of the given FF as inputs whereas the inputs of
the given FF are the outputs of the truth table.
• Then we draw the K map for each output and obtain the
simplified expressions.
• The conversion logic is then implemented using gates.
SR to D Flip flop Conversion
 SR to D Flip flop Conversion
Truth Table of conversion Logic K-map for S

Qn Qn
Input Present Next Flip flop Inputs Qn
0 1
state D
state
D 0 0 0
D Qn Qn+1 S R S D
0 0 0 0 X D 1 1 X
0 1 0 0 1
1 0 1 1 0 K-map for R
1 1 1 X 0
Qn Qn Qn R  D
Excitation Table for SR Flip Flop D 0 1

0 X 1
D
D 1 0 0
 D Flip-Flop Using SR Flip Flop
PR

Q
D S Q
CLK
R Q Q

CR
SR Flip flop to T Flip flop
 Conversion of SR Flip flop to T Flip flop
K-map for S
Input Present Next Flip flop Inputs Qn Qn
state Qn 0
state 1
T
T Qn Qn+1 S R
T 0 0 x
0 0 0 0 X S TQ n
0 1 1 X 0 T 1 1 0
1 0 1 1 0
1 1 0 0 1 K-map for R
Excitation Table for SR Flip Flop Qn Qn R  TQn
Qn
0 1
T
X 0
T 0
T 1 0 1
 T Flip-Flop Using SR Flip Flop

PR

T S Q Q

CLK
R Q Q

CR
SR Flip Flop to JK Flip Flop
 SR Flip Flop to JK Flip Flop
Inputs Outputs
J K Present Next state S R
state Qn Qn+1
0 0 0 0 0 ×
0 0 1 1 × 0
0 1 0 0 0 ×
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 × 0
1 1 0 1 1 0
1 1 1 0 0 1
Excitation Table for SR Flip Flop
 JK K-map for S
JK K-map for R
00 01 11 10
Qn 00 01 11 10
Qn
0 0 0 1 1
0 X X 0 0

1 X 0 0 X
1 0 1 1 0

S=J Qn
R=K Qn
 SR Flip Flop to JK Flip Flop

S Q
J Q

CLK SR-FF

K
R Q
Q
JK to T Flip flop Conversion
 JK to T Flip flop Conversion
K-map for J
Input Present Next Flip flop Inputs Qn Qn
state Qn 0
state 1
T
T Qn Qn+1 J K
T 0 0 x
0 0 0 0 X
J T
0 1 1 X 0 T 1 1 X
1 0 1 1 X
1 1 0 X 1 K-map for K
Excitation Table for JK Flip Flop Qn Qn K=T
Qn
0 1
T
X 0
T 0
T 1 X 1
 T Flip-Flop Using JK Flip Flop

PR

J
T Q Q
JK-FF
CLK
Q

K Q

CR
D Flip Flop to JK Flip Flop
 D Flip Flop to JK Flip Flop
Inputs Outputs
J K Present Next state D
state Qn Qn+1
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
 JK K-map for D
00 01 11 10
Qn

0 0 0 1 1
D= K Qn + JQn
1 1 0 0 1
 D Flip Flop to JK Flip Flop

Q
J D Q

CLK D-FF

Q
K Q
IC 7474 – Dual D Type Positive Edge triggered FF
• IC 7474 – Dual Positive Edge triggered D Flip Flop with PRESET
and CLEAR.
• These IC contain two independent D-type positive edge triggered
flip flops.

25
 IC 7474 – Dual D Type Positive Edge triggered FF
PR PR
4 10
2 5 12 9
D Q D Q

D-FF D-FF

CLK Q CLK Q
3 6 11 8
1 13

CR CR
+Vcc = Pin 14
GND = Pin 7

Connection Diagram
 IC 7474 –Function Table

Inputs Outputs
Operating Mode
PR CR D Q Q

Preset L H X H L

Clear H L X L H

Undetermined L L X H H

Set H H H H L

Reset H H L L H
 IC 7476-Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
• This device contains two independent positive pulse triggered J-
K flip-flops with complementary outputs.
• On the positive transition of the clock, the data from the J and K
inputs is transferred to the master.
• On the negative transition of the clock, the data from the master
is transferred to the slave.
• A LOW logic level on the preset or clear inputs will set or reset
the outputs regardless of logic levels of other inputs
 IC 7476 – Dual JK Flip Flop with Set and Clear
Connection Diagram:
 IC 7476 – Dual JK Flip Flop with Set and Clear
PR PR
2 7
16 15 12 11
K Q K Q
1 6
CLK D-FF CLK D-FF
J Q J Q
4 14 9 10
3 8

CR CR
+Vcc = Pin 5
GND = Pin 13
 IC 7476 – Dual JK Flip Flop with Set and Clear
Inputs Outputs
Operating Mode
PR CR J K Q Q

Preset L H X X H L
Clear H L X X L H
Undetermined L L X X H H
Toggle H H H H Q Q

Reset H H L H L H
Set H H H L H L
Hold H H L L Q Q
 Assignment
Q.1 Convert T Flip Flop to D Flip Flop

Q.2 Convert JK to SR Flip Flop

Q.3 Convert D Flip Flop to SR Flip Flop

Q.4 Design and implement T flip-flop using SR flip-flop.

• In next session i.e. Module 4 of Unit 3, we will discussed
about synchronous and asynchronous counter.
Thank You