ESP32-C6

Technical Reference Manual

Version 1.0
Espressif Systems
Copyright © 2024

www.espressif.com
About This Document
The ESP32-C6 Technical Reference Manual is targeted at developers working on low level software projects
that use the ESP32-C6 SoC. It describes the hardware modules listed below for the ESP32-C6 SoC and other
products in ESP32-C6 series. The modules detailed in this document provide an overview, list of features,
hardware architecture details, any necessary programming procedures, as well as register descriptions.

Navigation in This Document

Here are some tips on navigation through this extensive document:

• Release Status at a Glance on the very next page is a minimal list of all chapters from where you can
directly jump to a specific chapter.

• Use the Bookmarks on the side bar to jump to any specific chapters or sections from anywhere in the
document. Note this PDF document is configured to automatically display Bookmarks when open, which
is necessary for an extensive document like this one. However, some PDF viewers or browsers ignore
this setting, so if you don’t see the Bookmarks by default, try one or more of the following methods:

– Install a PDF Reader Extension for your browser;

– Download this document, and view it with your local PDF viewer;

– Set your PDF viewer to always automatically display the Bookmarks on the left side bar when open.

• Use the native Navigation function of your PDF viewer to navigate through the documents. Most PDF
viewers support to go Up, Down, Previous, Next, Back, Forward and Page with buttons, menu, or hot
keys.

• You can also use the built-in GoBack button on the upper right corner on each and every page to go
back to the previous place before you click a link within the document. Note this feature may only work
with some Acrobat-specific PDF viewers (for example, Acrobat Reader and Adobe DC) and browsers with
built-in Acrobat-specific PDF viewers or extensions (for example, Firefox).
Release Status at a Glance GoBack

Release Status at a Glance

Note that this manual in still work in progress. See our release progress below:

No. ESP32-C6 Chapters Progress

1 High-Performance CPU Published
2 RISC-V Trace Encoder (TRACE) Published
3 Low-Power CPU Published
4 GDMA Controller (GDMA) Published
5 System and Memory Published
6 eFuse Controller Published
7 IO MUX and GPIO Matrix (GPIO, IO MUX) Published
8 Reset and Clock Published
9 Chip Boot Control Published
10 Interrupt Matrix (INTMTX) Published
11 Event Task Matrix (SOC_ETM) Published
12 Low-Power Management Published
13 System Timer (SYSTIMER) Published
14 Timer Group (TIMG) Published
15 Watchdog Timers (WDT) Published
16 Permission Control (PMS) Published
17 System Registers Published
18 Debug Assistant (ASSIST_DEBUG) Published
19 AES Accelerator (AES) Published
20 ECC Accelerator (ECC) Published
21 HMAC Accelerator (HMAC) Published
22 RSA Accelerator (RSA) Published
23 SHA Accelerator (SHA) Published
24 Digital Signature (DS) Published
25 External Memory Encryption and Decryption (XTS_AES) Published
26 Random Number Generator (RNG) Published
27 UART Controller (UART, LP_UART, UHCI) Published
28 SPI Controller (SPI) Published
29 I2C Controller (I2C) Published
30 I2S Controller (I2S) Published
31 Pulse Count Controller (PCNT) Published
32 USB Serial/JTAG Controller (USB_SERIAL_JTAG) Published
33 Two-wire Automotive Interface (TWAI) Published
34 SDIO 2.0 Slave Controller (SDIO) Published
35 LED PWM Controller (LEDC) Published
36 Motor Control PWM (MCPWM) Published
37 Remote Control Peripheral (RMT) Published
38 Parallel IO Controller (PARL_IO) Published
39 On-Chip Sensor and Analog Signal Processing Published

Espressif Systems 3 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Release Status at a Glance GoBack

Note:

Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/documentation/esp32-c6_technical_reference_manual_en.pdf

Espressif Systems 4 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

Contents

1 High-Performance CPU 36
1.1 Overview 36
1.2 Features 36
1.3 Terminology 37
1.4 Address Map 37
1.5 Configuration and Status Registers (CSRs) 37
1.5.1 Register Summary 37
1.5.2 Register Description 39
1.6 Interrupt Controller 52
1.6.1 Features 52
1.6.2 Functional Description 52
1.6.3 Suggested Operation 54
1.6.3.1 Latency Aspects 54
1.6.3.2 Configuration Procedure 55
1.6.4 Registers 56
1.7 Core Local Interrupts (CLINT) 57
1.7.1 Overview 57
1.7.2 Features 57
1.7.3 Software Interrupt 57
1.7.4 Timer Counter and Interrupt 57
1.7.5 Register Summary 58
1.7.6 Register Description 58
1.8 Physical Memory Protection 62
1.8.1 Overview 62
1.8.2 Features 62
1.8.3 Functional Description 62
1.8.4 Register Summary 63
1.8.5 Register Description 63
1.9 Physical Memory Attribute (PMA) Checker 64
1.9.1 Overview 64
1.9.2 Features 64
1.9.3 Functional Description 64
1.9.4 Register Summary 65
1.9.5 Register Description 66
1.10 Debug 67
1.10.1 Overview 67
1.10.2 Features 68
1.10.3 Functional Description 68
1.10.4 JTAG Control 68
1.10.5 Register Summary 69
1.10.6 Register Description 69
1.11 Hardware Trigger 72

Espressif Systems 5 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

1.11.1 Features 72
1.11.2 Functional Description 72
1.11.3 Trigger Execution Flow 73
1.11.4 Register Summary 73
1.11.5 Register Description 74
1.12 Trace 78
1.12.1 Overview 78
1.12.2 Features 78
1.12.3 Functional Description 78
1.13 Debug Cross-Triggering 79
1.13.1 Overview 79
1.13.2 Features 79
1.13.3 Functional Description 79
1.13.4 Register Summary 80
1.13.5 Register Description 80
1.14 Dedicated IO 81
1.14.1 Overview 81
1.14.2 Features 81
1.14.3 Functional Description 81
1.14.4 Register Summary 82
1.14.5 Register Description 82
1.15 Atomic (A) Extension 84
1.15.1 Overview 84
1.15.2 Functional Description 84
1.15.2.1 Load Reserve (LR.W) Instruction 84
1.15.2.2 Store Conditional (SC.W) Instruction 84
1.15.2.3 AMO Instructions 85

2 RISC-V Trace Encoder (TRACE) 86

2.1 Terminology 86
2.2 Introduction 86
2.3 Features 87
2.4 Architectural Overview 88
2.5 Functional Description 89
2.5.1 Synchronization 89
2.5.2 Anchor Tag 89
2.5.3 Memory Writing Mode 89
2.5.4 Automatic Restart 90
2.6 Encoder Output Packets 90
2.6.1 Header 90
2.6.2 Index 90
2.6.3 Payload 91
2.6.3.1 Format 3 Packets 91
2.6.3.2 Format 2 Packets 92
2.6.3.3 Format 1 Packets 93
2.7 Interrupt 94

Espressif Systems 6 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

2.8 Programming Procedures 94

2.8.1 Enable Encoder 94
2.8.2 Disable Encoder 95
2.8.3 Decode Data Packets 95
2.9 Register Summary 96
2.10 Registers 97

3 Low-Power CPU 102

3.1 Features 102
3.2 Configuration and Status Registers (CSRs) 103
3.2.1 Register Summary 103
3.2.2 Registers 104
3.3 Interrupts and Exceptions 110
3.3.1 Interrupts 111
3.3.2 Interrupt Handling 111
3.3.3 Exceptions 111
3.4 Debugging 111
3.4.1 Features 112
3.4.2 Functional Description 112
3.4.3 Register Summary 112
3.4.4 Registers 113
3.5 Hardware Trigger 114
3.5.1 Features 114
3.5.2 Functional Description 114
3.5.3 Trigger Execution Flow 115
3.5.4 Register Summary 115
3.5.5 Registers 115
3.6 Performance Counter 118
3.7 System Access 119
3.7.1 Memory Access 119
3.7.2 Peripheral Access 119
3.8 Event Task Matrix Feature 119
3.9 Sleep and Wake-Up Process 120
3.9.1 Features 120
3.9.2 Process 120
3.9.3 Wake-Up Sources 122
3.10 Register Summary 122
3.11 Registers 122

4 GDMA Controller (GDMA) 124

4.1 Overview 124
4.2 Features 124
4.3 Architecture 125
4.4 Functional Description 126
4.4.1 Linked List 126
4.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer 127

Espressif Systems 7 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

4.4.3 Memory-to-Memory Data Transfer 128

4.4.4 Enabling GDMA 128
4.4.5 Linked List Reading Process 129
4.4.6 EOF 129
4.4.7 Accessing Internal RAM 129
4.4.8 Arbitration 130
4.4.9 Event Task Matrix Feature 130
4.5 GDMA Interrupts 131
4.6 Programming Procedures 132
4.6.1 Programming Procedures for GDMA’s Transmit Channel 132
4.6.2 Programming Procedures for GDMA’s Receive Channel 132
4.6.3 Programming Procedures for Memory-to-Memory Transfer 132
4.7 Register Summary 134
4.8 Registers 138

5 System and Memory 161

5.1 Overview 161
5.2 Features 161
5.3 Functional Description 162
5.3.1 Address Mapping 162
5.3.2 Internal Memory 163
5.3.3 External Memory 164
5.3.3.1 External Memory Address Mapping 164
5.3.3.2 Cache 164
5.3.3.3 Cache Operations 165
5.3.4 GDMA Address Space 166
5.3.5 Modules/Peripherals Address Mapping 166

6 eFuse Controller 170

6.1 Overview 170
6.2 Features 170
6.3 Functional Description 170
6.3.1 Structure 170
6.3.1.1 EFUSE_WR_DIS 177
6.3.1.2 EFUSE_RD_DIS 177
6.3.1.3 Data Storage 177
6.3.2 Programming of Parameters 179
6.3.3 Reading of Parameters by Users 181
6.3.4 eFuse VDDQ Timing 182
6.3.5 Parameters Used by Hardware Modules 182
6.3.6 Interrupts 183
6.4 Register Summary 184
6.5 Registers 188

7 IO MUX and GPIO Matrix (GPIO, IO MUX) 235

7.1 Overview 235

Espressif Systems 8 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

7.2 Features 235

7.3 Architectural Overview 236
7.4 Peripheral Input via GPIO Matrix 237
7.4.1 Overview 237
7.4.2 Signal Synchronization 238
7.4.3 Functional Description 238
7.4.4 Simple GPIO Input 240
7.5 Peripheral Output via GPIO Matrix 240
7.5.1 Overview 240
7.5.2 Functional Description 241
7.5.3 Simple GPIO Output 242
7.5.4 Sigma Delta Modulated Output (SDM) 242
7.5.4.1 Functional Description 242
7.5.4.2 SDM Configuration 243
7.6 Direct Input and Output via IO MUX 243
7.6.1 Overview 243
7.6.2 Functional Description 243
7.7 LP IO MUX for Low Power and Analog Input/Output 243
7.7.1 Overview 243
7.7.2 Low Power Capabilities 244
7.7.3 Analog Functions 244
7.8 Pin Functions in Light-sleep 244
7.9 Pin Hold Feature 245
7.10 Power Supplies and Management of GPIO Pins 245
7.10.1 Power Supplies of GPIO Pins 246
7.10.2 Power Supply Management 246
7.11 Peripheral Signal List 246
7.12 IO MUX Functions List 252
7.13 LP IO MUX Functions List 253
7.14 Event Task Matrix Function 254
7.15 Register Summary 255
7.15.1 GPIO Matrix Register Summary 255
7.15.2 IO MUX Register Summary 257
7.15.3 GPIO_EXT Register Summary 258
7.15.4 LP IO MUX Register Summary 259
7.16 Registers 260
7.16.1 GPIO Matrix Registers 260
7.16.2 IO MUX Registers 270
7.16.3 GPIO_EXT Registers 273
7.16.4 LP IO MUX Registers 283

8 Reset and Clock 293

8.1 Reset 293
8.1.1 Overview 293
8.1.2 Architectural Overview 293
8.1.3 Features 293

Espressif Systems 9 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

8.1.4 Functional Description 294

8.1.5 Peripheral Reset 295
8.2 Clock 295
8.2.1 Overview 295
8.2.2 Architectural Overview 295
8.2.3 Features 296
8.2.4 Functional Description 296
8.2.4.1 HP System Clock 296
8.2.4.2 LP System Clock 297
8.2.4.3 Peripheral Clocks 298
8.2.4.4 Wi-Fi and Bluetooth LE Clock 301
8.2.5 HP System Clock Gating Controlled by PMU 301
8.3 Programming Procedures 303
8.3.1 HP System Clock Configuration 303
8.3.2 LP System Clock Configuration 304
8.3.3 Peripheral Clock Reset and Configuration 304
8.4 Register Summary 305
8.4.1 PCR Registers 305
8.4.2 LP System Clock Registers 307
8.5 Registers 308
8.5.1 PCR Registers 308
8.5.2 LP Registers 353

9 Chip Boot Control 362

9.1 Overview 362
9.2 Functional Description 362
9.2.1 Default Configuration 362
9.2.2 Boot Mode Control 363
9.2.3 ROM Messages Printing Control 365
9.2.4 JTAG Signal Source Control 365
9.2.5 SDIO Sampling Input Edge and Output Driving Edge Control 366

10 Interrupt Matrix (INTMTX) 367

10.1 Overview 367
10.2 Features 367
10.3 Functional Description 368
10.3.1 Peripheral Interrupt Sources 368
10.3.2 CPU Interrupts 372
10.3.3 Assign Peripheral Interrupt Source to CPU Interrupt 372
10.3.3.1 Assign One Peripheral Interrupt Source (Source_X) to CPU 372
10.3.3.2 Assign Multiple Peripheral Interrupt Sources (Source_X) to CPU 372
10.3.3.3 Disable CPU Peripheral Interrupt Source (Source_X) 372
10.3.4 Query Current Interrupt Status of Peripheral Interrupt Source 373
10.4 Register Summary 374
10.4.1 Interrupt Matrix Register Summary 374
10.4.2 Interrupt Priority Register Summary 376

Espressif Systems 10 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

10.5 Registers 379

10.5.1 Interrupt Matrix Registers 379
10.5.2 Interrupt Priority Registers 382

11 Event Task Matrix (SOC_ETM) 386

11.1 Overview 386
11.2 Features 386
11.3 Functional Description 386
11.3.1 Architecture 386
11.3.2 Events 387
11.3.3 Tasks 390
11.3.4 Timing Considerations 394
11.3.5 Channel Control 395
11.4 Register Summary 396
11.5 Registers 399

12 Low-Power Management 403

12.1 Overview 403
12.2 Terminology 403
12.3 Features 403
12.4 Functional Description 404
12.4.1 Power Scheme 404
12.4.1.1 Regulators 405
12.4.1.2 Digital Power Domains 405
12.4.1.3 Analog Power Domains 406
12.4.2 PMU 406
12.4.2.1 PMU Main State Machine 407
12.4.2.2 Sleep/Wake-up Controller 408
12.4.2.3 Analog Power Controller 409
12.4.2.4 Digital Power Controller 410
12.4.2.5 Clock Controller 411
12.4.2.6 Backup Controller 414
12.4.2.7 System Controller 415
12.4.3 RTC Timer 415
12.4.4 Brownout Detector 416
12.5 Power Modes 417
12.6 RTC Boot 418
12.7 Event Task Matrix Feature 419
12.8 Interrupts 419
12.9 Register Summary 422
12.9.1 PMU Register Summary 422
12.9.2 Always-on Register Summary 424
12.9.3 RTC Timer Register Summary 424
12.9.4 Brownout Detector Register Summary 425
12.10 Registers 427
12.10.1 PMU Registers 427

Espressif Systems 11 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

12.10.2 Always-on Registers 467

12.10.3 RTC Timer Registers 468
12.10.4 Brownout Detector Registers 476

13 System Timer (SYSTIMER) 482

13.1 Overview 482
13.2 Features 482
13.3 Clock Source Selection 483
13.4 Functional Description 483
13.4.1 Counter 483
13.4.2 Comparator and Alarm 484
13.4.3 Event Task Matrix 485
13.4.4 Synchronization Operation 485
13.4.5 Interrupt 486
13.5 Programming Procedure 486
13.5.1 Read Current Count Value 486
13.5.2 Configure One-Time Alarm in Target Mode 486
13.5.3 Configure Periodic Alarms in Period Mode 487
13.5.4 Update After Light-sleep 487
13.6 Register Summary 488
13.7 Registers 490

14 Timer Group (TIMG) 505

14.1 Overview 505
14.2 Features 505
14.3 Functional Description 506
14.3.1 16-bit Prescaler and Clock Selection 506
14.3.2 54-bit Time-base Counter 506
14.3.3 Alarm Generation 507
14.3.4 Timer Reload 508
14.3.5 Event Task Matrix Feature 508
14.3.6 RTC_SLOW_CLK Frequency Calculation 509
14.3.7 Interrupts 510
14.4 Configuration and Usage 510
14.4.1 Timer as a Simple Clock 510
14.4.2 Timer as One-shot Alarm 511
14.4.3 Timer as Periodic Alarm by APB 511
14.4.4 Timer as Periodic Alarm by ETM 511
14.4.5 RTC_SLOW_CLK Frequency Calculation 512
14.5 Register Summary 514
14.6 Registers 515

15 Watchdog Timers (WDT) 529

15.1 Overview 529
15.2 Digital Watchdog Timers 530
15.2.1 Features 530

Espressif Systems 12 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

15.2.2 Functional Description 531

15.2.2.1 Clock Source and 32-Bit Counter 531
15.2.2.2 Stages and Timeout Actions 532
15.2.2.3 Write Protection 533
15.2.2.4 Flash Boot Protection 533
15.3 Super Watchdog 533
15.3.1 Features 533
15.3.2 Super Watchdog Controller 534
15.3.2.1 Structure 534
15.3.2.2 Workflow 534
15.4 Interrupts 534
15.5 Register Summary 535
15.6 Registers 535

16 Permission Control (PMS) 544

16.1 Overview 544
16.2 Features 545
16.3 Functional Description 545
16.3.1 TEE Controller Functional Description 545
16.3.2 APM Controller Functional Description 546
16.3.2.1 Architecture 546
16.3.2.2 Address Ranges 547
16.3.2.3 Access Permissions of Address Ranges 547
16.4 Programming Procedure 548
16.5 Illegal access and interrupts 549
16.6 Register Summary 550
16.6.1 High Performance APM Registers (HP_APM_REG) 550
16.6.2 Low Power APM Registers (LP_APM_REG) 551
16.6.3 Low Power APM0 Registers (LP_APM0_REG) 552
16.6.4 High Performance TEE Registers 553
16.6.5 Low Power TEE Registers 554
16.7 Registers 555
16.7.1 High Performance APM Registers (HP_APM_REG) 555
16.7.2 Low Power APM Registers (LP_APM_REG) 563
16.7.3 Low Power APM0 Registers (LP_APM0_REG) 570
16.7.4 High Performance TEE Registers 574
16.7.5 Low Power TEE Registers 575

17 System Registers 577

17.1 Overview 577
17.2 Features 577
17.3 Function Description 577
17.3.1 External Memory Encryption/Decryption Configuration 577
17.3.2 Anti-DPA Attack Security Control 577
17.3.3 HP Core/LP Core Debug Control 578
17.3.4 Bus Timeout Protection 578

Espressif Systems 13 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

17.3.4.1 CPU Peripheral Timeout Protection Register 578

17.3.4.2 HP Peripheral Timeout Protection Register 578
17.3.4.3 LP Peripheral Timeout Protection Register 579
17.4 Register Summary 580
17.5 Registers 581

18 Debug Assistant (ASSIST_DEBUG) 588

18.1 Overview 588
18.2 Features 588
18.3 Functional Description 588
18.3.1 Region Read/Write Monitoring 588
18.3.2 SP Monitoring 588
18.3.3 PC Logging 588
18.3.4 CPU/DMA Bus Access Logging 588
18.4 Recommended Operation 589
18.4.1 Region Monitoring and SP Monitoring Configuration 589
18.4.2 PC Logging Configuration 590
18.4.3 CPU/DMA Bus Access Logging Configuration 590
18.5 Register Summary 595
18.5.1 Summary of Bus Logging Configuration Registers 595
18.5.2 Summary of Other Registers 595
18.6 Registers 598
18.6.1 Bus Logging Configuration Registers 599
18.6.2 Other Registers 605

19 AES Accelerator (AES) 620

19.1 Introduction 620
19.2 Features 620
19.3 AES Working Modes 620
19.4 Typical AES Working Mode 622
19.4.1 Key, Plaintext, and Ciphertext 622
19.4.2 Endianness 622
19.4.3 Operation Process 624
19.5 DMA-AES Working Mode 624
19.5.1 Key, Plaintext, and Ciphertext 626
19.5.2 Endianness 626
19.5.3 Standard Incrementing Function 627
19.5.4 Block Number 627
19.5.5 Initialization Vector 627
19.5.6 Block Operation Process 628
19.6 Memory Summary 628
19.7 Register Summary 629
19.8 Registers 630

20 ECC Accelerator (ECC) 635

20.1 Introduction 635

Espressif Systems 14 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

20.2 Features 635

20.3 Terminology 635
20.3.1 ECC Basics 635
20.3.1.1 Elliptic Curve and Points on the Curves 635
20.3.1.2 Affine Coordinates and Jacobian Coordinates 635
20.3.2 Definitions of ESP32-C6’s ECC 636
20.3.2.1 Memory Blocks 636
20.3.2.2 Data and Data Block 636
20.3.2.3 Write Data 636
20.3.2.4 Read Data 637
20.3.2.5 Standard Calculation and Jacobian Calculation 637
20.4 Function Description 637
20.4.1 Key Size 637
20.4.2 Working Modes 637
20.4.2.1 Base Point Multiplication (Point Multi Mode) 638
20.4.2.2 Base Point Verification (Point Verif Mode) 638
20.4.2.3 Base Point Verification + Base Point Multiplication (Point Verif + Multi Mode) 638
20.4.2.4 Jacobian Point Multiplication (Jacobian Point Multi Mode) 638
20.4.2.5 Jacobian Point Verification (Jacobian Point Verif Mode) 639
20.4.2.6 Base Point Verification + Jacobian Point Multiplication (Point Verif + Jacobian
Point Multi Mode) 639
20.5 Clocks and Resets 639
20.6 Interrupts 639
20.7 Programming Procedures 640
20.8 Register Summary 641
20.9 Registers 642

21 HMAC Accelerator (HMAC) 646

21.1 Main Features 646
21.2 Functional Description 646
21.2.1 Upstream Mode 646
21.2.2 Downstream JTAG Enable Mode 647
21.2.3 Downstream Digital Signature Mode 647
21.2.4 HMAC eFuse Configuration 647
21.2.5 HMAC Process (Detailed) 648
21.3 HMAC Algorithm Details 650
21.3.1 Padding Bits 650
21.3.2 HMAC Algorithm Structure 651
21.4 Register Summary 653
21.5 Registers 655

22 RSA Accelerator (RSA) 662

22.1 Introduction 662
22.2 Features 662
22.3 Functional Description 662
22.3.1 Large-number Modular Exponentiation 662

Espressif Systems 15 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

22.3.2 Large-number Modular Multiplication 664

22.3.3 Large-number Multiplication 664
22.3.4 Options for Additional Acceleration 665
22.4 Memory Summary 667
22.5 Register Summary 667
22.6 Registers 668

23 SHA Accelerator (SHA) 672

23.1 Introduction 672
23.2 Features 672
23.3 Working Modes 672
23.4 Function Description 673
23.4.1 Preprocessing 673
23.4.1.1 Padding the Message 673
23.4.1.2 Parsing the Message 673
23.4.1.3 Setting the Initial Hash Value 674
23.4.2 Hash Operation 674
23.4.2.1 Typical SHA Mode Process 674
23.4.2.2 DMA-SHA Mode Process 675
23.4.3 Message Digest 676
23.4.4 Interrupt 677
23.5 Register Summary 678
23.6 Registers 679

24 Digital Signature (DS) 683

24.1 Overview 683
24.2 Features 683
24.3 Functional Description 683
24.3.1 Overview 683
24.3.2 Private Key Operands 684
24.3.3 Software Prerequisites 684
24.3.4 DS Operation at the Hardware Level 685
24.3.5 DS Operation at the Software Level 686
24.4 Memory Summary 688
24.5 Register Summary 689
24.6 Registers 690

25 External Memory Encryption and Decryption (XTS_AES) 693

25.1 Overview 693
25.2 Features 693
25.3 Module Structure 693
25.4 Functional Description 694
25.4.1 XTS Algorithm 694
25.4.2 Key 694
25.4.3 Target Memory Space 695
25.4.4 Data Writing 695

Espressif Systems 16 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

25.4.5 Manual Encryption Block 696

25.4.6 Auto Decryption Block 696
25.5 Software Process 697
25.6 Anti-DPA 698
25.7 Register Summary 699
25.8 Registers 700

26 Random Number Generator (RNG) 705

26.1 Introduction 705
26.2 Features 705
26.3 Functional Description 705
26.4 Programming Procedure 706
26.5 Register Summary 706
26.6 Register 706

27 UART Controller (UART, LP_UART, UHCI) 707

27.1 Overview 707
27.2 Features 707
27.3 UART Structure 708
27.4 Functional Description 709
27.4.1 Clock and Reset 709
27.4.2 UART FIFO 709
27.4.3 Baud Rate Generation and Detection 711
27.4.3.1 Baud Rate Generation 711
27.4.3.2 Baud Rate Detection 712
27.4.4 UART Data Frame 713
27.4.5 AT_CMD Character Structure 713
27.4.6 RS485 714
27.4.6.1 Driver Control 714
27.4.6.2 Turnaround Delay 714
27.4.6.3 Bus Snooping 715
27.4.7 IrDA 715
27.4.8 Wake-up 716
27.4.9 Flow Control 717
27.4.9.1 Hardware Flow Control 717
27.4.9.2 Software Flow Control 718
27.4.10 GDMA Mode 719
27.4.11 UART Interrupts 719
27.4.12 UHCI Interrupts 720
27.5 Programming Procedures 721
27.5.1 Register Type 721
27.5.2 Detailed Steps 721
27.5.2.1 Initializing UARTn 722
27.5.2.2 Configuring UARTn Communication 722
27.5.2.3 Enabling UARTn 723
27.6 Register Summary 724

Espressif Systems 17 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

27.6.1 UART Register Summary 724

27.6.2 LP UART Register Summary 725
27.6.3 UHCI Register Summary 726
27.7 Registers 728
27.7.1 UART Registers 728
27.7.2 LP UART Registers 750
27.7.3 UHCI Registers 770

28 SPI Controller (SPI) 793

28.1 Overview 793
28.2 Glossary 793
28.3 Features 794
28.4 Architectural Overview 795
28.5 Functional Description 795
28.5.1 Data Modes 795
28.5.2 Introduction to FSPI Bus Signals 796
28.5.3 Bit Read/Write Order Control 798
28.5.4 Transfer Types 800
28.5.5 CPU-Controlled Data Transfer 800
28.5.5.1 CPU-Controlled Master Transfer 800
28.5.5.2 CPU-Controlled Slave Transfer 802
28.5.6 DMA-Controlled Data Transfer 803
28.5.6.1 GDMA Configuration 803
28.5.6.2 GDMA TX/RX Buffer Length Control 804
28.5.7 Data Flow Control 805
28.5.7.1 GP-SPI2 Functional Blocks 805
28.5.7.2 Data Flow Control as Master 806
28.5.7.3 Data Flow Control as Slave 806
28.5.8 GP-SPI2 as a Master 807
28.5.8.1 State Machine 808
28.5.8.2 Register Configuration for State and Bit Mode Control 810
28.5.8.3 Full-Duplex Communication (1-bit Mode Only) 813
28.5.8.4 Half-Duplex Communication (1/2/4-bit Mode) 814
28.5.8.5 DMA-Controlled Configurable Segmented Transfer 816
28.5.9 GP-SPI2 Works as a Slave 819
28.5.9.1 Communication Formats 820
28.5.9.2 Supported CMD Values in Half-Duplex Communication 821
28.5.9.3 Slave Single Transfer and Slave Segmented Transfer 823
28.5.9.4 Configuration of Slave Single Transfer 824
28.5.9.5 Configuration of Slave Segmented Transfer in Half-Duplex 824
28.5.9.6 Configuration of Slave Segmented Transfer in Full-Duplex 825
28.6 CS Setup Time and Hold Time Control 825
28.7 GP-SPI2 Clock Control 826
28.7.1 Clock Phase and Polarity 827
28.7.2 Clock Control as Master 829
28.7.3 Clock Control as Slave 829

Espressif Systems 18 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

28.8 GP-SPI2 Timing Compensation 829

28.9 Interrupts 831
28.10 Register Summary 834
28.11 Registers 835

29 I2C Controller (I2C) 865

29.1 Overview 865
29.2 Features 865
29.3 I2C Architecture 866
29.4 Functional Description 868
29.4.1 Clock Configuration 868
29.4.2 SCL and SDA Noise Filtering 869
29.4.3 SCL Clock Stretching 869
29.4.4 Generating SCL Pulses in Idle State 869
29.4.5 Synchronization 870
29.4.6 Open-Drain Output 871
29.4.7 Timing Parameter Configuration 872
29.4.8 Timeout Control 874
29.4.9 Command Configuration 874
29.4.10 TX/RX RAM Data Storage 875
29.4.11 Data Conversion 876
29.4.12 Addressing Mode 876
29.4.13 R/W Bit Check in 10-bit Addressing Mode 877
29.4.14 To Start the I2C Controller 877
29.5 Functional differences between LP_I2C and I2C 877
29.6 Programming Example 878
29.6.1 I2Cmaster Writes to I2Cslave with a 7-bit Address in One Command Sequence 878
29.6.1.1 Introduction 878
29.6.1.2 Configuration Example 878
29.6.2 I2Cmaster Writes to I2Cslave with a 10-bit Address in One Command Sequence 879
29.6.2.1 Introduction 880
29.6.2.2 Configuration Example 880
29.6.3 I2Cmaster Writes to I2Cslave with Two 7-bit Addresses in One Command Sequence 881
29.6.3.1 Introduction 881
29.6.3.2 Configuration Example 882
29.6.4 I2Cmaster Writes to I2Cslave with a 7-bit Address in Multiple Command Sequences 883
29.6.4.1 Introduction 883
29.6.4.2 Configuration Example 884
29.6.5 I2Cmaster Reads I2Cslave with a 7-bit Address in One Command Sequence 885
29.6.5.1 Introduction 886
29.6.5.2 Configuration Example 886
29.6.6 I2Cmaster Reads I2Cslave with a 10-bit Address in One Command Sequence 888
29.6.6.1 Introduction 888
29.6.6.2 Configuration Example 888
29.6.7 I2Cmaster Reads I2Cslave with Two 7-bit Addresses in One Command Sequence 890
29.6.7.1 Introduction 890

Espressif Systems 19 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

29.6.7.2 Configuration Example 890

29.6.8 I2Cmaster Reads I2Cslave with a 7-bit Address in Multiple Command Sequences 892
29.6.8.1 Introduction 893
29.6.8.2 Configuration Example 894
29.7 Interrupts 896
29.8 Register Summary 897
29.9 I2C Register Summary 897
29.10 LP_I2C Register Summary 898
29.11 I2C Registers 900
29.11.1 LP_I2C Register 923

30 I2S Controller (I2S) 945

30.1 Overview 945
30.2 Terminology 945
30.3 Features 946
30.4 System Architecture 947
30.5 Supported Audio Standards 948
30.5.1 TDM Philips Standard 949
30.5.2 TDM MSB Alignment Standard 949
30.5.3 TDM PCM Standard 950
30.5.4 PDM Standard 950
30.6 I2S TX/RX Clock 951
30.7 I2S Reset 953
30.8 I2S Master/Slave Mode 953
30.8.1 Master/Slave TX Mode 953
30.8.2 Master/Slave RX Mode 954
30.9 Transmitting Data 954
30.9.1 Data Format Control 954
30.9.1.1 Bit Width Control of Channel Valid Data 954
30.9.1.2 Endian Control of Channel Valid Data 955
30.9.1.3 A-law/µ-law Compression and Decompression 955
30.9.1.4 Bit Width Control of Channel TX Data 956
30.9.1.5 Bit Order Control of Channel Data 956
30.9.2 Channel Mode Control 957
30.9.2.1 I2S Channel Control in TDM TX Mode 957
30.9.2.2 I2S Channel Control in PDM TX Mode 958
30.10 Receiving Data 961
30.10.1 Channel Mode Control 961
30.10.1.1 I2S Channel Control in TDM RX Mode 961
30.10.1.2 I2S Channel Control in PDM RX Mode 962
30.10.2 Data Format Control 962
30.10.2.1 Bit Order Control of Channel Data 962
30.10.2.2 Bit Width Control of Channel Storage (Valid) Data 962
30.10.2.3 Bit Width Control of Channel RX Data 963
30.10.2.4 Endian Control of Channel Storage Data 963
30.10.2.5 A-law/µ-law Compression and Decompression 963

Espressif Systems 20 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

30.11 Software Configuration Process 964

30.11.1 Configure I2S as TX Mode 964
30.11.2 Configure I2S as RX Mode 964
30.12 I2S Interrupts 965
30.12.1 Event Task Matrix Feature 965
30.13 Register Summary 967
30.14 Registers 968

31 Pulse Count Controller (PCNT) 985

31.1 Features 985
31.2 Functional Description 986
31.3 Applications 988
31.3.1 Channel 0 Incrementing Independently 988
31.3.2 Channel 0 Decrementing Independently 989
31.3.3 Channel 0 and Channel 1 Incrementing Together 989
31.4 Register Summary 991
31.5 Registers 992

32 USB Serial/JTAG Controller (USB_SERIAL_JTAG) 1000

32.1 Overview 1000
32.2 Features 1000
32.3 Functional Description 1002
32.3.1 CDC-ACM USB Interface Functional Description 1002
32.3.2 CDC-ACM Firmware Interface Functional Description 1003
32.3.3 USB-to-JTAG Interface: JTAG Command Processor 1004
32.3.4 USB-to-JTAG Interface: CMD_REP Usage Example 1005
32.3.5 USB-to-JTAG Interface: Response Capture Unit 1006
32.3.6 USB-to-JTAG Interface: Control Transfer Requests 1006
32.4 Recommended Operation 1007
32.5 Interrupts 1008
32.6 Register Summary 1010
32.7 Registers 1012

33 Two-wire Automotive Interface (TWAI) 1036

33.1 Features 1036
33.2 Protocol Overview 1036
33.2.1 TWAI Properties 1036
33.2.2 TWAI Messages 1037
33.2.2.1 Data Frames and Remote Frames 1038
33.2.2.2 Error and Overload Frames 1040
33.2.2.3 Interframe Space 1042
33.2.3 TWAI Errors 1042
33.2.3.1 Error Types 1042
33.2.3.2 Error States 1043
33.2.3.3 Error Counters 1043
33.2.4 TWAI Bit Timing 1044

Espressif Systems 21 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

33.2.4.1 Nominal Bit 1044

33.2.4.2 Hard Synchronization and Resynchronization 1045
33.3 Architectural Overview 1045
33.3.1 Registers Block 1046
33.3.2 Bit Stream Processor 1047
33.3.3 Error Management Logic 1047
33.3.4 Bit Timing Logic 1047
33.3.5 Acceptance Filter 1048
33.3.6 Receive FIFO 1048
33.4 Functional Description 1048
33.4.1 Modes 1048
33.4.1.1 Reset Mode 1048
33.4.1.2 Operation Mode 1048
33.4.2 Bit Timing 1049
33.4.3 Interrupt Management 1049
33.4.3.1 Receive Interrupt (RXI) 1050
33.4.3.2 Transmit Interrupt (TXI) 1050
33.4.3.3 Error Warning Interrupt (EWI) 1050
33.4.3.4 Data Overrun Interrupt (DOI) 1051
33.4.3.5 Error Passive Interrupt (TXI) 1051
33.4.3.6 Arbitration Lost Interrupt (ALI) 1051
33.4.3.7 Bus Error Interrupt (BEI) 1051
33.4.3.8 Bus Idle Status Interrupt (BISI) 1051
33.4.4 Transmit and Receive Buffers 1052
33.4.4.1 Overview of Buffers 1052
33.4.4.2 Frame Information 1052
33.4.4.3 Frame Identifier 1053
33.4.4.4 Frame Data 1054
33.4.5 Receive FIFO and Data Overruns 1054
33.4.6 Acceptance Filter 1055
33.4.6.1 Single Filter Mode 1056
33.4.6.2 Dual Filter Mode 1056
33.4.7 Error Management 1057
33.4.7.1 Error Warning Limit 1058
33.4.7.2 Error Passive 1058
33.4.7.3 Bus-Off and Bus-Off Recovery 1058
33.4.8 Error Code Capture 1059
33.4.9 Arbitration Lost Capture 1060
33.4.10 Transceiver Auto-Standby 1061
33.5 Register Summary 1062
33.6 Registers 1063

34 SDIO 2.0 Slave Controller (SDIO) 1078

34.1 Overview 1078
34.2 Features 1078
34.3 Architecture Overview 1078

Espressif Systems 22 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

34.4 Standards Compliance 1079

34.5 Functional Description 1079
34.5.1 Physical Bus 1079
34.5.2 Supported Commands 1079
34.5.3 I/O Function 0 Address Space 1080
34.5.4 I/O Function 1/2 Address Space Map 1082
34.5.4.1 Accessing SLC HOST Register Space 1083
34.5.4.2 Transferring Incremental-Address Packets 1083
34.5.4.3 Transferring Fixed-Address Packets 1083
34.5.5 DMA 1084
34.5.5.1 Linked List 1084
34.5.5.2 Write-Back of Linked List 1086
34.5.5.3 Data Padding and Discarding 1086
34.5.6 SDIO Bus Timing 1087
34.6 Interrupt 1088
34.6.1 Host Interrupt 1088
34.6.2 Slave Interrupt 1089
34.7 Packet Sending and Receiving Procedure 1089
34.7.1 Sending Packets to SDIO Host 1089
34.7.2 Receiving Packets from SDIO Host 1091
34.8 Register Summary 1094
34.8.1 HINF Register Summary 1094
34.8.2 SLC Register Summary 1094
34.8.3 SLC Host Register Summary 1095
34.9 Registers 1097
34.9.1 HINF Registers 1097
34.9.2 SLC Registers 1102
34.9.3 SLC Host Registers 1124

35 LED PWM Controller (LEDC) 1134

35.1 Overview 1134
35.2 Features 1134
35.3 Functional Description 1135
35.3.1 Architecture 1135
35.3.2 Timers 1135
35.3.2.1 Clock Source 1135
35.3.2.2 Clock Divider Configuration 1136
35.3.2.3 20-Bit Counter 1137
35.3.3 PWM Generators 1138
35.3.4 Duty Cycle Fading 1139
35.3.4.1 Linear Duty Cycle Fading 1139
35.3.4.2 Gamma Curve Fading 1140
35.3.4.3 Suspend and Resume Duty Cycle Fading 1142
35.3.5 Event Task Matrix Feature 1142
35.3.6 Interrupts 1144
35.4 Register Summary 1145

Espressif Systems 23 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

35.5 Registers 1148

36 Motor Control PWM (MCPWM) 1161

36.1 Overview 1161
36.2 Features 1161
36.3 Modules 1164
36.3.1 Overview 1164
36.3.1.1 Prescaler Module 1164
36.3.1.2 Timer Module 1164
36.3.1.3 Operator Module 1165
36.3.1.4 Fault Detection Module 1166
36.3.1.5 Capture Module 1167
36.3.1.6 ETM Module 1167
36.3.2 PWM Timer Module 1167
36.3.2.1 Configurations of the PWM Timer Module 1167
36.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 1168
36.3.2.3 Shadow Register of PWM Timer 1174
36.3.2.4 PWM Timer Synchronization and Phase Locking 1174
36.3.3 PWM Operator Module 1174
36.3.3.1 PWM Generator Module 1176
36.3.3.2 Dead Time Generator Module 1187
36.3.3.3 PWM Carrier Module 1190
36.3.3.4 Fault Detection Module 1193
36.3.4 Capture Module 1194
36.3.4.1 Introduction 1194
36.3.4.2 Capture Timer 1195
36.3.4.3 Capture Channel 1195
36.3.5 ETM Module 1195
36.3.5.1 Overview 1195
36.3.5.2 MCPWM-Related ETM Events 1195
36.3.5.3 MCPWM-Related ETM Tasks 1196
36.4 Register Summary 1198
36.5 Registers 1201

37 Remote Control Peripheral (RMT) 1274

37.1 Overview 1274
37.2 Features 1274
37.3 Functional Description 1275
37.3.1 RMT Architecture 1275
37.3.2 RMT RAM 1276
37.3.2.1 Structure of RAM 1276
37.3.2.2 Use of RAM 1276
37.3.2.3 RAM Access 1277
37.3.3 Clock 1277
37.3.4 Transmitter 1277
37.3.4.1 Normal TX Mode 1278

Espressif Systems 24 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

37.3.4.2 Wrap TX Mode 1278

37.3.4.3 TX Modulation 1278
37.3.4.4 Continuous TX Mode 1279
37.3.4.5 Simultaneous TX Mode 1279
37.3.5 Receiver 1279
37.3.5.1 Normal RX Mode 1279
37.3.5.2 Wrap RX Mode 1280
37.3.5.3 RX Filtering 1280
37.3.5.4 RX Demodulation 1280
37.3.6 Configuration Update 1280
37.3.7 Interrupts 1281
37.4 Register Summary 1282
37.5 Registers 1284

38 Parallel IO Controller (PARL_IO) 1299

38.1 Introduction 1299
38.2 Glossary 1299
38.3 Features 1299
38.4 Architectural Overview 1300
38.5 Functional Description 1301
38.5.1 Clock Generator 1301
38.5.2 Clock & Reset Restriction 1301
38.5.3 Master-Slave Mode 1303
38.5.4 Receive Modes of the RX Unit 1303
38.5.4.1 Level Enable Mode 1304
38.5.4.2 Pulse Enable Mode 1304
38.5.4.3 Software Enable Mode 1305
38.5.5 RX Unit GDMA SUC EOF Generation 1306
38.5.6 RX Unit Timeout 1306
38.5.7 Valid Signal Output of TX Unit 1306
38.5.8 Bus Idle Value of TX Unit 1306
38.5.9 Data Transfer in a Single Frame 1307
38.5.10 Bit Reordering in One Byte 1307
38.6 Programming Procedures 1307
38.6.1 Data Receiving Operation Process 1307
38.6.2 Data Transmitting Operation Process 1308
38.7 Application Examples 1308
38.7.1 Co-working with SPI 1309
38.7.2 Co-working with I2S 1310
38.7.3 Co-working with LCD 1311
38.8 Interrupts 1312
38.9 Register Summary 1313
38.10 Registers 1314

39 On-Chip Sensor and Analog Signal Processing 1323

39.1 Overview 1323

Espressif Systems 25 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
Contents GoBack

39.2 SAR ADC 1323

39.2.1 Overview 1323
39.2.2 Features 1323
39.2.3 Functional Description 1323
39.2.3.1 Input Signals 1325
39.2.3.2 ADC Conversion and Attenuation 1325
39.2.3.3 DIG ADC Controller 1325
39.2.3.4 DMA Support 1326
39.2.3.5 DIG ADC FSM 1326
39.2.3.6 ADC Filters 1329
39.2.3.7 Threshold Monitoring 1329
39.3 Temperature Sensor 1330
39.3.1 Overview 1330
39.3.2 Features 1330
39.3.3 Functional Description 1331
39.4 Event Task Matrix Feature 1332
39.4.1 SAR ADC’s ETM Feature 1332
39.4.2 Temperature Sensor’s ETM Feature 1332
39.5 Interrupts 1332
39.6 Register Summary 1334
39.7 Registers 1335

Related Documentation and Resources 1351

Glossary 1352
Abbreviations for Peripherals 1352
Abbreviations Related to Registers 1352
Access Types for Registers 1354

Programming Reserved Register Field 1356

Introduction 1356
Programming Reserved Register Field 1356

Interrupt Configuration Registers 1357

Revision History 1358

Espressif Systems 26 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Tables GoBack

List of Tables
1-2 CPU Address Map 37
1-4 Core Local Interrupt (CLINT) Sources 57
1-10 NAPOT encoding for maddress 73
2-2 Trace Encoder Parameters 88
2-3 Header Format 90
2-4 Index Format 91
2-5 Packet format 3 subformat 0 91
2-6 Packet format 3 subformat 1 91
2-7 Packet format 3 subformat 3 92
2-8 Packet format 2 92
2-9 Packet format 1 with address 93
2-10 Packet format 1 without address 94
3-2 LP CPU Exception Causes 111
3-5 Performance Counter 118
3-6 Wake Sources 122
4-1 Selecting Peripherals via Register Configuration 127
4-2 Descriptor Field Alignment Requirements 130
5-1 Memory Address Mapping 163
5-2 Module/Peripheral Address Mapping 167
6-1 Parameters in eFuse BLOCK0 172
6-2 Secure Key Purpose Values 175
6-3 Parameters in BLOCK1 to BLOCK10 176
6-4 Registers Information 181
6-5 Configuration of Default VDDQ Timing Parameters 182
7-1 Bit Used to Control IO MUX Functions in Light-sleep Mode 244
7-2 Peripheral Signals via GPIO Matrix 247
7-3 IO MUX Functions List 252
7-4 LP IO MUX Functions List 253
7-5 Analog Functions of IO MUX Pins 254
8-1 Reset Source 294
8-2 CPU_CLK Clock Source 296
8-3 Frequency of CPU_CLK, AHB_CLK and HP_ROOT_CLK 297
8-4 Derived Clock Source 299
8-5 HP Clocks Used by Each Peripheral 299
8-6 LP Clocks Used by Each Peripheral 300
8-7 Mapping Between PMU Register Bits and the Clock Gating of Peripherals’ Register R/W Operations302
8-8 Mapping Between PMU Register Bits and the Gating of Peripherals’ Operating Clock 303
9-1 Default Configuration of Strapping Pins 363
9-2 Boot Mode Control 363
9-3 ROM Message Printing Control 365
9-4 JTAG Signal Source Control 366
9-5 SDIO Input Sampling Edge/Output Driving Edge Control 366
10-1 CPU Peripheral Interrupt Source Mapping/Status Registers and Peripheral Interrupt Sources 369

Espressif Systems 27 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Tables GoBack

11-1 Selectable Events for ETM Channeln 387

11-2 Mappable Tasks for ETM Channeln 390
12-2 Wake-up Sources 409
12-3 HP System Peripherals’ Function Clocks 412
12-4 HP System Peripherals’ APB Clocks 413
12-5 Trigger Conditions for the RTC Timer 415
12-6 Preset Power Modes 418
13-1 UNITn Configuration Bits 484
13-2 Trigger Point 485
13-3 Synchronization Operation for Configuration Registers 486
14-1 Alarm Generation When Up-Down Counter Increments 507
14-2 Alarm Generation When Up-Down Counter Decrements 508
15-1 Timeout Actions 532
16-1 Management Area of PMP and APM 544
16-2 Configuring Access Path 547
17-1 Security Level 577
18-1 HP CPU Packet Format 592
18-2 LP CPU Packet Format 592
18-3 DMA Packet Format 592
18-4 LOST Packet Format 592
18-5 DMA Access Source 593
19-1 AES Accelerator Working Mode 621
19-2 Key Length and Encryption/Decryption 621
19-3 Working Status under Typical AES Working Mode 622
19-4 Text Endianness Type for Typical AES 622
19-5 Key Endianness Type for AES-128 Encryption and Decryption 623
19-6 Key Endianness Type for AES-256 Encryption and Decryption 623
19-7 Block Cipher Mode 624
19-8 Working Status under DMA-AES Working mode 626
19-9 TEXT-PADDING 626
19-10 Text Endianness for DMA-AES 627
20-1 ECC Accelerator Memory Blocks 636
20-2 ECC Accelerator Key Size Selection 637
20-3 ECC Accelerator’s Working Modes 638
21-1 HMAC Purposes and Configuration Value 648
22-1 Acceleration Performance 666
22-2 RSA Accelerator Memory Blocks 667
23-1 SHA Accelerator Working Mode 672
23-2 SHA Hash Algorithm Selection 673
23-3 The Storage and Length of Message Digest from Different Algorithms 676
25-1 Key generated based on Key A 694
25-2 Mapping Between Offsets and Registers 696
27-1 UART and LP UART Feautre Comparison 707
27-2 UART_CHAR_WAKEUP Mode Configuration 716
28-2 Data Modes Supported by GP-SPI2 796
28-3 Functional Description of FSPI Bus Signals 796

Espressif Systems 28 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Tables GoBack

28-4 Signals Used in Various SPI Modes 797

28-5 Bit Order Control in GP-SPI2 799
28-6 Supported Transfer Types as Master or Slave 800
28-7 Interrupt Trigger Condition on GP-SPI2 Data Transfer as Slave 804
28-8 Registers Used for State Control in 1/2/4-bit Modes 810
28-8 Registers Used for State Control in 1/2/4-bit Modes 811
28-9 Sending Sequence of Command Value 812
28-10 Sending Sequence of Address Value 813
28-11 BM Table for CONF State 818
28-12 An Example of CONF bufferi in Segmenti 819
28-13 BM Bit Value v.s. Register to Be Updated in This Example 819
28-14 Supported CMD Values in SPI Mode 822
28-14 Supported CMD Values in SPI Mode 823
28-15 Supported CMD Values in QPI Mode 823
28-16 Clock Phase and Polarity Configuration as Master 829
28-17 Clock Phase and Polarity Configuration as Slave 829
28-18 GP-SPI2 Interrupts as Master 833
28-19 GP-SPI2 Interrupts as Slave 833
29-1 I2C Synchronous Registers 871
30-2 I2S Signal Description 948
30-3 Bit Width of Channel Valid Data 955
30-4 Endian of Channel Valid Data 955
30-5 The Matching Between Valid Data Width and Number of TX Channel Supported 957
30-6 Data-Fetching Control in PDM Mode 959
30-7 I2S Channel Control in Normal PDM TX Mode 959
30-8 PCM-to-PDM TX Mode 959
30-9 The Matching Between Valid Data Width and Number of RX Channel Supported 961
30-10 Channel Storage Data Width 962
30-11 Channel Storage Data Endian 963
31-1 Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in Low State 987
31-2 Counter Mode. Positive Edge of Input Pulse Signal. Control Signal in High State 987
31-3 Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in Low State 987
31-4 Counter Mode. Negative Edge of Input Pulse Signal. Control Signal in High State 988
32-1 Standard CDC-ACM Control Requests 1002
32-2 CDC-ACM Settings with RTS and DTR 1003
32-3 Commands of a Nibble 1005
32-4 USB-to-JTAG Control Requests 1006
32-5 JTAG Capability Descriptors 1007
32-6 Reset SoC into Download Mode 1008
32-7 Reset SoC into Booting from flash 1008
33-1 Data Frames and Remote Frames in SFF and EFF 1039
33-2 Error Frame 1041
33-3 Overload Frame 1041
33-4 Interframe Space 1042
33-5 Segments of a Nominal Bit Time 1044
33-6 Bit Information of TWAI_BUS_TIMING_0_REG (0x18) 1049

Espressif Systems 29 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Tables GoBack

33-7 Bit Information of TWAI_BUS_TIMING_1_REG (0x1c) 1049

33-8 Buffer Layout for Standard Frame Format and Extended Frame Format 1052
33-9 TX/RX Frame Information (SFF/EFF)�TWAI Address 0x40 1052
33-10 TX/RX Identifier 1 (SFF); TWAI Address 0x44 1053
33-11 TX/RX Identifier 2 (SFF); TWAI Address 0x48 1053
33-12 TX/RX Identifier 1 (EFF); TWAI Address 0x44 1053
33-13 TX/RX Identifier 2 (EFF); TWAI Address 0x48 1053
33-14 TX/RX Identifier 3 (EFF); TWAI Address 0x4c 1054
33-15 TX/RX Identifier 4 (EFF); TWAI Address 0x50 1054
33-16 Bit Information of TWAI_ERR_CODE_CAP_REG (0x30) 1059
33-17 Bit Information of Bits SEG.4 - SEG.0 1059
33-18 Bit Information of TWAI_ARB_LOST_CAP_REG (0x2c) 1060
34-1 SDIO Slave CCCR Configuration 1080
34-2 SDIO Slave FBR Configuration 1081
35-1 Commonly-used Frequencies and Resolutions 1138
36-1 Configuration Parameters of the Operator Submodule 1165
36-2 Timing Events Used in PWM Generator 1177
36-3 Timing Events Priority When PWM Timer Increments 1177
36-4 Timing Events Priority when PWM Timer Decrements 1178
36-5 Dead Time Generator Switches Control Fields 1188
36-6 Typical Dead Time Generator Operating Modes 1188
36-7 MCPWM-Related ETM Events 1195
36-8 ETM Related Tasks 1196
37-1 Configuration Update 1281
39-1 SAR ADC Input Signals 1325
39-2 Temperature Offset 1331
39-7 Configuration of ENA/RAW/ST Registers 1357

Espressif Systems 30 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Figures GoBack

List of Figures
1-1 CPU Block Diagram 36
1-2 Debug System Overview 67
2-1 Trace Encoder Overview 86
2-2 Trace Overview 87
2-3 Trace packet Format 90
3-1 LP CPU Overview 102
3-2 Wake-Up and Sleep Flow of LP CPU 120
4-1 Modules with GDMA Feature and GDMA Channels 124
4-2 GDMA controller Architecture 125
4-3 Structure of a Linked List 126
4-4 Relationship among Linked Lists 128
5-1 System Structure and Address Mapping 162
5-2 Cache Structure 165
5-3 Modules/peripherals that can work with GDMA 166
6-1 Data Flow in eFuse 171
6-2 Shift Register Circuit (first 32 output) 178
6-3 Shift Register Circuit (last 12 output) 178
7-1 Architecture of IO MUX, LP IO MUX, and GPIO Matrix 236
7-2 Internal Structure of a Pad 237
7-3 GPIO Input Synchronized on Rising Edge or on Falling Edge of IO MUX Operating Clock 238
7-4 GPIO Filter Timing of GPIO Input Signals 239
7-5 Glitch Filter Timing Example 239
8-1 Reset Types 293
8-2 System Clock 295
8-3 Clock Configuration Example 305
9-1 Chip Boot Flow 364
10-1 Interrupt Matrix Structure 367
11-1 Event Task Matrix Architecture 386
11-2 ETM Channeln Architecture 387
11-3 Event Task Matrix Clock Architecture 394
12-1 ESP32-C6 Power Scheme 405
12-2 PMU Workflow 407
12-3 Brownout Reset Workflow 417
12-4 ESP32-C6 Boot Flow 419
13-1 System Timer Structure 482
13-2 System Timer Alarm Generation 483
14-1 Timer Group Overview 505
14-2 Timer Group Architecture 506
15-1 Watchdog Timers Overview 529
15-2 Digital Watchdog Timers in ESP32-C6 531
15-3 Super Watchdog Controller Structure 534
16-1 PMP-APM Management Relation 544
16-2 APM Controller Structure 546

Espressif Systems 31 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Figures GoBack

21-1 HMAC SHA-256 Padding Diagram 651

21-2 HMAC Structure Schematic Diagram 651
24-1 Software Preparations and Hardware Working Process 684
25-1 Architecture of the External Memory Encryption and Decryption 693
26-1 Noise Source 705
27-1 UART Structure 708
27-2 UART Controllers Division 711
27-3 The Timing Diagram of Weak UART Signals Along Falling Edges 712
27-4 Structure of UART Data Frame 713
27-5 AT_CMD Character Structure 713
27-6 Driver Control Diagram in RS485 Mode 714
27-7 The Timing Diagram of Encoding and Decoding in SIR mode 715
27-8 IrDA Encoding and Decoding Diagram 716
27-9 Hardware Flow Control Diagram 717
27-10 Connection between Hardware Flow Control Signals 718
27-11 Data Transfer in GDMA Mode 719
27-12 UART Programming Procedures 722
28-1 SPI Module Overview 795
28-2 Data Buffer Used in CPU-Controlled Transfer 800
28-3 GP-SPI2 Block Diagram 805
28-4 Data Flow Control in GP-SPI2 as Master 806
28-5 Data Flow Control in GP-SPI2 as Slave 806
28-6 GP-SPI2 State Machine as Master 809
28-7 Full-Duplex Communication Between GP-SPI2 Master and a Slave 813
28-8 Connection of GP-SPI2 to Flash and External RAM in 4-bit Mode 815
28-9 SPI Quad I/O Read Command Sequence Sent by GP-SPI2 to Flash 816
28-10 Configurable Segmented Transfer as Master 816
28-11 Recommended CS Timing and Settings When Accessing External RAM 826
28-12 Recommended CS Timing and Settings When Accessing Flash 826
28-13 SPI Clock Mode 0 or 2 828
28-14 SPI Clock Mode 1 or 3 828
28-15 Timing Compensation Control Diagram in GP-SPI2 as Master 830
28-16 Timing Compensation Example in GP-SPI2 as Master 831
29-1 I2C Master Architecture 866
29-2 I2C Slave Architecture 866
29-3 I2C Protocol Timing (Cited from Fig.31 in The I2C-bus specification Version 2.1) 867
29-4 I2C Timing Parameters (Cited from Table 5 in The I2C-bus specification Version 2.1) 868
29-5 I2C Timing Diagram 872
29-6 Structure of I2C Command Registers 874
29-7 I2Cmaster Writing to I2Cslave with a 7-bit Address 878
29-8 I2Cmaster Writing to a Slave with a 10-bit Address 880
29-9 I2Cmaster Writing to I2Cslave with Two 7-bit Addresses 881
29-10 I2Cmaster Writing to I2Cslave with a 7-bit Address in Multiple Sequences 883
29-11 I2Cmaster Reading I2Cslave with a 7-bit Address 886
29-12 I2Cmaster Reading I2Cslave with a 10-bit Address 888
29-13 I2Cmaster Reading N Bytes of Data from addrM of I2Cslave with a 7-bit Address 890

Espressif Systems 32 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Figures GoBack

29-14 I2Cmaster Reading I2Cslave with a 7-bit Address in Segments 893

30-1 ESP32-C6 I2S System Diagram 947
30-2 TDM Philips Standard Timing Diagram 949
30-3 TDM MSB Alignment Standard Timing Diagram 950
30-4 TDM PCM Standard Timing Diagram 950
30-5 PDM Standard Timing Diagram 951
30-6 I2S Clock Generator 951
30-7 TX Data Format Control 957
30-8 TDM Channel Control 958
30-9 PDM Channel Control Example 961
31-1 PCNT Block Diagram 985
31-2 PCNT Unit Architecture 986
31-3 Channel 0 Up Counting Diagram 988
31-4 Channel 0 Down Counting Diagram 989
31-5 Two Channels Up Counting Diagram 989
32-1 USB Serial/JTAG High Level Diagram 1001
32-2 USB Serial/JTAG Block Diagram 1002
33-1 Bit Fields in Data Frames and Remote Frames 1038
33-2 Fields of an Error Frame 1040
33-3 Fields of an Overload Frame 1041
33-4 The Fields within an Interframe Space 1042
33-5 Layout of a Bit 1046
33-6 TWAI Overview Diagram 1046
33-7 Acceptance Filter 1055
33-8 Single Filter Mode 1056
33-9 Dual Filter Mode 1057
33-10 Error State Transition 1058
33-11 Positions of Arbitration Lost Bits 1060
34-1 SDIO Slave Block Diagram 1078
34-2 CMD52 Content 1079
34-3 CMD53 Content 1080
34-4 Function 0 Address Space 1080
34-5 Function 1/2 Address Space Map 1082
34-6 DMA Linked List Descriptor Structure of the SDIO Slave 1084
34-7 DMA Linked List of the SDIO Slave 1085
34-8 Data Flow of Sending Incremental-address Packets From Host to Slave 1087
34-9 Sampling Timing Diagram 1087
34-10 Output Timing Diagram 1088
34-11 Procedure of Slave Sending Packets to Host 1090
34-12 Procedure of Slave Receiving Packets from Host 1092
34-13 Loading Receiving Buffer 1093
35-1 LED PWM Architecture 1134
35-2 Timer and PWM Generator Block Diagram 1135
35-3 Frequency Division When LEDC_CLK_DIV is a Non-Integer Value 1136
35-4 Relationship Between Counter And Resolution 1137
35-5 LED PWM Output Signal Diagram 1139

Espressif Systems 33 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Figures GoBack

35-6 Output Signal of Linear Duty Cycle Fading 1141

35-7 Output Signal of Gamma Curve Fading 1142
36-1 MCPWM Module Overview 1162
36-2 Prescaler Module 1164
36-3 Timer Module 1164
36-4 Operator Module 1165
36-5 Fault Detection Module 1166
36-6 Capture Module 1167
36-7 ETM Module 1167
36-8 Count-Up Mode Waveform 1169
36-9 Count-Down Mode Waveforms 1169
36-10 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 1169
36-11 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 1170
36-12 UTEP and UTEZ Generation in Count-Up Mode 1171
36-13 DTEP and DTEZ Generation in Count-Down Mode 1172
36-14 DTEP and UTEZ Generation in Count-Up-Down Mode 1172
36-15 Block Diagram of A PWM Operator 1175
36-16 Symmetrical Waveform in Count-Up-Down Mode 1179
36-17 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High 1180
36-18 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 1181
36-19 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Active High 1182
36-20 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Complementary 1183
36-21 Count-Up-Down, Fault or Synchronization Events, with Same Modulation on PWMxA and PWMxB1184
36-22 Example of an NCI Software-Force Event on PWMxA 1185
36-23 Example of a CNTU Software-Force Event on PWMxB 1186
36-24 Options for Setting up the Dead Time Generator Module 1188
36-25 Active High Complementary (AHC) Dead Time Waveforms 1189
36-26 Active Low Complementary (ALC) Dead Time Waveforms 1190
36-27 Active High (AH) Dead Time Waveforms 1190
36-28 Active Low (AL) Dead Time Waveforms 1191
36-29 Example of Waveforms Showing PWM Carrier Action 1192
36-30 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule1192
36-31 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 1193
37-1 RMT Architecture 1275
37-2 Format of Pulse Code in RAM 1276
38-1 PARLIO Architecture 1300
38-2 PARLIO Clock Generation 1301
38-3 Master Clock Positive Waveform 1303
38-4 Master Clock Negative Waveform 1303
38-5 Sub-Modes of Level Enable Mode for RX Unit 1304
38-6 Sub-Modes of Pulse Enable Mode for RX Unit 1305
38-7 Sub-Mode of Software Enable Mode for RX Unit 1306
39-1 SAR ADCs Function Overview 1324

Espressif Systems 34 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
List of Figures GoBack

39-2 Diagram of DIG ADC FSM 1326

39-3 APB_SARADC_SAR_PATT_TAB1_REG and Pattern Table Entry 0 - Entry 3 1327
39-4 APB_SARADC_SAR_PATT_TAB2_REG and Pattern Table Entry 4 - Entry 7 1328
39-5 Pattern Table Entry 1328
39-6 cmd1 configuration 1328
39-7 cmd0 Configuration 1328
39-8 DMA Data Format 1329
39-9 Temperature Sensor Structure 1330

Espressif Systems 35 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1 High-Performance CPU

1.1 Overview
ESP-RISC-V CPU is a 32-bit core based upon RISC-V instruction set architecture (ISA) comprising base integer
(I), multiplication/division (M), atomic (A) and compressed (C) standard extensions. The core has 4-stage,
in-order, scalar pipeline optimized for area, power and performance. CPU core complex has a debug module
(DM), interrupt-controller (INTC), core local interrupts (CLINT) and system bus (SYS BUS) interfaces for
memory and peripheral access.

ESP-RISC-V CPU

INTC IRQ

RV32IMAC
CORE
DM JTAG

IBUS DBUS

SBA
SYS BUS

IRAM DRAM AHB

Figure 1-1. CPU Block Diagram

1.2 Features
• RISC-V RV32IMAC ISA with four-stage pipeline that supports an operating clock frequency up to 160 MHz

• Compatible with RISC-V ISA Manual Volume I: Unprivileged ISA Version 2.2 and RISC-V ISA Manual,
Volume II: Privileged Architecture, Version 1.10

• Zero wait cycle access to on-chip SRAM and Cache for program and data access over IRAM/DRAM
interface

• Branch target buffer (BTB) with static branch prediction

• User (U) mode support along with interrupt delegation

• Interrupt controller with up to 28 external vectored interrupts for both M and U modes with 16
programmable priority and threshold levels

• Core local interrupts (CLINT) dedicated for each privilege mode

Espressif Systems 36 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

• Debug module (DM) compliant with the specification RISC-V External Debug Support Version 0.13 with
external debugger support over an industry-standard JTAG/USB port

• Support for instruction trace

• Debugger with a direct system bus access (SBA) to memory and peripherals

• Hardware trigger compliant to the specification RISC-V External Debug Support Version 0.13 with up to 4
breakpoints/watchpoints

• Physical memory protection (PMP) and attributes (PMA) for up to 16 configurable regions

• 32-bit AHB system bus for peripheral access

• Configurable events for core performance metrics

1.3 Terminology

branch an instruction which conditionally changes the execution flow

delta a change in the program counter that is other than the difference between two
instructions placed consecutively in memory
hart a RISC-V hardware thread
retire the final stage of executing an instruction, when the machine state is updated
trap the transfer of control to a trap handler caused by either an exception or an
interrupt

1.4 Address Map

Below table shows address map of various regions accessible by CPU for instruction, data, system bus
peripheral and debug.

Table 1-2. CPU Address Map

Name Description Starting Address Ending Address Access

IRAM/DRAM Instruction/Data region 0x4000_0000 0x4FFF_FFFF R/W
CPU CPU Sub-system region 0x2000_0000 0x2FFF_FFFF R/W
AHB AHB Peripheral region *default *default R/W

*default: Address not matching any of the specified ranges (IRAM, DRAM, CPU) are accessed using AHB
bus.

1.5 Configuration and Status Registers (CSRs)

1.5.1 Register Summary
Below is a list of CSRs available to the CPU. Except for the custom performance counter CSRs, all the
implemented CSRs follow the standard mapping of bit fields as described in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 1.10. It must be noted that even among the standard CSRs, not all bit
fields have been implemented, limited by the subset of features implemented in the CPU. Refer to the next
section for detailed description of the subset of fields implemented under each of these CSRs.

Espressif Systems 37 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Name Description Address Access

Machine Information CSRs
mvendorid Machine Vendor ID 0xF11 RO
marchid Machine Architecture ID 0xF12 RO
mimpid Machine Implementation ID 0xF13 RO
mhartid Machine Hart ID 0xF14 RO
Machine Trap Setup CSRs
mstatus Machine Mode Status 0x300 R/W
misa ¹ Machine ISA 0x301 R/W
mideleg Machine Interrupt Delegation Register 0x303 R/W
mie Machine Interrupt Enable Register 0x304 R/W
mtvec ² Machine Trap Vector 0x305 R/W
Machine Trap Handling CSRs
mscratch Machine Scratch 0x340 R/W
mepc Machine Trap Program Counter 0x341 R/W
mcause ³ Machine Trap Cause 0x342 R/W
mtval Machine Trap Value 0x343 R/W
mip Machine Interrupt Pending 0x344 R/W
User Trap Setup CSRs
ustatus User Mode Status 0x000 R/W
uie User Interrupt Enable Register 0x004 R/W
utvec User Trap Vector 0x005 R/W
User Trap Handling CSRs
uscratch User Scratch 0x040 R/W
uepc User Trap Program Counter 0x041 R/W
ucause User Trap Cause 0x042 R/W
uip User Interrupt Pending 0x044 R/W
Physical Memory Protection (PMP) CSRs
pmpcfg0 Physical memory protection configuration 0x3A0 R/W
pmpcfg1 Physical memory protection configuration 0x3A1 R/W
pmpcfg2 Physical memory protection configuration 0x3A2 R/W
pmpcfg3 Physical memory protection configuration 0x3A3 R/W
pmpaddr0 Physical memory protection address register 0x3B0 R/W
pmpaddr1 Physical memory protection address register 0x3B1 R/W
....
pmpaddr15 Physical memory protection address register 0x3BF R/W
Trigger Module CSRs (shared with Debug Mode)
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W
tcontrol Global Trigger Control 0x7A5 R/W

¹Although misa is specified as having both read and write access (R/W), its fields are hardwired and thus write has no effect. This is
what would be termed WARL (Write Any Read Legal) in RISC-V terminology
²mtvec only provides configuration for trap handling in vectored mode with the base address aligned to 256 bytes
³External interrupt IDs reflected in mcause include even those IDs which have been reserved by RISC-V standard for core internal sources.

Espressif Systems 38 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Name Description Address Access

Debug Mode CSRs
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
Performance Counter CSRs (Custom) ⁴
mpcer Machine Performance Counter Event 0x7E0 R/W
mpcmr Machine Performance Counter Mode 0x7E1 R/W
mpccr Machine Performance Counter Count 0x7E2 R/W
GPIO Access CSRs (Custom)
cpu_gpio_oen GPIO Output Enable 0x803 R/W
cpu_gpio_in GPIO Input Value 0x804 RO
cpu_gpio_out GPIO Output Value 0x805 R/W
Physical Memory Attributes Checker (PMAC) CSRs
pma_cfg0 Physical memory attribute configuration 0xBC0 R/W
pma_cfg1 Physical memory attribute configuration 0xBC1 R/W
pma_cfg2 Physical memory attribute configuration 0xBC2 R/W
pma_cfg3 Physical memory attribute configuration 0xBC3 R/W
....
pma_cfg15 Physical memory attribute configuration 0xBCF R/W
pma_addr0 Physical memory attribute address register 0xBD0 R/W
pma_addr1 Physical memory attribute address register 0xBD1 R/W
....
pma_addr15 Physical memory attribute address register 0xBDF R/W

Note that if write/set/clear operation is attempted on any of the CSRs which are read-only (RO), as indicated in
the above table, the CPU will generate illegal instruction exception.

1.5.2 Register Description

Register 1.1. mvendorid (0xF11)

ID
OR
ND
VE
M

31 0

0x00000612 Reset

MVENDORID Represents Vendor ID. (RO)

⁴These custom CSRs have been implemented in the address space reserved by RISC-V standard for custom use

Espressif Systems 39 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.2. marchid (0xF12)

ID
CH
AR
M
31 0

0x80000002 Reset

MARCHID Represents Architecture ID. (RO)

Register 1.3. mimpid (0xF13)

D
PI
IM
M
31 0

0x00000002 Reset

MIMPID Represents Implementation ID. (RO)

Register 1.4. mhartid (0xF14)

DI
RT
HA
M

31 0

0x00000000 Reset

MHARTID Represents Hart ID. (RO)

Espressif Systems 40 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.5. mstatus (0x300)

UP ed)

)
ed

ed

ed

ed
rv

rv

rv

rv

rv
se

se

se

se

se
E

IE
PP

PI

IE

E
(re

TW

(re

(re

(re

(re

UI
M

M
31 22 21 20 13 12 11 10 8 7 6 5 4 3 2 1 0

0x000 0 0x00 0x0 0x0 0 0x0 0 0 0x0 0 Reset

UIE Write 1 to enable the global user mode interrupt. (R/W)

MIE Write 1 to enable the global machine mode interrupt. (R/W)

UPIE Write 1 to enable the user previous interrupt (before trap). (R/W)

MPIE Write 1 to enable the machine previous interrupt (before trap). (R/W)

MPP Configures machine previous privilege mode (before trap).

0x0: User mode
0x3: Machine mode
Note: Only the lower bit is writable. Any write to the higher bit is ignored as it is directly tied to
the lower bit.
(R/W)

TW Configures whether to cause illegal instruction exception when WFI (Wait-for-Interrupt) instruc-
tion is executed in U mode.
0: Not cause illegal exception in U mode
1: Cause illegal instruction exception
(R/W)

Espressif Systems 41 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.6. misa (0x301)

)
ed
rv
se
XL

(re
M

M
W

O
U

G
N

C
H

B
Z

P
R
V

A
T
Y

E
F
X

J
L

I
31 30 29 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x1 0x0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 Reset

MXL Machine XLEN = 1 (32-bit). (RO)

Z Reserved = 0. (RO)

Y Reserved = 0. (RO)

X Non-standard extensions present = 0. (RO)

W Reserved = 0. (RO)

V Reserved = 0. (RO)

U User mode implemented = 1. (RO)

T Reserved = 0. (RO)

S Supervisor mode implemented = 0. (RO)

R Reserved = 0. (RO)

Q Quad-precision floating-point extension = 0. (RO)

P Reserved = 0. (RO)

O Reserved = 0. (RO)

N User-level interrupts supported = 0. (RO)

M Integer Multiply/Divide extension = 1. (RO)

L Reserved = 0. (RO)

K Reserved = 0. (RO)

J Reserved = 0. (RO)

I RV32I base ISA = 1. (RO)

H Hypervisor extension = 0. (RO)

G Additional standard extensions present = 0. (RO)

F Single-precision floating-point extension = 0. (RO)

E RV32E base ISA = 0. (RO)

D Double-precision floating-point extension = 0. (RO)

C Compressed Extension = 1. (RO)

B Reserved = 0. (RO)

A Atomic Extension = 1. (RO)

Espressif Systems 42 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.7. mideleg (0x303)

EG
EL
ID
M
31 0

0x00000111 Reset

MIDELEG Configures the U mode delegation state for each interrupt ID. Below interrupts are dele-
gated to U mode by default:
Bit 0: User software interrupt (CLINT)
Bit 4: User timer interrupt (CLINT)
Bit 8: User external interrupt
The default delegation can be modified at run-time if required.
(R/W)

Register 1.8. mie (0x304)

]

5]
:8

US :1]
31

6:

2
E[

E[

E[
E
E

IE
IE
XI

XI

XI
SI
TI

UT
M

M
M
M
31 8 7 6 5 4 3 2 1 0

0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset

USIE Write 1 to enable the user software interrupt. (R/W)

MSIE Write 1 to enable the machine software interrupt. (R/W)

UTIE Write 1 to enable the user timer interrupt. (R/W)

MTIE Write 1 to enable the machine timer interrupt. (R/W)

MXIE Write 1 to enable the 28 external interrupts. (R/W)

Register 1.9. mtvec (0x305)

)
ed
rv

E
se
SE

OD
(re
BA

31 8 7 2 1 0

0x000000 0x00 0x1 Reset

MODE Represents whether machine mode interrupts are vectored. Only vectored mode 0x1 is
available. (RO)

BASE Configures the higher 24 bits of trap vector base address aligned to 256 bytes. (R/W)

Espressif Systems 43 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.10. mscratch (0x340)

H
TC
RA
SC
M
31 0

0x00000000 Reset

MSCRATCH Configures machine scratch information for custom use. (R/W)

Register 1.11. mepc (0x341)

C
EP
M
31 0

0x00000000 Reset

MEPC Configures the machine trap/exception program counter. This is automatically updated with
address of the instruction which was about to be executed while CPU encountered the most
recent trap. (R/W)

Espressif Systems 44 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.12. mcause (0x342)

de
Co
g
la

)
F

n
ed

io
pt

rv

pt
rru

se

ce
te

(re

Ex
In

31 30 5 4 0

0 0x0000000 0x00 Reset

Exception Code This field is automatically updated with unique ID of the most recent exception or
interrupt due to which CPU entered trap. Possible exception IDs are:
0x1: PMP instruction access fault
0x2: Illegal instruction
0x3: Hardware breakpoint/watchpoint or EBREAK
0x5: PMP load access fault
0x6: Misaligned store address or AMO address
0x7: PMP store access or AMO access fault
0x8: ECALL from U mode
0xb: ECALL from M mode
Other values: reserved
Note: Exception ID 0x0 (instruction access misaligned) is not present because CPU always
masks the lowest bit of the address during instruction fetch.
(R/W)

Interrupt Flag This flag is automatically updated when CPU enters trap.
If this is found to be set, indicates that the latest trap occurred due to an interrupt. For exceptions
it remains unset.
Note: The interrupt controller is using up IDs in range 1-2, 5-6 and 8-31 for all external interrupt
sources. This is different from the RISC-V standard which has reserved IDs in range 0-15 for core
local interrupts only. Although local interrupt sources (CLINT) do use the reserved IDs 0, 3, 4
and 7.
(R/W)

Espressif Systems 45 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.13. mtval (0x343)

AL
TV
M
31 0

0x00000000 Reset

MTVAL Configures machine trap value. This is automatically updated with an exception dependent
data which may be useful for handling that exception.
Data is to be interpreted depending upon exception IDs:
0x1: Faulting virtual address of instruction
0x2: Faulting instruction opcode
0x5: Faulting data address of load operation
0x7: Faulting data address of store operation
Note: The value of this register is not valid for other exception IDs and interrupts.
(R/W)

Espressif Systems 46 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.14. mip (0x344)

UT :5]
:8

US :1]
31

2
P[

P[

P[
P
P

IP
IP
XI

XI

XI
SI
TI
M

M
M
M
31 8 7 6 5 4 3 2 1 0

0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset

USIP Configures the pending status of the user software interrupt.

0: Not pending
1: Pending
(R/W)

MSIP Configures the pending status of the machine software interrupt.

0: Not pending
1: Pending
(R/W)

UTIP Configures the pending status of the user timer interrupt.

0: Not pending
1: Pending
(R/W)

MTIP Configures the pending status of the machine timer interrupt.

0: Not pending
1: Pending
(R/W)

MXIP Configures the pending status of the 28 external interrupts.

0: Not pending
1: Pending
(R/W)

Register 1.15. ustatus (0x300)

)

)
ed

ed
rv

rv
se

se
IE

E
(re

(re
UP

UI

31 5 4 3 1 0

0x0000000 0 0x0 0 Reset

UIE Write 1 to enable the global user mode interrupt. (R/W)

UPIE Write 1 to enable the user previous interrupt (before trap). (R/W)

Espressif Systems 47 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.16. uie (0x004)

UX ed)

UX ed)
]

]
:8

US 1]
:5
31

:
rv

rv
[6

[2
E[

se

se
IE

IE

IE
IE
I

(re

(re
UX

UT
31 8 7 6 5 4 3 2 1 0

0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset

USIE Write 1 to enable the user software interrupt. (R/W)

UTIE Write 1 to enable the user timer interrupt. (R/W)

UXIE Write 1 to enable the 28 external interrupts delegated to U mode. (R/W)

Register 1.17. utvec (0x005)

)
ed
rv

E
se
SE

OD
(re
BA

M
31 8 7 2 1 0

0x000000 0x00 0x1 Reset

MODE Represents if user mode interrupts are vectored. Only vectored mode 0x1 is available. (RO)

BASE Configures the higher 24 bits of trap vector base address aligned to 256 bytes. (R/W)

Register 1.18. uscratch (0x040)

H
TC
RA
C
US

31 0

0x00000000 Reset

USCRATCH Configures user scratch information for custom use. (R/W)

Register 1.19. uepc (0x041)

PC
UE

31 0

0x00000000 Reset

UEPC Configures the user trap program counter. This is automatically updated with address of the
instruction which was about to be executed in User mode while CPU encountered the most
recent user mode interrupt. (R/W)

Espressif Systems 48 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.20. ucause (0x042)

de
Co
g
la

)
F

n
ed

io
pt

rv

pt
rru

se

ce
te

(re

Ex
In

31 30 5 4 0

0 0x0000000 0x00 Reset

Interrupt ID This field is automatically updated with the unique ID of the most recent user mode
interrupt due to which CPU entered trap. (R/W)

Interrupt Flag This flag would always be set because CPU can only enter trap due to user mode
interrupts as exception delegation is unsupported. (R/W)

Register 1.21. uip (0x044)

UX ed)

UX ed)
]
1:8

:1]
:4
rv

rv

[2
[3

[5
se

se
IP

IP

IP

IP
IP
(re

(re
UX

US
UT
31 8 7 6 5 4 3 2 1 0

0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset

USIP Configures the pending status of the user software interrupt.

0: Not pending
1: Pending
(R/W)

UTIP Configures the pending status of the user timer interrupt.

0: Not pending
1: Pending
(R/W)

UXIP Configures the pending status of the 28 external interrupts delegated to user mode.
0: Not pending
1: Pending
(R/W)

Espressif Systems 49 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.22. mpcer (0x7E0)

P H KEN

IN AZ ARD
JM NC _TA

LO RE ON

RD
BR NC P
)

RA M

O C

_H Z
ed

A H

ST A
(B _CO

ST _UN

LD _HA
rv

E
se

ID D

CL
ST

P
LE
A

JM
(re

CY
IN
31 11 10 9 8 7 6 5 4 3 2 1 0

0x000 0 0 0 0 0 0 0 0 0 0 0 Reset

INST_COMP Count Compressed Instructions. (R/W)

BRANCH_TAKEN Count Branches Taken. (R/W)

BRANCH Count Branches. (R/W)

JMP_UNCOND Count Unconditional Jumps. (R/W)

STORE Count Stores. (R/W)

LOAD Count Loads. (R/W)

IDLE Count IDLE Cycles. (R/W)

JMP_HAZARD Count Jump Hazards. (R/W)

LD_HAZARD Count Load Hazards. (R/W)

INST Count Instructions. (R/W)

CYCLE Count Clock Cycles. Cycle count does not increment during WFI mode.
Note: Each bit selects a specific event for counter to increment. If more than one event is
selected and occurs simultaneously, then counter increments by one only.
(R/W)

Register 1.23. mpcmr (0x7E1) T_ T

EN
UN SA
)
ed

CO NT_
rv
se

U
CO
(re

31 2 1 0

0 1 1 Reset

COUNT_SAT Configures counter saturation.

0: Overflow on maximum value
1: Halt on maximum value
(R/W)

COUNT_EN Configures whether to enable the counter.

0: Disable
1: Enable
(R/W)

Espressif Systems 50 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.24. mpccr (0x7E2)

CR
PC
M
31 0

0x00000000 Reset

MPCCR Represents the machine performance counter value. (R/W)

Espressif Systems 51 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.6 Interrupt Controller

1.6.1 Features
The interrupt controller allows capturing, masking and dynamic prioritization of interrupt sources routed from
peripherals to the RISC-V CPU. It supports:

• Up to 28 external asynchronous interrupts and 4 core local interrupt sources (CLINT) with unique IDs
(0-31)

• Configurable via read/write to memory mapped registers

• Delegable to user mode

• 15 levels of priority, programmable for each interrupt

• Support for both level and edge type interrupt sources

• Programmable global threshold for masking interrupts with lower priority

• Interrupts IDs mapped to trap-vector address offsets

For the complete list of interrupt registers and detailed configuration information, please refer to Chapter 10
Interrupt Matrix (INTMTX) > Section 10.4.2.

1.6.2 Functional Description

Each interrupt ID has 6 properties associated with it. These properties can be configured for the 28 external
interrupts (1-2, 5-6, 8-31), but are static (except mode) for the 4 local CLINT interrupts (0, 3, 4, 7). These
properties are as follows:

1. Mode (M/U):

• Determines the mode in which an interrupt is to be serviced.

• Programmed by setting or clearing the corresponding bit in mideleg CSR.

• If the bit is cleared for an interrupt in mideleg CSR, then that interrupt will be captured in M mode.

• If the bit is set for an interrupt in mideleg CSR, then it will be delegated to U mode.

2. Enable State (0-1):

• Determines if an interrupt is enabled to be captured and serviced by the CPU.

• Programmed by writing the corresponding bit in INTPRI_CORE0_CPU_INT_ENABLE_REG.

• Local CLINT interrupts have the corresponding bits reserved in the memory mapped registers thus
they are always enabled at the INTC level.

• An M mode interrupt (external or local) further needs to be unmasked at core level by setting the
corresponding bit in mie CSR.

• A U mode interrupt (external or local) further needs to be unmasked at core level by setting the
corresponding bits in uie CSR.

3. Type (0-1):

• Enables latching the state of an interrupt signal on its rising edge.

Espressif Systems 52 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

• Programmed by writing the corresponding bit in INTPRI_CORE0_CPU_INT_TYPE_REG.

• An interrupt for which type is kept 0 is referred as a ’level’ type interrupt.

• An interrupt for which type is set to 1 is referred as an ’edge’ type interrupt.

• Local CLINT interrupts are always ’level’ type and thus have the corresponding bits reserved in the
above register.

4. Priority (0-15):

• Determines which interrupt, among multiple pending interrupts, the CPU will service first.

• Programmed by writing to the INTPRI_CORE0_CPU_INT_PRI_n_REG for an external interrupt with

particular interrupt ID n.

• Enabled external interrupts with priorities less than the threshold value in
INTPRI_CORE0_CPU_INT_THRESH_REG are masked.

• Priority levels increase from 0 (lowest) to 15 (highest).

• Interrupts with same priority are statically prioritized by their IDs, lowest ID having highest priority.

• Local CLINT interrupts have static priorities associated with them, and thus have the corresponding
priority registers to be reserved.

• Local CLINT interrupts cannot be masked using the threshold values for either modes.

5. Pending State (0-1):

• Reflects the captured state of an enabled and unmasked external interrupt signal.

• For each external interrupt ID the corresponding bit in read-only

INTPRI_CORE0_CPU_INT_EIP_STATUS_REG gives its pending state.

• For each interrupt ID (local or external), the corresponding bit in the mip CSR for M mode interrupts
or uip CSR for U mode interrupts, also gives its pending state.

• A pending interrupt will cause CPU to enter trap if no other pending interrupt has higher priority.

• A pending interrupt is said to be ’claimed’ if it preempts the CPU and causes it to jump to the
corresponding trap vector address.

• All pending interrupts which are yet to be serviced are termed as ’unclaimed’.

6. Clear State (0-1):

• Toggling this will clear the pending state of claimed edge-type interrupts only.

• Toggled by first setting and then clearing the corresponding bit in

INTPRI_CORE0_CPU_INT_CLEAR_REG.

• Pending state of a level type interrupt is unaffected by this and must be cleared from source.

• Pending state of an unclaimed edge type interrupt can be flushed, if required, by first clearing the
corresponding bit in INTPRI_CORE0_CPU_INT_ENABLE_REG and then toggling same bit in
INTPRI_CORE0_CPU_INT_CLEAR_REG.

For detailed description of the core local interrupt sources, please refer to Section 1.7.

When CPU services a pending M/U mode interrupt, it:

Espressif Systems 53 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

• saves the address of the current un-executed instruction in mepc/uepc for resuming execution later.

• updates the value of mcause/ucause with the ID of the interrupt being serviced.

• copies the state of MIE/UIE into MPIE/UPIE, and subsequently clears MIE/UIE, thereby disabling
interrupts globally.

• enters trap by jumping to a word-aligned offset of the address stored in mtvec/utvec.

The word aligned trap address for an M mode interrupt with a certain ID = i can be calculated as (mtvec + 4i).
Similarly, the word aligned trap address for a U mode interrupt can be calculated as (utvec + 4i).

After jumping to the trap vector for the corresponding mode, the execution flow is dependent on software
implementation, although it can be presumed that the interrupt will get handled (and cleared) in some interrupt
service routine (ISR) and later the normal execution will resume once the CPU encounters MRET/URET
instruction for that mode.

Upon execution of MRET/URET instruction, the CPU:

• copies the state of MPIE/UPIE back into MIE/UIE, and subsequently clears MPIE/UPIE. This means that
if previously MPIE/UPIE was set, then, after MRET/URET, MIE/UIE will be set, thereby enabling interrupts
globally.

• jumps to the address stored in mepc/uepc and resumes execution.

It is possible to perform software assisted nesting of interrupts inside an ISR as explained in Section
1.6.3.

The below listed points outline the functional behavior of the controller:

• Only if an interrupt has priority higher or equal to the value in the threshold register, will it be reflected in
INTPRI_CORE0_CPU_INT_EIP_STATUS_REG.

• If an interrupt is visible in INTPRI_CORE0_CPU_INT_EIP_STATUS_REG and has yet to be serviced, then

it’s possible to mask it (and thereby prevent the CPU from servicing it) by either lowering the value of its
priority or increasing the global threshold.

• If an interrupt, visible in INTPRI_CORE0_CPU_INT_EIP_STATUS_REG, is to be flushed (and prevented

from being serviced at all), then it must be disabled (and cleared if it is of edge type).

1.6.3 Suggested Operation

1.6.3.1 Latency Aspects

There is latency involved while configuring the Interrupt Controller.

In steady state operation, the Interrupt Controller has a fixed latency of 4 cycles. Steady state means that no
changes have been made to the Interrupt Controller registers recently. This implies that any interrupt that is
asserted to the controller will take exactly 4 cycles before the CPU starts processing the interrupt. This further
implies that CPU may execute up to 5 instructions before the preemption happens.

Whenever any of its registers are modified, the Interrupt Controller enters into transient state, which may take
up to 4 cycles for it to settle down into steady state again. During this transient state, the ordering of interrupts
may not be predictable, and therefore, a few safety measures need to be taken in software to avoid any
synchronization issues.

Espressif Systems 54 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Also, it must be noted that the Interrupt Controller configuration registers lie in the APB address range, hence
any R/W access to these registers may take multiple cycles to complete.

In consideration of above mentioned characteristics, users are advised to follow the sequence described
below, whenever modifying any of the Interrupt Controller registers:

1. save the state of MIE and clear MIE to 0

2. read-modify-write one or more Interrupt Controller registers

3. execute FENCE instruction to wait for any pending write operations to complete

4. finally, restore the state of MIE

Due to its critical nature, it is recommended to disable interrupts globally (MIE=0) beforehand, whenever
configuring interrupt controller registers, and then restore MIE right after, as shown in the sequence
above.

After execution of the sequence above, the Interrupt Controller will resume operation in steady state.

1.6.3.2 Configuration Procedure

By default, interrupts are disabled globally, since the reset value of MIE bit in mstatus is 0. Software must set
MIE=1 after initialization of the interrupt stack (including setting mtvec to the interrupt vector address) is
done.

The threshold value for external interrupts in INTPRI_CORE0_CPU_INT_THRESH_REG is 0 by default. For

priority based masking of interrupts this could be initialized to 1 after CPU comes out of reset. That way all
interrupt sources which have default 0 priority are masked.

During normal execution, if an external interrupt n is to be enabled, the below sequence may be
followed:

1. save the state of MIE and clear MIE to 0

2. depending upon the type of the interrupt (edge/level), set/unset the nth bit of
INTPRI_CORE0_CPU_INT_TYPE_REG

3. set the priority by writing a value to INTPRI_CORE0_CPU_INT_PRI_n_REG in range 1 (lowest) to 15

(highest)

4. set the nth bit of INTPRI_CORE0_CPU_INT_ENABLE_REG

5. execute FENCE instruction

6. restore the state of MIE

When one or more interrupts become pending, the CPU acknowledges (claims) the interrupt with the highest
priority and jumps to the trap vector address corresponding to the interrupt’s ID. Software implementation may
read mcause to infer the type of trap (mcause(31) is 1 for interrupts and 0 for exceptions) and then the ID of
the interrupt (mcause(4-0) gives ID of interrupt or exception). This inference may not be necessary if each
entry in the trap vector are jump instructions to different trap handlers. Ultimately, the trap handler(s) will
redirect execution to the appropriate ISR for this interrupt.

Upon entering into an ISR, software must toggle the nth bit of INTPRI_CORE0_CPU_INT_CLEAR_REG if the
interrupt is of edge type, or clear the source of the interrupt if it is of level type.

Espressif Systems 55 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Software may also update the value of INTPRI_CORE0_CPU_INT_THRESH_REG and program MIE=1 for allowing
higher priority interrupts to preempt the current ISR (nesting), however, before doing so, all the state CSRs
must be saved (mepc, mstatus, mcause, etc.) since they will get overwritten due to occurrence of such an
interrupt. Later, when exiting the ISR, the values of these CSRs must be restored.

Finally, after the execution returns from the ISR back to the trap handler, MRET instruction is used to resume
normal execution.

Later, if the n interrupt is no longer needed and needs to be disabled, the following sequence may be
followed:

1. save the state of MIE and clear MIE to 0

2. check if the interrupt is pending in INTPRI_CORE0_CPU_INT_EIP_STATUS_REG

3. set/unset the nth bit of INTPRI_CORE0_CPU_INT_ENABLE_REG

4. if the interrupt is of edge type and was found to be pending in step 2 above, nth bit of
INTPRI_CORE0_CPU_INT_CLEAR_REG must be toggled, so that its pending status gets flushed

5. execute FENCE instruction

6. restore the state of MIE

Above is only a suggested scheme of operation. Actual software implementation may vary.

1.6.4 Registers
For the complete list of interrupt registers and configuration information, please refer to Section 10.4.2 and
Section 10.5.2 respectively.

Espressif Systems 56 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.7 Core Local Interrupts (CLINT)

1.7.1 Overview
The CPU supports 4 local level-type interrupt sources with static priorities as shown below.

Table 1-4. Core Local Interrupt (CLINT) Sources

ID Description Priority
0 U mode software interrupt 1
3 M mode software interrupt 3
4 U mode timer interrupt 0
7 M mode timer interrupt 2

These interrupt sources have reserved IDs and fixed priorities which cannot be masked via the interrupt
controller threshold registers for either modes.

Two of these interrupts (0 and 4) are by-default delegated to U mode as per the reset values of corresponding
bits in mideleg CSR.

It must be noted that regardless of the fixed priority of CLINT interrupts, pending external interrupt sources
always have higher priority over CLINT sources.

1.7.2 Features
• 4 local level-type interrupt sources with static priorities and IDs

• Memory mapped configuration and status registers

• Support for interrupts in both M and U modes

• 64-bit timer with interrupt with overflow flag

• Software interrupts

1.7.3 Software Interrupt

M and U mode software interrupt sources are controlled by setting or clearing the memory mapped registers
MSIP and USIP, respectively.

The MSIE/USIE bit must be set in mie/uie CSR for enabling the interrupt at core level for a particular
mode.

Pending state of this interrupt can be checked for either mode by reading the corresponding bit MSIP/USIP in
mip/uip CSR.

Note that by default U mode software interrupt with ID 0 has the corresponding bit set in mideleg CSR. This bit
can be toggled for using the interrupt in M mode instead. Similarly the bit corresponding to M mode software
interrupt can be set for using it in U mode.

1.7.4 Timer Counter and Interrupt

The CPU provides a local memory-mapped 64-bit wide M mode timer counter register MTIME which has both
read/write access. The timer counter can be enabled by setting the MTCE bit in MTIMECTL.

Espressif Systems 57 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

A read-only memory mapped UTIME is also provided for reading the timer counter from U mode, although it
always reflects the same value as in the corresponding M mode counter MTIME register.

Timer interrupt for M/U mode is enabled by setting the MTIE/UTIE bit in MTIMECTL/UTIMECTL. Also, the
MTIE/UTIE bit must be set in mie CSR for enabling the interrupt at core level for a particular mode.

Interrupt for M/U mode is asserted when the 64b timer value exceeds the 64b timer-compare value
programmed in MTIMECMP/UTIMECMP.

Pending state of M/U mode timer interrupt is reflected as the read-only MTIP/UTIP bit in
MTIMECTL/UTIMECTL.

For de-asserting the pending timer interrupt in M/U mode, either the MTIE/UTIE bit has to be cleared or the
value of the MTIMECMP/UTIMECMP register needs to be updated.

Pending state of this interrupt can be checked at core level for either mode by reading the corresponding bit
MTIP/UTIP in mip/uip.

Upon overflow of the 64b timer counter, the MTOF/UTOF bit in MTIMECTL/UTIMECTL gets set. It can be
cleared after appropriate handling of the overflow situation.

Note that by default U mode timer interrupt with ID 4 has the corresponding bit set in mideleg CSR. This bit
can be toggled for using the interrupt in M mode instead. Similarly the bit corresponding to M mode timer
interrupt can be set for using it in U mode.

1.7.5 Register Summary

The addresses in this section are relative to CPU sub-system base address provided in Figure 5-1 in Chapter 5
System and Memory.

Name Description Address Access

MSIP Core local machine software interrupt pending register 0x1800 R/W
MTIMECTL Core local machine timer interrupt control/status regis- 0x1804 R/W
ter
MTIME 64b core local timer counter value 0x1808 R/W
MTIMECMP 64b core local machine timer compare value 0x1810 R/W
USIP Core local user software interrupt pending register 0x1C00 R/W
UTIMECTL Core local user timer interrupt control/status register 0x1C04 R/W
UTIME Read-only 64b core local timer counter value 0x1C08 RO
UTIMECMP 64b core local user timer compare value 0x1C10 R/W

1.7.6 Register Description

The addresses in this section are relative to CPU subsystem base address provided in Figure 5-1 in Chapter 5
System and Memory.

Espressif Systems 58 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.25. MSIP (0x1800)

d)
rve
se

P
SI
(re

M
31 1 0

0x00000000 0 Reset

MSIP Configures the pending status of the machine software interrupt.

0: Not pending
1: Pending
(R/W)

Register 1.26. MTIMECTL (0x1804)

)
ed
rv

M F

E
se

P
E
TO

TC
TI
TI
(re

M
M
31 4 3 2 1 0

0x0000000 0 0 0 0 Reset

MTCE Configures whether to enable the CLINT timer counter.

0: Not enable
1: Enable
(R/W)

MTIE Write 1 to enable the machine timer interrupt. (R/W)

MTIP Represents the pending status of the machine timer interrupt.

0: Not pending
1: Pending
(RO)

MTOF Configures whether the machine timer overflows.

0: Not overflow
1: Overflow
(R/W)

Espressif Systems 59 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.27. MTIME (0x1808)

]
:32
63
E[
M
TI
M
63 32

0 Reset

]
:0
31
E[
M
TI
M
31 0

0 Reset

MTIME Configures the 64-bit CLINT timer counter value. (R/W)

Register 1.28. MTIMECMP (0x1810)

]
32
3:
6
P[
M
EC
M
TI
M

63 32

0 Reset
]
:0
31
P[
M
EC
M
TI
M

31 0

0 Reset

MTIMECMP Configures the 64-bit machine timer compare value. (R/W)

Register 1.29. USIP (0x1C00)

)
ed
rv
se

I P
(re

US

31 1 0

0x00000000 0 Reset

USIP Configures the pending status of the user software interrupt.

0: Not pending
1: Pending
(R/W)

Espressif Systems 60 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.30. UTIMECTL (0x1C04)

)
ed

ed
rv

rv
se

se
UT F
IP
IE
O
(re

(re
UT

UT
31 4 3 2 1 0

0x0000000 0 0 0 0 Reset

UTIE Write 1 to enable the user timer interrupt. (R/W)

UTIP Represents the pending status of the user timer interrupt. (RO)

UTOF Configures whether the user timer overflows.

0: Not overflow
1: Overflow
(R/W)

Register 1.31. UTIME (0x1C08)

]
32
6 3:
E[
IM
UT

63 32

0 Reset
]
:0
31
E[
I M
UT

31 0

0 Reset

UTIME Represents the read-only 64-bit CLINT timer counter value. (RO)

Register 1.32. UTIMECMP (0x1C10)

]
32
6 3:
P[
M
EC
IM
UT

63 32

0 Reset
]
:0
31
P[
M
EC
I M
UT

31 0

0 Reset

UTIMECMP Configures the 64-bit user timer compare value. (R/W)

Espressif Systems 61 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.8 Physical Memory Protection

1.8.1 Overview
The CPU core includes a Physical Memory Protection (PMP) unit fully compliant to RISC-V Instruction Set
Manual, Volume II: Privileged Architecture, Version 1.10, which can be used by software to set memory
access privileges (read, write and execute permissions) for required memory regions. In addition to standard
PMP checks, CPU core also implements custom Physical Memory Attributes (PMA) checkers to provide
additional permission checks based on pre-defined attributes.

1.8.2 Features
The PMP unit can be used to restrict access to physical memory. It supports 16 regions and a minimum
granularity of 4 bytes. Maximum supported NAPOT range is 4 GB.

1.8.3 Functional Description

Software can program the PMP unit’s configuration and address registers in order to contain faults and support
secure execution. PMP CSRs can only be programmed in machine-mode. Once the PMP unit is enabled by
configuring PMP CSRs, write, read and execute permission checks are applied to all the accesses in
user-mode as per programmed values of enabled 16 pmpcfgX and pmpaddrX registers (refer to the Register
Summary).

By default, PMP grants permission to all accesses in machine-mode and revokes permission of all access in
user-mode. This implies that it is mandatory to program the address range and valid permissions in pmpcfg
and pmpaddr registers (refer to the Register Summary) for any valid access to pass through in user-mode.
However, it is not required for machine-mode as PMP permits all accesses to go through by default. In cases
where PMP checks are also required in machine-mode, software can set the lock bit of required PMP entry to
enable permission checks on it. Once the lock bit is set, it can only be cleared through CPU reset.

When any instruction is being fetched from a memory region without execute permissions, an exception is
generated at processor level and exception cause is set as instruction access fault in mcause CSR. Similarly,
any load/store access without valid read/write permissions, will result in an exception generation with mcause
updated as load access and store access fault respectively. In case of load/store access faults, violating
address is captured in mtval CSR.

Espressif Systems 62 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.8.4 Register Summary

Below is a list of PMP CSRs supported by the CPU. These are only accessible from machine mode.

Name Description Address Access

pmpcfg0 Physical memory protection configuration. 0x3A0 R/W
pmpcfg1 Physical memory protection configuration. 0x3A1 R/W
pmpcfg2 Physical memory protection configuration. 0x3A2 R/W
pmpcfg3 Physical memory protection configuration. 0x3A3 R/W
pmpaddr0 Physical memory protection address register. 0x3B0 R/W
pmpaddr1 Physical memory protection address register. 0x3B1 R/W
pmpaddr2 Physical memory protection address register. 0x3B2 R/W
pmpaddr3 Physical memory protection address register. 0x3B3 R/W
pmpaddr4 Physical memory protection address register. 0x3B4 R/W
pmpaddr5 Physical memory protection address register. 0x3B5 R/W
pmpaddr6 Physical memory protection address register. 0x3B6 R/W
pmpaddr7 Physical memory protection address register. 0x3B7 R/W
pmpaddr8 Physical memory protection address register. 0x3B8 R/W
pmpaddr9 Physical memory protection address register. 0x3B9 R/W
pmpaddr10 Physical memory protection address register. 0x3BA R/W
pmpaddr11 Physical memory protection address register. 0x3BB R/W
pmpaddr12 Physical memory protection address register. 0x3BC R/W
pmpaddr13 Physical memory protection address register. 0x3BD R/W
pmpaddr14 Physical memory protection address register. 0x3BE R/W
pmpaddr15 Physical memory protection address register. 0x3BF R/W

1.8.5 Register Description

PMP unit implements all pmpcfg0-3 and pmpaddr0-15 CSRs as defined in RISC-V Instruction Set Manual
Volume II: Privileged Architecture, Version 1.10.

Espressif Systems 63 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.9 Physical Memory Attribute (PMA) Checker

1.9.1 Overview
CPU core also implements custom Physical Memory Attributes Checker (PMAC) to provide additional
permission checks based on pre-defined memory type configured through custom CSRs.

1.9.2 Features
PMAC supports below features:

• Configurable memory type for defined memory regions

• Configurable attribute for defined memory regions

1.9.3 Functional Description

Software can program the PMAC unit’s configuration and address registers in order to avoid faults due to
access to invalid memory regions. PMAC CSRs can only be programmed in machine-mode. Once enabled,
write, read and execute permission checks are applied to all the accesses irrespective of privilege mode as
per programmed values of enabled 16 pma_cfgX and pma_addrX registers (refer to the Register Summary).
Access to entries marked as invalid memory types will result in fetch fault or load/store fault exception, as the
case may be.

Exception generation and handling for PMAC related faults will be handled in similar way to PMP checks. When
any instruction is being fetched from a memory region configured as null or invalid memory region, an
exception is generated at processor level and exception cause is set as instruction access fault in mcause
CSR. Similarly, any load/store access to null or invalid memory region, will result in an exception generation
with mcause updated as load access and store access fault respectively. In case of load/store access faults,
violating address is captured in mtval CSR. For the PMAC entries configured as valid memory, the handling is
same as for PMP checks.

A lock bit per entry is also provided in case software wants to disable programming of PMAC registers. Once
the lock bit in any pma_cfgX register is set, respective pma_cfgX and pma_addrX registers can not be
programmed further, unless a CPU reset cycle is applied.

A 4-bit field in PMAC CSRs is also provided to define attributes for memory regions. These bits are not used
internally by CPU core for any purpose. Based on address match, these attributes are provided on load/store
interface as side-band signals and are used by cache controller block for its internal operation.

Espressif Systems 64 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.9.4 Register Summary

Below is a list of PMA CSRs supported by the CPU. These are only accessible from machine-mode:

Name Description Address Access

pma_cfg0 Physical Memory Attribute configuration 0xBC0 R/W
pma_cfg1 Physical Memory Attribute configuration 0xBC1 R/W
pma_cfg2 Physical Memory Attribute configuration 0xBC2 R/W
pma_cfg3 Physical Memory Attribute configuration 0xBC3 R/W
pma_cfg4 Physical Memory Attribute configuration 0xBC4 R/W
pma_cfg5 Physical Memory Attribute configuration 0xBC5 R/W
pma_cfg6 Physical Memory Attribute configuration 0xBC6 R/W
pma_cfg7 Physical Memory Attribute configuration 0xBC7 R/W
pma_cfg8 Physical Memory Attribute configuration 0xBC8 R/W
pma_cfg9 Physical Memory Attribute configuration 0xBC9 R/W
pma_cfg10 Physical Memory Attribute configuration 0xBCA R/W
pma_cfg11 Physical Memory Attribute configuration 0xBCB R/W
pma_cfg12 Physical Memory Attribute configuration 0xBCC R/W
pma_cfg13 Physical Memory Attribute configuration 0xBCD R/W
pma_cfg14 Physical Memory Attribute configuration 0xBCE R/W
pma_cfg15 Physical Memory Attribute configuration 0xBCF R/W
pma_addr0 Physical Memory Attribute address register 0xBD0 R/W
pma_addr1 Physical Memory Attribute address register 0xBD1 R/W
pma_addr2 Physical Memory Attribute address register 0xBD2 R/W
pma_addr3 Physical Memory Attribute address register 0xBD3 R/W
pma_addr4 Physical Memory Attribute address register 0xBD4 R/W
pma_addr5 Physical Memory Attribute address register 0xBD5 R/W
pma_addr6 Physical Memory Attribute address register 0xBD6 R/W
pma_addr7 Physical Memory Attribute address register 0xBD7 R/W
pma_addr8 Physical Memory Attribute address register 0xBD8 R/W
pma_addr9 Physical Memory Attribute address register 0xBD9 R/W
pma_addr10 Physical Memory Attribute address register 0xBDA R/W
pma_addr11 Physical Memory Attribute address register 0xBDB R/W
pma_addr12 Physical Memory Attribute address register 0xBDC R/W
pma_addr13 Physical Memory Attribute address register 0xBDD R/W
pma_addr14 Physical Memory Attribute address register 0xBDE R/W
pma_addr15 Physical Memory Attribute address register 0xBDF R/W

Espressif Systems 65 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.9.5 Register Description

Register 1.33. pma_cfgX (0xBC0-0xBCF)

TE

se E
ed

ed

PE d
U

re UT
TY rve
IB

EX E
rv

rv
re K

W D

EC
T
TR
se

se
C

A
RI
LO

RE
AT

re
A

31 30 29 28 27 24 23 5 4 3 2 1 0

2 0 0 0 0 0 0 0 0 0 Reset

A Configures address type. The functionality is the same as pmpcfg register’s A field. (R/W)
0x0: OFF
0x1: TOR
0x2: NA4
0x3: NAPOT
LOCK Configures whether to lock the corresponding pma_cfgX and pma_addrX. (R/W)
0: Not locked
1: Locked. The write permission to the corresponding pma_cfgX and pma_addrX is revoked.
It can only be unlocked by core reset.

ATTRIBUTE Configures the values to be driven on DRAM attribute ports. (R/W)

READ Configures read-permission for the corresponding region.

0: Read not allowed
1: Read allowed
(R/W)

WRITE Configures write-permission for the corresponding region.

0: Write not allowed
1: Write allowed
(R/W)

EXECUTE Configures execute-permission for the corresponding region.

0: Execution not allowed
1: Execution allowed
(R/W)

TYPE Configures region type. (R/W)

0x0: Invalid memory region (RWX access will be treated as 0, even if programmed to 1)
0x1: Valid memory region (Programmed RWX access will be applicable)

Register 1.34. pma_addrX (0xBD0-0xBDF)

DR
AD

31 0

0 Reset

ADDR Configures address. The functionality is same as pmpaddr register. (R/W)

Espressif Systems 66 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.10 Debug
1.10.1 Overview
This section describes how to debug software running on HP and LP CPU cores. Debug support is provided
through standard JTAG pins and complies to RISC-V External Debug Support Specification Version 0.13.

Figure 1-2 below shows the main components of External Debug Support.

Figure 1-2. Debug System Overview

The user interacts with the Debug Host (e.g. laptop), which is running a debugger (e.g. gdb). The debugger
communicates with a Debug Translator (e.g. OpenOCD, which may include a hardware driver) to communicate
with Debug Transport Hardware (e.g. ESP-Prog adapter). The Debug Transport Hardware connects the Debug
Host to the ESP-RISC-V Core’s Debug Transport Module (DTM) through standard JTAG interface. The DTM
provides access to the Debug Module (DM) using the Debug Module Interface (DMI).

The DM allows the debugger to halt selected cores. Abstract commands provide access to GPRs (general
purpose registers). The Program Buffer allows the debugger to execute arbitrary code on the core, which

Espressif Systems 67 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

allows access to additional CPU core state. Alternatively, additional abstract commands can provide access to
additional CPU core state. ESP-RISC-V core contains Trigger Module supporting 4 triggers. When trigger
conditions are met, core will halt spontaneously and inform the debug module that they have halted.

System bus access block allows memory and peripheral register access without using the core.

1.10.2 Features
Basic debug functionality supports below features:

• Provides necessary information about the implementation to the debugger.

• Allows the CPU core to be halted and resumed.

• CPU core registers (including CSRs) can be read/written by debugger.

• CPU can be debugged from the first instruction executed after reset.

• CPU core can be reset through debugger.

• CPU can be halted on software breakpoint (planted breakpoint instruction).

• Hardware single-stepping.

• Execute arbitrary instructions in the halted CPU by means of the program buffer. 16-word program buffer
is supported.

• System bus access is supported through word aligned address access.

• Supports four Hardware Triggers (can be used as breakpoints/watchpoints) as described in Section 1.11.

• Supports LP core debug.

• Supports cross-triggering between HP and LP core.

1.10.3 Functional Description

As mentioned earlier, Debug Scheme conforms to RISC-V External Debug Support Specification Version 0.13.
Please refer to the specification for functional operation details.

1.10.4 JTAG Control

Standard JTAG interface is the only way for DTM to access DM. The hardware provides two JTAG methods:
PAD_to_JTAG and USB_to_JTAG.

• PAD_to_JTAG : means that the JTAG’s signal source comes from IO.

• USB_to_JTAG : means that the JTAG’s signal source comes from USB Serial/JTAG Controller.

Which JTAG method to use depends on many factors. The following table shows the configuration
method.

Temporary EFUSE_DIS_ EFUSE_DIS_ EFUSE_DIS_ EFUSE_JTAG_ Strapping USB JTAG PAD JTAG
disable USB_JTAG USB_SERIAL_ PAD_JTAG 4 SEL_ENABLE Pin Status Status
JTAG 3,4 4 JTAG 4 4 GPIO15 5
0 0 0 0 0 x2 Available 1 Unavailable 1
0 0 0 0 1 1 Available Unavailable

Espressif Systems 68 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Temporary EFUSE_DIS_ EFUSE_DIS_ EFUSE_DIS_ EFUSE_JTAG_ Strapping USB JTAG PAD JTAG
disable USB_JTAG USB_SERIAL_ PAD_JTAG 4 SEL_ENABLE Pin Status Status
JTAG 3 4 JTAG 4 4 GPIO15 5
0 0 0 0 1 0 Unavailable Available
0 0 1 0 x x Unavailable Available
0 1 0 0 x x Unavailable Available
0 1 1 0 x x Unavailable Available
0 0 0 1 x x Available Unavailable
0 0 1 1 x x Unavailable Unavailable
0 1 0 1 x x Unavailable Unavailable
0 1 1 1 x x Unavailable Unavailable
1 x x x x x Unavailable Unavailable

Note:

1. Available: the corresponding JTAG function is available.

Unavailable: the corresponding JTAG function is not available.

2. x: do not care.

3. ”Temporary disable JTAG” means that if there are an even number of bits ”1” in EFUSE_SOFT_DIS_JTAG[2:0], the
JTAG function is turned on (the corresponding value in the table is 1), otherwise it is turned off (the corresponding
value in the table is 0). However, under certain special conditions of the HMAC Accelerator in ESP32-C6, the
JTAG function may be turned on even if there is an odd number of bits ”1” in EFUSE_SOFT_DIS_JTAG[2:0]. For
information on how HMAC affects JTAG functionality, please refer to Chapter HMAC Accelerator.

4. Please refer to Chapter eFuse Controller to get more information about eFuse.

5. Please refer to Chip Boot Control to get more information about the strapping pin GPIO15.

1.10.5 Register Summary

Below is the list of Debug CSRs supported by ESP-RISC-V CPU core:

Name Description Address Access

dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W

All the debug module registers are implemented in conformance to the specification RISC-V External Debug
Support Version 0.13. Please refer to it for more details.

1.10.6 Register Description

Below are the details of Debug CSRs supported by ESP-RISC-V core:

Espressif Systems 69 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.35. dcsr (0x7B0)

er

tim t
op n
e
gv

ed

eb d

op d

ed
st cou
m

re aku
e

st rve
ak
bu

rv

rv

rv
e

ep
us
re

re
se

se

se

se
e

v
xd

eb

pr
ca

st
re

re

re
31 28 27 16 15 14 13 12 11 10 9 8 6 5 3 2 1 0

4 0 0 0 0 0 0 0 0 0 0 0 Reset

xdebugver Represents the debug version.

4: External debug support exists
(RO)

ebreakm When 1, ebreak instructions in Machine Mode enter Debug Mode. (R/W)

ebreaku When 1, ebreak instructions in User/Application Mode enter Debug Mode. (R/W)

stopcount This feature is not implemented. Debugger will always read this bit as 0. (RO)

stoptime This feature is not implemented. Debugger will always read this bit as 0. (RO)

cause Explains why Debug Mode was entered. When there are multiple reasons to enter Debug
Mode in a single cycle, the cause with the highest priority number is the one written.
1: An ebreak instruction was executed. (priority 3)
2: The Trigger Module caused a halt. (priority 4)
3: haltreq was set. (priority 2)
4: The CPU core single stepped because step was set. (priority 1)
Other values are reserved for future use.
(RO)

step When set and not in Debug Mode, the core will only execute a single instruction and then
enter Debug Mode.
If the instruction does not complete due to an exception, the core will immediately enter Debug
Mode before executing the trap handler, with appropriate exception registers set.
Setting this bit does not mask interrupts. This is a deviation from the RISC-V External Debug
Support Specification Version 0.13.
(R/W)
prv Contains the privilege level the core was operating in when Debug Mode was entered. A de-
bugger can change this value to change the core’s privilege level when exiting Debug Mode.
Only 0x3 (machine mode) and 0x0 (user mode) are supported. (R/W)

Espressif Systems 70 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.36. dpc (0x7B1)

c
dp
31 0

0 Reset

dpc Upon entry to debug mode, dpc is written with the virtual address of the instruction that en-
countered the exception. When resuming, the CPU core’s PC is updated to the virtual address
stored in dpc. A debugger may write dpc to change where the CPU resumes. (R/W)

Register 1.37. dscratch0 (0x7B2)

0
ch
at
cr
ds
31 0

0 Reset

dscratch0 Used by Debug Module internally. (R/W)

Register 1.38. dscratch1 (0x7B3)

1
ch
at
cr
ds

31 0

0 Reset

dscratch1 Used by Debug Module internally. (R/W)

Espressif Systems 71 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.11 Hardware Trigger

1.11.1 Features
Hardware Trigger module provides breakpoint and watchpoint capability for debugging. It includes the
following features:

• 4 independent trigger units

• each unit can be configured for matching the address of program counter or load-store accesses

• can preempt execution by causing breakpoint exception

• can halt execution and transfer control to debugger

• support NAPOT (naturally aligned power-of-two regions) address encoding

1.11.2 Functional Description

The Hardware Trigger module provides four CSRs, which are listed under Section register summary. Among
these, tdata1 and tdata2 are abstract CSRs, which means they are shadow registers for accessing internal
registers for each of the four trigger units, one at a time.

To choose a particular trigger unit write the index (0-3) of that unit into tselect CSR. When tselect is written
with a valid index, the abstract CSRs tdata1 and tdata2 are automatically mapped to reflect internal registers of
that trigger unit. Each trigger unit has two internal registers, namely mcontrol and maddress, which are
mapped to tdata1 and tdata2, respectively.

Writing larger than allowed indexes to tselect will clip the written value to the largest valid index, which can be
read back. This property may be used for enumerating the number of available triggers during initialization or
when using a debugger.

Since software or debugger may need to know the type of the selected trigger to correctly interpret tdata1 and
tdata2, the 4 bits (31-28) of tdata1 encodes the type of the selected trigger. This type field is read-only and
always provides a value of 0x2 for every trigger, which stands for match type trigger, hence, it is inferred that
tdata1 and tdata2 are to be interpreted as mcontrol and maddress. The information regarding other possible
values can be found in the specification RISC-V External Debug Support Version 0.13, but this trigger module
only supports type 0x2.

Once a trigger unit has been chosen by writing its index to tselect, it will become possible to configure it by
setting the appropriate bits in mcontrol CSR (tdata1) and writing the target address to maddress CSR
(tdata2).

Each trigger unit can be configured to either cause breakpoint exception or enter debug mode, by writing to
the action field of mcontrol. This bit can only be written from debugger, thus by default a trigger, if enabled,
will cause breakpoint exception.

mcontrol for each trigger unit has a hit bit which may be read, after CPU halts or enters exception, to find out if
this was the trigger unit that fired. This bit is set as soon as the corresponding trigger fires, but it has to be
manually cleared before resuming operation. Although, failing to clear it does not affect normal execution in
any way.

Each trigger unit only supports match on address, although this address could either be that of a load/store
access or the virtual address of an instruction. The address and size of a region are specified by writing to

Espressif Systems 72 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

maddress (tdata2) CSR for the selected trigger unit. Larger than 1 byte region sizes are specified through
NAPOT (naturally aligned power-of-two) encoding (see Table 1-10) and enabled by setting match bit in
mcontrol. Note that for NAPOT encoded addresses, by definition, the start address is constrained to be
aligned to (i.e. an integer multiple of) the region size.

Table 1-10. NAPOT encoding for maddress

maddress(31-0) Start Address Size (bytes)

aaa...aaaaaaaaa0 aaa...aaaaaaaaa0 2
aaa...aaaaaaaa01 aaa...aaaaaaaa00 4
aaa...aaaaaaa011 aaa...aaaaaaa000 8
aaa...aaaaaa0111 aaa...aaaaaa0000 16
....
a01...1111111111 a00...0000000000 231

tcontrol CSR is common to all trigger units. It is used for preventing triggers from causing repeated exceptions
in machine-mode while execution is happening inside a trap handler. This also disables breakpoint exceptions
inside ISRs by default, although, it is possible to manually enable this right before entering an ISR, for
debugging purposes. This CSR is not relevant if a trigger is configured to enter debug mode.

1.11.3 Trigger Execution Flow

When hart is halted and enters debug mode due to the firing of a trigger (action = 1):

• dpc is set to current PC (in decode stage)

• cause field in dcsr is set to 2, which means halt due to trigger

• hit bit is set to 1, corresponding to the trigger(s) which fired

When hart goes into trap due to the firing of a trigger (action = 0) :

• mepc is set to current PC (in decode stage)

• mcause is set to 3, which means breakpoint exception

• mpte is set to the value in mte right before trap

• mte is set to 0

• hit bit is set to 1, corresponding to the trigger(s) which fired

Note: If two different triggers fire at the same time, one with action = 0 and another with action = 1, then hart
is halted and enters debug mode.

1.11.4 Register Summary

Below is a list of Trigger Module CSRs supported by the CPU. These are only accessible from
machine-mode.

Name Description Address Access

tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W

Espressif Systems 73 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Name Description Address Access

tcontrol Global Trigger Control 0x7A5 R/W

1.11.5 Register Description

Register 1.39. tselect (0x7A0)

)
ed
rv

t
ec
se

el
(re

ts
30 2 1 0

0x00000000 0x0 Reset

tselect Configures the index (0-3) of the selected trigger unit. (R/W)

Register 1.40. tdata1 (0x7A1)

e
od
pe

ta
dm

da
ty

31 28 27 26 0

0x2 0 0x3e00000 Reset

type Represents the trigger type. This field is reserved since only match type (0x2) triggers are
supported. (RO)

dmode This is set to 1 if a trigger is being used by the debugger.

0: Both Debug and M mode can write the tdata1 and tdata2 registers at the selected tselect.
1: Only Debug Mode can write the tdata1 and tdata2 registers at the selected tselect. Writes from
other modes are ignored.
Note: Only writable from debug mode.
(R/W)

data Configures the abstract tdata1 content. This will always be interpreted as fields of mcontrol
since only match type (0x2) triggers are supported. (R/W)

Register 1.41. tdata2 (0x7A2)

a2
at
td

31 0

0x00000000 Reset

tdata2 Configures the abstract tdata2 content. This will always be interpreted as maddress since
only match type (0x2) triggers are supported. (R/W)

Espressif Systems 74 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.42. tcontrol (0x7A5)

)
ed

ed
rv

rv
se

se
e
pt

te
(re

(re
m

m
31 8 7 6 1 0

0x000000 0 0x00 0 Reset

mpte Configures whether to enable the machine mode previous trigger.

When CPU is taking a machine mode trap, the value of mte is automatically pushed into this.
When CPU is executing MRET, its value is popped back into mte, so this becomes 0.
(R/W)

mte Configures whether to enable the machine mode trigger.

When CPU is taking a machine mode trap, its value is automatically pushed into mpte, so this
becomes 0 and triggers with action=0 are disabled globally.
When CPU is executing MRET, the value of mpte is automatically popped back into this.
(R/W)

Espressif Systems 75 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.43. mcontrol (0x7A1)

)
ed

ed

ed

ed

ed

st ute
rv

rv

rv

rv

rv
e

ch
od
se

se

se

se

se

e
tio

ec

ad
or
at
dm
(re

(re

(re

(re

(re
ac
t

ex
m

lo
hi

u
31 28 27 26 21 20 19 16 15 12 11 10 7 6 5 4 3 2 1 0

0x2 0 0x1f 0 0 0 0 0 0 0 0 0 0 0 Reset

dmode Same as dmode in tdata1. (RW *)

hit This is found to be 1 if the selected trigger had fired previously. This bit is to be cleared manually.
(R/W)

action Configures the selected trigger to perform one of the available actions when firing. Valid
options are:
0x0: cause breakpoint exception.
0x1: enter debug mode (only valid when dmode = 1)
Note: Writing an invalid value will set this to the default value 0x0.
(R/W)

match Configures the selected trigger to perform one of the available matching operations on a
data/instruction address. Valid options are:
0x0: exact byte match, i.e. address corresponding to one of the bytes in an access must match
the value of maddress exactly.
0x1: NAPOT match, i.e. at least one of the bytes of an access must lie in the NAPOT region
specified in maddress.
Note: Writing a larger value will clip it to the largest possible value 0x1.
(R/W)

m Set this for enabling selected trigger to operate in machine mode. (R/W)

u Set this for enabling selected trigger to operate in user mode. (R/W)

execute Set this for configuring the selected trigger to fire right before an instruction with matching
virtual address is executed by the CPU. (R/W)

store Set this for configuring the selected trigger to fire right before a store operation with matching
data address is executed by the CPU. (R/W)

load Set this for configuring the selected trigger to fire right before a load operation with matching
data address is executed by the CPU. (R/W)

Espressif Systems 76 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.44. maddress (0x7A2)

ss
re
d
ad
m
31 0

0x00000000 Reset

maddress Configures the address used by the selected trigger when performing match operation.
This is decoded as NAPOT when match=1 in mcontrol. (R/W)

Espressif Systems 77 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.12 Trace
1.12.1 Overview
In order to support non-intrusive software debug, the CPU core provides an instruction trace interface which
provides relevant information for offline debug purpose. This interface provides relevant information to Trace
Encoder block, which compresses the information and stores in memory allocated for it. Software decoders
can read this information from trace memory without interrupting the CPU core and re-generate the actual
program execution by the CPU core.

1.12.2 Features
The CPU core supports instruction trace feature and provides below information to Trace Encoder as
mandated in RISC-V Processor Trace Version 1.0:

• Number of instructions being retired.

• Occurrence of exception and interrupt along with cause and trap values.

• Current privilege level of hart.

• Instruction type of retired instructions for jumps, branches and return.

• Instruction address for instructions retired before and after program counter changes.

1.12.3 Functional Description

ESP-RISC-V CPU core implements mandatory instruction delta tracing, also known as branch tracing. It works
by tracking execution from a known start address by sending information about deltas taken by a program.
Deltas are typically introduced by jump, call, return, branch type instructions and also by interrupts and
exceptions. All such deltas along with additional details about cause and actual instructions/addresses are
communicated over high bandwidth instruction trace interface output from the core. Trace Encoder operates
on the information on this trace interface and compresses the information for storage in memory for offline
debug by a decoder. More information about the encoding is available in Chapter 2 RISC-V Trace Encoder
(TRACE).

The core does not have any internal registers to provide control over instruction trace interface. All register
controls are available in 2 RISC-V Trace Encoder (TRACE) block.

Espressif Systems 78 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.13 Debug Cross-Triggering

1.13.1 Overview
In a multi-core system, when the debugging software is running on a given core, it is useful that the other
cores do not change the state of the system. This requirement is addressed by synchronous halt and resume.
It is important that halt/resume information is communicated as quickly as possible to other cores. So, it is
better to do it based on chip infrastructure rather than commands through the debugger software running on
the host.

1.13.2 Features
• Control register to enable or disable cross-trigger between cores

• Overriding the RunStall functionality of a core

1.13.3 Functional Description

Such a scheme has been implemented by providing a custom control register in the debug module. The
register CORE_XT_EN implements a control bit to enable or disable cross-triggering mode. Once enabled, any
core halted due to events such as hardware trigger and ebreak instructions will also result in halting of other
cores without any intervention from the debugger. After halting of cores due to cross-trigger mode, it is not
possible to resume without debugger intervention. The debugger has to connect to all cores and resume
each core synchronously. Please note, debug cross trigger also halts any core which is stalled due to RunStall
functionality.

Espressif Systems 79 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.13.4 Register Summary

Below is a required control register implemented inside debug module.

Name Description Address Access

CORE_XT_EN Cross Triggering Control. 0x20000900 R/W

1.13.5 Register Description

Register 1.45. CORE_XT_EN (0x20000900)

d)
ve
r

n
se

_e
(re

xt
31 1 0

0 0 Reset

XT_EN Configures whether to enable the cross-trigger mode.

0: Disable
1: Enable
(R/W)

Espressif Systems 80 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.14 Dedicated IO
1.14.1 Overview
Normally, GPIOs are an APB peripheral, which means that changes to outputs and reads from inputs can get
stuck in write buffers or behind other transfers, and in general are slower because generally the APB bus runs
at a lower speed than the CPU. As an alternative, the CPU core implements I/O processors specific CPU
registers (CSRs) which are directly connected to the GPIO matrix or IO pads. As these registers can get
accessed in one instruction, speed is fast.

1.14.2 Features
• 8 dedicated IOs directly mapped on GPIOs

• No latency for driving output ports

• Two CPU cycle latency for sensing input values

1.14.3 Functional Description

The CPU core has a set of 8 inputs and outputs (pin value + pin output enable). These input and output ports
are directly connected to the GPIO matrix, through which they can be mapped on top-level pads. Please refer
to Chapter 7 IO MUX and GPIO Matrix (GPIO, IO MUX) for more details.

The CPU implements three custom CSRs:

• GPIO_IN is read-only and reflects the input value.

• GPIO_OUT is R/W and reflects the output value for the GPIOs.

• GPIO_OEN is R/W and reflects the output enable state for the GPIOs. It controls the pad direction.
Programming high would mean the pad should be configured in output mode. Programming low means
it should be configured in input mode.

Espressif Systems 81 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.14.4 Register Summary

Below is a list of custom dedicated IO CSRs implemented inside the core.

Name Description Address Access

cpu_gpio_oen GPIO Output Enable 0x803 R/W
cpu_gpio_in GPIO Input Value 0x804 RO
cpu_gpio_out GPIO Output Value 0x805 R/W

1.14.5 Register Description

Register 1.46. cpu_gpio_oen (0x803)

]
CP GP _O [6]

GP _O [2]
CP _GP _O [3]
CP _GP _O [5]
CP _GP _O [4]
CP _GP _O [7]

EN ]
[0
_O [1
U IO EN
U_ IO EN
U IO EN
U IO EN
U IO EN
U_ IO EN
I O EN
CP GP _O
U_ IO
)
ed

CP _GP
rv
se

U
CP
(re

31 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 Reset

CPU_GPIO_OEN Configures whether to enable GPIOn (n=0 ~ 21) output. CPU_GPIO_OEN[7:0] cor-
respond to output enable signals cpu_gpio_out_oen[7:0] in Table 7-2 Peripheral Signals via
GPIO Matrix. CPU_GPIO_OEN value matches that of cpu_gpio_out_oen. CPU_GPIO_OEN is the
enable signal of CPU_GPIO_OUT.
0: Disable GPIO output
1: Enable GPIO output
(R/W)

Register 1.47. cpu_gpio_in (0x804)

0]
CP GP _IN ]

GP _IN ]
CP _GP _IN ]
CP _GP _IN ]
CP _GP _IN ]
CP _GP _IN ]

IO [1]
U_ IO [6

U_ IO [2
U IO [3
U IO [5
U IO [4
U IO [7

N[
CP GP _IN

_I
U_ IO
)
ed

CP _GP
rv
se

U
CP
(re

31 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 Reset

CPU_GPIO_IN Represents GPIOn (n=0 ~ 21) input value. It is a CPU CSR to read input value (1=high,
0=low) from SoC GPIO pin.
CPU_GPIO_IN[7:0] correspond to input signals cpu_gpio_in[7:0] in Table 7-2 Peripheral Signals
via GPIO Matrix.
CPU_GPIO_IN[7:0] can only be mapped to GPIO pins through GPIO matrix. For details please
refer to Section 7.4 in Chapter IO MUX and GPIO Matrix (GPIO, IO MUX).
(RO)

Espressif Systems 82 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

Register 1.48. cpu_gpio_out (0x805)

]
CP GP _O [6]

GP _O [2]
CP _GP _O [3]
CP _GP _O [5]
CP _GP _O [4]
CP _GP _O [7]

UT ]
[0
_O [1
U IO UT
U_ IO UT
U IO UT
U IO UT
U IO UT
U_ IO UT
IO UT
CP _GP _O
U IO
)
ed

CP _GP
rv
se

U
CP
(re
31 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 Reset

CPU_GPIO_OUT Configures GPIOn (n=0 ~ 21) output value. It is a CPU CSR to write value (1=high,
0=low) to SoC GPIO pin. The value takes effect only when CPU_GPIO_OEN is set.
CPU_GPIO_OUT[7:0] correspond to output signals cpu_gpio_out[7:0] in Table 7-2 Peripheral
Signals via GPIO Matrix.
CPU_GPIO_OUT[7:0] can only be mapped to GPIO pins through GPIO matrix. For details please
refer to Section 7.5 in Chapter IO MUX and GPIO Matrix (GPIO, IO MUX).
(R/W)

Espressif Systems 83 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.15 Atomic (A) Extension

1.15.1 Overview
Support for atomic (A) extension is available in compliance with the RISC-V ISA Manual Volume I: Unprivileged
ISA Version 2.2, with an emphasis to guarantee forward progress, i.e. any situation that may cause data
memory lock for an indefinite amount of time is prevented by their very functionality.

The atomic instructions currently ignore the aq (acquire) and rl (release) bits as they are irrelevant to the
current architecture in which memory ordering is always guaranteed.

1.15.2 Functional Description

1.15.2.1 Load Reserve (LR.W) Instruction

The LR.W instruction simply locks a 32-bit aligned memory address to which the load access is being
performed. Once a 4-byte memory region is locked, it will remain locked, i.e. other harts won’t be able to
access this same memory location, until any of the following scenarios is encountered during
execution:

• any load operation

• any store operation

• any interrupts/exceptions

• backward jump/taken backward branch

• JALR

• ECALL/EBREAK/MRET/URET

• FENCE/FENCE.I

• debug mode

• critical section exceeding 64 bytes

• data address in SC.W instruction not matching that in LR.W instruction

If any of the above happens, except SC.W, the memory lock will be released immediately. If an SC instruction
is encountered instead, the lock will be released eventually (not immediately) in the manner described in
Section 1.15.2.2.

If a misaligned address is encountered, it will cause an exception with mcause = 6.

1.15.2.2 Store Conditional (SC.W) Instruction

The SC.W instruction first checks if the memory lock is still valid, and the address is the same as specified
during the last LR.W instruction. If so, only then will it perform the store to memory, and later release the lock
as soon as it gets an acknowledgement of operation completion from the memory.

On the other hand, if the lock is found to have been invalidated (due to any of the situations as described in
Section 1.15.2.1), it will set a fail code (currently always 1) in the destination register rd.

If a misaligned address is encountered, it will cause an exception with mcause = 6.

Espressif Systems 84 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
1 High-Performance CPU GoBack

1.15.2.3 AMO Instructions

An AMO instruction executes in 3 steps:

1. Read data from memory address given by rs1, and save it to destination register rd.

2. Combine the data in rd and rs2 according to the operation type and keep the result for Step 3 below.

3. Write the result obtained in Step 2 above to memory address given by rs1.

There are 9 different AMO operations: SWAP, ADD, AND, OR, XOR, MAX, MIN, MAXU and MINU.

During this whole process, the memory address is kept locked from being accessed by other harts. If a
misaligned address is encountered, it will cause an exception with mcause = 6.

For AMO operations both load and store access faults (PMP/PMA) are checked in the 1st step itself. For such
cases mcause = 7.

Espressif Systems 85 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

2 RISC-V Trace Encoder (TRACE)

The high-performance CPU (HP CPU) of ESP32-C6 supports instruction trace interface through the trace
encoder. The trace encoder connects to HP CPU’s instruction trace interface, compresses the information into
smaller packets, and then stores the packets in internal SRAM (see Chapter 5 System and Memory).

Instruction Trace Encoder

Trace
Interface
Encoder FIFO

HP
CPU
APB AHB
Transmission
Config
Control

Figure 2-1. Trace Encoder Overview

2.1 Terminology
To better illustrate the functions of the RISC-V Trace Encoder, the following terms are used in this
chapter.

hart RISC-V hardware thread

branch an instruction which conditionally changes the execution flow
uninferable discontinuity a program counter change that can not be inferred from the pro-
gram binary alone
delta a change in the program counter that is other than the difference
between two instructions placed consecutively in memory
trap the transfer of control to a trap handler caused by either an ex-
ception or an interrupt
qualification an instruction that meets the filtering criteria passes the qualifica-
tion, and will be traced
te_inst the name of the packet type emitted by the encoder
retire the final stage of executing an instruction, when the machine state
is updated

2.2 Introduction
In complex systems, understanding program execution flow is not straightforward. This may be due to a
number of factors, for example, interactions with other cores, peripherals, real-time events, poor
implementations, or some combination of all of the above.

It is hard to use a debugger to monitor the program execution flow of a running system in real time, as this is
intrusive and might affect the running state. But providing visibility of program execution is important.

That is where instruction trace comes in, which provides trace of the program execution.

Espressif Systems 86 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

ESP Chip

Debug Host
Instruction Trace
Interface
JTAG Trace Encoder
DTM
Debug
Translator JTAG/
USB-JTAG adapter
DMI HP CPU Core
BUS

Trace
Decoder System
DM Memory

Figure 2-2. Trace Overview

Figure 2-2 shows the schematics of instruction trace:

• The HP CPU core provides an instruction trace interface that outputs the instruction information executed
by the HP CPU. Such information includes instruction address, instruction type, etc. For more details
about ESP32-C6 HP CPU’s instruction trace interface, please refer to Chapter 1 High-Performance CPU.

• The trace encoder connects to the HP CPU’s instruction trace interface and compresses the information
into lower bandwidth packets, and then stores the packets in system memory.

• The debugger can dump the trace packets from the system memory via JTAG or USB Serial/JTAG, and
use a decoder to decompress and reconstruct the program execution flow. The Trace Decoder, usually
software on an external PC, takes in the trace packets and reconstructs the program instruction flow with
the program binary that runs on the originating hart. This decoding step can be done offline or in
real-time while the hart is executing.

This chapter mainly introduces the implementation details of ESP32-C6’s trace encoder.

2.3 Features
• Compatible with RISC-V Processor Trace Version 1.0. See Table 2-2 for the implemented parameters

• Arbitrary address range of the trace memory size

• Two synchronization modes:

– synchronization counter counts by packet

– synchronization counter counts by cycle

• Trace lost status to indicate packet loss

• Automatic restart after packet loss

• Memory writing in loop or non-loop mode

• Two interrupts:

Espressif Systems 87 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

– Triggered when the packet size exceeds the configured memory space

– Triggered when a packet is lost

• FIFO (128 × 8 bits) to buffer packets

Table 2-2. Trace Encoder Parameters

Parameter Name Value Description

arch_p 0 Initial version
bpred_size_p 0 Branch prediction mode is not supported
cache_size_p 0 Jump target cache mode is not supported
call_counter_size_p 0 Implicit return mode is not supported
ctype_width_p 0 Packets contain no context information
context_width_p 0 Packets contain no context information
ecause_width_p 5 Width of exception cause
ecause_choice_p 0 Multiple choice is not supported
f0s_width_p 0 Format 0 packets are not supported
filter_context_p 0
filter_excint_p 0
Filter function is not supported
filter_privilege_p 0
filter_tval_p 0
iaddress_lsb_p 1 Compressed instructions are supported
iaddress_width_p 32 The instruction bus is 32-bit
iretire_width_p 1 Width of the iretire bus
ilastsize_width_p 0 Width of the ilastsize
itype_width_p 3 Width of the itype bus
noncontext_p 1 Exclude context from te_inst packets
privilege_width_p 1 Only machine and user mode are supported
retires_p 1 Maximum number of instructions that can be retired per block
return_stack_size_p 0 Implicit return mode is not supported
sijump_p 0 Sequentially inferable jump mode is not supported
taken_branches_p 1 Only one instruction retired per cycle
impdef_width_p 0 Not implemented

For detailed descriptions of the above parameters, please refer to the RISC-V Processor Trace Version 1.0 >
Chapter Parameters and Discovery.

2.4 Architectural Overview

As shown in Figure 2-1, the trace encoder contains an encoder, a FIFO, a register configuration module, and a
transmission control module.

The encoder receives HP CPU’s instruction information via the instruction trace interface, compresses it into
different packets, and writes it to the internal FIFO.

The transmission control module writes the data in the FIFO to the internal SRAM through the AHB bus.

The FIFO is 128 deep and 8-bit wide. When the memory bandwidth is insufficient, the FIFO may overflow and

Espressif Systems 88 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

packet loss occurs. If a packet is lost, the encoder will send a packet to tell that a packet is lost, and will stop
working until the FIFO is empty.

2.5 Functional Description

2.5.1 Synchronization
In order to make the trace robust there must be regular synchronization points within the trace.
Synchronization is accomplished by sending a full valued instruction address. When the synchronization
counter value reaches the value of the TRACE_RESYNC_PROLONGED field of the
TRACE_RESYNC_PROLONGED_REG register, the encoder will send a synchronization packet (format 3
subformat 0, see Section 2.6.3.1).

There are two synchronization modes configured via TRACE_RESYNC_MODE:

• 0: Synchronization counter counts by cycle

• 1: Synchronization counter counts by packet

You can adjust the trace bandwidth by increasing the value of TRACE_RESYNC_PROLONGED_REG to reduce
the frequency of sending synchronization packets, thereby reducing the bandwidth occupied by
packets.

2.5.2 Anchor Tag

Since the length of data packets is variable, in order to identify boundaries between data packets when
packed packets are written to memory, ESP32-C6 inserts zero bytes between data packets:

• The maximum packet length is 13 bytes, so a sequence of at least 14 zero bytes cannot occur within a
packet. Therefore, the first non-zero byte seen after a sequence of at least 14 zero bytes must be the
first byte of a packet.

• Every time when 128 packets are transmitted, the encoder writes 14 zero bytes to the memory partition
boundary as anchor tags.

2.5.3 Memory Writing Mode

When writing the trace memory, the size of the trace packets might exceed the capacity of the memory. In
this case, you can choose whether to wrap around the trace memory or not by configuring the memory writing
mode:

• Loop mode: When the size of the trace packets exceeds the capacity of the trace memory (namely
when TRACE_MEM_CURRENT_ADDR_REG reaches the value of TRACE_MEM_END_ADDR_REG), the
trace memory is wrapped around, so that the encoder loops back to the memory’s starting address
TRACE_MEM_START_ADDR_REG, and old data in the memory will be overwritten by new data.

• Non-loop mode: When the size of the trace packets exceeds the capacity of the trace memory, the
trace memory is not wrapped around. The encoder stops at TRACE_MEM_END_ADDR_REG, and old
data will be retained.

Espressif Systems 89 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

2.5.4 Automatic Restart

When packets are lost due to FIFO overflow, the encoder will stop working and need to be resumed by
software. If the TRACE_RESTART_ENA bit of TRACE_TRIGGER_REG is set, once the FIFO is empty, the encoder
can automatically be restarted and does not need to be resumed by software.

If the automatic restart feature is enabled, the encoder will be restarted in any case. Therefore, to disable the
encoder, the automatic restart feature must be disabled first by clearing the TRACE_RESTART_ENA bit of the
TRACE_TRIGGER_REG register.

2.6 Encoder Output Packets

This section mainly introduces ESP32-C6 trace encoder output packet format. ESP32-C6 only implements
mandatory instruction delta tracing. It does not support the following optional features:

• Delta address mode (run-time configurable modes is supported)

• Context information and all context-related fields

• Optional sideband signals

• Trigger outputs from the Debug Module

For details about the above features, please refer RISC-V Processor Trace Version 1.0 (referred to below as the
specification).

Header Index Payload

(1 byte) (2 bytes) (1~10 bytes)

Figure 2-3. Trace packet Format

A packet includes header, index and payload. Header, index and payload are transmitted sequentially in bit
stream form, from the fields listed at the top of tables below to the fields listed at the bottom. If a field consists
of multiple bits, then the least significant bit is transmitted first.

2.6.1 Header
Header is 1-byte long. The format of header is shown in Table 2-3.

Table 2-3. Header Format

Field Bits Description Value

length 5 Length of whole packet 4~13
placeholder 3 Reserved 0

2.6.2 Index
Index has 2 bytes. The format of index is shown in Table 2-4.

Espressif Systems 90 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Table 2-4. Index Format

Field Bits Description Value

index 16 The index of each packet 0~65536

2.6.3 Payload
The length of payload ranges from 1 byte to 10 bytes.

2.6.3.1 Format 3 Packets

Format 3 packets are used for synchronization, and report supporting information. There are 4 subformats
defined in the specification. ESP32-C6 only supports 3 of them.

Format 3 Subformat 0 - Synchronization

This packet contains all the information the decoder needs to fully identify an instruction. It is sent for the first
traced instruction (unless that instruction also happens to be a first in an exception handler), and when
synchronization has been scheduled by expiry of the synchronization timer. The payload length is 5
bytes.

Table 2-5. Packet format 3 subformat 0

Field name Bits Description

format 2 11 (sync): Synchronization
subformat 2 00 (start): Start of tracing, or resync
Set to 0 if the address points to a branch instruction, and the
branch 1 branch was taken. Set to 1 if the instruction is not a branch or if
the branch is not taken.
privilege 1 The privilege level of the reported instruction
Full instruction address. The address must be left shifted 1 bit in
address 31
order to recreate the original byte address.
sign_extend 3 Reserved

Format 3 Subformat 1 - Exception

This packet also contains all the information the decoder needs to fully identify an instruction. It is sent
following an exception or interrupt, and includes the cause, the ’trap value’ (for exceptions), and the address
of the trap handler or of the exception itself. The length is 10 bytes.

Table 2-6. Packet format 3 subformat 1

Field name Bits Description

format 2 11 (sync): Synchronization
subformat 2 01 (exception): Exception cause and trap handler address
Set to 0 if the address points to a branch instruction, and the
branch 1 branch was taken. Set to 1 if the instruction is not a branch or if
the branch is not taken.

Espressif Systems 91 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Field name Bits Description

privilege 1 The privilege level of the reported instruction
ecause 5 Exception cause
interrupt 1 Interrupt
Full instruction address. The value of this field must be left
address 31
shifted 1 bit in order to recreate original byte address.
Exception address if ecause is 2 and interrupt is 0, or trap value
tvalepc 32
otherwise
sign_extend 6 Reserved

Format 3 Subformat 3 - Support

This packet provides supporting information to aid the decoder. It is issued when the trace is ended. The
length is 1 byte.

Table 2-7. Packet format 3 subformat 3

Field name Bits Description

format 2 11 (sync): Synchronization
subformat 2 11 (support): Supporting information for the decoder
enable 1 Indicates if the encoder is enabled
Indicates qualification status:
• 00 (no_change): No change to filter qualification
• 01 (ended_rep): Qualification ended, preceding instruction
sent explicitly to indicate last qualification instruction
qual_status 2
• 10 (trace lost): One or more packets lost
• 11 (ended_upd): Qualification ended, preceding te_inst
would have been sent anyway due to an updiscon, even if
wasn’t the last qualified instruction
sign_extend 1 Reserved

2.6.3.2 Format 2 Packets

This packet contains only an instruction address, and is used when the address of an instruction must be
reported, and there is no reported branch information. The length is 5 bytes.

Table 2-8. Packet format 2

Field name Bits Description

format 2 10 (addr-only): No branch information
address 31 Full instruction address
ESP32-C6 don’t support notification, so this bit is always same
notify 1
with the MSB of address.
If the value of this bit is different from notify, it indicates that this
packet is reporting the instruction following an uninferable
updiscon 1
discontinuity and is also the instruction before an exception,
privilege change or resync.

Espressif Systems 92 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Field name Bits Description

sign_extend 5

2.6.3.3 Format 1 Packets

This packet includes branch information, and is used when either the branch information must be reported (for
example because the branch map is full), or when the address of instruction must be reported, and there has
must been at least one branch since the previous packet. This packet only supports full address mode.

Format 1 - address, branch_map

The length is variable.

Table 2-9. Packet format 1 with address

Field name Bits Description

format 2 01: Includes branch information
Number of valid bits branch_map. The number of bits of
branch_map is determined as follows:
• 0: (cannot occur for this format)
• 1: 1 bit
• 2-3: 3 bits
branches 5
• 4-7: 7 bits
• 8-15: 15 bits
• 16-31: 31 bits
For example if branches = 12, branch_map is 15-bit long, and the
12 LSBs are valid.
An array of bits indicating whether branches are taken or not. Bit
0 represents the oldest branch instruction executed. For each
bit:
branch_map Variable
• 0: branch taken
• 1: branch not taken
The field Bits is variable and determined by the branches field.
address 31 Full instruction address
ESP32-C6 don’t support notification, so this bit is always same
notify 1
with the MSB of address.
If the value of this bit is different from notify, it indicates that this
packet is reporting the instruction following an uninferable
updiscon 1
discontinuity and is also the instruction before an exception,
privilege change or resync.
The field bits are determined by the branches. The number of
bits of sign_extend is as follows:
• 1: 7 bits
• 2-3: 5 bits
• 4-7: 1 bit
• 8-15: 1 bit
sign_extend Variable
• 16-32: 31 bits

Espressif Systems 93 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Format 1 - no address, branch_map

The length is 5 bytes.

Table 2-10. Packet format 1 without address

Field name Bits Description

format 2 01: includes branch information
Number of valid bits in branch_map. The length of branch_map
branches 5
is 31 bits. Only 0 valid.
An array of bits indicating whether branches are taken or not. Bit
0 represents the oldest branch instruction executed. For each
31 bit:
• 0: branch taken
branch_map
• 1: branch not taken
sign_extend 2 Reserved

2.7 Interrupt
• TRACE_MEM_FULL_INTR: Triggered when the packet size exceeds the capacity of the trace memory,
namely when TRACE_MEM_CURRENT_ADDR_REG reaches the value of TRACE_MEM_END_ADDR_REG.
If necessary, this interrupt can be enabled to notify the HP CPU for processing, such as applying for a
new memory space again.

• TRACE_FIFO_OVERFLOW_INTR: Triggered when the internal FIFO overflows and one or more packets
have been lost.

After enabling the trace encoder interrupts, map them to numbered CPU interrupts through the Interrupt
Matrix, so that the HP CPU can respond to these trace encoder interrupts. For details, please refer to Chapter
10 Interrupt Matrix (INTMTX).

2.8 Programming Procedures

2.8.1 Enable Encoder
• Configure the address space for the trace memory via TRACE_MEM_START_ADDR_REG and
TRACE_MEM_END_ADDR_REG

• Update the value of TRACE_MEM_CURRENT_ADDR_REG to the value of

TRACE_MEM_START_ADDR_REG by setting TRACE_MEM_CURRENT_ADDR_UPDATE

• (Optional) Configure the memory writing mode via the TRACE_MEM_LOOP bit of TRACE_TRIGGER_REG

– 0: Non-loop mode

– 1: Loop mode (default)

• Configure the synchronization mode via the TRACE_RESYNC_MODE bit of

TRACE_RESYNC_PROLONGED_REG

– 0: count by cycle (default)

Espressif Systems 94 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

– 1: count by packet

• (Optional) Configures the threshold for the synchronization counter (default value is 128) via
TRACE_RESYNC_PROLONGED_REG

• (Optional) Enable Interrupt

– Set the corresponding bit of TRACE_INTR_ENA_REG to enable the corresponding interrupt

– Set the corresponding bit of TRACE_INTR_CLR_REG to clear the corresponding interrupt

– Read TRACE_INTR_RAW_REG to know which interrupt occurs

• (Optional) Enable automatic restart by setting the TRACE_RESTART_ENA bit of TRACE_TRIGGER_REG.

This function is enabled by default

• Enable the trace encoder by setting the TRACE_TRIGGER_ON field of TRACE_TRIGGER_REG

Once the encoder is enabled, it will keep tracing the HP CPU’s instruction trace interface and writing packets
to the trace memory.

2.8.2 Disable Encoder

• Disable automatic restart by clearing the TRACE_RESTART_ENA bit of TRACE_TRIGGER_REG

• Stop the encoder by setting the TRACE_TRIGGER_OFF bit of TRACE_TRIGGER_REG

• Confirm whether all data in the FIFO have been written into the memory by reading the
TRACE_FIFO_EMPTY bit

2.8.3 Decode Data Packets

• Find the first address to decode

– Read the TRACE_MEM_FULL_INTR_RAW bit of the TRACE_INTR_RAW_REG register to know if the

trace memory is full

* if read 1, read the trace packets from TRACE_MEM_START_ADDR_REG

* if read 0, and the loop mode is enabled, then the old trace packets are overwritten. In this
case, read the TRACE_MEM_CURRENT_ADDR_REG to know the last writing address, and use
this address as the first address to decode

• Use the decoder to decode data packets

– The decoder reads all data packets starting from the first address, and reconstructs the data stream
with the binary file

– As mentioned in 2.6, the encoder writes 14 zero bytes to the memory partition boundary every time
when 128 packets are transmitted. Given this fact, the first non-zero byte after 14 zero bytes should
be the header of a new packet

Espressif Systems 95 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

2.9 Register Summary

The addresses in this section are relative to RISC-V Trace Encoder base address provided in Table 5-2 in
Chapter 5 System and Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

Memory configuration registers
TRACE_MEM_START_ADDR_REG Memory start address 0x0000 R/W
TRACE_MEM_END_ADDR_REG Memory end address 0x0004 R/W
TRACE_MEM_CURRENT_ADDR_REG Memory current address 0x0008 RO
TRACE_MEM_ADDR_UPDATE_REG Memory address update 0x000C WT
FIFO status register
TRACE_FIFO_STATUS_REG FIFO status register 0x0010 RO
Interrupt registers
TRACE_INTR_ENA_REG Interrupt enable register 0x0014 R/W
TRACE_INTR_RAW_REG Interrupt raw status register 0x0018 RO
TRACE_INTR_CLR_REG Interrupt clear register 0x001C WT
Trace configuration registers
TRACE_TRIGGER_REG Trace enable register 0x0020 varies
TRACE_RESYNC_PROLONGED_REG Resynchronization configuration register 0x0024 R/W
Clock gating control and configuration register
TRACE_CLOCK_GATE_REG Clock gating control register 0x0028 R/W
Version register
TRACE_DATE_REG Version control register 0x03FC R/W

Espressif Systems 96 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

2.10 Registers
The addresses in this section are relative to RISC-V Trace Encoder base address provided in Table 5-2 in
Chapter 5 System and Memory.

Register 2.1. TRACE_MEM_START_ADDR_REG (0x0000)

R
DD
_A
RT
TA
_S
EM
M
E_
AC
TR
31 0

0x000000 Reset

TRACE_MEM_START_ADDR Configures the start address of trace memory. (R/W)

Register 2.2. TRACE_MEM_END_ADDR_REG (0x0004)

R
DD
_A
ND
_E
EM
E_M
AC
TR

31 0

0xffffffff Reset

TRACE_MEM_END_ADDR Configures the end address of trace memory. (R/W)

Register 2.3. TRACE_MEM_CURRENT_ADDR_REG (0x0008)

R
ADD
T_
REN
UR
_C
EM
E_M
AC
TR

31 0

0x000000 Reset

TRACE_MEM_CURRENT_ADDR Represents the current memory address for writing. (RO)

Espressif Systems 97 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Register 2.4. TRACE_MEM_ADDR_UPDATE_REG (0x000C)

AT
UPD
R_
DD
_A
NT
RE
UR
_C
EM
d)

M
ve

E_
r

AC
se
(re

TR
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TRACE_MEM_CURRENT_ADDR_UPDATE Configures whether to update the current memory ad-

dress to the start address of the memory.
0: Not update
1: Update
(WT)

Register 2.5. TRACE_FIFO_STATUS_REG (0x0010)

M US
Y
_E AT
PT
FO ST
FI K_
E_ R
AC WO
)
ed

TR CE_
rv
se

A
(re

TR
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

TRACE_FIFO_EMPTY Represents the FIFO status.

0: Not empty
1: Empty
(RO)

TRACE_WORK_STATUS Represents the encoder status.

0: Not tracing instruction.
1: Tracing instructions and reporting packets.
(RO)

Espressif Systems 98 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Register 2.6. TRACE_INTR_ENA_REG (0x0014)

A
EN
R_
W NA
NT
LO _E
_I
RF TR
VE _IN
_O LL
FO U
FI _F
E_ EM
d)

AC M
ve

TR CE_
r
se

A
(re

TR
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TRACE_FIFO_OVERFLOW_INTR_ENA Write 1 to enable TRACE_FIFO_OVERFLOW_INTR. (R/W)

TRACE_MEM_FULL_INTR_ENA Write 1 to enable TRACE_MEM_FULL_INTR. (R/W)

Register 2.7. TRACE_INTR_RAW_REG (0x0018)

W
RA
R_
W AW
NT
LO _R
_I
RF TR
VE _IN
_O LL
FO U
FI _F
E_ EM
)

AC M
ed

TR CE_
rv
se

A
(re

TR
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TRACE_FIFO_OVERFLOW_INTR_RAW The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.

(RO)

TRACE_MEM_FULL_INTR_RAW The raw interrupt status of TRACE_MEM_FULL_INTR. (RO)

Register 2.8. TRACE_INTR_CLR_REG (0x001C)

LR
C
R_
W LR
NT
LO _C
_I
RF TR
VE _IN
_O LL
FO U
FI _F
E_ EM
)

AC M
ed

TR CE_
rv
se

A
(re

TR

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TRACE_FIFO_OVERFLOW_INTR_CLR Write 1 to clear TRACE_FIFO_OVERFLOW_INTR. (WT)

TRACE_MEM_FULL_INTR_CLR Write 1 to clear TRACE_MEM_FULL_INTR. (WT)

Espressif Systems 99 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Register 2.9. TRACE_TRIGGER_REG (0x0020)

E_ IGG OO A

R_ F
ON
AC TR _L N

GE OF
TR E P
TR CE_ EM T_E

IG R_
A M AR
TR E_ ST
AC RE
)
ed

TR CE_
rv
se

A
(re

TR
31 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Reset

TRACE_TRIGGER_ON Configures whether or not to enable the trace encoder.

0: Invalid. No effect
1: Enable
(WT)

TRACE_TRIGGER_OFF Configures whether to stop the trace encoder.

0: Invalid. No effect
1: Stop
(WT)

TRACE_MEM_LOOP Configures memory mode.

0: Non-loop mode
1: Loop mode
(R/W)

TRACE_RESTART_ENA Configures whether or not to enable the automatic restart function for the
encoder.
0: Disable
1: Enable
(R/W)

Register 2.10. TRACE_RESYNC_PROLONGED_REG (0x0024)

D
NGE
LO
E
OD

RO
M

_P
C_

NC
YN

SY
ES

E
)
ed

_R

_R
rv

E
AC

AC
se
(re

TR

TR

31 25 24 23 0

0 0 0 0 0 0 0 0 128 Reset

TRACE_RESYNC_PROLONGED Configures the threshold for the synchronization counter. (R/W)

TRACE_RESYNC_MODE Configures the synchronization mode.

0: Count by cycle
1: Count by packet
(R/W)

Espressif Systems 100 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
2 RISC-V Trace Encoder (TRACE) GoBack

Register 2.11. TRACE_CLOCK_GATE_REG (0x0028)

N
K _E
CL
d)
ve

E_
r

AC
se
(re

TR
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

TRACE_CLK_EN Configures register clock gating. 0: Support clock only when the application
writes registers to save power.
1: Always force the clock on for registers.
This bit doesn’t affect register access.
(R/W)

Register 2.12. TRACE_DATE_REG (0x03FC)

E
AT
)
ed

_D
rv

E
AC
se
(re

TR

31 28 27 0

0 0 0 0 0x2203030 Reset

TRACE_DATE Version control register. (R/W)

Espressif Systems 101 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

3 Low-Power CPU
The ESP32-C6 Low-Power CPU (LP CPU) is a 32-bit processor based upon RISC-V ISA comprising integer (I),
multiplication/division (M), atomic (A), and compressed (C) standard extensions. It features ultra-low power
consumption and has a 2-stage, in-order, and scalar pipeline. The LP CPU core complex has an interrupt
controller (INTC), a debug module (DM), and system bus (SYS BUS) interfaces for memory and peripheral
access.

The LP CPU is in sleep mode by default (see Section 3.9). It can stay powered on when the chip enters
Deep-sleep mode (see Chapter 12 Low-Power Management for details) and can access most peripherals and
memories (see Chapter 5 System and Memory for details). It has two application scenarios:

• Power insensitive scenario: When the High-Performance CPU (HP CPU) is active, the LP CPU can assist
the HP CPU with some speed- and efficiency-insensitive controls and computations.

• Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP CPU can
be woken up to handle some external wake-up events.

HP Power Domain LP Power Domain

HP CPU LP CPU

HP Peripherals SYS Memory LP Peripherals LP RAM

Figure 3-1. LP CPU Overview

3.1 Features
The LP CPU has the following features:

• Operating clock frequency up to 20 MHz

• 1 vector interrupts

• Debug module compliant with RISC-V External Debug Support Version 0.13 with external debugger
support over an industry-standard JTAG/USB port

• Hardware trigger compliant with RISC-V External Debug Support Version 0.13 with up to 2
breakpoints/watchpoints

• 32-bit AHB system bus for peripheral and memory access

• Core performance metric events

• Able to wake up the HP CPU and send an interrupt to it

• Access to HP memory and LP memory

• Access to the entire peripheral address space

Espressif Systems 102 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

3.2 Configuration and Status Registers (CSRs)

3.2.1 Register Summary
Below is a list of CSRs available to the CPU. Except for the custom performance counter CSRs, all the
implemented CSRs follow the standard mapping of bit fields as described in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 1.10. It must be noted that even among the standard CSRs, not all bit
fields have been implemented, limited by the subset of features implemented in the CPU. Refer to the next
section for a detailed description of the subset of fields implemented under each of these CSRs.

Name Description Address Access

Machine Information CSR
mhartid Machine Hart ID 0xF14 RO
Machine Trap Setup CSRs
mstatus Machine Mode Status 0x300 R/W
misa ⁵ Machine ISA 0x301 R/W
mie Machine Interrupt Enable 0x304 R/W
mtvec ⁶ Machine Trap Vector 0x305 R/W
Machine Trap Handling CSRs
mscratch Machine Scratch 0x340 R/W
mepc Machine Trap Program Counter 0x341 R/W
mcause ⁷ Machine Trap Cause 0x342 R/W
mtval Machine Trap Value 0x343 R/W
mip Machine Interrupt Pending 0x344 R/W
Trigger Module CSRs (shared with Debug Mode)
tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W
Debug Mode CSRs
dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W
Machine Counter/Timer CSRs
mcycle Machine Clock Cycle Counter 0xB00 R/W
minstret Machine Retired Instruction Counter 0xB02 R/W
mhpmcountern(n:3-12) Machine Performance Monitor Counter 0xB00+n R/W
mcycleh The higher 32 bits of mcycle 0xB80 R/W
minstreth The higher 32 bits of minstret 0xB82 R/W
mhpmcounternh(n:3-12) The higher 32 bits of mhpmcountern(n:3-12) 0xB80+n R/W
Machine Counter Setup CSR
mcountinhibit Machine Counter Control 0x320 R/W

⁵Although misa is specified as having both read and write access (R/W), its fields are hardwired and thus write has no effect. This is
what would be termed WARL (Write Any Read Legal) in RISC-V terminology.
⁶mtvec only provides configuration for trap handling in vectored mode with the base address aligned to 256 bytes.
⁷External interrupt IDs reflected in mcause include even those IDs which have been reserved by RISC-V standard for core internal sources.

Espressif Systems 103 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Note that if write, set, or clear operation is attempted on any of the read-only (RO) CSRs indicated in the above
table, the CPU will generate an illegal instruction exception.

3.2.2 Registers

Register 3.1. mhartid (0xF14)

ID
RT
HA
M
31 0

0x00000001 Reset

MHARTID Represents Hart ID. The LP CPU hart ID is 1. (RO)

Register 3.2. mstatus (0x300)

)

)
ed

ed

ed

ed

ed
rv

rv

rv

rv

rv
se

se

se

se

se
E
PP

PI

IE
(re

TW

(re

(re

(re

(re
M

M
31 22 21 20 13 12 11 10 8 7 6 4 3 2 0

0x000 0 0x00 0x0 0x0 0 0x0 0 0x0 Reset

MIE Write 1 to enable the global machine mode interrupt. (R/W)

MPIE Write 1 to enable the machine previous interrupt (before trap). (R/W)

MPP Configures machine previous privilege mode (before trap).

0x3: Machine mode
Other values: Invalid
Note: Only the lower bit is writable. Any write to the higher bit is ignored as it is directly tied to
the lower bit.
(R/W)

TW Configures whether to cause illegal instruction exception when WFI (Wait-for-Interrupt) instruc-
tion is executed in User mode.
0: Not cause illegal exception in User mode
1: Cause illegal instruction exception
(R/W)

Espressif Systems 104 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.3. misa (0x301)

)
ed
rv
se
XL

(re
M

M
W

O
U

G
N

C
H

B
Z

P
R
V

A
T
Y

E
F
X

J
L

I
31 30 29 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x1 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 Reset

MXL Machine XLEN = 1 (32-bit). (RO)

Z Reserved = 0. (RO)

Y Reserved = 0. (RO)

X Non-standard extensions present = 0. (RO)

W Reserved = 0. (RO)

V Reserved = 0. (RO)

U User mode implemented = 0. (RO)

T Reserved = 0. (RO)

S Supervisor mode implemented = 0. (RO)

R Reserved = 0. (RO)

Q Quad-precision floating-point extension = 0. (RO)

P Reserved = 0. (RO)

O Reserved = 0. (RO)

N User-level interrupts supported = 0. (RO)

M Integer Multiply/Divide extension = 1. (RO)

L Reserved = 0. (RO)

K Reserved = 0. (RO)

J Reserved = 0. (RO)

I RV32I base ISA = 1. (RO)

H Hypervisor extension = 0. (RO)

G Additional standard extensions present = 0. (RO)

F Single-precision floating-point extension = 0. (RO)

E RV32E base ISA = 0. (RO)

D Double-precision floating-point extension = 0. (RO)

C Compressed Extension = 1. (RO)

B Reserved = 0. (RO)

A Atomic Standard Extension = 1. (RO)

Espressif Systems 105 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.4. mie (0x304)

d)

)
ed
IE rve

rv
se

se
(re

(re
31 30 29 0

0x0 0x0 0x0 Reset

IE Write 1 to enable the interrupt. (R/W)

Register 3.5. mtvec (0x305)

)
ed
rv

E
se
SE

OD
(re
BA

M
31 8 7 2 1 0

0x000000 0x00 0x1 Reset

MODE Represents whether machine mode interrupts are vectored. Only vectored mode 0x1 is
available. (RO)

BASE Configures the higher 24 bits of trap vector base address aligned to 256 bytes. (R/W)

Register 3.6. mscratch (0x340)

H
TC
RA
SC
M

31 0

0x00000000 Reset

MSCRATCH Contains machine scratch information for custom use. (R/W)

Register 3.7. mepc (0x341)

C
EP
M

31 0

0x00000000 Reset

MEPC Configures the machine trap/exception program counter. This is automatically updated with
address of the instruction which was about to be executed while CPU encountered the most
recent trap. (R/W)

Espressif Systems 106 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.8. mcause (0x342)

de
Co
g
la

)
F

n
ed

io
pt

rv

pt
rru

se

ce
te

(re

Ex
In

31 30 5 4 0

0 0x0000000 0x00 Reset

Exception Code This field is automatically updated with unique ID of the most recent exception or
interrupt due to which CPU entered trap. Possible exception IDs are:
0x2: Illegal instruction
0x3: Hardware breakpoint/watchpoint or EBREAK
0x6: Misaligned atomic instructions
Note: Exception ID 0x0 (instruction access misaligned) is not present because CPU always
masks the lowest bit of the address during instruction fetch.
(R/W)

Interrupt Flag This flag is automatically updated when CPU enters trap. If this is found to be set,
it indicates that the latest trap occurred due to an interrupt. For exceptions it remains unset.
(R/W)

Register 3.9. mtval (0x343)

AL
TV
M

31 0

0x00000000 Reset

MTVAL Configures machine trap value. This is automatically updated with an exception dependent
data which may be useful for handling that exception. Data is to be interpreted depending upon
exception IDs:
0x1: Faulting virtual address of instruction
0x2: Faulting instruction opcode
0x5: Faulting data address of load operation
0x7: Faulting data address of store operation
Note: The value of this register is not valid for other exception IDs and interrupts.
(R/W)

Espressif Systems 107 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.10. mip (0x344)

d)

)
ed
IP rve

rv
se

se
(re

(re
31 30 29 0

0x0 0x0 0x0 Reset

IP Configures the pending status of the interrupt.

0: Not pending
1: Pending
(R/W)

Register 3.11. mcycle (0xB00)

e
cl
cy
m

31 0

0x0 Reset

MCYCLE Configures the lower 32 bits of the clock cycle counter. (R/W)

Register 3.12. minstret (0xB02)

t
re
st
in
m

31 0

0x0 Reset

MINSTRET Configures the lower 32 bits of the instruction counter. (R/W)

Register 3.13. mhpmcountern(n: 3-12) (0xB00+n)

n
er
unt
co
m
hp
m

31 0

0x0 Reset

MHPMCOUNTERn Configures the lower 32 bits of the performance counter n. (R/W)

Espressif Systems 108 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.14. mcycleh (0xB80)

eh
cl
cy
m
31 0

0x0 Reset

MCYCLEH Configures the higher 32 bits of the clock cycle counter. (R/W)

Register 3.15. minstreth (0xB82)

th
re
st
in
m
31 0

0x0 Reset

MINSTRETH Configures the higher 32 bits of the instruction counter. (R/W)

Register 3.16. mhpmcountern(n: 3-12)h (0xB80+n)

h
rn
te
un
co
m
hp
m

31 0

0x0 Reset

MHPMCOUNTERnh Configures the higher 32 bits of the performance counter n. (R/W)

Espressif Systems 109 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.17. mcouninhibit (0x320)

d )
CY rve
se
M

(re
HP

IR
31 3 2 1 0

0x0 0x0 0x0 0x0 Reset

HPM Configures whether the performance counter n(n:3-12) increments.

0: The counter does not count
1: The counter increments
(R/W)

IR Configure whether the instruction counter increments.

0: The counter does not count
1: The counter increments
(R/W)

CY Configure whether the clock cycle counter increments.

0: The counter does not count
1: The counter increments
(R/W)

3.3 Interrupts and Exceptions

The LP CPU handles interrupts and exceptions according to RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Version 1.10. After entering an interrupt/exception handler, the CPU:

• Saves the current program counter (PC) value to the mepc CSR

• Copies the state of MIE of mstatus to MPIE of mstatus

• Saves the current privileged mode to MPP of mstatus

• Clears MIE of mstatus

• Toggles the privileged mode to machine mode (M mode)

• Jumps to the handler address

– For exceptions, the handler address is the base address of the vector table in the mtvec CSR.

– For interrupts, the handler address is mtvec + 4 ∗ 30.

After the mret instruction is executed, the core jumps to the PC saved in the mepc CSR and restores the
value of MPIE of mstatus to MIE of mstatus .

When the core starts up, the base address of the vector table is initialized to the boot address 0x50000000.
After startup, the base address can be changed by writing to the mtvec CSR. For more information about
CSRs, see Section 3.2.1.

The core fetches instructions from address 0x50000080 after reset.

Espressif Systems 110 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

3.3.1 Interrupts
The ESP32-C6 LP CPU supports only one interrupt entry, to which all interrupt events jump. The LP CPU
supports the following peripheral interrupt sources:

• Power Management Unit (PMU)

• Low-Power Timer (RTC_TIMER)

• Low-Power UART (LP_UART)

• Low-Power I2C (LP_I2C)

• Low-Power IO MUX (LP IO MUX)

For more information on those peripheral interrupts, please refer to the corresponding chapter.

3.3.2 Interrupt Handling

By default, interrupts are disabled globally because the MIE bit in mstatus has a reset value of 0. Software
must set this bit to enable global interrupts.

1. Enable interrupts

• To enable interrupts globally, set the MIE bit of mstatus.

• To enable Interrupt 30, set the 30th bit of mie CSR.

2. After interrupts are enabled, the LP CPU can respond to interrupts. It also needs to configure interrupts
of the peripherals so that they can send an interrupt signal to the LP CPU.

3. After the interrupt is triggered, the LP CPU jumps to mtvec + 4 ∗ 30.

4. After enterring the interrupt handler, users need to read LPPERI_INTERRUPT_SOURCE_REG to get the
peripheral that triggered the interrupt and process the interrupt. Note that if the interrupts are triggered
by multiple peripherals, the CPU will process them one by one in sequence until none is left. If not all
interrupts are processed, the CPU will enter the interrupt handler again.

5. To clear interrupts, just clear the interrupt signal of the peripheral.

3.3.3 Exceptions
The LP CPU supports the RISC-V standard exceptions and can trigger the following exceptions:

Table 3-2. LP CPU Exception Causes

Exception ID Description
2 Illegal instructions
3 Breakpoints (EBREAK)
6 Misaligned atomic instructions

3.4 Debugging
This section describes how to debug and test the LP CPU. Debug support is provided through standard JTAG
pins and complies with RISC-V External Debug Support Version 0.13.

Espressif Systems 111 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

For ESP32-C6 system debugging overview, please refer to Section 1.10 Debug > Figure 1-2.

The user interacts with the Debug Host (e.g. laptop), which is running a debugger (e.g., gdb). The debugger
communicates with a Debug Translator (e.g. OpenOCD, which may include a hardware driver) to communicate
with Debug Transport Hardware (e.g. ESP-Prog adapter). The Debug Transport Hardware connects the Debug
Host to the CPU’s Debug Transport Module (DTM) through a standard JTAG interface. The DTM provides
access to the debug module (DM) using the Debug Module Interface (DMI).

DM supports multi-core debugging in compliance with the specification RISC-V External Debug Support
Version 0.13, and can control the HP CPU and the LP CPU simultaneously. Hart 1 represents the LP CPU. Users
can use OpenOCD to select a hart (0: HP CPU, 1: LP CPU) for debugging.

The LP CPU implements four registers for core debugging: dcsr, dpc, dscratch0, and dscratch1. All of those
registers can only be accessed from debug mode. If software attempts to access them when the LP CPU is
not in debug mode, an illegal instruction exception will be triggered.

3.4.1 Features
The Low-Power CPU has the following debugging features:

• Provides necessary information about the implementation to the debugger.

• Allows the CPU core to be halted and resumed.

• CPU core registers (including CSRs) can be read/written by the debugger.

• CPU core can be reset through the debugger.

• CPU can be halted on software breakpoint (planted breakpoint instruction).

• Hardware single-stepping.

• Two hardware triggers (which can be used as breakpoints/watchpoints). See Section 3.5 for details.

3.4.2 Functional Description

The debugging mechanism adheres to the specification RISC-V External Debug Support Version 0.13. For a
detailed description of the debugging features, refer to the specification.

According to the specification, a hart can be in the following states: nonexistent, unavail, running, and halted.
By default, the LP CPU is in the unavail state. To connect the LP CPU for debugging, users need to clear the
state by configuring the LPPERI_CPU_REG register.

3.4.3 Register Summary

The following table lists the debug CSRs supported for the LP CPU.

Name Description Address Access

dcsr Debug Control and Status 0x7B0 R/W
dpc Debug PC 0x7B1 R/W
dscratch0 Debug Scratch Register 0 0x7B2 R/W
dscratch1 Debug Scratch Register 1 0x7B3 R/W

All debug module registers are implemented in accordance with the specification RISC-V External Debug

Espressif Systems 112 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Support Version 0.13. For more information, refer to the specification.

3.4.4 Registers
The following is a detailed description of the debug CSR supported by the LP CPU.

Register 3.18. dcsr (0x7B0)

er

d)

eb ed)

)
ed

ed
gv

ve

(re m

u
rv

rv

rv
ak

ak
bu

e
se

se

se

se

ep
us
re

re
e

v
(re

(re

(re
xd

eb

pr
ca

st
31 28 27 16 15 14 13 12 11 9 8 6 5 3 2 1 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset

xdebugver Represents the debug version.

4: External debug support exists
(RO)

ebreakm Configures execution of the EBREAK instruction in machine mode.

0: Trigger an exception with mcause = 3
1: Enter debug mode
(R/W)

ebreaku Configures execution of the EBREAK instruction in user mode.

0: Trigger an exception with mcause = 3 as described in privileged mode
1: Enter debug mode
(R/W)

cause Represents the reason why debug mode was entered. When there are multiple reasons to
enter debug mode in a single cycle, the cause with the highest priority number is the one written.
1: An EBREAK instruction was executed. (priority 3)
2: The Trigger Module caused a halt. (priority 4)
3: haltreq was set. (priority 2)
4: The CPU core single stepped because step was set. (priority 1)
Other values: reserved for future use
(RO)

step When set and not in Debug Mode, the core will only execute a single instruction and then
enter Debug Mode.
If the instruction does not complete due to an exception, the core will immediately enter Debug
Mode before executing the trap handler, with appropriate exception registers set.
Setting this bit does not mask interrupts. This is a deviation from the RISC-V External Debug
Support Specification Version 0.13.
(R/W)

prv Contains the privilege level the core is operating in when debug mode is entered. A debugger
can change this value to change the core’s privilege level when exiting debug mode. Only 0x3
(machine mode) and 0x0 (user mode) are supported. (RO)

Espressif Systems 113 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.19. dpc (0x7B1)

c
dp
31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

dpc Upon entry to debug mode, dpc is written with the address of the next instruction that will be
executed. When resuming, the CPU core’s PC is updated to the address stored in dpc. In debug
mode, dpc can be modified. This field can be accessed in debug mode. (R/W)

Register 3.20. dscratch0 (0x7B2)

0
ch
at
cr
ds
31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

dscratch0 Used by the debug module internally. (R/W)

Register 3.21. dscratch1 (0x7B3)

1
ch
at
cr
ds

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

dscratch1 Used by the debug module internally.(R/W)

3.5 Hardware Trigger

3.5.1 Features
Hardware Trigger module provides breakpoint and watchpoint capability for debugging. It has the following
features:

• Two independent trigger units

• Configurable unit to match the address of the program counter

• Able to halt execution and transfer control to the debugger

3.5.2 Functional Description

The hardware trigger module provides three CSRs. See Section 3.5 for details. Among these, tdata1 and
tdata2 are abstract CSRs, which means they are shadow registers for accessing internal registers in the trigger
units, one at a time.

Espressif Systems 114 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

To select a specific trigger unit, the corresponding number (0-1) needs to be written to the tselect CSR. When
a valid value is written, the abstract CSRs, tdata1 and tdata2, automatically match the internal registers of the
trigger unit. Each trigger unit has two internal registers, namely mcontrol and maddress, which are mapped to
tdata1 and tdata2, respectively.

Writing a value more than 1 to tselect will set tselect to 1.

Since software or debugger may need to know the type of the selected trigger to correctly interpret tdata1 and
tdata2, the 4-bit field (31-28) of tdata1 encodes the type of the selected trigger. This type field is read-only
and always provides a value of 0x2 for every trigger, which stands for support for address and data matching.
Hence, it is inferred that tdata1 and tdata2 are to be interpreted as fields of mcontrol and maddress,
respectively. The specification RISC-V External Debug Support Version 0.13 provides information on other
possible values, but the trigger module only supports the 0x2 type.

Once a trigger unit has been chosen by writing its index to tselect, it will become possible to configure it by
setting the appropriate bits in mcontrol CSR (tdata1) and writing the target address to maddress CSR
(tdata2).

3.5.3 Trigger Execution Flow

When a hart is halted and enters debug mode due to the firing of a trigger (action = 1):

• dpc is set to the current PC in the decoding phase

• The cause field in dcsr is set to 2, which means halt due to trigger

3.5.4 Register Summary

Below is a list of Trigger Module CSRs supported by the CPU. These are only accessible from machine
mode.

Name Description Address Access

tselect Trigger Select Register 0x7A0 R/W
tdata1 Trigger Abstract Data 1 0x7A1 R/W
mcontrol tdata1 Shadow Register 0x7A1 R/W
tdata2 Trigger Abstract Data 2 0x7A2 R/W

3.5.5 Registers

Register 3.22. tselect (0x7A0)

ct
ele
ts

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

tselect Configures the index of the selected trigger unit. (R/W)

Espressif Systems 115 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.23. tdata1 (0x7A1)

e
od
pe

ta
dm

da
ty

31 28 27 26 0

0 0 1 0 1 0 x 1 0 4 0 Reset

type Represents the trigger type. This field is reserved since only match type (0x2) triggers are
supported. (RO)

dmode This is set to 1 if a trigger is being used by the debugger. This field is reserved since it is
only supported in debug mode. (RO)

data Configures the abstract tdata1 content. This will always be interpreted as fields of mcontrol
since only match type (0x2) triggers are supported. (R/W)

Register 3.24. tdata2 (0x7A2)

a2
at
td

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

tdata2 Configures the abstract tdata2 content. This will always be interpreted as maddress since
only match type (0x2) triggers are supported. (R/W)

Espressif Systems 116 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.25. mcontrol (0x7A1)

d)
ed

ax

s rve

st ute
rv

km

ch
tim ct
od

o
se

se
n
in

e
tio

ec
el

ad
le

ai
as

or
at
dm
(re

(re
siz

ch
se

ac
t

ex
m

lo
hi

u
31 28 27 26 21 20 19 18 17 16 15 12 11 10 7 6 5 4 3 2 1 0

0x2 0 0x0 0 0 0 0 0001 0 0 0 0 0 0 0 0 0 Reset

dmode Same as dmode in tdata1. (RO)

maskmax Represents the maximum NAPOT range.

0: A byte. Only exact match is supported.
Other values: Not supported.
(RO)

hit Not implemented in hardware. This field remains 0. (RO)

select Configures to select between an address match or a data match.

0: Perform a match on the virtual address
1: Perform a match on the data value loaded or stored, or the instruction executed
Note: Only address match is implemented. This field remains 0.
(RO)

timing Configures when the trigger will take action.

0: Take action before the instruction is executed
1: Take action after the instruction is executed
Note: The field remains 0.
(RO)

sizelo Only match of any size is supported. This field remains 0. (RO)

action Configure action of the selected trigger after it is triggered.

0x0: Cause a breakpoint exception
0x1: Enter debug mode (Valid only when dmode = 1)
Note: Only entering debug mode is supported. This field remains 1.
(RO)

CHAIN Not implemented in hardware. This field remains 0. (RO)

match Configures the trigger to perform the matching operation of the lower data/instruction ad-
dress.
0x0: Exact match. Namely, the address corresponding to a certain byte during the access must
exactly match the value of maddress.
0x1: NAPOT match. Namely, at least one byte during the access is in the NAPOT region specified
in maddress.
Note: Only exact byte match is supported. This field remains 0.
(R/W)

m Set this field to make the selected trigger operate in machine mode. (RO)

S Set this field to make the selected trigger operate in supervisor mode. Operation in supervisor
mode is not supported. This field is always 0. (RO)

Continued on the next page...

Espressif Systems 117 ESP32-C6 TRM (Version 1.0)
Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.25. mcontrol (0x7A1)

Continued from the previous page...

U Set this field to make the selected trigger operate in user mode. Operation in user mode is not
supported. This field is always 0. (RO)

execute Configures whether to enable the selected trigger to match the virtual address of instruc-
tions.
0: Not enable
1: Enable
(R/W)

store Set this field to make the selected trigger match the virtual address of the memory write
operation. Not supported by hardware. This field is always 0. (RO)

load Set this field to make the selected trigger match the virtual address of a memory read operation.
Not supported by hardware. This field is always 0. (RO)

Register 3.26. maddress (0x7A2)

ss
re
d
ad
m

31 0

0x00000000 Reset

maddress Configures the address used by the selected trigger when performing match operation.
(R/W)

3.6 Performance Counter

The LP CPU implements a clock cycle counter mcycle(h), an instruction counter minstret(h), and 10 event
counters mhpmcountern(n:3-12). The clock cycle counter and instruction counter are always available and
each is 64-bit wide. Other performance counters are 40-bit wide each.

By default, all counters are enabled after reset. A counter can be enabled or disabled individually via the
corresponding bit in the mcountinhibit CSR.

As shown in Table 3-5, each counter is dedicated to counting a particular event.

Table 3-5. Performance Counter

Counter Counted Event

mcycle Clock cycles
minstret The number of instructions
mhpmcounter3 Wait cycles for memory access
mhpmcounter4 Wait cycles for fetching instructions

Espressif Systems 118 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Counter Counted Event

mhpmcounter5 The number of memory read operations. An unaligned read is counted as two.
mhpmcounter6 The number of memory write operations. An unaligned write is counted as two.
mhpmcounter7 The number of unconditional jump instructions (jal, jr, jalr)
mhpmcounter8 The number of branch instructions
mhpmcounter9 The number of taken branch instructions
mhpmcounter10 The number of compressed instructions
mhpmcounter11 Wait cycles for multiplication instructions
mhpmcounter12 Wait cycles for division instructions

3.7 System Access

3.7.1 Memory Access
The ESP32-C6 LP CPU can access LP SRAM and HP SRAM. For more information, please refer to Section 5
System and Memory.

• LP SRAM: 16 KB starting from 0x5000_0000 to 0x5000_3FFF, where you can fetch instructions, read
data, write data, etc.

• HP SRAM: 512 KB starting from 0x4080_0000 to 0x4087_FFFF, where you can fetch instructions, read
data, write data, etc.

Note:
The LP CPU has a high latency to access the HP SRAM, but can access the LP SRAM with no latency.

The LP CPU supports the atomic instruction set. Both the LP CPU and the HP CPU can access memory
through atomic instructions, thus achieving atomicity of memory access. For details on the atomic instruction
set, please refer to RISC-V Instruction Set Manual Volume I: Unprivileged ISA, Version 2.2.

3.7.2 Peripheral Access

Table 5-2 in Chapter 5 System and Memory lists the peripherals accessible by the LP CPU and their base
addresses.

3.8 Event Task Matrix Feature

The LP CPU on ESP32-C6 supports the Event Task Matrix (ETM) function, which allows LP CPU’s ETM tasks to
be triggered by any peripherals’ ETM events, or LP CPU’s ETM events to trigger any peripherals’ ETM tasks.
This section introduces the ETM tasks and events related to the LP CPU. For more information, please refer to
Chapter 11 Event Task Matrix (SOC_ETM).

LP CPU can receive the following ETM task:

• ULP_TASK_WAKEUP_CPU: Wakes up the LP CPU.

LP CPU can generate the following ETM events:

• ULP_EVT_ERR_INTR: Indicates that an LP CPU exception occurs.

Espressif Systems 119 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

• ULP_EVT_START_INTR: Indicates that the LP CPU clock is turned on.

3.9 Sleep and Wake-Up Process

3.9.1 Features
• Able to sleep, wake up, and operate independently in the low-power system when the HP CPU is
sleeping

• Able to actively configure registers to enter the sleep status based on software operating status

• Wake-up events:

– The HP CPU setting the register PMU_HP_TRIGGER_LP

– The interrupt state of the LP IO

– ETM events

– The RTC timer timeout

– The LP UART receiving a certain number of RX pulses when REG_UART_WAKEUP_EN is enabled

3.9.2 Process
The LP CPU is in sleep by default and its wake-up module follows the process below to wake it up for work
and make it sleep.

To configure wake-up sources, please refer to Table 3-6.

Sleep Wake-up flow Work Sleep flow Sleep

Software Halt Run (work) Run (slp pre) Halt
LP bus idle

Wake up and Clk on Clk off

Clear stall Start sleep flow Update LP
send power-up
Hardware request to PMU Enable intr
Reset
Sets stall Reset
state to
IDLE
Disable intr enable
release
(Optional)
Wait for PMU to
send completion
signal

stall PMU_LP_CPU_SLP_STALL_EN == 1
Stall stall unstall
unstall PMU_LP_CPU_SLP_STALL_EN == 0

disable PMU_LP_CPU_SLP_BYPASS_INTR_EN == 1
Interrupt disable enable
enable PMU_LP_CPU_SLP_BYPASS_INTR_EN == 0

enable PMU_LP_CPU_SLP_RESET_EN == 1
Reset enable disable
disable PMU_LP_CPU_SLP_RESET_EN == 0

PMU_LP_CPU_SLP_STALL_WAIT

Figure 3-2. Wake-Up and Sleep Flow of LP CPU

The first startup of the LP CPU after power-up depends on the wake-up enable and wake-up source
configuration by the HP CPU.

• Initialization of the LP CPU

Espressif Systems 120 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

– Initialize the LP memory.

– Start the LP CPU. Since the startup of the LP CPU depends on the wake-up process, it is
recommended to use the PMU_HP_TRIGGER_LP register to start the initialization of the LP CPU in
the following way:

* Set PMU_LP_CPU_WAKEUP_EN to 0x1

* Set PMU_HP_TRIGGER_LP to 0x1

* The LP CPU will go through the wake-up process to start running

• Wake-up process:

– The wake-up module receives a wake-up signal and sends a power-up request to the PMU.

– If the current power consumption state (clock, power supply, etc.) meets the requirements of the
LP CPU, the PMU will immediately reply with the completion signal. Otherwise, it will adjust the
power consumption state before replying with the completion signal.

– The wake-up module disables the STALL state of the LP CPU and enables interrupt receiving.

– The wake-up module starts the clock, releases reset (ignore this step if reset is not enabled for
sleep), and starts working.

• Sleep process:

– The LP CPU configures the register PMU_LP_CPU_SLEEP_REQ to enable the wake-up module to
start the sleep process.

– If PMU_LP_CPU_SLP_STALL_EN is 1, the wake-up module enables the STALL state of the LP CPU. If
it is 0, the module does not enable that state.

– The wake-up module waits for PMU_LP_CPU_SLP_STALL_WAIT LP CPU clock cycles, and then
turns off the LP CPU clock. If PMU_LP_CPU_SLP_RESET_EN is 1, the module enables reset of the
LP CPU.

Espressif Systems 121 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

3.9.3 Wake-Up Sources

Table 3-6. Wake Sources

Register Value 1 Wake-Up Source Description

The HP CPU sets the regis-
ter PMU_HP_TRIGGER_LP to
0x1 Register PMU_HP_TRIGGER_LP wake up the LP CPU, and sets
PMU_HP_SW_TRIGGER_INT_CLR to clear
this wake-up source.
The LP UART receives a certain number of RX
pulses. REG_UART_WAKEUP_EN needs to be
0x2 LP UART enabled. For more information, please refer to
Chapter 27 UART Controller (UART, LP_UART,
UHCI).
This wake-up source uses the LP IO interrupt
status register signal. For more information,
0x4 LP IO
please refer to Chapter 7 IO MUX and GPIO
Matrix (GPIO, IO MUX).
Wake-up sources received from ETM can
wake up the LP CPU. For more information,
0x8 ETM
please refer to Chapter 11 Event Task Matrix
(SOC_ETM).
RTC timer target 1 timeout interrupt control.
0x10 RTC timer For more information, please refer to Chapter
12 Low-Power Management.
1 Value of the PMU_LP_CPU_WAKEUP_EN register

3.10 Register Summary

The addresses in this section are relative to Low-Power Peripheral base address provided in Table 5-2 in
Chapter 5 System and Memory.

Name Description Address Access

LPPERI_CPU_REG LP CPU Control Register 0x000C R/W
LPPERI_INTERRUPT_SOURCE_REG LP CPU Interrupt Status Register 0x0020 RO

3.11 Registers
The addresses in this section are relative to Low-Power Peripheral base address provided in Table 5-2 in
Chapter 5 System and Memory.

Espressif Systems 122 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
3 Low-Power CPU GoBack

Register 3.27. LPPERI_CPU_REG (0x000C)

E
BL
IA
AL
AV
N
_U
M
BG
_D
RE
CO
P

d)
_L

ve
RI

r
se
PE

(re
LP

31 30 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

LPPERI_LPCORE_DBGM_UNAVALIABLE Configures the LP CPU state.

0: LP CPU can connect to JTAG
1: LP CPU is unavailable and cannot connect to JTAG
(R/W)

Register 3.28. LPPERI_INTERRUPT_SOURCE_REG (0x0020)

CE
O UR
_S
PT
RU
ER
NT
_I
LP
)
ed

I_
rv

ER
se

P
(re

LP
31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

LPPERI_LP_INTERRUPT_SOURCE Represents the LP interrupt source.

Bit 5: PMU_LP_INT
Bit 4: Reserved
Bit 3: RTC_Timer_LP_INT
Bit 2: LP_UART_INT
Bit 1: LP_I2C_INT
Bit 0: LP_IO_INT
(RO)

Espressif Systems 123 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4 GDMA Controller (GDMA)

4.1 Overview
General Direct Memory Access (GDMA) is a feature that allows peripheral-to-memory, memory-to-peripheral,
and memory-to-memory data transfer at high speed. The CPU is not involved in the GDMA transfer and
therefore is more efficient with less workload.

The GDMA controller in ESP32-C6 has six independent channels, i.e. three transmit channels and three
receive channels. These six channels are shared by peripherals with the GDMA feature, and can be assigned
to any of such peripherals, including SPI2, UHCI (UART0/UART1), I2S, AES, SHA, ADC, and PARLIO. UART0 and
UART1 use UHCI together.

The GDMA controller uses fixed-priority and round-robin channel arbitration schemes to manage peripherals’
needs for bandwidth.

GDMA Channels Modules

Rx channel 0 SPI2

Tx channel 0 UHCI0 (UART0/UART1)

I2S
Rx channel 1
AES
Tx channel 1
SHA

Rx channel 2
ADC

Tx channel 2 PARLIO

Figure 4-1. Modules with GDMA Feature and GDMA Channels

4.2 Features
The GDMA controller has the following features:

• AHB bus architecture

• Programmable length of data to be transferred in bytes

• Linked list of descriptors

• INCR burst transfer when accessing internal RAM

• Access to an address space of 384 KB at most in internal RAM

• Three transmit channels and three receive channels

• Software-configurable selection of peripheral requesting its service

• Fixed channel priority and round-robin channel arbitration

Espressif Systems 124 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4.3 Architecture
In ESP32-C6, all modules that need high-speed data transfer support GDMA. The GDMA controller and CPU
data bus have access to the same address space in internal RAM. Figure 4-2 shows the basic architecture of
the GDMA controller.

GDMA Controller

Rx Channel 0 Peri 0

Tx Channel 0 Peri 1

Internal Rx Channel 1
RAM Peri Peri 2
Arbiter
Select
Tx Channel 1

Rx Channel 2

Tx Channel 2 Peri n

Figure 4-2. GDMA controller Architecture

The GDMA controller has six independent channels, i.e. three transmit channels and three receive channels.
Every channel can be connected to different peripherals. In other words, channels are general-purpose,
shared by peripherals.

The GDMA controller reads data from or writes data to internal RAM via AHB_BUS. Before this, the GDMA
controller uses fixed-priority arbitration scheme for channels requesting read or write access. For available
address range of Internal RAM, please see Chapter 5 System and Memory.

Software can use the GDMA controller through linked lists. These linked lists, stored in internal RAM, consist of
outlinkn and inlinkn, where n indicates the channel number (ranging from 0 to 2). The GDMA controller reads
an outlinkn (i.e. a linked list of transmit descriptors) from internal RAM and transmits data in corresponding
RAM according to the outlinkn, or reads an inlinkn (i.e. a linked list of receive descriptors) and stores received
data into specific address space in RAM according to the inlinkn.

Espressif Systems 125 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4.4 Functional Description

4.4.1 Linked List

Figure 4-3. Structure of a Linked List

Figure 4-3 shows the structure of a linked list. An outlink and an inlink have the same structure. A linked list is
formed by one or more descriptors, and each descriptor consists of three words. Linked lists should be in
internal RAM for the GDMA controller to be able to use them. The meanings of a descriptor’s fields are as
follows:

• owner (DW0) [31]: Specifies who is allowed to access the buffer that this descriptor points to.
0: CPU can access the buffer.
1: The GDMA controller can access the buffer.
When the GDMA controller stops using the buffer, this bit in a receive descriptor is automatically cleared
by hardware, and this bit in a transmit descriptor can only be automatically cleared by hardware if
GDMA_OUT_AUTO_WRBACK_CHn is set to 1. Software can disable automatic clearing by hardware by
setting GDMA_OUT_LOOP_TEST_CHn or GDMA_IN_LOOP_TEST_CHn bit. When software loads a linked
list, this bit should be set to 1.
Note: GDMA_OUT is the prefix of transmit channel registers, and GDMA_IN is the prefix of receive
channel registers.

• suc_eof (DW0) [30]: Specifies whether the GDMA_IN_SUC_EOF_CHn_INT or

GDMA_OUT_EOF_CHn_INT interrupt will be triggered when the data corresponding to this descriptor has
been received or transmitted.
1’b0: No interrupt will be triggered after the current descriptor’s successful transfer;
1’b1: An interrupt will be triggered after the current descriptor’s successful transfer.
For receive descriptors, software needs to clear this bit to 0, and hardware will set it to 1 after receiving
data containing the EOF flag.
For transmit descriptors, software needs to set this bit to 1 as needed.
If software configures this bit to 1 in a descriptor, the GDMA will include the EOF flag in the data sent to
the corresponding peripheral, indicating to the peripheral that this data segment marks the end of one
transfer phase.

Espressif Systems 126 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

• reserved (DW0) [29]: Reserved. Value of this bit does not matter.

• err_eof (DW0) [28]: Specifies whether the received data has errors.
0: The received data does not have errors.
1: The received data has errors.
This bit is used only when UHCI or PARLIO uses GDMA to receive data. When an error is detected in the
received data segment corresponding to a descriptor, this bit in the receive descriptor is set to 1 by
hardware.

• reserved (DW0) [27:24]: Reserved.

• length (DW0) [23:12]: Specifies the number of valid bytes in the buffer that this descriptor points to. This
field in a transmit descriptor is written by software and indicates how many bytes can be read from the
buffer; this field in a receive descriptor is written by hardware automatically and indicates how many valid
bytes have been stored into the buffer.

• size (DW0) [11:0]: Specifies the size of the buffer that this descriptor points to.

• buffer address pointer (DW1): Address of the buffer. This field can only point to internal RAM.

• next descriptor address (DW2): Address of the next descriptor. If the current descriptor is the last one,
this value is 0. This field can only point to internal RAM.

If the length of data received is smaller than the size of the buffer, the GDMA controller will not use available
space of the buffer in the next transaction.

4.4.2 Peripheral-to-Memory and Memory-to-Peripheral Data Transfer

The GDMA controller can transfer data from memory to peripheral (transmit) and from peripheral to memory
(receive). A transmit channel transfers data in the specified memory location to a peripheral’s transmitter via an
outlinkn, whereas a receive channel transfers data received by a peripheral to the specified memory location
via an inlinkn.

Every transmit and receive channel can be connected to any peripheral with GDMA feature. Table 4-1 illustrates
how to select the peripheral to be connected via registers. “Dummy-n” corresponds to register values for
memory-to-memory data transfer. When a channel is connected to a peripheral, the rest channels cannot be
connected to that peripheral.

Table 4-1. Selecting Peripherals via Register Configuration

GDMA_PERI_IN_SEL_CHn
Peripheral
GDMA_PERI_OUT_SEL_CHn
0 SPI2
1 Dummy-1
2 UHCI
3 I2S
4 Dummy-4
5 Dummy-5
6 AES
7 SHA
8 ADC
9 PARLIO

Espressif Systems 127 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

10 ~ 15 Dummy-10 ~ 15
16 ~ 63 Invalid

4.4.3 Memory-to-Memory Data Transfer

The GDMA controller also allows memory-to-memory data transfer. Such data transfer can be enabled by
setting GDMA_MEM_TRANS_EN_CHn, which connects the output of transmit channel n to the input of
receive channel n. Note that a transmit channel is only connected to the receive channel with the same
number (n), and GDMA_PERI_IN_SEL_CHn and GDMA_PERI_OUT_SEL_CHn should be configured to the
same value corresponding to “Dummy”.

4.4.4 Enabling GDMA

Software uses the GDMA controller through linked lists. When the GDMA controller receives data, software
loads an inlink, configures GDMA_INLINK_ADDR_CHn field with address of the first receive descriptor, and sets
GDMA_INLINK_START_CHn bit to enable GDMA. When the GDMA controller transmits data, software loads an
outlink, prepares data to be transmitted, configures GDMA_OUTLINK_ADDR_CHn field with address of the first
transmit descriptor, and sets GDMA_OUTLINK_START_CHn bit to enable GDMA. GDMA_INLINK_START_CHn bit
and GDMA_OUTLINK_START_CHn bit are cleared automatically by hardware.

In some cases, you may want to append more descriptors to a DMA transfer that is already started. Naively, it
would seem to be possible to do this by clearing the EOF bit of the final descriptor in the existing list and
setting its next descriptor address pointer field (DW2) to the first descriptor of the to-be-added list. However,
this strategy fails if the existing DMA transfer is almost or entirely finished. Instead, the GDMA controller has
specialized logic to make sure a DMA transfer can be continued or restarted: if the transfer is ongoing, the
controller will make sure to take the appended descriptors into account; if the transfer has already finished,
the controller will restart with the new descriptors. This is implemented by the Restart function.

When using the Restart function, software needs to rewrite address of the first descriptor in the new list to
DW2 of the last descriptor in the loaded list, and set GDMA_INLINK_RESTART_CHn bit or
GDMA_OUTLINK_RESTART_CHn bit (these two bits are cleared automatically by hardware). As shown in Figure
4-4, by doing so hardware can obtain the address of the first descriptor in the new list when reading the last
descriptor in the loaded list, and then read the new list.

Figure 4-4. Relationship among Linked Lists

Espressif Systems 128 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4.4.5 Linked List Reading Process

Once configured and enabled by software, the GDMA controller starts to read the linked list from internal RAM.
The GDMA performs checks on descriptors in the linked list. Only if descriptors pass the checks, the
corresponding GDMA channel will start data transfer. If the descriptors fail any of the checks, hardware will
trigger descriptor error interrupt (either GDMA_IN_DSCR_ERR_CHn_INT or
GDMA_OUT_DSCR_ERR_CHn_INT), and the channel will halt.

The checks performed on descriptors are:

• Owner bit check when GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn is set to 1.

If the owner bit is 0, the buffer is accessed by the CPU. In this case, the owner bit fails the check. The
owner bit will not be checked if GDMA_IN_CHECK_OWNER_CHn or GDMA_OUT_CHECK_OWNER_CHn is
0.

• Buffer address pointer (DW1) check. If the buffer address pointer points to 0x40800000 ~ 0x4087FFFF
(please refer to Section 4.4.7), it passes the check. Otherwise it fails the check.

After software detects a descriptor error interrupt, it must reset the corresponding channel, and enable GDMA
by setting GDMA_OUTLINK_START_CHn or GDMA_INLINK_START_CHn bit.

Note: The third word (DW2) in a descriptor can only point to a location in internal RAM, given that the third
word points to the next descriptor to use and that all descriptors must be in internal memory.

4.4.6 EOF
The GDMA controller uses EOF (end of frame) flags to indicate the end of data segment transfer
corresponding to a specific descriptor.

Before the GDMA controller transmits data, GDMA_OUT_TOTAL_EOF_CHn_INT_ENA bit should be set to enable
GDMA_OUT_TOTAL_EOF_CHn_INT interrupt. If data in the buffer pointed by the last descriptor (with EOF) has
been transmitted, a GDMA_OUT_TOTAL_EOF_CHn_INT interrupt is generated.

Before the GDMA controller receives data, GDMA_IN_SUC_EOF_CHn_INT_ENA bit should be set to enable
GDMA_IN_SUC_EOF_CHn_INT interrupt. If a data segment with an EOF flag has been received successfully, a
GDMA_IN_SUC_EOF_CHn_INT interrupt is generated. In addition, when GDMA channel is connected to UHCI
or PARLIO, the GDMA controller also supports GDMA_IN_ERR_CHn_EOF_INT interrupt. This interrupt is
enabled by setting GDMA_IN_ERR_EOF_CHn_INT_ENA bit, and it indicates that a data segment corresponding
to a descriptor has been received with errors.

When detecting a GDMA_OUT_TOTAL_EOF_CHn_INT or a GDMA_IN_SUC_EOF_CHn_INT interrupt, software

can record the value of GDMA_OUT_EOF_DES_ADDR_CHn or GDMA_IN_SUC_EOF_DES_ADDR_CHn field, i.e.
address of the last descriptor. Therefore, software can tell which descriptors have been used and reclaim
them as needed.

Note: In this chapter, EOF of transmit descriptors refers to suc_eof, while EOF of receive descriptors refers to
both suc_eof and err_eof.

4.4.7 Accessing Internal RAM

Any transmit and receive channels of GDMA can access 0x40800000 ~ 0x4087FFFF in internal RAM. To
improve data transfer efficiency, GDMA can send data in burst mode, which is disabled by default. This mode

Espressif Systems 129 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

is enabled for receive channels by setting GDMA_IN_DATA_BURST_EN_CHn, and enabled for transmit
channels by setting GDMA_OUT_DATA_BURST_EN_CHn.

Table 4-2. Descriptor Field Alignment Requirements

Inlink/Outlink Burst Mode Size Length Buffer Address Pointer

0 — — —
Inlink
1 Word-aligned — Word-aligned
0 — — —
Outlink
1 — — —

Table 4-2 lists the requirements for descriptor field alignment when accessing internal RAM.

When burst mode is disabled, size, length, and buffer address pointer in both transmit and receive descriptors
do not need to be word-aligned. That is, for a descriptor, GDMA can read data of specified length (1 ~ 4095
bytes) from any start addresses in the accessible address range, or write received data of the specified length
(1 ~ 4095 bytes) to any contiguous addresses in the accessible address range.

When burst mode is enabled, size, length, and buffer address pointer in transmit descriptors are also not
necessarily word-aligned. However, size and buffer address pointer in receive descriptors except length
should be word-aligned.

4.4.8 Arbitration
To ensure timely response to peripherals running at a high speed with low latency (such as SPI), the GDMA
controller implements a fixed-priority channel arbitration scheme. That is to say, each channel can be
assigned a priority from 0 ~ 5 (in total 6 levels). The larger the number, the higher the priority, and the more
timely the response. When several channels are assigned the same priority, the GDMA controller adopts a
round-robin arbitration scheme.

4.4.9 Event Task Matrix Feature

The GDMA controller on ESP32-C6 supports the Event Task Matrix (ETM) function, which allows GDMA’s ETM
tasks to be triggered by any peripherals’ ETM events, or GDMA’s ETM events to trigger any peripherals’ ETM
tasks. This section introduces the ETM tasks and events related to GDMA. For more information, please refer
to Chapter 11 Event Task Matrix (SOC_ETM).

GDMA can receive the following ETM tasks:

• GDMA_TASK_IN_START_CHn: Enables the corresponding RX channel n for data transfer.

• GDMA_TASK_OUT_START_CHn: Enables the corresponding TX channel n for data transfer.

Note:
Above ETM tasks can achieve the same functions as CPU configuring GDMA_INLNIK_START_CHn and GDMA_OUTLINK_START_CHn.
When GDMA_IN_ETM_EN_CHn or GDMA_OUT_ETM_EN_CHn is 1, only ETM tasks can be used to configure the transfer
direction and enable the corresponding GDMA channel. When GDMA_IN_ETM_EN_CHn or GDMA_OUT_ETM_EN_CHn
is 0, only CPU can be used to enable the corresponding GDMA channel.

GDMA can generate the following ETM events:

Espressif Systems 130 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

• GDMA_EVT_IN_DONE_CHn: Indicates that the data has been received according to the receive
descriptor via channel n.

• GDMA_EVT_IN_SUC_EOF_CHn: Indicates that the data corresponding to a receive descriptor has been
received via channel n and the EOF bit of this descriptor is 1.

• GDMA_EVT_IN_FIFO_EMPTY_CHn: Indicates that the RX FIFO has become empty.

• GDMA_EVT_IN_FIFO_FULL_CHn: Indicates that the RX FIFO has become full.

• GDMA_EVT_OUT_DONE_CHn: Indicates that the data has been transmitted according to the transmit
descriptor via channel n.

• GDMA_EVT_OUT_SUC_EOF_CHn: Indicates that the data corresponding to a transmit descriptor has

been transmitted or received via channel n and the EOF bit of this descriptor is 1.

• GDMA_EVT_OUT_TOTAL_EOF_CHn: Indicates that the data corresponding to the last transmit descriptors
has been sent via transmit channel n and the EOF bit of this descriptor is 1.

• GDMA_EVT_OUT_FIFO_EMPTY_CHn: Indicates that the TX FIFO has become empty.

• GDMA_EVT_OUT_FIFO_FULL_CHn: Indicates that the TX FIFO has become full.

In practical applications, GDMA’s ETM events can trigger its own ETM tasks. For example, the
GDMA_EVT_OUT_TOTAL_EOF_CH0 event can trigger the GDMA_TASK_IN_START_CH1 task, and in this way
trigger a new round of GDMA operations.

4.5 GDMA Interrupts

• GDMA_OUT_TOTAL_EOF_CHn_INT: Triggered when all data corresponding to a linked list (including
multiple descriptors) has been sent via transmit channel n.

• GDMA_IN_DSCR_EMPTY_CHn_INT: Triggered when the size of the buffer pointed by receive descriptors
is smaller than the length of data to be received via receive channel n.

• GDMA_OUT_DSCR_ERR_CHn_INT: Triggered when an error is detected in a transmit descriptor on

transmit channel n.

• GDMA_IN_DSCR_ERR_CHn_INT: Triggered when an error is detected in a receive descriptor on receive

channel n.

• GDMA_OUT_EOF_CHn_INT: Triggered when EOF in a transmit descriptor is 1 and data corresponding to

this descriptor has been sent via transmit channel n. If GDMA_OUT_EOF_MODE_CHn is 0, this interrupt
will be triggered when the last byte of data corresponding to this descriptor enters GDMA’s transmit
channel; if GDMA_OUT_EOF_MODE_CHn is 1, this interrupt is triggered when the last byte of data is
taken from GDMA’s transmit channel.

• GDMA_OUT_DONE_CHn_INT: Triggered when all data corresponding to a transmit descriptor has been
sent via transmit channel n.

• GDMA_IN_ERR_EOF_CHn_INT: Triggered when an error is detected in the data segment corresponding

to a descriptor received via receive channel n. This interrupt is used only for UHCI peripheral (UART0 or
UART1) or PARLIO.

• GDMA_IN_SUC_EOF_CHn_INT: Triggered when the suc_eof bit in a receive descriptor is 1 and the data
corresponding to this receive descriptor has been received via receive channel n.

Espressif Systems 131 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

• GDMA_IN_DONE_CHn_INT: Triggered when all data corresponding to a receive descriptor has been
received via receive channel n.

4.6 Programming Procedures

The clock gating for GDMA can be configured via PCR_GDMA_CLK_EN, and is enabled by default. GDMA can
be reset by configuring PCR_GDMA_RST_EN.

4.6.1 Programming Procedures for GDMA’s Transmit Channel

To transmit data, GDMA’s transmit channel should be configured by software as follows:

1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer.

2. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor.

3. Configure GDMA_PERI_OUT_SEL_CHn with the value corresponding to the peripheral to be connected,

as shown in Table 4-1.

4. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer.

5. Configure and enable the corresponding peripheral (SPI2, UHCI (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals.

6. Wait for GDMA_OUT_TOTAL_EOF_CHn_INT interrupt, which indicates the completion of data transfer.

4.6.2 Programming Procedures for GDMA’s Receive Channel

To receive data, GDMA’s receive channel should be configured by software as follows:

1. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel
and FIFO pointer.

2. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor.

3. Configure GDMA_PERI_IN_SEL_CHn with the value corresponding to the peripheral to be connected, as

shown in Table 4-1.

4. Set GDMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer.

5. Configure and enable the corresponding peripheral (SPI2, UHCI (UART0 or UART1), I2S, AES, SHA, and
ADC). See details in individual chapters of these peripherals.

4.6.3 Programming Procedures for Memory-to-Memory Transfer

To transfer data from one memory location to another, GDMA should be configured by software as
follows:

1. Set GDMA_OUT_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s transmit channel
and FIFO pointer.

2. Set GDMA_IN_RST_CHn first to 1 and then to 0, to reset the state machine of GDMA’s receive channel
and FIFO pointer.

3. Load an outlink, and configure GDMA_OUTLINK_ADDR_CHn with address of the first transmit descriptor.

Espressif Systems 132 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4. Load an inlink, and configure GDMA_INLINK_ADDR_CHn with address of the first receive descriptor.

5. Set GDMA_MEM_TRANS_EN_CHn to enable memory-to-memory transfer.

6. Set GDMA_OUTLINK_START_CHn to enable GDMA’s transmit channel for data transfer.

7. Set GDMA_INLINK_START_CHn to enable GDMA’s receive channel for data transfer.

8. If the suc_eof bit is set in a transmit descriptor, a GDMA_IN_SUC_EOF_CHn_INT interruptwill be

triggered when the data segment corresponding to this descriptor has been transmitted.

Espressif Systems 133 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4.7 Register Summary

The addresses in this section are relative to GDMA base address provided in Table 5-2 in Chapter 5 System
and Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

Interrupt Registers
GDMA_IN_INT_RAW_CH0_REG Raw interrupt status of RX channel 0 0x0000 R/WTC/SS
GDMA_IN_INT_ST_CH0_REG Masked interrupt status of RX channel 0x0004 RO
0
GDMA_IN_INT_ENA_CH0_REG Interrupt enable bits of RX channel 0 0x0008 R/W
GDMA_IN_INT_CLR_CH0_REG Interrupt clear bits of RX channel 0 0x000C WT
GDMA_IN_INT_RAW_CH1_REG Raw interrupt status interrupt of TX 0x0010 R/WTC/SS
channel 1
GDMA_IN_INT_ST_CH1_REG Masked interrupt status of TX channel 1 0x0014 RO
GDMA_IN_INT_ENA_CH1_REG Interrupt enable bits of TX channel 1 0x0018 R/W
GDMA_IN_INT_CLR_CH1_REG Interrupt clear bits of TX channel 1 0x001C WT
GDMA_IN_INT_RAW_CH2_REG Raw interrupt status of RX channel 2 0x0020 R/WTC/SS
GDMA_IN_INT_ST_CH2_REG Masked interrupt status of RX channel 0x0024 RO
2
GDMA_IN_INT_ENA_CH2_REG Interrupt enable bits of RX channel 2 0x0028 R/W
GDMA_IN_INT_CLR_CH2_REG Interrupt clear bits of RX channel 2 0x002C WT
GDMA_OUT_INT_RAW_CH0_REG Raw interrupt status of TX channel 0 0x0030 R/WTC/SS
GDMA_OUT_INT_ST_CH0_REG Masked interrupt status of TX channel 0x0034 RO
0
GDMA_OUT_INT_ENA_CH0_REG Interrupt enable bits of TX channel 0 0x0038 R/W
GDMA_OUT_INT_CLR_CH0_REG Interrupt clear bits of TX channel 0 0x003C WT
GDMA_OUT_INT_RAW_CH1_REG Raw interrupt status of TX channel 1 0x0040 R/WTC/SS
GDMA_OUT_INT_ST_CH1_REG Masked interrupt status of TX channel 1 0x0044 RO
GDMA_OUT_INT_ENA_CH1_REG Interrupt enable bits of TX channel 1 0x0048 R/W
GDMA_OUT_INT_CLR_CH1_REG Interrupt clear bits of TX channel 1 0x004C WT
GDMA_OUT_INT_RAW_CH2_REG Raw interrupt status of TX channel 2 0x0050 R/WTC/SS
GDMA_OUT_INT_ST_CH2_REG Masked interrupt status of TX channel 2 0x0054 RO
GDMA_OUT_INT_ENA_CH2_REG Interrupt enable bits of TX channel 2 0x0058 R/W
GDMA_OUT_INT_CLR_CH2_REG Interrupt clear bits of TX channel 2 0x005C WT
Debug Registers
GDMA_AHB_TEST_REG Reserved 0x0060 R/W
Configuration Registers
GDMA_MISC_CONF_REG Miscellaneous register 0x0064 R/W
GDMA_IN_CONF0_CH0_REG Configuration register 0 of RX channel 0x0070 R/W
0
GDMA_IN_CONF1_CH0_REG Configuration register 1 of RX channel 0 0x0074 R/W
GDMA_IN_POP_CH0_REG Pop control register of RX channel 0 0x007C varies

Espressif Systems 134 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Name Description Address Access

GDMA_IN_LINK_CH0_REG Linked list descriptor configuration and 0x0080 varies
control register of RX channel 0
GDMA_OUT_CONF0_CH0_REG Configuration register 0 of TX channel 0x00D0 R/W
0
GDMA_OUT_CONF1_CH0_REG Configuration register 1 of TX channel 0 0x00D4 R/W
GDMA_OUT_PUSH_CH0_REG Push control register of RX channel 0 0x00DC varies
GDMA_OUT_LINK_CH0_REG Linked list descriptor configuration and 0x00E0 varies
control register of TX channel 0
GDMA_IN_CONF0_CH1_REG Configuration register 0 of RX channel 1 0x0130 R/W
GDMA_IN_CONF1_CH1_REG Configuration register 1 of RX channel 1 0x0134 R/W
GDMA_IN_POP_CH1_REG Pop control register of RX channel 1 0x013C varies
GDMA_IN_LINK_CH1_REG Linked list descriptor configuration and 0x0140 varies
control register of RX channel 1
GDMA_OUT_CONF0_CH1_REG Configuration register 0 of TX channel 1 0x0190 R/W
GDMA_OUT_CONF1_CH1_REG Configuration register 1 of TX channel 1 0x0194 R/W
GDMA_OUT_PUSH_CH1_REG Push control register of RX channel 1 0x019C varies
GDMA_OUT_LINK_CH1_REG Linked list descriptor configuration and 0x01A0 varies
control register of TX channel 1
GDMA_IN_CONF0_CH2_REG Configuration register 0 of RX channel 0x01F0 R/W
2
GDMA_IN_CONF1_CH2_REG Configuration register 1 of RX channel 2 0x01F4 R/W
GDMA_IN_POP_CH2_REG Pop control register of RX channel 2 0x01FC varies
GDMA_IN_LINK_CH2_REG Linked list descriptor configuration and 0x0200 varies
control register of RX channel 2
GDMA_OUT_CONF0_CH2_REG Configuration register 0 of TX channel 2 0x0250 R/W
GDMA_OUT_CONF1_CH2_REG Configuration register 1 of TX channel 2 0x0254 R/W
GDMA_OUT_PUSH_CH2_REG Push control register of RX channel 2 0x025C varies
GDMA_OUT_LINK_CH2_REG Linked list descriptor configuration and 0x0260 varies
control register of TX channel 2
Version Register
GDMA_DATE_REG Version control register 0x0068 R/W
Status Registers
GDMA_INFIFO_STATUS_CH0_REG Receive FIFO status of RX channel 0 0x0078 RO
GDMA_IN_STATE_CH0_REG Receive status of RX channel 0 0x0084 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG Receive descriptor address when EOF 0x0088 RO
occurs on RX channel 0
GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG Receive descriptor address when er- 0x008C RO
rors occur of RX channel 0
GDMA_IN_DSCR_CH0_REG Address of the next receive descriptor 0x0090 RO
pointed by the current pre-read receive
descriptor on RX channel 0
GDMA_IN_DSCR_BF0_CH0_REG Address of the current pre-read receive 0x0094 RO
descriptor on RX channel 0

Espressif Systems 135 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Name Description Address Access

GDMA_IN_DSCR_BF1_CH0_REG Address of the previous pre-read re- 0x0098 RO
ceive descriptor on RX channel 0
GDMA_OUTFIFO_STATUS_CH0_REG Transmit FIFO status of TX channel 0 0x00D8 RO
GDMA_OUT_STATE_CH0_REG Transmit status of TX channel 0 0x00E4 RO
GDMA_OUT_EOF_DES_ADDR_CH0_REG Transmit descriptor address when EOF 0x00E8 RO
occurs on TX channel 0
GDMA_OUT_EOF_BFR_DES_ADDR_CH0 The last transmit descriptor address 0x00EC RO
_REG when EOF occurs on TX channel 0
GDMA_OUT_DSCR_CH0_REG Address of the next transmit descriptor 0x00F0 RO
pointed by the current pre-read trans-
mit descriptor on TX channel 0
GDMA_OUT_DSCR_BF0_CH0_REG Address of the current pre-read trans- 0x00F4 RO
mit descriptor on TX channel 0
GDMA_OUT_DSCR_BF1_CH0_REG Address of the previous pre-read trans- 0x00F8 RO
mit descriptor on TX channel 0
GDMA_INFIFO_STATUS_CH1_REG Receive FIFO status of RX channel 1 0x0138 RO
GDMA_IN_STATE_CH1_REG Receive status of RX channel 1 0x0144 RO
GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG Receive descriptor address when EOF 0x0148 RO
occurs on RX channel 1
GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG Receive descriptor address when er- 0x014C RO
rors occur of RX channel 1
GDMA_IN_DSCR_CH1_REG Address of the next receive descriptor 0x0150 RO
pointed by the current pre-read receive
descriptor on RX channel 1
GDMA_IN_DSCR_BF0_CH1_REG Address of the current pre-read receive 0x0154 RO
descriptor on RX channel 1
GDMA_IN_DSCR_BF1_CH1_REG Address of the previous pre-read re- 0x0158 RO
ceive descriptor on RX channel 1
GDMA_OUTFIFO_STATUS_CH1_REG Transmit FIFO status of TX channel 1 0x0198 RO
GDMA_OUT_STATE_CH1_REG Transmit status of TX channel 1 0x01A4 RO
GDMA_OUT_EOF_DES_ADDR_CH1_REG Transmit descriptor address when EOF 0x01A8 RO
occurs on TX channel 1
GDMA_OUT_EOF_BFR_DES_ADDR_CH1 The last transmit descriptor address 0x01AC RO
_REG when EOF occurs on TX channel 1
GDMA_OUT_DSCR_CH1_REG Address of the next transmit descriptor 0x01B0 RO
pointed by the current pre-read trans-
mit descriptor on TX channel 1
GDMA_OUT_DSCR_BF0_CH1_REG Address of the current pre-read trans- 0x01B4 RO
mit descriptor on TX channel 1
GDMA_OUT_DSCR_BF1_CH1_REG Address of the previous pre-read trans- 0x01B8 RO
mit descriptor on TX channel 1
GDMA_INFIFO_STATUS_CH2_REG Receive FIFO status of RX channel 2 0x01F8 RO
GDMA_IN_STATE_CH2_REG Receive status of RX channel 2 0x0204 RO

Espressif Systems 136 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Name Description Address Access

GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG Receive descriptor address when EOF 0x0208 RO
occurs on RX channel 2
GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG Receive descriptor address when er- 0x020C RO
rors occur of RX channel 2
GDMA_IN_DSCR_CH2_REG Address of the next receive descriptor 0x0210 RO
pointed by the current pre-read receive
descriptor on RX channel 2
GDMA_IN_DSCR_BF0_CH2_REG Address of the current pre-read receive 0x0214 RO
descriptor on RX channel 2
GDMA_IN_DSCR_BF1_CH2_REG Address of the previous pre-read re- 0x0218 RO
ceive descriptor on RX channel 2
GDMA_OUTFIFO_STATUS_CH2_REG Transmit FIFO status of TX channel 2 0x0258 RO
GDMA_OUT_STATE_CH2_REG Transmit status of TX channel 2 0x0264 RO
GDMA_OUT_EOF_DES_ADDR_CH2_REG Transmit descriptor address when EOF 0x0268 RO
occurs on TX channel 2
GDMA_OUT_EOF_BFR_DES_ADDR_CH2 The last transmit descriptor address 0x026C RO
_REG when EOF occurs on TX channel 2
GDMA_OUT_DSCR_CH2_REG Address of the next transmit descriptor 0x0270 RO
pointed by the current pre-read trans-
mit descriptor on TX channel 2
GDMA_OUT_DSCR_BF0_CH2_REG Address of the current pre-read trans- 0x0274 RO
mit descriptor on TX channel 2
GDMA_OUT_DSCR_BF1_CH2_REG Address of the previous pre-read trans- 0x0278 RO
mit descriptor on TX channel 2
Priority Registers
GDMA_IN_PRI_CH0_REG Priority register of RX channel 0 0x009C R/W
GDMA_OUT_PRI_CH0_REG Priority register of TX channel 0 0x00FC R/W
GDMA_IN_PRI_CH1_REG Priority register of RX channel 1 0x015C R/W
GDMA_OUT_PRI_CH1_REG Priority register of TX channel 1 0x01BC R/W
GDMA_IN_PRI_CH2_REG Priority register of RX channel 2 0x021C R/W
GDMA_OUT_PRI_CH2_REG Priority register of TX channel 2 0x027C R/W
Peripheral Selection Registers
GDMA_IN_PERI_SEL_CH0_REG Peripheral selection register of RX 0x00A0 R/W
channel 0
GDMA_OUT_PERI_SEL_CH0_REG Peripheral selection register of TX 0x0100 R/W
channel 0
GDMA_IN_PERI_SEL_CH1_REG Peripheral selection register of RX 0x0160 R/W
channel 1
GDMA_OUT_PERI_SEL_CH1_REG Peripheral selection register of TX 0x01C0 R/W
channel 1
GDMA_IN_PERI_SEL_CH2_REG Peripheral selection register of RX 0x0220 R/W
channel 2
GDMA_OUT_PERI_SEL_CH2_REG Peripheral selection register of TX 0x0280 R/W
channel 2

Espressif Systems 137 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

4.8 Registers
The addresses in this section are relative to GDMA base address provided in Table 5-2 in Chapter 5 System
and Memory.

Register 4.1. GDMA_IN_INT_RAW_CHn_REG (n: 0-2) (0x0000+0x10*n)

E_ _C _IN T_R RAW

CH H0 T_ AW

RA AW
ON OF H0 IN T_

IN T_ W
GD A_ _ER R_E PT INT AW
A_ S E _ H W

0_ _IN RA
_D _E C 0_ IN
M IN_ R_ RR Y_C _RA

T_ R
W
M IN C M _ _R

IN UC OF_ CH 0_
GD A_ _DS R_E CH0 INT
M IN C F_ _
GD A_ _DS OV CH0
M IN O_ F_
GD A_ FIF UD
M IN O_
GD A_ IF
M INF
)
ed

GD A _
rv
se

M
GD
(re

31 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_DONE_CHn_INT_RAW The raw interrupt status of GDMA_IN_DONE_CHn_INT.

(R/WTC/SS)

GDMA_IN_SUC_EOF_CHn_INT_RAW The raw interrupt status of GDMA_IN_SUC_EOF_CHn_INT. For

UHCI this bit turns to 1 when the last data byte pointed by one receive descriptor has been
received and no data error is detected for RX channel 0. (R/WTC/SS)

GDMA_IN_ERR_EOF_CHn_INT_RAW The raw interrupt status of GDMA_IN_ERR_EOF_CHn_INT.

Valid only for UHCI or PARLIO. (R/WTC/SS)

GDMA_IN_DSCR_ERR_CHn_INT_RAW The raw interrupt status of GDMA_IN_DSCR_ERR_CHn_INT.

(R/WTC/SS)

GDMA_IN_DSCR_EMPTY_CHn_INT_RAW The raw interrupt status of

GDMA_IN_DSCR_EMPTY_CHn_INT. (R/WTC/SS)

GDMA_INFIFO_OVF_CHn_INT_RAW The raw interrupt status of GDMA_INFIFO_OVF_CHn_INT.

(R/WTC/SS)

GDMA_INFIFO_UDF_CHn_INT_RAW The raw interrupt status of GDMA_INFIFO_UDF_CHn_INT.

(R/WTC/SS)

Espressif Systems 138 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.2. GDMA_IN_INT_ST_CHn_REG (n: 0-2) (0x0004+0x10*n)

E_ _C _IN T_S T
ON OF H0 IN T_S
CH H0 T_ T

T_ ST
0_ _IN ST
_D _E C 0_ IN
GD A_ _ER R_E PT INT T
M IN_ R_ RR Y_C _ST
M IN C M _ _S

IN UC OF_ CH 0_

IN T_
ST
GD A_ _DS R_E CH0 INT

A_ S E _ H
M IN C F_ _
GD A_ _DS OV CH0
M IN O_ F_
GD A_ FIF UD
M IN O_
GD A_ IF
M INF
d)
ve

GD A_
r
se

M
GD
(re
31 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_DONE_CHn_INT_ST The masked interrupt status of GDMA_IN_DONE_CHn_INT. (RO)

GDMA_IN_SUC_EOF_CHn_INT_ST The masked interrupt status of GDMA_IN_SUC_EOF_CHn_INT.

(RO)

GDMA_IN_ERR_EOF_CHn_INT_ST The masked interrupt status of GDMA_IN_ERR_EOF_CHn_INT.

(RO)

GDMA_IN_DSCR_ERR_CHn_INT_ST The masked interrupt status of

GDMA_IN_DSCR_ERR_CHn_INT. (RO)

GDMA_IN_DSCR_EMPTY_CHn_INT_ST The masked interrupt status of

GDMA_IN_DSCR_EMPTY_CHn_INT. (RO)

GDMA_INFIFO_OVF_CHn_INT_ST The masked interrupt status of GDMA_INFIFO_OVF_CHn_INT.

(RO)

GDMA_INFIFO_UDF_CHn_INT_ST The masked interrupt status of GDMA_INFIFO_UDF_CHn_INT.

(RO)

Espressif Systems 139 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.3. GDMA_IN_INT_ENA_CHn_REG (n: 0-2) (0x0008+0x10*n)

E_ _C _IN T_E ENA

CH H0 T_ NA
ON OF H0 IN T_

EN NA
IN T_ A
GD A_ _ER R_E PT INT NA
A_ S E _ H A

0_ _IN EN
_D _E C 0_ IN
M IN_ R_ RR Y_C _EN

T_ E
A
M IN C M _ _E

IN UC OF_ CH 0_
GD A_ _DS R_E CH0 INT
M IN C F_ _
GD A_ _DS OV CH0
M IN O_ F_
GD A_ FIF UD
M IN O_
GD A_ FIF
)
ed

M IN
GD A _
rv
se

M
GD
(re
31 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_DONE_CHn_INT_ENA Write 1 to enable GDMA_IN_DONE_CHn_INT. (R/W)

GDMA_IN_SUC_EOF_CHn_INT_ENA Write 1 to enable GDMA_IN_SUC_EOF_CHn_INT. (R/W)

GDMA_IN_ERR_EOF_CHn_INT_ENA Write 1 to enable GDMA_IN_ERR_EOF_CHn_INT. (R/W)

GDMA_IN_DSCR_ERR_CHn_INT_ENA Write 1 to enable GDMA_IN_DSCR_ERR_CHn_INT. (R/W)

GDMA_IN_DSCR_EMPTY_CHn_INT_ENA Write 1 to enable GDMA_IN_DSCR_EMPTY_CHn_INT.

(R/W)

GDMA_INFIFO_OVF_CHn_INT_ENA Write 1 to enable GDMA_INFIFO_OVF_CHn_INT. (R/W)

GDMA_INFIFO_UDF_CHn_INT_ENA Write 1 to enable GDMA_INFIFO_UDF_CHn_INT. (R/W)

Espressif Systems 140 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.4. GDMA_IN_INT_CLR_CHn_REG (n: 0-2) (0x000C+0x10*n)

E_ _C _IN T_C LR
ON OF H0 IN T_C
CH H0 T_ LR

CL LR
IN T_ R
GD A_ _ER R_E PT INT LR
A_ S E _ H R

0_ _IN CL
_D _E C 0_ IN

T_ C
M IN_ R_ RR Y_C _CL

R
M IN C M _ _C

IN UC OF_ CH 0_
GD A_ _DS R_E CH0 INT
M IN C F_ _
GD A_ _DS OV CH0
M IN O_ F_
GD A_ FIF UD
M IN O_
GD A_ IF
M INF
d)
ve

GD A_
r
se

M
GD
(re
31 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_DONE_CHn_INT_CLR Write 1 to clear GDMA_IN_DONE_CHn_INT. (WT)

GDMA_IN_SUC_EOF_CHn_INT_CLR Write 1 to clear GDMA_IN_SUC_EOF_CHn_INT. (WT)

GDMA_IN_ERR_EOF_CHn_INT_CLR Write 1 to clear GDMA_IN_ERR_EOF_CHn_INT. (WT)

GDMA_IN_DSCR_ERR_CHn_INT_CLR Write 1 to clear GDMA_IN_DSCR_ERR_CHn_INT. (WT)

GDMA_IN_DSCR_EMPTY_CHn_INT_CLR Write 1 to clear GDMA_IN_DSCR_EMPTY_CHn_INT. (WT)

GDMA_INFIFO_OVF_CHn_INT_CLR Write 1 to clear GDMA_INFIFO_OVF_CHn_INT. (WT)

GDMA_INFIFO_UDF_CHn_INT_CLR Write 1 to clear GDMA_INFIFO_UDF_CHn_INT. (WT)

Espressif Systems 141 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.5. GDMA_OUT_INT_RAW_CHn_REG (n: 0-2) (0x0030+0x10*n)

H0 _R NT_ W
W
_C INT _I RA
_I AW RA
OU EO _E F_C NT AW
DO CH _C _I W
T_ F_ RR H0 _RA
NE 0_ H0 NT_

AW
A_ T_ CR O _I R
M OU DS _E H0 T_

_R
GD A_ T_ TAL _C _IN

NT
M OU O VF H0
GD A_ T_T _O F_C
M OU IFO D
GD A_ TF _U
M OU IFO
GD A _ TF
M OU
d)
ve

GD A _
r
se

M
GD
(re
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUT_DONE_CHn_INT_RAW The raw interrupt status of GDMA_OUT_DONE_CHn_INT.

(R/WTC/SS)

GDMA_OUT_EOF_CHn_INT_RAW The raw interrupt status of GDMA_OUT_EOF_CHn_INT.

(R/WTC/SS)

GDMA_OUT_DSCR_ERR_CHn_INT_RAW The raw interrupt status of

GDMA_OUT_DSCR_ERR_CHn_INT. (R/WTC/SS)

GDMA_OUT_TOTAL_EOF_CHn_INT_RAW The raw interrupt status of

GDMA_OUT_TOTAL_EOF_CHn_INT. (R/WTC/SS)

GDMA_OUTFIFO_OVF_CHn_INT_RAW The raw interrupt status of GDMA_OUTFIFO_OVF_CHn_INT.

(R/WTC/SS)

GDMA_OUTFIFO_UDF_CHn_INT_RAW The raw interrupt status of GDMA_OUTFIFO_UDF_CHn_INT.

(R/WTC/SS)

Espressif Systems 142 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.6. GDMA_OUT_INT_ST_CHn_REG (n: 0-2) (0x0034+0x10*n)

_C INT _I ST
_I T ST
OU EO _E F_C NT T

NE 0_ H0 NT_
T_ F_ RR H0 _ST

H0 _S NT_
A_ T_ CR O _I S
M OU DS _E H0 T_

T
DO CH _C _I

_S
GD A_ T_ TAL _C _IN

NT
M OU O VF H0
GD A_ T_T _O F_C
M OU IFO D
GD A_ TF _U
M OU IFO
GD A _ TF
M OU
d)
ve

GD A _
r
se

M
GD
(re
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUT_DONE_CHn_INT_ST The masked interrupt status of GDMA_OUT_DONE_CHn_INT. (RO)

GDMA_OUT_EOF_CHn_INT_ST The masked interrupt status of GDMA_OUT_EOF_CHn_INT. (RO)

GDMA_OUT_DSCR_ERR_CHn_INT_ST The masked interrupt status of

GDMA_OUT_DSCR_ERR_CHn_INT. (RO)

GDMA_OUT_TOTAL_EOF_CHn_INT_ST The masked interrupt status of

GDMA_OUT_TOTAL_EOF_CHn_INT. (RO)

GDMA_OUTFIFO_OVF_CHn_INT_ST The masked interrupt status of

GDMA_OUTFIFO_OVF_CHn_INT. (RO)

GDMA_OUTFIFO_UDF_CHn_INT_ST The masked interrupt status of

GDMA_OUTFIFO_UDF_CHn_INT. (RO)

Espressif Systems 143 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.7. GDMA_OUT_INT_ENA_CHn_REG (n: 0-2) (0x0038+0x10*n)

H0 _E NT_ A
A
_C INT _I EN
_I NA EN
OU EO _E F_C NT NA
DO CH _C _I A
T_ F_ RR H0 _EN
NE 0_ H0 NT_
A_ T_ CR O _I E

NA
M OU DS _E H0 T_

_E
GD A_ T_ TAL _C _IN

NT
M OU O VF H0
GD A_ T_T _O F_C
M OU IFO D
GD A_ TF _U
M OU IFO
GD A _ TF
M OU
d)
ve

GD A _
r
se

M
GD
(re
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUT_DONE_CHn_INT_ENA Write 1 to enable GDMA_OUT_DONE_CHn_INT. (R/W)

GDMA_OUT_EOF_CHn_INT_ENA Write 1 to enable GDMA_OUT_EOF_CHn_INT. (R/W)

GDMA_OUT_DSCR_ERR_CHn_INT_ENA Write 1 to enable GDMA_OUT_DSCR_ERR_CHn_INT. (R/W)

GDMA_OUT_TOTAL_EOF_CHn_INT_ENA Write 1 to enable GDMA_OUT_TOTAL_EOF_CHn_INT. (R/W)

GDMA_OUTFIFO_OVF_CHn_INT_ENA Write 1 to enable GDMA_OUTFIFO_OVF_CHn_INT. (R/W)

GDMA_OUTFIFO_UDF_CHn_INT_ENA Write 1 to enable GDMA_OUTFIFO_UDF_CHn_INT. (R/W)

Register 4.8. GDMA_OUT_INT_CLR_CHn_REG (n: 0-2) (0x003C+0x10*n)

H0 _C NT_ R
R
_C INT _I CL
_I LR CL
OU EO _E F_C NT LR
DO CH _C _I R
NE 0_ H0 NT_
T_ F_ RR H0 _CL
A_ T_ CR O _I C

LR
M OU DS _E H0 T_

_C
GD A_ T_ TAL _C _IN

NT
M OU O VF H0
GD A_ T_T _O F_C
M OU IFO D
GD A_ TF _U
M OU IFO
GD A_ TF
M OU
)
ed

GD A _
rv
se

M
GD
(re

31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUT_DONE_CHn_INT_CLR Write 1 to clear GDMA_OUT_DONE_CHn_INT. (WT)

GDMA_OUT_EOF_CHn_INT_CLR Write 1 to clear GDMA_OUT_EOF_CHn_INT. (WT)

GDMA_OUT_DSCR_ERR_CHn_INT_CLR Write 1 to clear GDMA_OUT_DSCR_ERR_CHn_INT. (WT)

GDMA_OUT_TOTAL_EOF_CHn_INT_CLR Write 1 to clear GDMA_OUT_TOTAL_EOF_CHn_INT. (WT)

GDMA_OUTFIFO_OVF_CHn_INT_CLR Write 1 to clear GDMA_OUTFIFO_OVF_CHn_INT. (WT)

GDMA_OUTFIFO_UDF_CHn_INT_CLR Write 1 to clear GDMA_OUTFIFO_UDF_CHn_INT. (WT)

Espressif Systems 144 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.9. GDMA_AHB_TEST_REG (0x0060)

E
DR

OD
AD

M
ST

ST
rv _TE

TE
B_
B
d)

)
(re AH

AH
ed
ve

A_

A_
r
se

se
M

M
GD

GD
(re
31 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_AHB_TESTMODE Reserved. (R/W)

GDMA_AHB_TESTADDR Reserved. (R/W)

Register 4.10. GDMA_MISC_CONF_REG (0x0064)

ER
NT
S

_I
DI

ST
I_

_R
M d ) PR
se AR EN

BM
GD rve B_
(re A_ K_
)

AH
M CL
ed

GD A_

A_
rv
se

M
GD
(re

31 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_AHBM_RST_INTER Write 1 and then 0 to reset the internal AHB FSM. (R/W)

GDMA_ARB_PRI_DIS Configures whether or not to disable the fixed-priority channel arbitration.

0: Enable
1: Disable
(R/W)

GDMA_CLK_EN Configures clock gating.

0: Support clock only when the application writes registers.
1: Always force the clock on for registers.
(R/W)

Espressif Systems 145 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.11. GDMA_IN_CONF0_CHn_REG (n: 0-2) (0x0070+0xC0*n)

_C ST N H0
H0 H0
ST TE _E _C
IN OO UR _E 0

H0 _C _C
A_ L B ST H
_R P_ ST N
M IN_ R_ UR _C
M IN TA S 0
GD A_ DSC _B _EN
GD A_ _DA RAN CH
M IN _T N_
GD A_ EM _E
M M M
GD A_ ET
M IN_
d)
ve

GD A _
r
se

M
GD
(re
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_RST_CHn Write 1 and then 0 to reset GDMA channel 0 RX FSM and RX FIFO pointer.(R/W)

GDMA_IN_LOOP_TEST_CHn Reserved. (R/W)

GDMA_INDSCR_BURST_EN_CHn Configures whether or not to enable INCR burst transfer for RX

channel n to read descriptors.
0: Disable
1: Enable
(R/W)

GDMA_IN_DATA_BURST_EN_CHn Configures whether or not to enable INCR burst transfer for RX

channel n.
0: Disable
1: Enable
(R/W)

GDMA_MEM_TRANS_EN_CHn Configures whether or not to enable memory-to-memory data trans-

fer.
0: Disable
1: Enable
(R/W)

GDMA_IN_ETM_EN_CHn Configures whether or not to enable ETM control for RX channeln.

0: Disable
1: Enable
(R/W)

Espressif Systems 146 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.12. GDMA_IN_CONF1_CHn_REG (n: 0-2) (0x0074+0xC0*n)

0
CH
R_
NE
W
_O
CK
HE
_C
)

d)
ed

IN

ve
A_
rv

r
se

se
M
GD
(re

(re
31 13 12 11 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_IN_CHECK_OWNER_CHn Configures whether or not to enable owner bit check for RX chan-
nel n.
0: Disable
1: Enable
(R/W)

Register 4.13. GDMA_IN_POP_CHn_REG (n: 0-2) (0x007C+0xC0*n)

H0
0

_C
H
_C

TA
OP

DA
_P

_R
FO

FO
FI

FI
)
ed

IN

IN
A_

A_
rv
se

M
GD

GD
(re

31 13 12 11 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800 Reset

GDMA_INFIFO_RDATA_CHn Represents the data popped from GDMA FIFO. (RO)

GDMA_INFIFO_POP_CHn Configures whether to pop data from GDMA FIFO.

0: Invalid. No effect
1: Pop
(WT)

Espressif Systems 147 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.14. GDMA_IN_LINK_CHn_REG (n: 0-2) (0x0080+0xC0*n)

0
CH
NK TO C 0
LI S T_ H

T_
_A P_ H0
IN K_ AR T_C

0
M INL K_S STA H0

O_ 0

CH
RE
UT CH
GD A_ LIN RE _C
A _ IN T R

R_
M IN K_ RK

DD
GD A_ LIN PA

_A
M IN K_

NK
GD A_ IN

LI
M INL
d)

IN
ve

GD A_

A_
r
se

M
GD

GD
(re

31 25 24 23 22 21 20 19 0

0 0 0 0 0 0 0 1 0 0 0 1 0x000 Reset

GDMA_INLINK_ADDR_CHn Represents the lower 20 bits of the first receive descriptor’s address.
(R/W)

GDMA_INLINK_AUTO_RET_CHn Configures whether or not to return to the current receive descrip-

tor’s address when there are some errors in current receiving data.
0: Not return
1: Return
(R/W)

GDMA_INLINK_STOP_CHn Configures whether to stop GDMA’s RX channel n from receiving data.

0: Invalid. No effect
1: Stop
(WT)

GDMA_INLINK_START_CHn Configures whether or not to enable GDMA’s RX channel n for data

transfer.
0: Disable
1: Enable
(WT)

GDMA_INLINK_RESTART_CHn Configures whether to restart RX channel n for GDMA transfer.

0: Invalid. No effect
1: Restart
(WT)

GDMA_INLINK_PARK_CHn Represents the status of the receive descriptor’s FSM.

0: Running
1: Idle
(RO)

Espressif Systems 148 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.15. GDMA_OUT_CONF0_CHn_REG (n: 0-2) (0x00D0+0xC0*n)

OU LO _W _C _C n
T_ OP RB Hn Hn
A_ T_ TO DE EN H

n CH Hn
M OU AU O T_ _C

CH T_ _C
GD A_ T_ F_M RS EN

n
T_ ES K
M OU EO BU T_
M OU SC B Hn

RS _T AC
GD A_ T_ R_ URS
GD A_ TD TA_ _C
M OU DA EN
GD A_ T_ M_
M OU ET
GD A_ T_
M OU
)
ed

GD A_
rv
se

M
GD
(re
31 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset

GDMA_OUT_RST_CHn Configures the reset state of GDMA channel n TX FSM and TX FIFO pointer.
0: Release reset
1: Reset
(R/W)

GDMA_OUT_LOOP_TEST_CHn Reserved. (R/W)

GDMA_OUT_AUTO_WRBACK_CHn Configures whether or not to enable automatic outlink write-

back when all the data in TX FIFO has been transmitted.
0: Disable
1: Enable
(R/W)

GDMA_OUT_EOF_MODE_CHn Configures when to generate EOF flag.

0: EOF flag for TX channel n is generated when data to be transmitted has been pushed into
FIFO in GDMA.
1: EOF flag for TX channel n is generated when data to be transmitted has been popped from
FIFO in GDMA.
(R/W)

GDMA_OUTDSCR_BURST_EN_CHn Configures whether or not to enable INCR burst transfer for TX

channel n reading descriptors.
0: Disable
1: Enable
(R/W)

GDMA_OUT_DATA_BURST_EN_CHn Configures whether or not to enable INCR burst transfer for TX

channel n.
0: Disable
1: Enable
(R/W)

GDMA_OUT_ETM_EN_CHn Configures whether or not to enable ETM control for TX channel n.

0: Disable
1: Enable
( (R/W)

Espressif Systems 149 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.16. GDMA_OUT_CONF1_CHn_REG (n: 0-2) (0x00D4+0xC0*n)

0
CH
R_
NE
OW
K_
EC
CH
T_
OU
d)

d)
ve

ve
A_
r

r
se

se
M
GD
(re

(re
31 13 12 11 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUT_CHECK_OWNER_CHn Configures whether or not to enable owner bit check for TX

channel n.
0: Disable
1: Enable
(R/W)

Register 4.17. GDMA_OUT_PUSH_CHn_REG (n: 0-2) (0x00DC+0xC0*n)

0
0

H
CH

_C
H_

TA
DA
US

W
P
O_

O_
IF

IF
TF

TF
OU

OU
)
ed

A_

A_
rv
se

M
GD

GD
(re

31 10 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

GDMA_OUTFIFO_WDATA_CHn Represents the data that need to be pushed into GDMA FIFO. (R/W)

GDMA_OUTFIFO_PUSH_CHn Configures whether to push data into GDMA FIFO.

0: Invalid. No effect
1: Push
(WT)

Espressif Systems 150 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.18. GDMA_OUT_LINK_CHn_REG (n: 0-2) (0x00E0+0xC0*n)

OP CH 0
ST T_ H
_C 0
K_ R _C

0
TL K_ STA H0

H0

H
IN STA RT

_C
OU IN RE _C

DR
A _ TL _ K
M OU INK AR

AD
GD A_ TL K_P

K_
M OU IN

IN
GD A_ TL

TL
M OU

OU
d)
ve

GD A_

A_
r
se

M
GD

GD
(re

31 24 23 22 21 20 19 0

0 0 0 0 0 0 0 0 1 0 0 0 0x000 Reset

GDMA_OUTLINK_ADDR_CHn Represents the lower 20 bits of the first transmit descriptor’s address.
(R/W)

GDMA_OUTLINK_STOP_CHn Configures whether to stop GDMA’s TX channel n from transmitting

data.
0: Invalid. No effect
1: Stop
(WT)

GDMA_OUTLINK_START_CHn Configures whether to enable GDMA’s TX channel n for data transfer.

0: Disable
1: Enable
(WT)

GDMA_OUTLINK_RESTART_CHn Configures whether to restart TX channel n for GDMA transfer.

0: Invalid. No effect
1: Restart
(WT)

GDMA_OUTLINK_PARK_CHn Represents the status of the transmit descriptor’s FSM.

0: Running
1: Idle
(RO)

Register 4.19. GDMA_DATE_REG (0x0068)

TE
DA
A_
M
GD

31 0

0x2202250 Reset

GDMA_DATE Version control register. (R/W)

Espressif Systems 151 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.20. GDMA_INFIFO_STATUS_CHn_REG (n: 0-2) (0x0078+0xC0*n)

_C 0
DE 2B H0
UN ER_ _C 0

H0
1B H
N_ D 3B H

R_ _C
AI UN R_ _C
EM IN_ DE 4B
IN EM _ DE 0
A_ R AIN N H
_R A UN R_

L _ H0
M IN_ M _U Y_C

0
0

UL Y_C
CH
GD A_ _RE AIN GR

H
_C

_F PT
M IN M N

NT
GD A_ _RE _HU

FI EM
_C

IN O_
M IN F

FO

FO
GD A_ _BU

A_ IF
FI

M INF
)

d)
ed

M IN

IN
ve
GD A_

A_

GD A_
rv

r
se

se
M

M
GD

GD

GD
(re

(re
31 28 27 26 25 24 23 22 8 7 2 1 0

0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset

GDMA_INFIFO_FULL_CHn Represents whether or not L1 RX FIFO is full.

0: Not Full
1: Full
(RO)

GDMA_INFIFO_EMPTY_CHn Represents whether or not L1 RX FIFO is empty.

0: Not empty
1: Empty
(RO)

GDMA_INFIFO_CNT_CHn Represents the number of data bytes in L1 RX FIFO for RX channel n. (RO)

GDMA_IN_REMAIN_UNDER_1B_CHn Reserved. (RO)

GDMA_IN_REMAIN_UNDER_2B_CHn Reserved. (RO)

GDMA_IN_REMAIN_UNDER_3B_CHn Reserved. (RO)

GDMA_IN_REMAIN_UNDER_4B_CHn Reserved. (RO)

GDMA_IN_BUF_HUNGRY_CHn Reserved. (RO)

Espressif Systems 152 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.21. GDMA_IN_STATE_CHn_REG (n: 0-2) (0x0084+0xC0*n)

0
CH
0

R_
CH

DD
E_

A
AT
H0

R_
ST

SC
_C

R_

_D
TE

C
TA

NK
DS
_S

LI
_
d)

IN

IN

IN
ve

A_

A_

A_
r
se

M
GD

GD

GD
(re

31 23 22 20 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_INLINK_DSCR_ADDR_CHn Represents the lower 18 bits of the next receive descriptor ad-
dress that is pre-read (but not processed yet). If the current receive descriptor is the last de-
scriptor, then this field represents the address of the current receive descriptor. (RO)

GDMA_IN_DSCR_STATE_CHn Reserved. (RO)

GDMA_IN_STATE_CHn Reserved. (RO)

Register 4.22. GDMA_IN_SUC_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x0088+0xC0*n)

0
CH
R_
DD
_A
ES
_D
OF
_E
UC
_S
IN
A_
M
GD

31 0

0x000000 Reset

GDMA_IN_SUC_EOF_DES_ADDR_CHn Represents the address of the receive descriptor when the

EOF bit in this descriptor is 1. (RO)

Espressif Systems 153 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.23. GDMA_IN_ERR_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x008C+0xC0*n)

0
CH
R_
A DD
S_
DE
F_
EO
R_
_ ER
IN
A_
M
GD
31 0

0x000000 Reset

GDMA_IN_ERR_EOF_DES_ADDR_CHn Represents the address of the receive descriptor when

there are some errors in the currently received data. Valid only for UHCI or PARLIO. (RO)

Register 4.24. GDMA_IN_DSCR_CHn_REG (n: 0-2) (0x0090+0xC0*n)

H0
_C
CR
DS
K_
N
LI
IN
A_
M
GD

31 0

0 Reset

GDMA_INLINK_DSCR_CHn Represents the address of the next receive descriptor x+1 pointed by
the current receive descriptor that is pre-read. (RO)

Register 4.25. GDMA_IN_DSCR_BF0_CHn_REG (n: 0-2) (0x0094+0xC0*n)

H 0
_C
F0
B
R_
SC
_D
NK
LI
IN
A_
M
GD

31 0

0 Reset

GDMA_INLINK_DSCR_BF0_CHn Represents the address of the current receive descriptor x that is

pre-read. (RO)

Espressif Systems 154 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.26. GDMA_IN_DSCR_BF1_CHn_REG (n: 0-2) (0x0098+0xC0*n)

0
CH
F 1_
_B
SCR
K _D
IN
L
IN
A_
M
GD
31 0

0 Reset

GDMA_INLINK_DSCR_BF1_CHn Represents the address of the previous receive descriptor x-1 that
is pre-read. (RO)

Register 4.27. GDMA_OUTFIFO_STATUS_CHn_REG (n: 0-2) (0x00D8+0xC0*n)

_C 0
DE 2B H0
UN ER_ _C 0

H0
1B H
N_ D 3B H

R_ _C
AI N _ C
M _U ER B_
RE IN ND _4

_C 0
T_ MA _U ER

LL CH
H0
0
OU RE IN ND

FU TY_
CH
A_ T_ A U

T_

O_ P
M OU REM IN_

IF EM
N
_C
GD A_ T_ MA

TF O_
FO
M OU RE

OU IF
FI

A_ TF
GD A_ T_

T
M OU

OU

M U
)

)
ed

ed

O
GD A_

A_

GD A_
rv

rv
se

se
M

M
GD

GD

GD
(re

(re

31 27 26 25 24 23 22 8 7 2 1 0

0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset

GDMA_OUTFIFO_FULL_CHn Represents whether or not L1 TX FIFO is full.

0: Not Full
1: Full
(RO)

GDMA_OUTFIFO_EMPTY_CHn Represents whether or not L1 TX FIFO is empty.

0: Not empty
1: Empty
(RO)

GDMA_OUTFIFO_CNT_CHn Represents the number of data bytes in L1 TX FIFO for TX channel n.

(RO)

GDMA_OUT_REMAIN_UNDER_1B_CHn Reserved. (RO)

GDMA_OUT_REMAIN_UNDER_2B_CHn Reserved. (RO)

GDMA_OUT_REMAIN_UNDER_3B_CHn Reserved. (RO)

GDMA_OUT_REMAIN_UNDER_4B_CHn Reserved. (RO)

Espressif Systems 155 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.28. GDMA_OUT_STATE_CHn_REG (n: 0-2) (0x00E4+0xC0*n)

0
CH
R_
0
CH

DD
E_

_A
AT
0

CR
CH

ST

S
E_

R_

_D
AT

SC

NK
ST

LI
T_

T_

T
OU

OU

OU
)
ed

A_

A_

A_
rv
se

M
GD

GD

GD
(re

31 23 22 20 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_OUTLINK_DSCR_ADDR_CHn Represents the lower 18 bits of the next transmit descriptor

address that is pre-read (but not processed yet). If the current transmit descriptor is the last
descriptor, then this field represents the address of the current transmit descriptor. (RO)

GDMA_OUT_DSCR_STATE_CHn Reserved. (RO)

GDMA_OUT_STATE_CHn Reserved. (RO)

Register 4.29. GDMA_OUT_EOF_DES_ADDR_CHn_REG (n: 0-2) (0x00E8+0xC0*n)

0
CH
R_
DD
A
S_
DE
F_
EO
T_
OU
A_
M
GD

31 0

0x000000 Reset

GDMA_OUT_EOF_DES_ADDR_CHn Represents the address of the transmit descriptor when the

EOF bit in this descriptor is 1. (RO)

Espressif Systems 156 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.30. GDMA_OUT_EOF_BFR_DES_ADDR_CHn_REG (n: 0-2) (0x00EC+0xC0*n)

0
CH
R_
DD
A
S_
DE
R_
BF
F_
EO
T_
OU
A_
M
GD
31 0

0x000000 Reset

GDMA_OUT_EOF_BFR_DES_ADDR_CHn Represents the address of the transmit descriptor before

the last transmit descriptor. (RO)

Register 4.31. GDMA_OUT_DSCR_CHn_REG (n: 0-2) (0x00F0+0xC0*n)

H 0
_C
CR
DS
K_
IN
TL
OU
A_
M
GD

31 0

0 Reset

GDMA_OUTLINK_DSCR_CHn Represents the address of the next transmit descriptor y+1 pointed
by the current transmit descriptor that is pre-read. (RO)

Register 4.32. GDMA_OUT_DSCR_BF0_CHn_REG (n: 0-2) (0x00F4+0xC0*n)

H 0
_C
F0
_B
CR
DS
K_
IN
TL
OU
A_
M
GD

31 0

0 Reset

GDMA_OUTLINK_DSCR_BF0_CHn Represents the address of the current transmit descriptor y that

is pre-read. (RO)

Espressif Systems 157 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.33. GDMA_OUT_DSCR_BF1_CHn_REG (n: 0-2) (0x00F8+0xC0*n)

0
CH
1_
F
_B
S CR
_D
K
IN
TL
OU
A_
M
GD
31 0

0 Reset

GDMA_OUTLINK_DSCR_BF1_CHn Represents the address of the previous transmit descriptor y-1

that is pre-read. (RO)

Register 4.34. GDMA_IN_PRI_CHn_REG (n: 0-2) (0x009C+0xC0*n)

H0
_C
RI
_P
)

RX
ed

A_
rv
se

M
GD
(re

31 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_RX_PRI_CHn Configures the priority of RX channel n.

Value range: 0 ~ 9
The larger of the value, the higher of the priority. (R/W)

Register 4.35. GDMA_OUT_PRI_CHn_REG (n: 0-2) (0x00FC+0xC0*n)

H0
_C
RI
_P
)

TX
ed

A_
rv
se

M
GD
(re

31 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GDMA_TX_PRI_CHn Configures the priority of TX channel n.

Value range: 0 ~ 9
The larger of the value, the higher of the priority. (R/W)

Espressif Systems 158 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.36. GDMA_IN_PERI_SEL_CHn_REG (n: 0-2) (0x00A0+0xC0*n)

0
CH
L_
SE
N_
_I
RI
d)

PE
ve

A_
r
se

M
GD
(re
31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3f Reset

GDMA_PERI_IN_SEL_CHn Configures the peripheral connected to RX channel n.

0: SPI2
1: Dummy-1
2: UHCI
3: I2S0
4: Dummy-4
5: Dummy-5
6: AES
7: SHA
8: ADC
9: Parallel IO
10 ~ 15: Dummy-10 ~ 15
16 ~ 63: Invalid
(R/W)

Espressif Systems 159 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
4 GDMA Controller (GDMA) GoBack

Register 4.37. GDMA_OUT_PERI_SEL_CHn_REG (n: 0-2) (0x0100+0xC0*n)

H0
_C
EL
_S
UT
_O
RI
d)

PE
ve

A_
r
se

M
GD
(re
31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3f Reset

GDMA_PERI_OUT_SEL_CHn Configures the peripheral connected to TX channel n.

0: SPI2
1: Dummy-1
2: UHCI
3: I2S0
4: Dummy-4
5: Dummy-5
6: AES
7: SHA
8: ADC
9: Parallel IO
10 ~ 15: Dummy-10 ~ 15
16 ~ 63: Invalid
(R/W)

Espressif Systems 160 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

5 System and Memory

5.1 Overview
ESP32-C6 is an ultra-low power and highly-integrated system that integrates:

• a high-performance 32-bit RISC-V single-core processor (HP CPU), four-stage pipeline, clock frequency
up to 160 MHz

• a low-power 32-bit RISC-V single-core processor (LP CPU), two-stage pipeline, clock frequency up to
20 MHz

All internal memory, external memory, and peripherals are located on the HP CPU and LP CPU buses.

5.2 Features
• Address Space

– 832 KB of internal memory address space accessed from the instruction bus or data bus

– 832 KB of peripheral address space

– 16 MB of external memory virtual address space accessed from the instruction bus or the data bus

– 512 KB of internal DMA address space

• Internal Memory

– 320 KB internal ROM

– 512 KB HP SRAM

– 16 KB LP SRAM

• External Memory

– Supports up to 16 MB external flash

• Peripheral Space

– 51 modules/peripherals in total

• GDMA

– 8 GDMA-supported modules/peripherals

Figure 5-1 illustrates the system structure and address mapping.

Espressif Systems 161 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

Figure 5-1. System Structure and Address Mapping

Note:

• The range of addresses available in the address space may be larger than the actual available memory of a
particular type.

• For CPU Sub-system, please refer to Chapter 1 High-Performance CPU.

5.3 Functional Description

5.3.1 Address Mapping
All the non-reserved addresses are accessible by the instruction bus and the data bus, that is, the instruction
bus and the data bus access the same address space.

Both data bus and instruction bus of the HP CPU and LP CPU are little-endian. The HP CPU and LP CPU can
access data via the data bus using single-byte, double-byte, and 4-byte alignment.

The CPU can:

• directly access the internal memory via both data bus and instruction bus.

• (for HP CPU only) directly access the external memory which is mapped into the address space via
cache.

• directly access modules/peripherals via data bus.

Table 5-1 lists the address ranges on the data bus and instruction bus and their corresponding target
memories.

Espressif Systems 162 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

Table 5-1. Memory Address Mapping

Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3FFF_FFFF Reserved
Data/Instruction bus 0x4000_0000 0x4004_FFFF 320 KB ROM*
0x4005_0000 0x407F_FFFF Reserved
Data/Instruction bus 0x4080_0000 0x4087_FFFF 512 KB HP SRAM*
0x4088_0000 0x41FF_FFFF Reserved
Data/Instruction bus 0x4200_0000 0x42FF_FFFF 16 MB External memory
0x4300_0000 0x4FFF_FFFF Reserved
Data/Instruction bus 0x5000_0000 0x5000_3FFF 16 KB LP SRAM*
0x5000_4000 0x5FFF_FFFF Reserved
Data/Instruction bus 0x6000_0000 0x600C_FFFF 832 KB Peripherals
0x600D_0000 0xFFFF_FFFF Reserved
* All of the internal memories are managed by Permission Control module. An internal
memory can only be accessed when it is allowed by Permission Control, then the in-
ternal memory can be available to the HP CPU and LP CPU. For more information about
Permission Control, please refer to Chapter 16 Permission Control (PMS).

5.3.2 Internal Memory

ESP32-C6 consists of the following three types of internal memory:

• ROM (320 KB): The ROM is a read-only memory and can not be programmed. It contains the ROM code
of some low-level system software and read-only data.

• HP SRAM (512 KB): The HP SRAM is a volatile memory that can be quickly accessed by the HP CPU or
LP CPU (generally within a single HP CPU clock cycle for HP CPU).

• LP SRAM (16 KB): LP SRAM is also a volatile memory, however, in Deep-sleep mode, data stored in the
LP SRAM will not be lost. The LP SRAM can be accessed by the HP CPU or LP CPU and is usually used
to store program instructions and data that need to be kept in sleep mode.

1. ROM

This 320 KB ROM is a read-only memory, addressed by the HP CPU through the instruction bus or through the
data bus via 0x4000_0000 ~ 0x4004_FFFF, as shown in Table 5-1.

2. HP SRAM

This 512 KB HP SRAM is a read-and-write memory, accessed by the HP CPU or LP CPU through the instruction
bus or through the data bus as shown in Table 5-1.

3. LP SRAM

This 16 KB LP SRAM is a read-and-write memory, accessed by the HP CPU or LP CPU through the instruction
bus or through the data bus via their shared address 0x5000_0000 ~ 0x5000_3FFF as shown in Table
5-1.

LP SRAM can be accessed by the following modes:

Espressif Systems 163 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

• high-speed mode, i.e., the LP SRAM is accessed in HP CPU clock frequency. In this case:

– HP CPU can access the LP SRAM without any latency.

– But the latency of LP CPU accessing LP SRAM ranges from a few dozen to dozens of LP CPU
cycles.

• low-speed mode, i.e., the LP SRAM is accessed in LP CPU clock frequency. In this case:

– LP CPU can access the LP SRAM with zero cycle latency.

– But the latency of HP CPU accessing LP SRAM ranges from a few dozen to dozens of HP CPU
cycles.

You can switch the modes based on your application scenarios.

• If the LP CPU is not working, you can switch to high-speed mode to improve the access speed of the
HP CPU.

• If the LP CPU is executing code in the LP SRAM, you can switch to the low-speed mode.

When the HP CPU is in sleep mode, you must switch to the low-speed mode.

Detailed configuration is as follows:

• Configure LP_AON_FAST_MEM_MUX_SEL to select the mode needed:

– 1: high-speed mode

– 0: low-speed mode

• Set LP_AON_FAST_MEM_MUX_SEL_UPDATE to start mode switch.

• Read LP_AON_FAST_MEM_MUX_SEL_STATUS to check if mode switch is done:

– 0: mode is switched

– 1: mode is not switched

5.3.3 External Memory

ESP32-C6 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to external flash.
ESP32-C6 also supports hardware manual encryption and automatic decryption based on XTS-AES algorithm
to protect users’ programs and data in the external flash.

5.3.3.1 External Memory Address Mapping

The HP CPU accesses the external memory via the cache. According to information inside the MMU (Memory
Management Unit), the cache maps the HP CPU’s address (0x4200_0000 ~ 0x42FF_FFFF) into a physical
address of the external memory. Due to this address mapping, ESP32-C6 can address up to 16 MB external
flash. Note that the instruction bus shares the same address space (16 MB) with the data bus to access the
external memory.

5.3.3.2 Cache

As shown in Figure 5-2, ESP32-C6 has a read-only uniform cache which is four-way set-associative. Its size is
32 KB and its block size is 32 bytes. The cache is accessible by the instruction bus and the data bus at the

Espressif Systems 164 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

same time, but can only respond to one of them at a time. When a cache miss occurs, the cache controller
will initiate a request to the external memory.

Figure 5-2. Cache Structure

5.3.3.3 Cache Operations

ESP32-C6 cache supports the following operations:

1. Invalidate: This operation is used to remove valid data in the cache. Once this operation is done, the
deleted data is stored only in the external memory. If the HP CPU wants to access the data again, it
needs to access the external memory. There are two types of invalidate operation: Invalidate-All and
Manual-Invalidate. Manual-Invalidate is performed only on data in the specified area in the cache, while
Invalidate-All is performed on all data in the cache.

2. Preload: This operation is to load instructions and data into the cache in advance. The minimum unit of
preload-operation is one block. There are two types of preload-operation: manual preload
(Manual-Preload) and automatic preload (Auto-Preload). Manual-Preload means that the hardware
prefetches a piece of continuous data according to the virtual address specified by the software.
Auto-Preload means the hardware prefetches a piece of continuous data according to the current
address where the cache hits or misses (depending on configuration).

3. Lock/Unlock: The lock operation is used to prevent the data in the cache from being easily replaced.
There are two types of lock: prelock and manual lock. When prelock is enabled, the cache locks the
data in the specified area when filling the missing data to cache memory, while the data outside the
specified area will not be locked. When manual lock is enabled, the cache checks the data that is
already in the cache memory and locks the data only if it falls in the specified area, and leaves the data
outside the specified area unlocked. When there are missing data, the cache will replace the data in the
unlocked way first, so the data in the locked way is always stored in the cache and will not be replaced.
But when all ways within the cache are locked, the cache will replace data, as if it was not locked.
Unlocking is the reverse of locking, except that it only can be done manually.

Please note that Invalidate-All operation only works on the unlocked data. If you expect to perform such
operation on the locked data, please unlock them first.

Espressif Systems 165 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

5.3.4 GDMA Address Space

The General Direct Memory Access (GDMA) peripheral consisting of three TX channels and three RX channels
provides Direct Memory Access (DMA) service, including:

• data transfers between different locations of internal memory

• data transfers between modules/peripherals and internal memory

GDMA uses the same addresses as the data bus to access HP SRAM, i.e., GDMA uses address range
0x4080_0000 ~ 0x4087_FFFF to access HP SRAM.

Eight modules/peripherals in ESP32-C6 work together with GDMA. As shown in Figure 5-3, eight vertical lines
correspond to these eight modules/peripherals with GDMA function. The horizontal line represents a certain
channel of GDMA (can be any channel), and the intersection of the vertical line and the horizontal line
indicates that a module/peripheral has the ability to access the corresponding channel of GDMA. If there are
multiple intersections on the same line, it means that these peripherals/modules can not enable the GDMA
function at the same time.

Figure 5-3. Modules/peripherals that can work with GDMA

These modules/peripherals can access any memory available to GDMA. For more information, please refer to
Chapter 4 GDMA Controller (GDMA).

Note:
When accessing a memory via GDMA, a corresponding access permission is needed, otherwise this access may fail.
For more information about permission control, please refer to Chapter 16 Permission Control (PMS).

5.3.5 Modules/Peripherals Address Mapping

Table 5-2 lists all the modules/peripherals and their respective address ranges. Note that the address space of
specific modules/peripherals is defined by “Boundary Address” (including both Low Address and High

Espressif Systems 166 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

Address).

Table 5-2. Module/Peripheral Address Mapping

Boundary Address
Target Size (KB)
Low Address High Address
UART Controller 0 (UART0) 0x6000_0000 0x6000_0FFF 4
UART Controller 1 (UART1) 0x6000_1000 0x6000_1FFF 4
External Memory Encryption and Decryption 0x6000_2000 0x6000_2FFF 4
(XTS_AES)
Reserved 0x6000_3000 0x6000_3FFF
I2C Controller (I2C) 0x6000_4000 0x6000_4FFF 4
UHCI Controller (UHCI) 0x6000_5000 0x6000_5FFF 4
Remote Control Peripheral (RMT) 0x6000_6000 0x6000_6FFF 4
LED PWM Controller (LEDC) 0x6000_7000 0x6000_7FFF 4
Timer Group 0 (TIMG0) 0x6000_8000 0x6000_8FFF 4
Timer Group 1 (TIMG1) 0x6000_9000 0x6000_9FFF 4
System Timer (SYSTIMER) 0x6000_A000 0x6000_AFFF 4
Two-wire Automotive Interface 0 (TWAI0) 0x6000_B000 0x6000_BFFF 4
I2S Controller (I2S) 0x6000_C000 0x6000_CFFF 4
Two-wire Automotive Interface 1 (TWAI1) 0x6000_D000 0x6000_DFFF 4
Successive Approximation ADC (SAR ADC) 0x6000_E000 0x6000_EFFF 4
USB Serial/JTAG Controller 0x6000_F000 0x6000_FFFF 4
Interrupt Matrix (INTMTX) 0x6001_0000 0x6001_0FFF 4
Reserved 0x6001_1000 0x6001_1FFF
Pulse Count Controller (PCNT) 0x6001_2000 0x6001_2FFF 4
Event Task Matrix (SOC_ETM) 0x6001_3000 0x6001_3FFF 4
Motor Control PWM (MCPWM) 0x6001_4000 0x6001_4FFF 4
Parallel IO Controller (PARL_IO) 0x6001_5000 0x6001_5FFF 4
SDIO HINF* 0x6001_6000 0x6001_6FFF 4
SDIO SLC* 0x6001_7000 0x6001_7FFF 4
SDIO SLCHOST * 0x6001_8000 0x6001_8FFF 4
Reserved 0x6001_9000 0x6007_FFFF
GDMA Controller (GDMA) 0x6008_0000 0x6008_0FFF 4
General Purpose SPI2 (GP-SPI2) 0x6008_1000 0x6008_1FFF 4
Reserved 0x6008_2000 0x6008_7FFF
AES Accelerator (AES) 0x6008_8000 0x6008_8FFF 4
SHA Accelerator (SHA) 0x6008_9000 0x6008_9FFF 4
RSA Accelerator (RSA) 0x6008_A000 0x6008_AFFF 4
ECC Accelerator (ECC) 0x6008_B000 0x6008_BFFF 4
Digital Signature (DS) 0x6008_C000 0x6008_CFFF 4
HMAC Accelerator (HMAC) 0x6008_D000 0x6008_DFFF 4
Reserved 0x6008_E000 0x6008_FFFF
IO MUX 0x6009_0000 0x6009_0FFF 4
GPIO Matrix 0x6009_1000 0x6009_1FFF 4
Cont’d on next page

Espressif Systems 167 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

Table 5-2 – cont’d from previous page

Boundary Address
Target Size (KB)
Low Address High Address
Memory Access Monitor (MEM_MONITOR)* 0x6009_2000 0x6009_2FFF 4
Reserved 0x6009_4000 0x6009_4FFF
HP System Register (HP_SYSREG) 0x6009_5000 0x6009_5FFF 4
Power/Clock/Reset (PCR) Register 0x6009_6000 0x6009_6FFF 4
Reserved 0x6009_7000 0x6009_7FFF
Trusted Execution Environment (TEE) Regis- 0x6009_8000 0x6009_8FFF 4
ter*
Access Permission Management Controller 0x6009_9000 0x6009_9FFF 4
(HP_APM)*
Reserved 0x6009_A000 0x600A_FFFF
Power Management Unit (PMU) 0x600B_0000 0x600B_03FF 1
Low-power Clock/Reset Register 0x600B_0400 0x600B_07FF 1
(LP_CLKRST)
eFuse Controller (EFUSE) 0x600B_0800 0x600B_0BFF 1
RTC Timer (RTC_TIMER) 0x600B_0C00 0x600B_0FFF 1
Low-power Always-on Register (LP_AON) 0x600B_1000 0x600B_13FF 1
Low-power UART (LP_UART) 0x600B_1400 0x600B_17FF 1
Low-power I2C (LP_I2C) 0x600B_1800 0x600B_1BFF 1
RTC Watch Dog Timer (RTC_WDT) 0x600B_1C00 0x600B_1FFF 1
Low-power IO MUX (LP IO MUX) 0x600B_2000 0x600B_23FF 1
I2C Analog Master (I2C_ANA_MST) 0x600B_2400 0x600B_27FF 1
Low-power Peripheral (LPPERI) 0x600B_2800 0x600B_2BFF 1
Low-power Analog Peripheral (LP_ANA_PERI) 0x600B_2C00 0x600B_2FFF 1
Reserved 0x600B_3000 0x600B_33FF
Low-power Trusted Execution Environment 0x600B_3400 0x600B_37FF 1
(LP_TEE)*
Low-power Access Permission Management 0x600B_3800 0x600B_3BFF 1
(LP_APM)*
Reserved 0x600B_3C00 0x600B_FFFF
RISC-V Trace Encoder (TRACE) 0x600C_0000 0x600C_0FFF 4
Reserved 0x600C_1000 0x600C_1FFF
DEBUG ASSIST (ASSIST_DEBUG)* 0x600C_2000 0x600C_2FFF 4
Reserved 0x600C_3000 0x600C_4FFF
Interrupt Priority Register (INTPRI) 0x600C_5000 0x600C_5FFF 4
Reserved 0x600C_6000 0x600C_FFFF
* The address space of this module/peripheral is not continuous.

Note:
As shown in the figure 5-1�

• HP CPU can access all peripherals listed in the table 5-2.

Espressif Systems 168 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
5 System and Memory GoBack

• LP CPU can access all peripherals listed in the table 5-2 except RISC-V Trace Encoder (TRACE), DEBUG ASSIST
(ASSIST_DEBUG) and Interrupt Priority Register (INTPRI).

Espressif Systems 169 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

6 eFuse Controller

6.1 Overview
ESP32-C6 contains a 4096-bit eFuse memory to store parameters and user data. The parameters include
control parameters for some hardware modules, system data parameters and keys used for the decryption
module. Once an eFuse bit is programmed to 1, it can never be reverted to 0. The eFuse controller programs
individual bits of parameters in eFuse according to user configurations. From outside the chip, eFuse data can
only be read via the eFuse controller. For some data, such as some keys stored in eFuse for internal use by
hardware cryptography modules (e.g., digital signature, HMAC), if read protection is not enabled, the data can
be read from outside the chip; if read protection is enabled, the data cannot be read from outside the
chip.

6.2 Features
• 4096-bit one-time programmable storage including 1792 bits reserved for custom use

• Configurable write protection

• Configurable read protection

• Various hardware encoding schemes against data corruption

6.3 Functional Description

6.3.1 Structure
The eFuse system consists of the eFuse controller and eFuse memory. Data flow in this system is shown in
Figure 6-1.

Users can program bits in the eFuse memory via the eFuse controller by writing the data to be programmed to
the programming register and executing the programming instruction. For detailed programming steps, please
refer to Section 6.3.2.

Users cannot directly read the data programmed in the eFuse memory, so they need to read the programmed
data into the Reading Data Register of the corresponding address segment through the eFuse controller.
During the reading process, if the data is inconsistent with that in the eFuse memory, the eFuse controller can
automatically correct it through the hardware encoding mechanism (see Section 6.3.1.3 for details), and send
the error message to the error report register. For detailed steps to read parameters, please refer to the
Section 6.3.3.

Espressif Systems 170 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Figure 6-1. Data Flow in eFuse

Data in eFuse memory is organized in 11 blocks (BLOCK0 ~ BLOCK10).

BLOCK0 holds most parameters for software and hardware uses.

Table 6-1 lists all the parameters accessible (readable and usable) to users in BLOCK0 and their offsets, bit
widths, accessibility by hardware, write protection, and brief function description. For more description on the
parameters, please click the link of the corresponding parameter in the table.

The EFUSE_WR_DIS parameter is used to disable write protection of other parameters. EFUSE_RD_DIS is
used to disable read protection of BLOCK4 ~ BLOCK10. For more information on these two parameters, please
see Section 6.3.1.1 and Section 6.3.1.2.

Espressif Systems 171 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
 Espressif Systems

6 eFuse Controller
Table 6-1. Parameters in eFuse BLOCK0

Write Protection
Bit Accessible
Parameters by EFUSE_WR_DIS Description
Width by Hardware
Bit Number

Represents whether writing of eFuse bits by eFuse con-

EFUSE_WR_DIS 32 Y N/A
troller is disabled.
Represents whether reading data from BLOCK4 ~ 10 in
EFUSE_RD_DIS 7 Y 0
eFuse memory by users is disabled.
Represents whether the pads of UART and SDIO are
EFUSE_SWAP_UART_SDIO_EN 1 Y 2
swapped or not.
EFUSE_DIS_ICACHE 1 Y 2 Represents whether iCache is disabled.
Submit Documentation Feedback

Represents whether the USB-to-JTAG function in the USB

EFUSE_DIS_USB_JTAG 1 Y 2
module is disabled.
EFUSE_DIS_DOWNLOAD_ICACHE 1 Y 2 Represents whether iCache is disabled in Download mode.
Represents whether the USB_Serial_JTAG module is dis-
172

EFUSE_DIS_USB_SERIAL_JTAG 1 Y 2
abled.
Represents whether the function to force the chip into
EFUSE_DIS_FORCE_DOWNLOAD 1 Y 2
Download mode is disabled.
Represents whether the SPI0 controller is disabled in
EFUSE_SPI_DOWNLOAD_MSPI_DIS 1 Y 17
boot_mode_download.
EFUSE_DIS_TWAI 1 Y 2 Represents whether the TWAI controller is disabled.
Represents whether the selection of a JTAG signal source
through the strapping value of GPIO15 is enabled when
ESP32-C6 TRM (Version 1.0)

EFUSE_JTAG_SEL_ENABLE 1 Y 2
both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG
are configured to 0.
EFUSE_SOFT_DIS_JTAG 3 Y 31 Represents whether JTAG is disabled in the soft way.
Represents whether JTAG is disabled in the hard way (per-
EFUSE_DIS_PAD_JTAG 1 Y 2
manently).

GoBack
Cont’d on next page
 Espressif Systems

6 eFuse Controller
Table 6-1 – cont’d from previous page
Write Protection
Bit Accessible
Parameters by EFUSE_WR_DIS Description
Width by Hardware
Bit Number

Represents whether flash encryption is disabled (except in

EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT 1 Y 2
SPI boot mode).
EFUSE_USB_EXCHG_PINS 1 Y 30 Represents whether the D+ and D- pins are exchanged.
Represents whether the VDD_SPI pin is used as a regular
EFUSE_VDD_SPI_AS_GPIO 1 Y 30
GPIO.
Represents whether RTC watchdog timeout threshold is
EFUSE_WDT_DELAY_SEL 2 Y 3
selected at startup.
Represents whether SPI boot encryption/decryption is en-
Submit Documentation Feedback

EFUSE_SPI_BOOT_CRYPT_CNT 3 Y 4
abled.
Represents whether revoking the first Secure Boot key is
EFUSE_SECURE_BOOT_KEY_REVOKE0 1 N 5
enabled.
173

Represents whether revoking the second Secure Boot key

EFUSE_SECURE_BOOT_KEY_REVOKE1 1 N 6
is enabled.
Represents whether revoking the third Secure Boot key is
EFUSE_SECURE_BOOT_KEY_REVOKE2 1 N 7
enabled.
EFUSE_KEY_PURPOSE_0 4 Y 8 Represents Key0 purpose. See Table 6-2.
EFUSE_KEY_PURPOSE_1 4 Y 9 Represents Key1 purpose. See Table 6-2.
EFUSE_KEY_PURPOSE_2 4 Y 10 Represents Key2 purpose. See Table 6-2.
EFUSE_KEY_PURPOSE_3 4 Y 11 Represents Key3 purpose. See Table 6-2.
ESP32-C6 TRM (Version 1.0)

EFUSE_KEY_PURPOSE_4 4 Y 12 Represents Key4 purpose. See Table 6-2.

EFUSE_KEY_PURPOSE_5 4 Y 13 Represents Key5 purpose. See Table 6-2.
Represents the security level of anti-DPA (differential power
EFUSE_SEC_DPA_LEVEL 2 Y 14
analysis) attack.
Represents whether defense against DPA attack is en-
EFUSE_CRYPT_DPA_ENABLE 1 Y 15

GoBack
abled.
EFUSE_SECURE_BOOT_EN 1 N 16 Represents whether Secure Boot is enabled or disabled.
Cont’d on next page
 Espressif Systems

6 eFuse Controller
Table 6-1 – cont’d from previous page
Write Protection
Bit Accessible
Parameters by EFUSE_WR_DIS Description
Width by Hardware
Bit Number

Represents whether aggressive revocation of Secure Boot

EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE 1 N 16
is enabled.
EFUSE_FLASH_TPUW 4 N 18 Represents the flash waiting time after power-up.
EFUSE_DIS_DOWNLOAD_MODE 1 N 18 Represents whether all download modes are disabled.
EFUSE_DIS_DIRECT_BOOT 1 N 18 Represents whether direct boot mode is disabled.
Represents whether print from USB-Serial-JTAG during
EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT 1 N 18
ROM boot is disabled.
Represents whether the USB-Serial-JTAG download func-
Submit Documentation Feedback

EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE 1 N 18
tion is disabled.
EFUSE_ENABLE_SECURITY_DOWNLOAD 1 N 18 Represents whether security download is enabled.
EFUSE_UART_PRINT_CONTROL 2 N 18 Represents the type of UART printing.
174

Represents whether ROM code is forced to send a resume

EFUSE_FORCE_SEND_RESUME 1 N 18
command during SPI boot.
Represents the version used by ESP-IDF anti-rollback fea-
EFUSE_SECURE_VERSION 16 N 18
ture.
Represents whether FAST VERIFY ON WAKE is disabled or
EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE 1 N 19
enabled when Secure Boot is enabled.
ESP32-C6 TRM (Version 1.0)

GoBack
6 eFuse Controller GoBack

Table 6-2 lists all key purposes and their values. Setting the eFuse parameter EFUSE_KEY_PURPOSE_n
declares the purpose of KEYn (n: 0 ~ 5).

Table 6-2. Secure Key Purpose Values

Key
Purpose Purposes
Values
0 User purposes
1 Reserved
2 Reserved
3 Reserved
4 XTS_AES_128_KEY (flash/SRAM encryption and decryption)
5 HMAC Downstream mode (both JTAG and DS)
6 JTAG in HMAC Downstream mode
7 Digital Signature peripheral in HMAC Downstream mode
8 HMAC Upstream mode
9 SECURE_BOOT_DIGEST0 (secure boot key digest)
10 SECURE_BOOT_DIGEST1 (secure boot key digest)
11 SECURE_BOOT_DIGEST2 (secure boot key digest)

Table 6-3 provides the details of parameters in BLOCK1 ~ BLOCK10.

Espressif Systems 175 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
 Espressif Systems

6 eFuse Controller
Table 6-3. Parameters in BLOCK1 to BLOCK10

Write Protection by Read Protection

Accessible
BLOCK Parameters Bit Width EFUSE_WR_DIS by EFUSE_RD_DIS Description
by Hardware
Bit Number Bit Number

BLOCK1 EFUSE_MAC 48 N 20 N/A MAC address

EFUSE_MAC_EXT 16 N 20 N/A Extended MAC address
EFUSE_SYS_DATA_PART0 69 N 20 N/A System data
BLOCK2 EFUSE_SYS_DATA_PART1 256 N 21 N/A System data
BLOCK3 EFUSE_USR_DATA 256 N 22 N/A User data
BLOCK4 EFUSE_KEY0_DATA 256 Y 23 0 KEY0 or user data
BLOCK5 EFUSE_KEY1_DATA 256 Y 24 1 KEY1 or user data
Submit Documentation Feedback

BLOCK6 EFUSE_KEY2_DATA 256 Y 25 2 KEY2 or user data

BLOCK7 EFUSE_KEY3_DATA 256 Y 26 3 KEY3 or user data
BLOCK8 EFUSE_KEY4_DATA 256 Y 27 4 KEY4 or user data
BLOCK9 EFUSE_KEY5_DATA 256 Y 28 5 KEY5 or user data
176

BLOCK10 EFUSE_SYS_DATA_PART2 256 N 29 6 System data

ESP32-C6 TRM (Version 1.0)

GoBack
6 eFuse Controller GoBack

Among these blocks, BLOCK4 ~ 9 can be used to store KEY0 ~ 5. Up to six 256-bit keys can be written into
eFuse. Whenever a key is written, its purpose value should also be written (see table 6-2). For example, when
a key for the JTAG function in HMAC Downstream mode is written to KEY3 (i.e., BLOCK7), its key purpose value
6 should also be written to EFUSE_KEY_PURPOSE_3.

Note:
Do not program the XTS-AES key into the KEY5 block, i.e., BLOCK9. Otherwise, the key may be unreadable. Instead,
program it into the preceding blocks, i.e., BLOCK4 ~ BLOCK8. The last block, BLOCK9, is used to program other keys.

BLOCK1 ~ BLOCK10 use the RS coding scheme, so there are some limitations on writing to these parameters.
For more detailed information, please refer to Section 6.3.1.3 and Section 6.3.2.

6.3.1.1 EFUSE_WR_DIS

Parameter EFUSE_WR_DIS determines whether individual eFuse parameters are write-protected. After
EFUSE_WR_DIS has been programmed, execute an eFuse read operation so the new values would take
effect.

Column “Write Protection by EFUSE_WR_DIS Bit Number” in Table 6-1 and Table 6-3 list the specific bits in
EFUSE_WR_DIS that disable writing.

When the write protection bit of a parameter is set to 0, it means that this parameter is not write-protected and
can be programmed, unless it has been programmed before.

When the write protection bit of a parameter is set to 1, it means that this parameter is write-protected and
none of its bits can be modified, with non-programmed bits always remaining 0 and programmed bits always
remaining 1. That is to say, if a parameter is write-protected, it will always remain in this state and cannot be
changed.

6.3.1.2 EFUSE_RD_DIS

Only the parameters in BLOCK4 ~ BLOCK10 can be set to be read-protected from users, as shown in column
“Read Protection by EFUSE_RD_DIS Bit Number” of Table 6-3. After EFUSE_RD_DIS has been programmed,
execute an eFuse read operation so the new values would take effect.

If the corresponding EFUSE_RD_DIS bit is 0, the parameter controlled by this bit is not read-protected from
users. If it is 1, the parameter controlled by it is read-protected from users.

Other parameters that are not in BLOCK4 ~ BLOCK10 can always be read by users.

When BLOCK4 ~ BLOCK10 are set to be read-protected, the data in them can still be read by hardware
cryptography modules if the EFUSE_KEY_PURPOSE_n bit is set accordingly.

6.3.1.3 Data Storage

Internally, eFuse uses the hardware encoding scheme to protect data from corruption. The scheme and the
encoding process are invisible to users.

All BLOCK0 parameters except for EFUSE_WR_DIS are stored with four backups, meaning each bit is stored
four times. This backup scheme is not visible to users.

Espressif Systems 177 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

In BLOCK0, EFUSE_WR_DIS occupies 32 bits, and other parameters takes 152 bits each. So, the eFuse
memory space occupied by BLOCK0 is 32 + 152 * 4 = 640 bits.

BLOCK1 ~ BLOCK10 use RS (44, 32) coding scheme that supports up to 6 bytes of automatic error correction.
The primitive polynomial of RS (44, 32) is p(x) = x8 + x4 + x3 + x2 + 1.

Figure 6-2. Shift Register Circuit (first 32 output)

Figure 6-3. Shift Register Circuit (last 12 output)

The shift register circuit shown in Figure 6-2 and 6-3 processes 32 data bytes using RS (44, 32). This coding
scheme encodes 32 bytes of data into 44 bytes:

• Bytes [0:31] are the data bytes itself

• Bytes [32:43] are the encoded parity bytes stored in 8-bit flip-flops DFF1, DFF2, ..., DFF12 (gf_mul_n is
the result of multiplying a byte of data in GF (28 ) by αn , where n is an integer).

After that, the hardware programs into eFuse the 44-byte codeword consisting of the data bytes and the parity
bytes. When the eFuse block is read, the eFuse controller automatically decodes the codeword and applies
error correction if needed.

Because the RS check codes are generated on the entire 32-byte eFuse block, each block can only be
written once.

Since the size of BLOCK1 is less than 32 bytes, the unused bits will be treated as 0 by hardware during the RS
(44, 32) encoding. Thus, the final coding result will not be affected.

Espressif Systems 178 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Among blocks using the RS (44, 32) coding scheme, the parameters in BLOCK1 is 24 bytes, and the RS check
code is 12 bytes, so BLOCK1 occupies 24 + 12 = 36 bytes in eFuse memory.

The parameter in other blocks (Block2 ~ 10) is 32 bytes respectively, and the RS check code is 12 bytes, so
they occupy (32 + 12) * 9 = 396 bytes in eFuse memory.

6.3.2 Programming of Parameters

The eFuse controller can only program eFuse parameters in one block at a time. BLOCK0 ~ BLOCK10 share
the same address range to store the parameters to be programmed. Configure parameter EFUSE_BLK_NUM
to indicate which block should be programmed.

Since there is a one-to-one correspondence between the reading data registers and the programming data
registers (see table 6-4 for details), users can find out where the data to be programmed is located in
programming registers by checking the parameter description and the parameter location in the corresponding
read registers.

For example, if the user wants to program the parameter EFUSE_DIS_ICACHE in BLOCK0 to 1, they can first
search the reading data registers EFUSE_RD_REPEAT_DATA0 ~ 4_REG in BLOCK0 for where the parameter is
located, namely, the 8th bit in EFUSE_RD_REPEAT_DATA0_REG. So, the user can set the 8th bit of
EFUSE_PGM_DATA1_REG to 1 and follow the programming steps below. After the steps are completed, the
corresponding bit in the eFuse memory will be programmed to 1.

Programming preparation

• Programming BLOCK0

1. Set EFUSE_BLK_NUM to 0.

2. Write into EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA5_REG the data to be programmed to

BLOCK0.
The data in EFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG and
EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG does not affect the
programming of BLOCK0.

• Programming BLOCK1

1. Set EFUSE_BLK_NUM to 1.

2. Write into EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA5_REG the data to be programmed to

BLOCK1. Write into EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG the
corresponding RS check code.
The data in EFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG does not affect the programming
of BLOCK1. When calculating RS check of BLOCK1 using software, please treat the 8 bytes as 0.

• Programming BLOCK2 ~ 10

1. Set EFUSE_BLK_NUM to the block number.

2. Write into EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG the data to be programmed. Write

into EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG the corresponding
RS code.

Programming process

The process of programming parameters is as follows:

Espressif Systems 179 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

1. Configure the value of parameter EFUSE_BLK_NUM to determine the block to be programmed.

2. Write parameters to be programmed to registers EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG

and EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG.

3. Make sure the eFuse programming voltage VDDQ is configured correctly as described in Section 6.3.4.

4. Configure the field EFUSE_OP_CODE of register EFUSE_CONF_REG to 0x5A5A.

5. Configure the field EFUSE_PGM_CMD of register EFUSE_CMD_REG to 1.

6. Poll register EFUSE_CMD_REG until it is 0x0, or wait for a PGM_DONE interrupt. For more information on
how to identify a PGM_DONE or READ_DONE interrupt, please see the end of Section 6.3.3.

7. Clear the parameters in EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG and

EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG.

8. Trigger an eFuse read operation (see Section 6.3.3) to update eFuse registers with the new values.

9. Check error record registers. If the values read in error record registers are not 0, the programming
process should be performed again following above steps 1 ~ 7. Please check the following error record
registers for different eFuse blocks:

• BLOCK0: EFUSE_RD_REPEAT_ERR0_REG ~ EFUSE_RD_REPEAT_ERR4_REG

• BLOCK1: EFUSE_MAC_SPI_8M_ERR_NUM, EFUSE_MAC_SPI_8M_FAIL

• BLOCK2: EFUSE_SYS_PART1_ERR_NUM, EFUSE_SYS_PART1_FAIL

• BLOCK3: EFUSE_USR_DATA_ERR_NUM, EFUSE_USR_DATA_FAIL

• BLOCK4: EFUSE_KEY0_ERR_NUM, EFUSE_KEY0_FAIL

• BLOCK5: EFUSE_KEY1_ERR_NUM, EFUSE_KEY1_FAIL

• BLOCK6: EFUSE_KEY2_ERR_NUM, EFUSE_KEY2_FAIL

• BLOCK7: EFUSE_KEY3_ERR_NUM, EFUSE_KEY3_FAIL

• BLOCK8: EFUSE_KEY4_ERR_NUM, EFUSE_KEY4_FAIL

• BLOCK9: EFUSE_KEY5_ERR_NUM, EFUSE_KEY5_FAIL

• BLOCK10: EFUSE_SYS_PART2_ERR_NUM, EFUSE_SYS_PART2_FAIL

Limitations

In BLOCK0, each bit can be programmed separately. However, we recommend to minimize programming
cycles and program all the bits of a parameter in one programming action. In addition, after all parameters
controlled by a certain bit of EFUSE_WR_DIS are programmed, that bit should be immediately programmed.
The programming of parameters controlled by a certain bit of EFUSE_WR_DIS, and the programming of the bit
itself can even be completed at the same time in one programming action.

BLOCK1 cannot be programmed by users as it has been programmed at manufacturing.

BLOCK2 ~ 10 can only be programmed once. Repeated programming is not allowed.

Espressif Systems 180 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

6.3.3 Reading of Parameters by Users

Users cannot read eFuse bits directly. The eFuse controller hardware reads all eFuse bits and stores the
results to their corresponding registers in its memory space. Then, users can read eFuse bits by reading the
registers that start with EFUSE_RD_. Details are provided in Table 6-4.

Table 6-4. Registers Information

BLOCK Read Registers Registers When Programming This Block

0 EFUSE_RD_WR_DIS_REG EFUSE_PGM_DATA0_REG
0 EFUSE_RD_REPEAT_DATA0 ~ 4_REG EFUSE_PGM_DATA1 ~ 5_REG
1 EFUSE_RD_MAC_SPI_SYS_0 ~ 5_REG EFUSE_PGM_DATA0 ~ 5_REG
2 EFUSE_RD_SYS_DATA_PART1_0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
3 EFUSE_RD_USR_DATA0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
4-9 EFUSE_RD_KEYn_DATA0 ~ 7_REG (n: 0 ~ 5) EFUSE_PGM_DATA0 ~ 7_REG
10 EFUSE_RD_SYS_DATA_PART2_0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG

Updating reading data registers

The eFuse controller reads eFuse memory to update corresponding registers. This read operation happens at
system reset and can also be triggered manually by users as needed (e.g., if new eFuse values have been
programmed). The process of triggering a read operation by users is as follows:

1. Configure the field EFUSE_OP_CODE in register EFUSE_CONF_REG to 0x5AA5.

2. Configure the field EFUSE_READ_CMD in register EFUSE_CMD_REG to 1.

3. Poll register EFUSE_CMD_REG until it is 0x0, or wait for a READ_DONE interrupt. Information on how to
identify a PGM_DONE or READ_DONE interrupt is provided below in this section.

4. Read the values of each parameter from eFuse memory.

The eFuse read registers will hold all values until the next read operation.

Error detection

Error record registers allow users to detect if there is any inconsistency between the parameter read by eFuse
controller and that in eFuse memory.

Registers EFUSE_RD_REPEAT_ERR0 ~ 3_REG indicate if there are any errors in programming parameters
(except EFUSE_WR_DIS) to BLOCK0. The value 1 indicates an error is detected in programming the
corresponding bit. The value 0 indicates no error.

Registers EFUSE_RD_RS_ERR0 ~ 1_REG store the number of corrected bytes as well as the result of RS
decoding when eFuse controller reads BLOCK1 ~ BLOCK10.

The values of the above registers will be updated every time the reading data registers of eFuse controller
have been updated.

Identifying program/read operation

The methods to identify the completion of a program/read operation are described below. Please note that bit
1 corresponds to a program operation, and bit 0 corresponds to a read operation.

Espressif Systems 181 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

• Method one: Poll bit 1/0 in register EFUSE_INT_RAW_REG until it becomes 1, which represents the
completion of a program/read operation.

• Method two:

1. Set bit 1/0 in register EFUSE_INT_ENA_REG to 1 to enable the eFuse controller to post a
PGM_DONE or READ_DONE interrupt.

2. Configure the Interrupt Matrix to enable the CPU to respond to eFuse interrupt signals. See Chapter
10 Interrupt Matrix (INTMTX).

3. Wait for the PGM_DONE or READ_DONE interrupt.

4. Set bit 1/0 in register EFUSE_INT_CLR_REG to 1 to clear the PGM_DONE or READ_DONE interrupt.

Note

When eFuse controller is updating its registers, it will use EFUSE_PGM_DATAn_REG (n=0, 1, ... ,7) again to
store data. So please do not write important data into these registers before this updating process is
initiated.
During the chip boot process, eFuse controller will automatically update data from eFuse memory into the
registers that can be accessed by users. Users can get programmed eFuse data by reading corresponding
registers. Thus, there is no need to update the reading data registers in such case.

6.3.4 eFuse VDDQ Timing

The eFuse controller operates at the clock frequency of 20 MHz, and its programming voltage VDDQ should
be configured as follows:

• EFUSE_DAC_NUM (the rising period of VDDQ): The default value of VDDQ is 2.5 V and the voltage
increases by 0.01 V in each clock cycle. The default value of this parameter is 255.

• EFUSE_DAC_CLK_DIV (the clock divisor of VDDQ): The clock period to program VDDQ should be larger
than 1 µs.

• EFUSE_PWR_ON_NUM (the power-up time for VDDQ): The programming voltage should be stabilized
after this time, which means the value of this parameter should be configured to exceed the result of
EFUSE_DAC_CLK_DIV times EFUSE_DAC_NUM.

• EFUSE_PWR_OFF_NUM (the power-out time for VDDQ): The value of this parameter should be larger
than 10 µs.

Table 6-5. Configuration of Default VDDQ Timing Parameters

EFUSE_DAC_NUM EFUSE_DAC_CLK_DIV EFUSE_PWR_ON_NUM EFUSE_PWR_OFF_NUM

0xFF 0x28 0x3000 0x190

6.3.5 Parameters Used by Hardware Modules

Some hardware modules are directly connected to the eFuse peripheral in order to use the parameters that
are marked with “Y” in columns “Accessible by Hardware” of Table 6-1 and Table 6-3. Users cannot intervene
in this process.

Espressif Systems 182 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

6.3.6 Interrupts
• PGM_DONE interrupt: Triggered when eFuse programming has finished. To enable this interrupt, set the
EFUSE_PGM_DONE_INT_ENA field of register EFUSE_INT_ENA_REG to 1.

• READ_DONE interrupt: Triggered when eFuse reading has finished. To enable this interrupt, set the
EFUSE_READ_DONE_INT_ENA field of register EFUSE_INT_ENA_REG to 1.

Espressif Systems 183 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

6.4 Register Summary

The addresses in this section are relative to eFuse controller base address provided in Table 5-2 in Chapter 5
System and Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

Programming Data Register
EFUSE_PGM_DATA0_REG Register 0 that stores data to be programmed 0x0000 R/W
EFUSE_PGM_DATA1_REG Register 1 that stores data to be programmed 0x0004 R/W
EFUSE_PGM_DATA2_REG Register 2 that stores data to be programmed 0x0008 R/W
EFUSE_PGM_DATA3_REG Register 3 that stores data to be programmed 0x000C R/W
EFUSE_PGM_DATA4_REG Register 4 that stores data to be programmed 0x0010 R/W
EFUSE_PGM_DATA5_REG Register 5 that stores data to be programmed 0x0014 R/W
EFUSE_PGM_DATA6_REG Register 6 that stores data to be programmed 0x0018 R/W
EFUSE_PGM_DATA7_REG Register 7 that stores data to be programmed 0x001C R/W
EFUSE_PGM_CHECK_VALUE0_REG Register 0 that stores the RS code to be pro- 0x0020 R/W
grammed
EFUSE_PGM_CHECK_VALUE1_REG Register 1 that stores the RS code to be pro- 0x0024 R/W
grammed
EFUSE_PGM_CHECK_VALUE2_REG Register 2 that stores the RS code to be pro- 0x0028 R/W
grammed
Reading Data Register
EFUSE_RD_WR_DIS_REG Register 0 of BLOCK0 0x002C RO
EFUSE_RD_REPEAT_DATA0_REG Register 1 of BLOCK0 0x0030 RO
EFUSE_RD_REPEAT_DATA1_REG Register 2 of BLOCK0 0x0034 RO
EFUSE_RD_REPEAT_DATA2_REG Register 3 of BLOCK0 0x0038 RO
EFUSE_RD_REPEAT_DATA3_REG Register 4 of BLOCK0 0x003C RO
EFUSE_RD_REPEAT_DATA4_REG Register 5 of BLOCK0 0x0040 RO
EFUSE_RD_MAC_SPI_SYS_0_REG Register 0 of BLOCK1 0x0044 RO
EFUSE_RD_MAC_SPI_SYS_1_REG Register 1 of BLOCK1 0x0048 RO
EFUSE_RD_MAC_SPI_SYS_2_REG Register 2 of BLOCK1 0x004C RO
EFUSE_RD_MAC_SPI_SYS_3_REG Register 3 of BLOCK1 0x0050 RO
EFUSE_RD_MAC_SPI_SYS_4_REG Register 4 of BLOCK1 0x0054 RO
EFUSE_RD_MAC_SPI_SYS_5_REG Register 5 of BLOCK1 0x0058 RO
EFUSE_RD_SYS_PART1_DATA0_REG Register 0 of BLOCK2 (system) 0x005C RO
EFUSE_RD_SYS_PART1_DATA1_REG Register 1 of BLOCK2 (system) 0x0060 RO
EFUSE_RD_SYS_PART1_DATA2_REG Register 2 of BLOCK2 (system) 0x0064 RO
EFUSE_RD_SYS_PART1_DATA3_REG Register 3 of BLOCK2 (system) 0x0068 RO
EFUSE_RD_SYS_PART1_DATA4_REG Register 4 of BLOCK2 (system) 0x006C RO
EFUSE_RD_SYS_PART1_DATA5_REG Register 5 of BLOCK2 (system) 0x0070 RO
EFUSE_RD_SYS_PART1_DATA6_REG Register 6 of BLOCK2 (system) 0x0074 RO
EFUSE_RD_SYS_PART1_DATA7_REG Register 7 of BLOCK2 (system) 0x0078 RO
EFUSE_RD_USR_DATA0_REG Register 0 of BLOCK3 (user) 0x007C RO
EFUSE_RD_USR_DATA1_REG Register 1 of BLOCK3 (user) 0x0080 RO

Espressif Systems 184 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Name Description Address Access

EFUSE_RD_USR_DATA2_REG Register 2 of BLOCK3 (user) 0x0084 RO
EFUSE_RD_USR_DATA3_REG Register 3 of BLOCK3 (user) 0x0088 RO
EFUSE_RD_USR_DATA4_REG Register 4 of BLOCK3 (user) 0x008C RO
EFUSE_RD_USR_DATA5_REG Register 5 of BLOCK3 (user) 0x0090 RO
EFUSE_RD_USR_DATA6_REG Register 6 of BLOCK3 (user) 0x0094 RO
EFUSE_RD_USR_DATA7_REG Register 7 of BLOCK3 (user) 0x0098 RO
EFUSE_RD_KEY0_DATA0_REG Register 0 of BLOCK4 (KEY0) 0x009C RO
EFUSE_RD_KEY0_DATA1_REG Register 1 of BLOCK4 (KEY0) 0x00A0 RO
EFUSE_RD_KEY0_DATA2_REG Register 2 of BLOCK4 (KEY0) 0x00A4 RO
EFUSE_RD_KEY0_DATA3_REG Register 3 of BLOCK4 (KEY0) 0x00A8 RO
EFUSE_RD_KEY0_DATA4_REG Register 4 of BLOCK4 (KEY0) 0x00AC RO
EFUSE_RD_KEY0_DATA5_REG Register 5 of BLOCK4 (KEY0) 0x00B0 RO
EFUSE_RD_KEY0_DATA6_REG Register 6 of BLOCK4 (KEY0) 0x00B4 RO
EFUSE_RD_KEY0_DATA7_REG Register 7 of BLOCK4 (KEY0) 0x00B8 RO
EFUSE_RD_KEY1_DATA0_REG Register 0 of BLOCK5 (KEY1) 0x00BC RO
EFUSE_RD_KEY1_DATA1_REG Register 1 of BLOCK5 (KEY1) 0x00C0 RO
EFUSE_RD_KEY1_DATA2_REG Register 2 of BLOCK5 (KEY1) 0x00C4 RO
EFUSE_RD_KEY1_DATA3_REG Register 3 of BLOCK5 (KEY1) 0x00C8 RO
EFUSE_RD_KEY1_DATA4_REG Register 4 of BLOCK5 (KEY1) 0x00CC RO
EFUSE_RD_KEY1_DATA5_REG Register 5 of BLOCK5 (KEY1) 0x00D0 RO
EFUSE_RD_KEY1_DATA6_REG Register 6 of BLOCK5 (KEY1) 0x00D4 RO
EFUSE_RD_KEY1_DATA7_REG Register 7 of BLOCK5 (KEY1) 0x00D8 RO
EFUSE_RD_KEY2_DATA0_REG Register 0 of BLOCK6 (KEY2) 0x00DC RO
EFUSE_RD_KEY2_DATA1_REG Register 1 of BLOCK6 (KEY2) 0x00E0 RO
EFUSE_RD_KEY2_DATA2_REG Register 2 of BLOCK6 (KEY2) 0x00E4 RO
EFUSE_RD_KEY2_DATA3_REG Register 3 of BLOCK6 (KEY2) 0x00E8 RO
EFUSE_RD_KEY2_DATA4_REG Register 4 of BLOCK6 (KEY2) 0x00EC RO
EFUSE_RD_KEY2_DATA5_REG Register 5 of BLOCK6 (KEY2) 0x00F0 RO
EFUSE_RD_KEY2_DATA6_REG Register 6 of BLOCK6 (KEY2) 0x00F4 RO
EFUSE_RD_KEY2_DATA7_REG Register 7 of BLOCK6 (KEY2) 0x00F8 RO
EFUSE_RD_KEY3_DATA0_REG Register 0 of BLOCK7 (KEY3) 0x00FC RO
EFUSE_RD_KEY3_DATA1_REG Register 1 of BLOCK7 (KEY3) 0x0100 RO
EFUSE_RD_KEY3_DATA2_REG Register 2 of BLOCK7 (KEY3) 0x0104 RO
EFUSE_RD_KEY3_DATA3_REG Register 3 of BLOCK7 (KEY3) 0x0108 RO
EFUSE_RD_KEY3_DATA4_REG Register 4 of BLOCK7 (KEY3) 0x010C RO
EFUSE_RD_KEY3_DATA5_REG Register 5 of BLOCK7 (KEY3) 0x0110 RO
EFUSE_RD_KEY3_DATA6_REG Register 6 of BLOCK7 (KEY3) 0x0114 RO
EFUSE_RD_KEY3_DATA7_REG Register 7 of BLOCK7 (KEY3) 0x0118 RO
EFUSE_RD_KEY4_DATA0_REG Register 0 of BLOCK8 (KEY4) 0x011C RO
EFUSE_RD_KEY4_DATA1_REG Register 1 of BLOCK8 (KEY4) 0x0120 RO
EFUSE_RD_KEY4_DATA2_REG Register 2 of BLOCK8 (KEY4) 0x0124 RO
EFUSE_RD_KEY4_DATA3_REG Register 3 of BLOCK8 (KEY4) 0x0128 RO
EFUSE_RD_KEY4_DATA4_REG Register 4 of BLOCK8 (KEY4) 0x012C RO

Espressif Systems 185 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Name Description Address Access

EFUSE_RD_KEY4_DATA5_REG Register 5 of BLOCK8 (KEY4) 0x0130 RO
EFUSE_RD_KEY4_DATA6_REG Register 6 of BLOCK8 (KEY4) 0x0134 RO
EFUSE_RD_KEY4_DATA7_REG Register 7 of BLOCK8 (KEY4) 0x0138 RO
EFUSE_RD_KEY5_DATA0_REG Register 0 of BLOCK9 (KEY5) 0x013C RO
EFUSE_RD_KEY5_DATA1_REG Register 1 of BLOCK9 (KEY5) 0x0140 RO
EFUSE_RD_KEY5_DATA2_REG Register 2 of BLOCK9 (KEY5) 0x0144 RO
EFUSE_RD_KEY5_DATA3_REG Register 3 of BLOCK9 (KEY5) 0x0148 RO
EFUSE_RD_KEY5_DATA4_REG Register 4 of BLOCK9 (KEY5) 0x014C RO
EFUSE_RD_KEY5_DATA5_REG Register 5 of BLOCK9 (KEY5) 0x0150 RO
EFUSE_RD_KEY5_DATA6_REG Register 6 of BLOCK9 (KEY5) 0x0154 RO
EFUSE_RD_KEY5_DATA7_REG Register 7 of BLOCK9 (KEY5) 0x0158 RO
EFUSE_RD_SYS_PART2_DATA0_REG Register 0 of BLOCK10 (system) 0x015C RO
EFUSE_RD_SYS_PART2_DATA1_REG Register 1 of BLOCK10 (system) 0x0160 RO
EFUSE_RD_SYS_PART2_DATA2_REG Register 2 of BLOCK10 (system) 0x0164 RO
EFUSE_RD_SYS_PART2_DATA3_REG Register 3 of BLOCK10 (system) 0x0168 RO
EFUSE_RD_SYS_PART2_DATA4_REG Register 4 of BLOCK10 (system) 0x016C RO
EFUSE_RD_SYS_PART2_DATA5_REG Register 5 of BLOCK10 (system) 0x0170 RO
EFUSE_RD_SYS_PART2_DATA6_REG Register 6 of BLOCK10 (system) 0x0174 RO
EFUSE_RD_SYS_PART2_DATA7_REG Register 7 of BLOCK10 (system) 0x0178 RO
Report Register
EFUSE_RD_REPEAT_ERR0_REG Programming error record register 0 of 0x017C RO
BLOCK0
EFUSE_RD_REPEAT_ERR1_REG Programming error record register 1 of 0x0180 RO
BLOCK0
EFUSE_RD_REPEAT_ERR2_REG Programming error record register 2 of 0x0184 RO
BLOCK0
EFUSE_RD_REPEAT_ERR3_REG Programming error record register 3 of 0x0188 RO
BLOCK0
EFUSE_RD_REPEAT_ERR4_REG Programming error record register 4 of 0x0190 RO
BLOCK0
EFUSE_RD_RS_ERR0_REG Programming error record register 0 of 0x01C0 RO
BLOCK1-10
EFUSE_RD_RS_ERR1_REG Programming error record register 1 of 0x01C4 RO
BLOCK1-10
Configuration Register
EFUSE_CLK_REG eFuse clock configuration register 0x01C8 R/W
EFUSE_CONF_REG eFuse operation mode configuration register 0x01CC R/W
EFUSE_CMD_REG eFuse command register 0x01D4 varies
EFUSE_DAC_CONF_REG Controls the eFuse programming voltage 0x01E8 R/W
EFUSE_RD_TIM_CONF_REG Configures read timing parameters 0x01EC R/W
EFUSE_WR_TIM_CONF1_REG Configuration register 1 of eFuse programming 0x01F0 R/W
timing parameters
EFUSE_WR_TIM_CONF2_REG Configuration register 2 of eFuse program- 0x01F4 R/W
ming timing parameters

Espressif Systems 186 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Name Description Address Access

EFUSE_WR_TIM_CONF0_REG Configuration register 0 of eFuse program- 0x01F8 varies
ming timing parameters
Status Register
EFUSE_STATUS_REG eFuse status register 0x01D0 RO
Interrupt Register
EFUSE_INT_RAW_REG eFuse raw interrupt register 0x01D8 R/SS/WTC
EFUSE_INT_ST_REG eFuse interrupt status register 0x01DC RO
EFUSE_INT_ENA_REG eFuse interrupt enable register 0x01E0 R/W
EFUSE_INT_CLR_REG eFuse interrupt clear register 0x01E4 WO
Version Control Register
EFUSE_DATE_REG Version control register 0x01FC R/W

Espressif Systems 187 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

6.5 Registers
The addresses in this section are relative to eFuse controller base address provided in Table 5-2 in Chapter 5
System and Memory.

Register 6.1. EFUSE_PGM_DATA0_REG (0x0000)

_0
A
AT
_D
GM
_P
SE
U
EF
31 0

0x000000 Reset

EFUSE_PGM_DATA_0 Configures the 0th 32-bit data to be programmed. (R/W)

Register 6.2. EFUSE_PGM_DATA1_REG (0x0004)

_1
A
AT
_D
PGM
E_
US
EF

31 0

0x000000 Reset

EFUSE_PGM_DATA_1 Configures the 1st 32-bit data to be programmed. (R/W)

Register 6.3. EFUSE_PGM_DATA2_REG (0x0008)

_2
A
AT
_D
M
PG
E_
US
EF

31 0

0x000000 Reset

EFUSE_PGM_DATA_2 Configures the 2nd 32-bit data to be programmed. (R/W)

Espressif Systems 188 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.4. EFUSE_PGM_DATA3_REG (0x000C)

_3
A
AT
_D
GM
_P
SE
U
EF
31 0

0x000000 Reset

EFUSE_PGM_DATA_3 Configures the 3rd 32-bit data to be programmed. (R/W)

Register 6.5. EFUSE_PGM_DATA4_REG (0x0010)

_4
A
AT
_D
M
PG
E_
US
EF

31 0

0x000000 Reset

EFUSE_PGM_DATA_4 Configures the 4th 32-bit data to be programmed. (R/W)

Register 6.6. EFUSE_PGM_DATA5_REG (0x0014)

_5
A
AT
_D
M
PG
E_
US
EF

31 0

0x000000 Reset

EFUSE_PGM_DATA_5 Configures the 5th 32-bit data to be programmed. (R/W)

Register 6.7. EFUSE_PGM_DATA6_REG (0x0018)

_6
A
AT
_D
GM
E _P
US
EF

31 0

0x000000 Reset

EFUSE_PGM_DATA_6 Configures the 6th 32-bit data to be programmed. (R/W)

Espressif Systems 189 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.8. EFUSE_PGM_DATA7_REG (0x001C)

A _7
AT
_D
GM
_P
SE
U
EF
31 0

0x000000 Reset

EFUSE_PGM_DATA_7 Configures the 7th 32-bit data to be programmed. (R/W)

Register 6.9. EFUSE_PGM_CHECK_VALUE0_REG (0x0020)

_0
TA
DA
S_
_R
GM
_P
SE
U
EF

31 0

0x000000 Reset

EFUSE_PGM_RS_DATA_0 Configures the 0th 32-bit RS code to be programmed. (R/W)

Register 6.10. EFUSE_PGM_CHECK_VALUE1_REG (0x0024)

_1
TA
DA
S_
_R
M
PG
E_
US
EF

31 0

0x000000 Reset

EFUSE_PGM_RS_DATA_1 Configures the 1st 32-bit RS code to be programmed. (R/W)

Espressif Systems 190 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.11. EFUSE_PGM_CHECK_VALUE2_REG (0x0028)

_2
TA
DA
S_
_R
GM
_P
SE
U
EF
31 0

0x000000 Reset

EFUSE_PGM_RS_DATA_2 Configures the 2nd 32-bit RS code to be programmed. (R/W)

Register 6.12. EFUSE_RD_WR_DIS_REG (0x002C)

IS
D
R_
E_W
US
EF

31 0

0x000000 Reset

EFUSE_WR_DIS Represents whether programming of individual eFuse memory bit is disabled.

1: Disabled
0: Enabled
(RO)

Espressif Systems 191 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.13. EFUSE_RD_REPEAT_DATA0_REG (0x0030)

T
YP
CR
EN
L_

EF SE_ IS_ WN RIA LO DIS

HE
UA

US DI US LO L_ AD
U D DO SE WN I_

SW ICA JTA _I G
AN

AP CH G CAC
EF E_ S_ B_ DO SP

E_ S_ B_ AD JTA

N
EX AS_ _2
RV _0

_E
RV _1

AG M

US DI US E_ _M
LE
G_ PIO
D0

NS

IO
JT D_
ED

ED

AB

EF SE_ IS_ RC AD
G

SD
VE

PI
CH G

D_ OA

TA

U D O LO

T_
ER

US SP W E
PA NL

_J

_U E
SE

SE

EF E_ S_T EL_

EF SE_ IS_ WN

AR
ES

B_ I_

IS
S_ W

EF E_ _ I
RE

RE

A
US SP

_D
_R

DI DO

U D DO
US DI _S

IS
_

_D
FT
E_ D_
US PT4

T4

T4

EF E_ AG
E_ S_

I
SO

RD
RP

RP

)
US VD

US JT
US DI
ed
_R

E_

E_

EF E_

EF SE_

E_

EF E_

E_
rv
SE

US

US

US

US

US
se
U

U
(re
EF

EF

EF

EF

EF

EF

EF

EF
31 30 29 28 27 26 25 24 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 0

0x0 0 0x0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0 0 0x0 Reset

EFUSE_RD_DIS Represents whether reading of individual eFuse block (BLOCK4 ~ BLOCK10) is dis-
abled.
1: Disabled
0: Enabled
(RO)

EFUSE_SWAP_UART_SDIO_EN Represents whether the pads of UART and SDIO are swapped or
not.
1: Swapped
0: Not swapped
(RO)

EFUSE_DIS_ICACHE Represents whether icache is disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_USB_JTAG Represents whether the USB-to-JTAG function is disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_DOWNLOAD_ICACHE Represents whether iCache is disabled in Download mode.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_USB_SERIAL_JTAG Represents whether USB-Serial-JTAG is disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_FORCE_DOWNLOAD Represents whether the function that forces chip into download
mode is disabled.
1: Disabled
0: Enabled
(RO)

Continued on the next page...

Espressif Systems 192 ESP32-C6 TRM (Version 1.0)
Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.13. EFUSE_RD_REPEAT_DATA0_REG (0x0030)

Continued from the previous page...

EFUSE_SPI_DOWNLOAD_MSPI_DIS Represents whether SPI0 controller is disabled during

boot_mode_download.
1: Disabled
0: Enabled
(RO)

EFUSE_DIS_TWAI Represents whether TWAI function is disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_JTAG_SEL_ENABLE Represents whether the selection of a JTAG signal source

through the strapping value of GPIO15 is enabled when both EFUSE_DIS_PAD_JTAG and
EFUSE_DIS_USB_JTAG are configured to 0.
1: Enabled
0: Disabled
(RO)

EFUSE_SOFT_DIS_JTAG Represents whether JTAG is disabled in the soft way. It can be restarted
via HMAC.
Odd count of bits with a value of 1: Disabled
Even count of bits with a value of 1: Enabled
(RO)

EFUSE_DIS_PAD_JTAG Represents whether JTAG is disabled in the hard way (permanently).

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT Represents whether flash encryption is disabled

(except in SPI boot mode).
1: Disabled
0: Enabled
(RO)

EFUSE_USB_EXCHG_PINS Represents whether the D+ and D- pins are exchanged.

1: Exchanged
0: Not exchanged
(RO)

EFUSE_VDD_SPI_AS_GPIO Represents whether the VDD_SPI pin is used as a regular GPIO.

1: Used as a regular GPIO
0: Not used as a regular GPIO
(RO)

Continued on the next page...

Espressif Systems 193 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.13. EFUSE_RD_REPEAT_DATA0_REG (0x0030)

Continued from the previous page...

EFUSE_RPT4_RESERVED0_2 Reserved. (RO)

EFUSE_RPT4_RESERVED0_1 Reserved. (RO)

EFUSE_RPT4_RESERVED0_0 Reserved. (RO)

Espressif Systems 194 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.14. EFUSE_RD_REPEAT_DATA1_REG (0x0034)

0
Y_ VO 2
VO 1
KE RE KE
RE KE
KE
T_ Y_ VO
OO KE RE

T
CN
_B T_ Y_

_0
T_
RE OO KE

D1
_0

YP
_1

EL
CU _B T_

E
SE

SE

RV
CR
SE RE OO

_S
PO

PO

SE
AY
T_
E_ CU _B

EL

E
OO
UR

UR

US SE RE

_R
_D
P

B
EF E_ CU

T4
Y_

Y_

I_

DT

RP
SP
KE

KE

US SE

W
E_

E_

EF E_

E_

E_

E_
US

US

US

US

US

US
EF

EF

EF

EF

EF

EF
31 28 27 24 23 22 21 20 18 17 16 15 0

0x0 0x0 0 0 0 0x0 0x0 0x00 Reset

EFUSE_RPT4_RESERVED1_0 Reserved. (RO)

EFUSE_WDT_DELAY_SEL Represents whether RTC watchdog timeout threshold is selected at

startup.
1: Selected.
0: Not selected
(RO)

EFUSE_SPI_BOOT_CRYPT_CNT Represents whether SPI boot encryption/decryption is enabled.

Odd count of bits with a value of 1: Enabled
Even count of bits with a value of 1: Disabled
(RO)

EFUSE_SECURE_BOOT_KEY_REVOKE0 Represents whether revoking the first Secure Boot key is

enabled.
1: Enabled
0: Disabled
(RO)

EFUSE_SECURE_BOOT_KEY_REVOKE1 Represents whether revoking the second Secure Boot key

is enabled.
1: Enabled
0: Disabled
(RO)

EFUSE_SECURE_BOOT_KEY_REVOKE2 Represents whether revoking the third Secure Boot key is

enabled.
1: Enabled
0: Disabled
(RO)

EFUSE_KEY_PURPOSE_0 Represents the purpose of Key0. (RO)

EFUSE_KEY_PURPOSE_1 Represents the purpose of Key1. (RO)

Espressif Systems 195 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.15. EFUSE_RD_REPEAT_DATA2_REG (0x0038)

E
OK
EV
_R
VE
SI
T_ ER EN ES
US RYP ES OT_ GR
0

LE
EN _1
2_

C _R O AG

AB
A _ D2

2
3
4
5
ED

L
E_ T4 _B T_

E_

E_

E_

E_
VE
DP VE
RV

US RP RE OO
UW

OS

OS

OS

OS
LE
SE

EF E_ CU _B

A_

RP

RP

RP

RP
P

RE
_T

US SE RE

DP

PU

PU

PU

PU
H

EF E_ CU

C_
T4
AS

Y_

Y_

Y_

Y_
RP

KE

KE

KE

KE
US SE

SE
FL
E_

E_

EF E_

E_

E_

E_

E_

E_
US

US

US

US

US

US

US
EF

EF

EF

EF

EF

EF

EF

EF
31 28 27 22 21 20 19 18 17 16 15 12 11 8 7 4 3 0

0x0 0x0 0 0 1 0 0x0 0x0 0x0 0x0 0x0 Reset

EFUSE_KEY_PURPOSE_2 Represents the purpose of Key2. (RO)

EFUSE_KEY_PURPOSE_3 Represents the purpose of Key3. (RO)

EFUSE_KEY_PURPOSE_4 Represents the purpose of Key4. (RO)

EFUSE_KEY_PURPOSE_5 Represents the purpose of Key5. (RO)

EFUSE_SEC_DPA_LEVEL Represents the security level of anti-DPA attack.

0: Security level is SEC_DPA_OFF
1: Security level is SEC_DPA_LOW
2: Security level is SEC_DPA_MIDDLE
3: Security level is SEC_DPA_HIGH
For more information, please refer to Chapter 17 System Registers > Section 17.3.2.
(RO)

EFUSE_CRYPT_DPA_ENABLE Represents whether defense against DPA attack is enabled.

1: Enabled
0: Disabled
(RO)

EFUSE_RPT4_RESERVED2_1 Reserved. (RO)

EFUSE_SECURE_BOOT_EN Represents whether Secure Boot is enabled.

1: Enabled
0: Disabled
(RO)

EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE Represents whether aggressive revocation of Se-

cure Boot is enabled.
1: Enabled
0: Disabled
(RO)

EFUSE_RPT4_RESERVED2_0 Reserved. (RO)

EFUSE_FLASH_TPUW Represents the flash waiting time after power-up. Measurement unit: ms.
When the value is less than 15, the waiting time is the programmed value. Otherwise, the waiting
time is a fixed value, i.e. 30 ms. (RO)

Espressif Systems 196 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.16. EFUSE_RD_REPEAT_DATA3_REG (0x003C)

E
OD
M
D_
E

NT
AK

OA

RI
_W

NL

_P
S_ E RI _5 D AD
ST

OW

M
DI DIR SE D3 G_ LO
FA

RO
E_ S_ B_ VE JTA N
E_

US DI US ER L_ OW

OA T _

E
D ME

NL O AG
BL

OD
US RP US EC TRO

EF SE_ IS_ ES RIA Y_D

2
T_ _0

VE _3
_4

W BO JT
SA

VE SU
ER 3_1

3_

M
DO CT_ AL_
OO D3

ER D3
D3
DI

ON

U D _R SE IT
N

D_
ER RE

ED

EF E_ T4 _ R
_B VE

ES VE
ES D_
SI

U
C
V

T_
ER
RE ER

_R ER
_R N

N
US PT4 _SE

EF E_ S_ _S
_V
CU ES

ES

US PT4 ES

RI

B
RE

US DI LE
SE _R

_R

R _R

_P
R E
E_ RC

EF E_ AB
U

RT
E_ T4

T4

E_ T4
EC

US EN
US FO
US RP

RP

US RP

UA
_S
EF SE_

EF SE_

E_

EF E_

E_

EF E_
SE

US

US
U

U
EF

EF

EF

EF

EF

EF

EF
31 30 29 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0x00 0 0 0x0 0 0 0x0 0 0 0 0 0 0 Reset

EFUSE_DIS_DOWNLOAD_MODE Represents whether all download modes are disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_DIRECT_BOOT Represents whether direct boot mode is disabled.

1: Disabled
0: Enabled
(RO)

EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT Represents whether print from USB-Serial-JTAG dur-

ing ROM boot is disabled.
1: Disabled
0: Enabled
(RO)

EFUSE_RPT4_RESERVED3_5 Reserved. (RO)

EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE Represents whether the USB-Serial-JTAG

download function is disabled.
1: Disabled
0: Enabled
(RO)

EFUSE_ENABLE_SECURITY_DOWNLOAD Represents whether security download is enabled. Only

UART is supported for download. Reading/writing RAM or registers is not supported (i.e. Stub
download is not supported).
1: Enabled
0: Disabled
(RO)

Continued on the next page...

Espressif Systems 197 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.16. EFUSE_RD_REPEAT_DATA3_REG (0x003C)

Continued from the previous page...

EFUSE_UART_PRINT_CONTROL Represents the type of UART printing.

0: Force enable printing.
1: Enable printing when GPIO8 is reset at low level.
2: Enable printing when GPIO8 is reset at high level.
3: Force disable printing.
(RO)

EFUSE_RPT4_RESERVED3_4 Reserved. (RO)

EFUSE_RPT4_RESERVED3_3 Reserved. (RO)

EFUSE_RPT4_RESERVED3_2 Reserved. (RO)

EFUSE_RPT4_RESERVED3_1 Reserved. (RO)

EFUSE_FORCE_SEND_RESUME Represents whether ROM code is forced to send a resume com-

mand during SPI boot.
1: Forced.
0: Not forced.
(RO)

EFUSE_SECURE_VERSION Represents the security version used by ESP-IDF anti-rollback feature.

(RO)

EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE Represents whether FAST VERIFY ON WAKE is dis-

abled when Secure Boot is enabled.
1: Disabled
0: Enabled
(RO)

EFUSE_RPT4_RESERVED3_0 Reserved. (RO)

Register 6.17. EFUSE_RD_REPEAT_DATA4_REG (0x0040)

_0

_1
D4

D4
E

E
RV

RV
SE

SE
RE

RE
4_

4_
PT

PT
_R

_R
E

E
US

US
EF

EF

31 24 23 0

0x0 0x0000 Reset

EFUSE_RPT4_RESERVED4_1 Reserved. (RO)

EFUSE_RPT4_RESERVED4_0 Reserved. (RO)

Espressif Systems 198 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.18. EFUSE_RD_MAC_SPI_SYS_0_REG (0x0044)

_0
AC
E _M
US
EF
31 0

0x000000 Reset

EFUSE_MAC_0 Represents the low 32 bits of MAC address. (RO)

Register 6.19. EFUSE_RD_MAC_SPI_SYS_1_REG (0x0048)

XT
_E

_1
AC

AC
M

_M
E_

E
US

US
EF

EF
31 16 15 0

0x00 0x00 Reset

EFUSE_MAC_1 Represents the high 16 bits of MAC address. (RO)

EFUSE_MAC_EXT Represents the extended bits of MAC address. (RO)

Register 6.20. EFUSE_RD_MAC_SPI_SYS_2_REG (0x004C)

D
E
RV
_1

SE
NF

RE
CO

I_
D_

P
_S
PA

AC
I_
SP

_M
E_

E
US

US
EF

EF

31 14 13 0

0x000 0x00 Reset

EFUSE_MAC_SPI_RESERVED Reserved. (RO)

EFUSE_SPI_PAD_CONF_1 Represents the first part of SPI_PAD_CONF. (RO)

Espressif Systems 199 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.21. EFUSE_RD_MAC_SPI_SYS_3_REG (0x0050)

_0
T0

_2
NF
AR
_P

CO
TA

D_
DA

PA
S_

I_
SP
SY
E_

E_
US

US
EF

EF
31 18 17 0

0x00 0x000 Reset

EFUSE_SPI_PAD_CONF_2 Represents the second part of SPI_PAD_CONF. (RO)

EFUSE_SYS_DATA_PART0_0 Represents the first 14 bits of the zeroth part of system data. (RO)

Register 6.22. EFUSE_RD_MAC_SPI_SYS_4_REG (0x0054)

1
0_
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART0_1 Represents the first 32 bits of the zeroth part of system data. (RO)

Register 6.23. EFUSE_RD_MAC_SPI_SYS_5_REG (0x0058)

_2
T0
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART0_2 Represents the second 32 bits of the zeroth part of system data. (RO)

Espressif Systems 200 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.24. EFUSE_RD_SYS_PART1_DATA0_REG (0x005C)

0
1_
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_0 Represents the zeroth 32 bits of the first part of system data. (RO)

Register 6.25. EFUSE_RD_SYS_PART1_DATA1_REG (0x0060)

1
1_
RT
PA
_
TA
DA
_
YS
E_S
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_1 Represents the first 32 bits of the first part of system data. (RO)

Register 6.26. EFUSE_RD_SYS_PART1_DATA2_REG (0x0064)

2
1_
RT
PA
_
TA
DA
_
YS
E _S
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_2 Represents the second 32 bits of the first part of system data. (RO)

Espressif Systems 201 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.27. EFUSE_RD_SYS_PART1_DATA3_REG (0x0068)

3
1_
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_3 Represents the third 32 bits of the first part of system data. (RO)

Register 6.28. EFUSE_RD_SYS_PART1_DATA4_REG (0x006C)

4
1_
RT
PA
_
TA
DA
_
YS
E_S
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_4 Represents the fourth 32 bits of the first part of system data. (RO)

Register 6.29. EFUSE_RD_SYS_PART1_DATA5_REG (0x0070)

_5
T1
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_5 Represents the fifth 32 bits of the first part of system data. (RO)

Espressif Systems 202 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.30. EFUSE_RD_SYS_PART1_DATA6_REG (0x0074)

6
1_
RT
PA
_
TA
_ DA
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_6 Represents the sixth 32 bits of the first part of system data. (RO)

Register 6.31. EFUSE_RD_SYS_PART1_DATA7_REG (0x0078)

_7
T1
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART1_7 Represents the seventh 32 bits of the first part of system data. (RO)

Register 6.32. EFUSE_RD_USR_DATA0_REG (0x007C)

0
TA
DA
R_
S
E _U
US
EF

31 0

0x000000 Reset

EFUSE_USR_DATA0 Represents the zeroth 32 bits of BLOCK3 (user). (RO)

Espressif Systems 203 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.33. EFUSE_RD_USR_DATA1_REG (0x0080)

1A
AT
_D
SR
E _U
US
EF
31 0

0x000000 Reset

EFUSE_USR_DATA1 Represents the first 32 bits of BLOCK3 (user). (RO)

Register 6.34. EFUSE_RD_USR_DATA2_REG (0x0084)

2
TA
DA
R_
US
E_
US
EF

31 0

0x000000 Reset

EFUSE_USR_DATA2 Represents the second 32 bits of BLOCK3 (user). (RO)

Register 6.35. EFUSE_RD_USR_DATA3_REG (0x0088)

3
TA
DA
R_
S
_U
SE
U
EF

31 0

0x000000 Reset

EFUSE_USR_DATA3 Represents the third 32 bits of BLOCK3 (user). (RO)

Register 6.36. EFUSE_RD_USR_DATA4_REG (0x008C)

4
TA
DA
R_
S
E _U
US
EF

31 0

0x000000 Reset

EFUSE_USR_DATA4 Represents the fourth 32 bits of BLOCK3 (user). (RO)

Espressif Systems 204 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.37. EFUSE_RD_USR_DATA5_REG (0x0090)

A5
AT
_D
SR
_U
E
US
EF
31 0

0x000000 Reset

EFUSE_USR_DATA5 Represents the fifth 32 bits of BLOCK3 (user). (RO)

Register 6.38. EFUSE_RD_USR_DATA6_REG (0x0094)

6
TA
DA
R_
US
E_
US
EF

31 0

0x000000 Reset

EFUSE_USR_DATA6 Represents the sixth 32 bits of BLOCK3 (user). (RO)

Register 6.39. EFUSE_RD_USR_DATA7_REG (0x0098)

7
TA
DA
R_
US
E_
US
EF

31 0

0x000000 Reset

EFUSE_USR_DATA7 Represents the seventh 32 bits of BLOCK3 (user). (RO)

Register 6.40. EFUSE_RD_KEY0_DATA0_REG (0x009C)

0A
AT
_D
Y0
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA0 Represents the zeroth 32 bits of KEY0. (RO)

Espressif Systems 205 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.41. EFUSE_RD_KEY0_DATA1_REG (0x00A0)

1
TA
DA
0_
EY
E_K
US
EF
31 0

0x000000 Reset

EFUSE_KEY0_DATA1 Represents the first 32 bits of KEY0. (RO)

Register 6.42. EFUSE_RD_KEY0_DATA2_REG (0x00A4)

A2
AT
_D
Y0
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA2 Represents the second 32 bits of KEY0. (RO)

Register 6.43. EFUSE_RD_KEY0_DATA3_REG (0x00A8)

3
TA
DA
0_
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA3 Represents the third 32 bits of KEY0. (RO)

Register 6.44. EFUSE_RD_KEY0_DATA4_REG (0x00AC)

4
TA
DA
0_
EY
E _K
US
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA4 Represents the fourth 32 bits of KEY0. (RO)

Espressif Systems 206 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.45. EFUSE_RD_KEY0_DATA5_REG (0x00B0)

5
TA
DA
0_
EY
_K
SE
U
EF
31 0

0x000000 Reset

EFUSE_KEY0_DATA5 Represents the fifth 32 bits of KEY0. (RO)

Register 6.46. EFUSE_RD_KEY0_DATA6_REG (0x00B4)

6
TA
DA
0_
EY
E_K
US
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA6 Represents the sixth 32 bits of KEY0. (RO)

Register 6.47. EFUSE_RD_KEY0_DATA7_REG (0x00B8)

A7
AT
_D
Y0
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY0_DATA7 Represents the seventh 32 bits of KEY0. (RO)

Register 6.48. EFUSE_RD_KEY1_DATA0_REG (0x00BC)

0
TA
DA
1_
EY
E _K
US
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA0 Represents the zeroth 32 bits of KEY1. (RO)

Espressif Systems 207 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.49. EFUSE_RD_KEY1_DATA1_REG (0x00C0)

1
TA
DA
1_
EY
E_K
US
EF
31 0

0x000000 Reset

EFUSE_KEY1_DATA1 Represents the first 32 bits of KEY1. (RO)

Register 6.50. EFUSE_RD_KEY1_DATA2_REG (0x00C4)

2
TA
DA
1_
K EY
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA2 Represents the second 32 bits of KEY1. (RO)

Register 6.51. EFUSE_RD_KEY1_DATA3_REG (0x00C8)

3
TA
DA
1_
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA3 Represents the third 32 bits of KEY1. (RO)

Register 6.52. EFUSE_RD_KEY1_DATA4_REG (0x00CC)

A4
AT
_D
Y1
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA4 Represents the fourth 32 bits of KEY1. (RO)

Espressif Systems 208 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.53. EFUSE_RD_KEY1_DATA5_REG (0x00D0)

5
TA
DA
1_
EY
E _K
US
EF
31 0

0x000000 Reset

EFUSE_KEY1_DATA5 Represents the fifth 32 bits of KEY1. (RO)

Register 6.54. EFUSE_RD_KEY1_DATA6_REG (0x00D4)

A6
AT
_D
Y1
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA6 Represents the sixth 32 bits of KEY1. (RO)

Register 6.55. EFUSE_RD_KEY1_DATA7_REG (0x00D8)

7
TA
DA
1_
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY1_DATA7 Represents the seventh 32 bits of KEY1. (RO)

Register 6.56. EFUSE_RD_KEY2_DATA0_REG (0x00DC)

0
TA
DA
2_
EY
E _K
US
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA0 Represents the zeroth 32 bits of KEY2. (RO)

Espressif Systems 209 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.57. EFUSE_RD_KEY2_DATA1_REG (0x00E0)

A1
AT
_D
2
EY
_K
E
US
EF
31 0

0x000000 Reset

EFUSE_KEY2_DATA1 Represents the first 32 bits of KEY2. (RO)

Register 6.58. EFUSE_RD_KEY2_DATA2_REG (0x00E4)

2
TA
DA
2_
EY
_K
E
US
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA2 Represents the second 32 bits of KEY2. (RO)

Register 6.59. EFUSE_RD_KEY2_DATA3_REG (0x00E8)

A3
AT
_D
Y2
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA3 Represents the third 32 bits of KEY2. (RO)

Register 6.60. EFUSE_RD_KEY2_DATA4_REG (0x00EC)

A4
AT
_D
Y2
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA4 Represents the fourth 32 bits of KEY2. (RO)

Espressif Systems 210 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.61. EFUSE_RD_KEY2_DATA5_REG (0x00F0)

A5
AT
_D
Y2
KE
E_
US
EF
31 0

0x000000 Reset

EFUSE_KEY2_DATA5 Represents the fifth 32 bits of KEY2. (RO)

Register 6.62. EFUSE_RD_KEY2_DATA6_REG (0x00F4)

6
A
AT
_D
Y2
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA6 Represents the sixth 32 bits of KEY2. (RO)

Register 6.63. EFUSE_RD_KEY2_DATA7_REG (0x00F8)

A7
AT
_D
2
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY2_DATA7 Represents the seventh 32 bits of KEY2. (RO)

Register 6.64. EFUSE_RD_KEY3_DATA0_REG (0x00FC)

0
A
AT
_D
Y3
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA0 Represents the zeroth 32 bits of KEY3. (RO)

Espressif Systems 211 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.65. EFUSE_RD_KEY3_DATA1_REG (0x0100)

1
TA
DA
3_
EY
_K
E
US
EF
31 0

0x000000 Reset

EFUSE_KEY3_DATA1 Represents the first 32 bits of KEY3. (RO)

Register 6.66. EFUSE_RD_KEY3_DATA2_REG (0x0104)

A2
AT
_D
Y3
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA2 Represents the second 32 bits of KEY3. (RO)

Register 6.67. EFUSE_RD_KEY3_DATA3_REG (0x0108)

A3
AT
_D
Y3
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA3 Represents the third 32 bits of KEY3. (RO)

Register 6.68. EFUSE_RD_KEY3_DATA4_REG (0x010C)

4
TA
DA
3_
EY
_K
E
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA4 Represents the fourth 32 bits of KEY3. (RO)

Espressif Systems 212 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.69. EFUSE_RD_KEY3_DATA5_REG (0x0110)

5
TA
DA
3_
EY
_K
E
US
EF
31 0

0x000000 Reset

EFUSE_KEY3_DATA5 Represents the fifth 32 bits of KEY3. (RO)

Register 6.70. EFUSE_RD_KEY3_DATA6_REG (0x0114)

6
TA
DA
3_
EY
_K
E
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA6 Represents the sixth 32 bits of KEY3. (RO)

Register 6.71. EFUSE_RD_KEY3_DATA7_REG (0x0118)

A7
AT
_D
Y3
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY3_DATA7 Represents the seventh 32 bits of KEY3. (RO)

Register 6.72. EFUSE_RD_KEY4_DATA0_REG (0x011C)

0
TA
DA
4_
EY
_K
E
US
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA0 Represents the zeroth 32 bits of KEY4. (RO)

Espressif Systems 213 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.73. EFUSE_RD_KEY4_DATA1_REG (0x0120)

1
TA
DA
4_
EY
E_K
US
EF
31 0

0x000000 Reset

EFUSE_KEY4_DATA1 Represents the first 32 bits of KEY4. (RO)

Register 6.74. EFUSE_RD_KEY4_DATA2_REG (0x0124)

2
TA
DA
4_
EY
E_K
US
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA2 Represents the second 32 bits of KEY4. (RO)

Register 6.75. EFUSE_RD_KEY4_DATA3_REG (0x0128)

3
TA
DA
4_
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA3 Represents the third 32 bits of KEY4. (RO)

Register 6.76. EFUSE_RD_KEY4_DATA4_REG (0x012C)

4
TA
DA
_
Y4
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA4 Represents the fourth 32 bits of KEY4. (RO)

Espressif Systems 214 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.77. EFUSE_RD_KEY4_DATA5_REG (0x0130)

5
TA
DA
4_
EY
E_K
US
EF
31 0

0x000000 Reset

EFUSE_KEY4_DATA5 Represents the fifth 32 bits of KEY4. (RO)

Register 6.78. EFUSE_RD_KEY4_DATA6_REG (0x0134)

6
TA
DA
4_
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA6 Represents the sixth 32 bits of KEY4. (RO)

Register 6.79. EFUSE_RD_KEY4_DATA7_REG (0x0138)

7
TA
DA
_
Y4
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY4_DATA7 Represents the seventh 32 bits of KEY4. (RO)

Register 6.80. EFUSE_RD_KEY5_DATA0_REG (0x013C)

A0
AT
_D
Y5
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA0 Represents the zeroth 32 bits of KEY5. (RO)

Espressif Systems 215 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.81. EFUSE_RD_KEY5_DATA1_REG (0x0140)

A1
AT
_D
5
EY
_K
E
US
EF
31 0

0x000000 Reset

EFUSE_KEY5_DATA1 Represents the first 32 bits of KEY5. (RO)

Register 6.82. EFUSE_RD_KEY5_DATA2_REG (0x0144)

A2
AT
_D
Y5
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA2 Represents the second 32 bits of KEY5. (RO)

Register 6.83. EFUSE_RD_KEY5_DATA3_REG (0x0148)

A3
AT
_D
Y5
KE
E_
US
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA3 Represents the third 32 bits of KEY5. (RO)

Register 6.84. EFUSE_RD_KEY5_DATA4_REG (0x014C)

4
TA
DA
5_
EY
_K
E
US
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA4 Represents the fourth 32 bits of KEY5. (RO)

Espressif Systems 216 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.85. EFUSE_RD_KEY5_DATA5_REG (0x0150)

A 5
AT
_D
5
EY
_K
SE
U
EF
31 0

0x000000 Reset

EFUSE_KEY5_DATA5 Represents the fifth 32 bits of KEY5. (RO)

Register 6.86. EFUSE_RD_KEY5_DATA6_REG (0x0154)

6
TA
DA
5_
EY
E_K
US
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA6 Represents the sixth 32 bits of KEY5. (RO)

Register 6.87. EFUSE_RD_KEY5_DATA7_REG (0x0158)

A7
AT
_D
5
EY
_K
SE
U
EF

31 0

0x000000 Reset

EFUSE_KEY5_DATA7 Represents the seventh 32 bits of KEY5. (RO)

Register 6.88. EFUSE_RD_SYS_PART2_DATA0_REG (0x015C)

_0
T2
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_0 Represents the 0th 32 bits of the 2nd part of system data. (RO)

Espressif Systems 217 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.89. EFUSE_RD_SYS_PART2_DATA1_REG (0x0160)

_1
2
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_1 Represents the 1st 32 bits of the 2nd part of system data. (RO)

Register 6.90. EFUSE_RD_SYS_PART2_DATA2_REG (0x0164)

_2
2
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_2 Represents the 2nd 32 bits of the 2nd part of system data. (RO)

Register 6.91. EFUSE_RD_SYS_PART2_DATA3_REG (0x0168)

_3
2
RT
PA
_
TA
DA
_
YS
E _S
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_3 Represents the 3rd 32 bits of the 2nd part of system data. (RO)

Espressif Systems 218 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.92. EFUSE_RD_SYS_PART2_DATA4_REG (0x016C)

_4
2
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_4 Represents the 4th 32 bits of the 2nd part of system data. (RO)

Register 6.93. EFUSE_RD_SYS_PART2_DATA5_REG (0x0170)

_5
T2
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_5 Represents the 5th 32 bits of the 2nd part of system data. (RO)

Register 6.94. EFUSE_RD_SYS_PART2_DATA6_REG (0x0174)

_6
T2
AR
_P
TA
DA
S_
SY
E_
US
EF

31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_6 Represents the 6th 32 bits of the 2nd part of system data. (RO)

Espressif Systems 219 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.95. EFUSE_RD_SYS_PART2_DATA7_REG (0x0178)

_7
2
RT
PA
_
TA
DA
_
YS
_S
SE
U
EF
31 0

0x000000 Reset

EFUSE_SYS_DATA_PART2_7 Represents the 7th 32 bits of the 2nd part of system data. (RO)

Espressif Systems 220 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.96. EFUSE_RD_REPEAT_ERR0_REG (0x017C)

R
ER
T_
YP
CR

E_ S_ B_ AD JTA _E RR
EN

R
US DI US LO L_ AD _E
SW ICA JTA _I G_ RR

ER
_U E_ ER H R
L_

EF SE_ IS_ WN RIA LO DIS

AP CH G_ CAC ER

RR
AR ER R E_
_2
0_ _0

1
ED RR_

RR UA

RR

_E
U D DO SE WN I_
NS RR
R

RR

RR
RV _ER

_E AN

EF E_ S_ B_ DO SP

EN
EF E_ _ WN R _E
RR
PI _E
E

EX S_ _E

_E

AG M

US DI US E_ _M
E

O_
G_ PIO

_E
D0

US DI DO ER L
JT D_

T_ R
ED

EF E_ _ I_ AB

I
EF SE_ IS_ RC AD
G

SD
VE

CH G

D_ OA

TA
RV

U D FO LO
ER

RR
US SP W E
PA NL

_J
SE

SE

EF E_ S_T EL_
A
ES

_E
B_ I_

IS
S_ W
RE

RE

A
US SP

_D
_R

DI DO

US DI _S

IS
_

_D
FT
E_ D_
US PT4

T4

T4

EF E_ AG
E_ S_

S
I
SO

RD
RP

RP

)
US VD

US JT
US DI
ed
_R

E_

E_

EF E_

EF E_

E_

EF E_

E_
rv
SE

US

US

US

US

US

US
se
U

(re
EF

EF

EF

EF

EF

EF

EF

EF
31 30 29 28 27 26 25 24 21 20 19 18 16 15 14 13 12 11 10 9 8 7 6 0

0x0 0 0x0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0 0 0 0x0 Reset

EFUSE_RD_DIS_ERR Any bit of this field being 1 represents a programming error of RD_DIS. (RO)

EFUSE_SWAP_UART_SDIO_EN_ERR This bit being 1 represents a programming error of

SWAP_UART_SDIO_EN. (RO)

EFUSE_DIS_ICACHE_ERR This bit being 1 represents a programming error of DIS_ICACHE. (RO)

EFUSE_DIS_USB_JTAG_ERR This bit being 1 represents a programming error of DIS_USB_JTAG.

(RO)

EFUSE_DIS_DOWNLOAD_ICACHE_ERR This bit being 1 represents a programming error of

DIS_DOWNLOAD_ICACHE. (RO)

EFUSE_DIS_USB_SERIAL_JTAG_ERR This bit being 1 represents a programming error of

DIS_USB_DEVICE. (RO)

EFUSE_DIS_FORCE_DOWNLOAD_ERR This bit being 1 represents a programming error of

DIS_FORCE_DOWNLOAD. (RO)

EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR This bit being 1 represents a programming error of

SPI_DOWNLOAD_MSPI_DIS. (RO)

EFUSE_DIS_TWAI_ERR This bit being 1 represents a programming error of DIS_TWAI. (RO)

EFUSE_JTAG_SEL_ENABLE_ERR This bit being 1 represents a programming error of

JTAG_SEL_ENABLE. (RO)

EFUSE_SOFT_DIS_JTAG_ERR Any bit of this field being 1 represents a programming error of

SOFT_DIS_JTAG. (RO)

EFUSE_DIS_PAD_JTAG_ERR This bit being 1 represents a programming error of DIS_PAD_JTAG.

(RO)

EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR This bit being 1 represents a programming error

of DIS_DOWNLOAD_MANUAL_ENCRYPT. (RO)

Continued on the next page...

Espressif Systems 221 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.96. EFUSE_RD_REPEAT_ERR0_REG (0x0080)

Continued from the previous page...

EFUSE_USB_EXCHG_PINS_ERR This bit being 1 represents a programming error of

USB_EXCHG_PINS. (RO)

EFUSE_VDD_SPI_AS_GPIO_ERR This bit being 1 represents a programming error of

VDD_SPI_AS_GPIO. (RO)

EFUSE_RPT4_RESERVED0_ERR_2 Reserved. (RO)

EFUSE_RPT4_RESERVED0_ERR_1 Reserved. (RO)

EFUSE_RPT4_RESERVED0_ERR_0 Reserved. (RO)

Espressif Systems 222 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.97. EFUSE_RD_REPEAT_ERR1_REG (0x0180)

VO 1_ R

R
0_ R
RE KE ER

ER
KE ER
Y_ VO 2_
KE RE KE

R
ER
T_ Y_ VO

0
R_
_
OO KE RE

NT
R

R
RR

RR
ER

_B T_ Y_

_E
_C
_E

_E
RE OO KE
0_

D1
PT
_1

EL
CU _B T_
E_

E
Y
SE

RV
CR
SE RE OO

_S
OS
PO

SE
AY
T_
E_ CU _B
RP

EL

E
OO
UR

US SE RE

_R
PU

_D
P

B
EF SE_ CU

T4
Y_

Y_

I_

DT

RP
SP
KE

KE

U SE

W
E_

E_

EF E_

E_

E_

E_
US

US

US

US

US

US
EF

EF

EF

EF

EF

EF
31 28 27 24 23 22 21 20 18 17 16 15 0

0x0 0x0 0 0 0 0x0 0x0 0x00 Reset

EFUSE_RPT4_RESERVED1_ERR_0 Reserved. (RO)

EFUSE_WDT_DELAY_SEL_ERR Any bit of this field being 1 represents a programming error of

WDT_DELAY_SEL. (RO)

EFUSE_SPI_BOOT_CRYPT_CNT_ERR Any bit of this field being 1 represents a programming error of

SPI_BOOT_CRYPT_CNT. (RO)

EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR This bit being 1 represents a programming error of SE-

CURE_BOOT_KEY_REVOKE0. (RO)

EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR This bit being 1 represents a programming error of SE-

CURE_BOOT_KEY_REVOKE1. (RO)

EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR This bit being 1 represents a programming error of SE-

CURE_BOOT_KEY_REVOKE2. (RO)

EFUSE_KEY_PURPOSE_0_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_0. (RO)

EFUSE_KEY_PURPOSE_1_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_1. (RO)

Espressif Systems 223 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.98. EFUSE_RD_REPEAT_ERR2_REG (0x0184)

R
ER
E_
OK
EV
_R
C_ SER AB ERR IVE
0

_E RR
E EN _ S

_1
R_

_R A_ EN ES

RR
D2 _E

R
R
R

R
ER

RR
US PT4 DP OT_ GR

ER
ER
ER

ER
VE LE
2_

E
R T_ O AG
RR

2_
4_
5_

3_
L_
ED

E_ YP _B T_
_E

E_

E_

E_

E_
VE
RV

US CR RE OO
UW

OS

OS

OS

OS
LE
SE

EF E_ U B

A_

RP

RP

RP

RP
P

_
RE
_T

US SE RE

DP

PU

PU

PU

PU
H

EF E_ CU
T4
AS

Y_

Y_

Y_

Y_
C
RP

KE

KE

KE

KE
US SE

SE
FL
E_

E_

EF E_

E_

E_

E_

E_

E_
US

US

US

US

US

US

US
EF

EF

EF

EF

EF

EF

EF

EF
31 28 27 22 21 20 19 18 17 16 15 12 11 8 7 4 3 0

0x0 0x0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 Reset

EFUSE_KEY_PURPOSE_2_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_2. (RO)

EFUSE_KEY_PURPOSE_3_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_3. (RO)

EFUSE_KEY_PURPOSE_4_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_4. (RO)

EFUSE_KEY_PURPOSE_5_ERR Any bit of this field being 1 represents a programming error of

KEY_PURPOSE_5. (RO)

EFUSE_SEC_DPA_LEVEL_ERR This bit being 1 represents a programming error of SEC_DPA_LEVEL.

(RO)

EFUSE_RPT4_RESERVED2_ERR_1 Reserved. (RO)

EFUSE_CRYPT_DPA_ENABLE_ERR This bit being 1 represents a programming error of

CRYPT_DPA_ENABLE. (RO)

EFUSE_SECURE_BOOT_EN_ERR This bit being 1 represents a programming error of SE-

CURE_BOOT_EN. (RO)

EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR This bit being 1 represents a programming er-

ror of SECURE_BOOT_AGGRESSIVE_REVOKE. (RO)

EFUSE_RPT4_RESERVED2_ERR_0 Reserved. (RO)

EFUSE_FLASH_TPUW_ERR Any bit of this field being 1 represents a programming error of

FLASH_TPUW. (RO)

Espressif Systems 224 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.99. EFUSE_RD_REPEAT_ERR3_REG (0x0188)

R
ER
E_
OD
_M
_5 N RR
AD
DO CT_ R RR OW _E
LO
S_ E ER _E D AD
DI DIR T_ D3 G_ LO

R
ED RR_ R

ER
R

ER

E_ _ IN E TA N
_2
0

ER 3
4
ER 3_E _E
1

E_
US DI PR R _ OW
R_

NT 3_ R_
ON R_

L_
RR

M R
D ME
RR

OD
ER

D R

D_ R
U RP US EC TRO

EF SE_ SB_ ES RIA Y_D

_E

VE _E

E
_E

VE SU
3_

OA T_
J
3

3
N

U U _R SE IT
ER RE

NL O
ED

L
IO

EF SE_ T4 B_ UR

W BO
ES VE
ES D_

_C
RS
RV

V
_R ER

R
_R N
VE
SE

E
US PT4 _SE

EF SE_ IS_ _S
ES

US PT4 ES

RI
E_
RE

U D LE
_R

R _R

_P
R

R E
4_

E_ RC

EF SE_ AB
CU

RT
T4

E_ T4
PT

S
U EN
US FO

RP

US RP

UA
SE
_R

E_

EF SE_

E_

EF E_

E_

EF E_
SE

US

US

US
U

U
EF

EF

EF

EF

EF

EF

EF
31 30 29 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x0 0x00 0 0 0x0 0 0 0x0 0 0 0 0 0 0 Reset

EFUSE_DIS_DOWNLOAD_MODE_ERR This bit being 1 represents a programming error of

DIS_DOWNLOAD_MODE. (RO)

EFUSE_DIS_DIRECT_BOOT_ERR This bit being 1 represents a programming error of

DIS_DIRECT_BOOT. (RO)

EFUSE_USB_PRINT_ERR This bit being 1 represents a programming error of

UART_PRINT_CHANNEL. (RO)

EFUSE_RPT4_RESERVED3_ERR_5 Reserved. (RO)

EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR This bit being 1 represents a program-

ming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. (RO)

EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR This bit being 1 represents a programming error of

ENABLE_SECURITY_DOWNLOAD. (RO)

EFUSE_UART_PRINT_CONTROL_ERR Any bit of this field being 1 represents a programming error of

UART_PRINT_CONTROL. (RO)

EFUSE_RPT4_RESERVED3_ERR_4 Reserved. (RO)

EFUSE_RPT4_RESERVED3_ERR_3 Reserved. (RO)

EFUSE_RPT4_RESERVED3_ERR_2 Reserved. (RO)

EFUSE_RPT4_RESERVED3_ERR_1 Reserved. (RO)

EFUSE_FORCE_SEND_RESUME_ERR This bit being 1 represents a programming error of

FORCE_SEND_RESUME. (RO)

EFUSE_SECURE_VERSION_ERR Any bit of this field being 1 represents a programming error of SE-
CURE_VERSION. (RO)

EFUSE_RPT4_RESERVED3_ERR_0 Reserved. (RO)

Espressif Systems 225 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.100. EFUSE_RD_REPEAT_ERR4_REG (0x0190)

_0

1
R_
RR

ER
_E

4_
4
ED

ED
RV

RV
SE

SE
RE

E
_R
_
T4

T4
RP

RP
E_

E_
US

US
EF

EF
31 24 23 0

0x0 0x0000 Reset

EFUSE_RPT4_RESERVED4_ERR_1 Reserved. (RO)

EFUSE_RPT4_RESERVED4_ERR_0 Reserved. (RO)

Espressif Systems 226 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.101. EFUSE_RD_RS_ERR0_REG (0x01C0)

U M
M
M

_N
NU
NU

RR
AI
R_
R_
UM

M
UM

IL
M

_E
_F
UM

ER
NU

FA
AI
NU

ER

8M

M
_N
_N

_F
_N

1_

1_
R_

_8
A_
R_

IL

L
L

RR

I_
RR
L

TA

RT

RT
IL

RR

AI
AI
I

T
ER

PI
A
ER
FA

P
FA

DA

DA
_E
_F

_F
_E
_F

PA

PA
_E

_S

_S
0_
_

4_

R_

R_
Y0
Y2

Y2
Y3

Y3

S_

S_
Y4

Y1

Y1

AC

AC
EY

US

US
KE

KE

KE

KE

KE

KE

KE

KE

KE

SY

SY

M
K
E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_

E_
US

US

US

US

US

US

US

US

US

US

US

US

US

US

US

US
EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF

EF
31 30 28 27 26 24 23 22 20 19 18 16 15 14 12 11 10 8 7 6 4 3 2 0

0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 0 0x0 Reset

EFUSE_MAC_SPI_8M_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_MAC_SPI_8M_FAIL Represents whether programming MAC_SPI_8M failed.

0: No failure and the data of MAC_SPI_8M is reliable.
1: Programming user data failed and the number of error bytes is over 6.
(RO)

EFUSE_SYS_PART1_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_SYS_PART1_FAIL Represents whether programming system part1 data failed.

0: No failure and the data of system part1 is reliable.
1: Programming user data failed and the number of error bytes is over 6.
(RO)

EFUSE_USR_DATA_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_USR_DATA_FAIL Represents whether programming user data failed.

0: No failure and the user data is reliable.
1: Programming user data failed and the number of error bytes is over 6.
(RO)

EFUSE_KEY0_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY0_FAIL Represents whether programming key0 data failed.

0: No failure and the data of key0 is reliable.
1: Programming key0 failed and the number of error bytes is over 6.
(RO)

EFUSE_KEY1_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY1_FAIL Represents whether programming key1 data failed.

0: No failure and the data of key1 is reliable.
1: Programming key1 failed and the number of error bytes is over 6.
(RO)

EFUSE_KEY2_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY2_FAIL Represents whether programming key2 data failed.

0: No failure and the data of key2 is reliable.
1: Programming key2 failed and the number of error bytes is over 6.
(RO)

Continued on the next page...

Espressif Systems 227 ESP32-C6 TRM (Version 1.0)
Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.101. EFUSE_RD_RS_ERR0_REG (0x01C0)

Continued from the previous page...

EFUSE_KEY3_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY3_FAIL Represents whether programming key3 data failed.

0: No failure and the data of key3 is reliable.
1: Programming key3 failed and the number of error bytes is over 6.
(RO)

EFUSE_KEY4_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY4_FAIL Represents whether programming key4 data failed.

0: No failure and the data of key4 is reliable.
1: Programming key4 failed and the number of error bytes is over 6.
(RO)

Register 6.102. EFUSE_RD_RS_ERR1_REG (0x01C4)

UM
_N
IL

RR

UM
FA

_E

_N
2_

T2

RR
RT

AI
AR

_E
_F
PA

Y5

Y5
_

_
YS

YS

KE

KE
)
ed

_S

_S

E_

E_
rv

SE

SE

US

US
se

U
(re

EF

EF

EF

EF
31 8 7 6 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset

EFUSE_KEY5_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_KEY5_FAIL Represents whether programming key5 data failed.

0: No failure and the data of key5 is reliable.
1: Programming key5 failed and the number of error bytes is over 6.
(RO)

EFUSE_SYS_PART2_ERR_NUM Represents the number of error bytes. (RO)

EFUSE_SYS_PART2_FAIL Represents whether programming system part2 data failed.

0: No failure and the data of system part2 is reliable.
1: Programming user data failed and the number of error bytes is over 6.
(RO)

Espressif Systems 228 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.103. EFUSE_CLK_REG (0x01C8)

D N
_P _O
CE CE
_F _F PU
OR OR
EM LK _
M _C CE
E_ EM OR
N

US M _F
_E

EF SE_ EM
K
CL
)

d)

U M
ed

ve
E_

EF SE_
rv

r
US
se

se

U
(re

(re
EF

EF
31 17 16 15 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset

EFUSE_MEM_FORCE_PD Configures whether or not to force eFuse SRAM into power-saving mode.
1: Force
0: No effect
(R/W)

EFUSE_MEM_CLK_FORCE_ON Configures whether or not to force activate clock signal of eFuse

SRAM.
1: Force activate
0: No effect
(R/W)

EFUSE_MEM_FORCE_PU Configures whether or not to force eFuse SRAM into working mode.
1: Force
0: No effect
(R/W)

EFUSE_CLK_EN Configures whether or not to force enable eFuse register configuration clock sig-
nal.
1: Force
0: The clock is enabled only during the reading and writing of registers
(R/W)

Register 6.104. EFUSE_CONF_REG (0x01CC)

DE
CO
P_
)
ed

_O
rv

E
US
se
(re

EF

31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 Reset

EFUSE_OP_CODE Configures operation command type.

0x5A5A: Pprogramming operation command
0x5AA5: Read operation command
Other values: No effect
(R/W)

Espressif Systems 229 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.105. EFUSE_STATUS_REG (0x01D0)

T
CN
T_
BI
D_
LI
A
_V

E
K0

AT
BL
d)

d)

ST
ve

ve
E_

E_
r

r
US

US
se

se
(re

(re
EF

EF
31 20 19 10 9 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 0x0 Reset

EFUSE_STATE Represents the state of the eFuse state machine. (RO)

EFUSE_BLK0_VALID_BIT_CNT Represents the number of block valid bit. (RO)

Register 6.106. EFUSE_CMD_REG (0x01D4)

D
AD MD
UM

M
_C
RE _C
_N

E_ M
LK

US PG
)
ed

B
E_

EF E_
rv

US

US
se
(re

EF

EF
31 6 5 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 Reset

EFUSE_READ_CMD Configures whether or not to send read command.

1: Send
0: No effect
(R/W/SC)

EFUSE_PGM_CMD Configures whether or not to send programming command.

1: Send
0: No effect
(R/W/SC)

EFUSE_BLK_NUM Represents the serial number of the block to be programmed. Value 0-10 cor-
responds to block number 0-10, respectively. (R/W)

Espressif Systems 230 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.107. EFUSE_INT_RAW_REG (0x01D8)

W
IN AW
RA
E_ T_R
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_READ_DONE_INT_RAW The raw interrupt status of read_done. (R/SS/WTC)

EFUSE_PGM_DONE_INT_RAW The raw interrupt status of pgm_done. (R/SS/WTC)

Register 6.108. EFUSE_INT_ST_REG (0x01DC)

ST
IN T
E_ T_S
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_READ_DONE_INT_ST The masked interrupt status of read_done. (RO)

EFUSE_PGM_DONE_INT_ST The masked interrupt status of pgm_done. (RO)

Register 6.109. EFUSE_INT_ENA_REG (0x01E0)

A
IN NA
EN
E_ T_E
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_READ_DONE_INT_ENA Write 1 to enable read_done interrupt. (R/W)

EFUSE_PGM_DONE_INT_ENA Write 1 to enable pgm_done interrupt. (R/W)

Espressif Systems 231 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.110. EFUSE_INT_CLR_REG (0x01E4)

R
IN LR
CL
E_ T_C
T_
ON IN
_D E_
AD ON
RE _D
E_ M
US PG
)
ed

EF SE_
rv
se

U
(re

EF
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EFUSE_READ_DONE_INT_CLR Write 1 to clear read_done interrupt. (WO)

EFUSE_PGM_DONE_INT_CLR Write 1 to clear pgm_done interrupt. (WO)

Register 6.111. EFUSE_DAC_CONF_REG (0x01E8)

L
SE
D_

IV
PA

_D
_
UM

LK

LK
R

_C

_C
L
_C

C_

AC

AC
DA
OE
)
ed

_D

_D
E_

E_
rv

E
US

US

US

US
se
(re

EF

EF

EF

EF
31 18 17 16 9 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 0 28 Reset

EFUSE_DAC_CLK_DIV Configures the division factor of the rising clock of the programming voltage.
(R/W)

EFUSE_DAC_CLK_PAD_SEL Don’t care. (R/W)

EFUSE_DAC_NUM Configures the rising period of the programming voltage. Measurement unit:
Divided clock frequency by EFUSE_DAC_CLK_DIV. (R/W)

EFUSE_OE_CLR Reduces the power supply of the programming voltage. (R/W)

Espressif Systems 232 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.112. EFUSE_RD_TIM_CONF_REG (0x01EC)

M
NU
T_
NI

_A
I
D_

A
UR

R_
A

D
RE

TH
TR
S
_T
E_

E_

E_
SE
US

US

US
U
EF

EF

EF

EF
31 24 23 16 15 8 7 0

0x12 0x1 0x2 0x1 Reset

EFUSE_THR_A Configures the read hold time. Measurement unit: One cycle of the eFuse core
clock. (R/W)

EFUSE_TRD Configures the read time. Measurement unit: One cycle of the eFuse core clock.
(R/W)

EFUSE_TSUR_A Configures the read setup time. Measurement unit: One cycle of the eFuse core
clock. (R/W)

EFUSE_READ_INIT_NUM Configures the waiting time of reading eFuse memory. Measurement unit:
One cycle of the eFuse core clock. (R/W)

Register 6.113. EFUSE_WR_TIM_CONF1_REG (0x01F0)

M
NU
N_

_A
O
A

R_

UP
P_

PW
TH

TS
E_

E_

E_
US

US

US
EF

EF

EF

31 24 23 8 7 0

0x1 0x3000 0x1 Reset

EFUSE_TSUP_A Configures the programming setup time. Measurement unit: One cycle of the
eFuse core clock.(R/W)

EFUSE_PWR_ON_NUM Configures the power up time for VDDQ. Measurement unit: One cycle of
the eFuse core clock. (R/W)

EFUSE_THP_A Configures the programming hold time. Measurement unit: One cycle of the eFuse
core clock. (R/W)

Espressif Systems 233 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
6 eFuse Controller GoBack

Register 6.114. EFUSE_WR_TIM_CONF2_REG (0x01F4)

UM
_N
O FF
R_
GM

PW
TP
E_

E_
US

US
EF

EF
31 16 15 0

0xc8 0x190 Reset

EFUSE_PWR_OFF_NUM Configures the power outage time for VDDQ. Measurement unit: One cycle
of the eFuse core clock. (R/W)

EFUSE_TPGM Configures the active programming time. Measurement unit: One cycle of the eFuse
core clock. (R/W)

Register 6.115. EFUSE_WR_TIM_CONF0_REG (0x01F8)

I VE
CT
NA

TE
_I
GM

DA
UP
)

)
P
ed

ed

ed
_T

E_
rv

rv

rv
E
US

US
se

se

se
(re

(re

(re
EF

EF

31 21 20 13 12 11 1 0

0 0 0 0 0 0 0 0 0 0 0 0x1 0 0x0 0 Reset

EFUSE_UPDATE Configures whether to update multi-bit register signals.

1: Update
0: No effect
(WT)

EFUSE_TPGM_INACTIVE Configures the inactive programming time. Measurement unit: One cycle
of the eFuse core clock. (R/W)

Register 6.116. EFUSE_DATE_REG (0x01FC)

TE
DA
)
ed

E_
rv

US
se
(re

EF

31 28 27 0

0 0 0 0 0x2206300 Reset

EFUSE_DATE Version control register. (R/W)

Espressif Systems 234 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

7.1 Overview
The ESP32-C6 chip features 31 GPIO pins. Each pin can be used as a general-purpose I/O, or be connected
to an internal peripheral signal. Through GPIO matrix, IO MUX, and low-power (LP) IO MUX, peripheral input
signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these
modules provide highly configurable I/O.

Note:

• The 31 GPIO pins are numbered from GPIO0 ~ GPIO30.

• For chip variants without an in-package flash, GPIO14 is not led out to any chip pins, so GPIO14 is not available
to users.

• For chip variants with an in-package flash, GPIO24 ~ GPIO30 are dedicated to connecting the in-package flash,
not for other uses. GPIO10 ~ GPIO11 are not led out to any chip pins, thus not available to users. The remaining
22 GPIO pins (numbered GPIO0 ~ GPIO9, GPIO12 ~ GPIO23) are configurable by users.

7.2 Features
GPIO matrix has the following features:

• A full-switching matrix between the peripheral input/output signals and the GPIO pins.

• 85 peripheral input signals sourced from the input of any GPIO pins.

• 93 peripheral output signals routed to the output of any GPIO pins.

• Signal synchronization for peripheral inputs based on IO MUX operating clock. For more information
about the operating clock of IO MUX, please refer to Section 8 Reset and Clock.

• GPIO Filter hardware for input signal filtering.

• Glitch Filter hardware for second time filtering on input signal.

• Sigma delta modulated (SDM) output.

• GPIO simple input and output.

IO MUX has the following features:

• Better high-frequency digital performance achieved by some digital signals (SPI, JTAG, UART) bypassing
GPIO matrix. In this case, IO MUX is used to connect these pins directly to peripherals.

• A configuration register IO_MUX_GPIOn_REG provided for each GPIO pin. The pin can be configured to

– perform GPIO function routed by GPIO matrix;

– or perform direct connection bypassing GPIO matrix.

LP IO MUX has the following feature:

• Control of eight LP GPIO pins (GPIO0 ~ GPIO7) that can be used by the peripherals in ULP and LP system.

Espressif Systems 235 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.3 Architectural Overview

Figure 7-1 shows in details how GPIO matrix, IO MUX, and LP IO MUX route signals from pins to peripherals, and
from peripherals to pins.

Figure 7-1. Architecture of IO MUX, LP IO MUX, and GPIO Matrix

1. Only part of peripheral input signals (marked “yes” in column “Direct input through IO MUX” in Table 7-2)
can bypass GPIO matrix. The other input signals can only be routed to peripherals via GPIO matrix.

2. There are only 31 inputs from GPIO SYNC to GPIO matrix, since ESP32-C6 provides 31 GPIO pins in total.
Note:

• For chip variants without an in-package flash, there are 30 inputs from GPIO SYNC to GPIO matrix in
total. GPIO14 is not led out to any chip pins.

• For chip variants with an in-package flash, there are only 22 inputs from GPIO SYNC to GPIO matrix
in total. GPIO10 ∼ GPIO11 are not let out to chip pins, and GPIO24 ∼ GPIO30 are used to connect
the in-package flash.

3. The pins supplied by VDDPST1 or by VDDPST2 are controlled by the signals: IE, OE, WPU, and WPD.

4. Only part of peripheral outputs (marked “yes” in column “Direct output through IO MUX” in Table 7-2) can
be routed to pins bypassing GPIO matrix. The other output signals can only be routed to pins via GPIO
matrix.

5. There are 31 outputs (corresponding to GPIO pin X: 0 ~ 30) from GPIO matrix to IO MUX. Note:

Espressif Systems 236 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

• For chip variants without an in-package flash, there are 30 outputs (corresponding to GPIO X: 0 ~
13, 15 ~ 30) from GPIO matrix to IO MUX in total.

• For chip variants with an in-package flash, there are only 22 outputs (corresponding to GPIO X: 0 ~
9, 12 ~ 23) from GPIO matrix to IO MUX in total.

Figure 7-2 shows the internal structure of a pad, which is an electrical interface between the chip logic and the
GPIO pin. The structure is applicable to all 31 GPIO pins and can be controlled using IE, OE, WPU, and WPD
signals.

Figure 7-2. Internal Structure of a Pad

• IE: input enable

• OE: output enable

• WPU: internal weak pull-up resistor

• WPD: internal weak pull-down resistor

• Bonding pad: a terminal point of the chip logic used to make a physical connection from the chip die to
GPIO pin in the chip package

7.4 Peripheral Input via GPIO Matrix

7.4.1 Overview
To receive a peripheral input signal via GPIO matrix, the matrix is configured to source the peripheral input
signal from one of the 31 GPIOs (0 ~ 30), see Table 7-2. Meanwhile, the register corresponding to the
peripheral signal should be set to receive input signal via GPIO matrix.

As shown in Figure 7-1, when GPIO matrix is used to input a signal from the pin, all external input signals are
sourced from the GPIO pins and then filtered by the GPIO Filter, as shown in Step 2 in Section 7.4.3.

The Glitch Filter hardware can filter eight of the output signals from the GPIO Filter, and the other unselected
signals go directly to the GPIO SYNC hardware, as shown in Step 3 in Section 7.4.3.

Espressif Systems 237 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

All signals filtered by the GPIO Filter hardware or the Glitch Filter hardware are synchronized by the GPIO SYNC
hardware to IO MUX operating clock and then enter the GPIO matrix, see Section 7.4.2. Such signal filtering
and synchronization features apply to all GPIO matrix signals but do not apply when using the IO MUX.

7.4.2 Signal Synchronization GPIO Input Synchronization

GPIO_PINx_SYNC1_BYPASS[0]

GPIO_PINx_SYNC1_BYPASS[1]
GPIO Input
0
GPIO_PINx_SYNC2_BYPASS[0]

0
negative GPIO_PINx_SYNC2_BYPASS[1]
1
sync
0

positive 1 0
sync
negative 1
sync

positive 1
sync
First-level synchronizer
Second-level synchronizer

Figure 7-3. GPIO Input Synchronized on Rising Edge or on Falling Edge of IO MUX Operating Clock

Figure 7-3 shows the functionality of GPIO SYNC. In the figure, negative sync and positive sync mean GPIO
input is synchronized on falling edge and on rising edge of IO MUX operating clock respectively.

The synchronization function is disabled by default by the synchronizer, i.e., GPIO_PINx_SYNC1/2_BYPASS

[1:0] = 0. But when an asynchronous peripheral signal is connected to the pin, the signal should be
synchronized by the two-level synchronizer (i.e., the first-level synchronizer and the second-level
synchronizer as shown in Figure 7-3) to lower the probability of causing metastability. For more information,
see Step 4 in the following section.

7.4.3 Functional Description

To read GPIO pin X1 into peripheral signal Y, follow the steps below:

1. Configure register GPIO_FUNCy_IN_SEL_CFG_REG corresponding to peripheral signal Y in GPIO matrix:

• Set GPIO_SIGy_IN_SEL to enable peripheral signal input via GPIO matrix.

• Set GPIO_FUNCy_IN_SEL to the desired GPIO pin, i.e., X here.

Note that some peripheral signals have no valid GPIO_SIGy_IN_SEL bit, namely, these peripherals can
only receive input signals via GPIO matrix.

2. Optionally enable the GPIO Filter for pin input signals by setting IO_MUX_GPIOx_FILTER_EN. Only the
signals with a valid width of more than two clock cycles can be sampled, see Figure 7-4.

Espressif Systems 238 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Figure 7-4. GPIO Filter Timing of GPIO Input Signals

3. Glitch filter hardware supports eight channels, each of which selects one signal from the 31 (0~30)
output signals from the GPIO Filter hardware and conducts the second-time filtering on the selected
signal. This Glitch Filter hardware can be used to filter slow-speed signals. To enable this feature, follow
the steps below:

• Configure GPIO_EXT_FILTER_CHn_INPUT_IO_NUM to m. n (0 ~ 7) represents the channel number.

m (0 ~ 30) represents the GPIO pin number.

• Configure GPIO_EXT_FILTER_CHn_WINDOW_WIDTH to VALUE1 and

GPIO_EXT_FILTER_CHn_WINDOW_THRES to VALUE2. During VALUE1 + 1 cycles, if there are VALUE2
+ 1 input signals that do not match the current output signal value, the Glitch Filter hardware inverts
the output signal. GPIO_EXT_FILTER_CHn_WINDOW_WIDTH and
GPIO_EXT_FILTER_CHn_WINDOW_THRES can be configured to the same value VALUE3, then only
signals with a width greater than VALUE3 + 1 clock cycles will be sampled.

• Set GPSD_FILTER_CHn_EN to enable channel n.

An example is shown in Figure 7-5, where GPIO_EXT_FILTER_CHx_WINDOW_WIDTH is configured to 3

and GPIO_EXT_FILTER_CHx_WINDOW_THRES to 2. The output signal value (signal_out) keeps as “0” in
the four clock cycles before T1. The input signal value (signal_in) has been “1” for three clock cycles in
the same period, then the output signal is inverted to “1” after T1.

Figure 7-5. Glitch Filter Timing Example

4. Synchronize GPIO input signals. To do so, please set GPIO_PINx_REG corresponding to GPIO pin X as
follows:

• Set GPIO_PINx_SYNC1_BYPASS to enable input signal synchronized on rising edge or on falling

edge in the first-level synchronization, see Figure 7-3.

• Set GPIO_PINx_SYNC2_BYPASS to enable input signal synchronized on rising edge or on falling

edge in the second-level synchronization, see Figure 7-3.

Espressif Systems 239 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

5. Configure IO MUX register to enable pin input. For this end, please set IO_MUX_GPIOx_REG
corresponding to GPIO pin X as follows:

• Set IO_MUX_GPIOx_FUN_IE to enable input2 .

• Set or clear IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD as desired to enable or

disable pull-up and pull-down resistors.

For example, to connect I2S MSCK input signal 3 (I2S_MCLK_in, signal index 12) to GPIO7, please follow the
steps below. Note that GPIO7 is also named as MTDO pin.

1. Set GPIO_SIG12_IN_SEL in register GPIO_FUNC12_IN_SEL_CFG_REG to enable peripheral signal input

via GPIO matrix.

2. Set GPIO_FUNC12_IN_SEL in register GPIO_FUNC12_IN_SEL_CFG_REG to 7, i.e., select GPIO7.

3. Set IO_MUX_GPIO7_FUN_IE in register IO_MUX_GPIO7_REG to enable pin input.

Note:

1. One input pin can be connected to multiple peripheral input signals.

2. The input signal can be inverted by configuring GPIO_FUNCy_IN_INV_SEL.

3. It is possible to have a peripheral read a constantly low or constantly high input value without connecting this
input to a pin. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO number:
• When GPIO_FUNCy_IN_SEL is set to 0x3C, input signal is always 0.
• When GPIO_FUNCy_IN_SEL is set to 0x38, input signal is always 1.

7.4.4 Simple GPIO Input

GPIO matrix can also be used for simple GPIO input. For this case, the input value of one GPIO pin can be read
at any time without routing the GPIO input to any peripherals. GPIO_IN_REG holds the input values of each
GPIO pin.

To implement simple GPIO input, follow the steps below:

• Set IO_MUX_GPIOx_FUN_IE in register IO_MUX_GPIOx_REG, to enable pin input.

• Read the GPIO input from GPIO_IN_REG[x].

7.5 Peripheral Output via GPIO Matrix

7.5.1 Overview
To output a signal from a peripheral via GPIO matrix, the matrix is configured to route peripheral output signals
(only signals with a name assigned in the column “Output signal” in Table 7-2) to one of the 31 GPIOs (0 ~ 30).
Note:

• For chip variants without an in-package flash, output signals can be mapped to 30 GPIO pins, i.e., GPIO0
~ GPIO13, GPIO15 ~ GPIO30.

• For chip variants with an in-package flash, output signals can only be mapped to 22 GPIO pins, i.e.,
GPIO0 ~ GPIO9, GPIO12 ~ GPIO23.

Espressif Systems 240 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

The output signal is routed from the peripheral into GPIO matrix and then into IO MUX. IO MUX must be
configured to set the chosen pin to GPIO function. This enables the GPIO output signal to be connected to
the pin.

Note:
There is a range of peripheral output signals (97 ~ 100 in Table 7-2) which are not connected to any peripheral, but to
the input signals (97 ~ 100) directly.

7.5.2 Functional Description

The 93 output signals (signals with a name assigned in the column “Output signal” in Table 7-2) can be set to
go through GPIO matrix into IO MUX and then to a pin. Figure 7-1 illustrates the configuration.

To output peripheral signal Y to a particular GPIO pin X1 , follow the steps below:

1. Configure registers GPIO_FUNCx_OUT_SEL_CFG_REG and GPIO_ENABLE_REG[x] corresponding to GPIO

pin X in GPIO matrix. Recommended operation: use corresponding W1TS (write 1 to set) and W1TC (write
1 to clear) registers to set or clear GPIO_ENABLE_REG.

• Set the GPIO_FUNCx_OUT_SEL field in register GPIO_FUNCx_OUT_SEL_CFG_REG to the index of

the desired peripheral output signal Y.

• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in register
GPIO_FUNCx_OUT_SEL_CFG_REG and the bit in register GPIO_ENABLE_W1TS_REG, corresponding
to GPIO pin X. To have the output enable signal decided by internal logic (for example, the SPIQ_oe
in column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0” in Table 7-2), clear the
GPIO_FUNCx_OEN_SEL bit instead.

• Set the corresponding bit in register GPIO_ENABLE_W1TC_REG to disable the output from the GPIO
pin.

2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in register GPIO_PINx_REG corresponding
to GPIO pin X.

3. Configure IO MUX register to enable output via GPIO matrix. Set IO_MUX_GPIOx_REG corresponding to
GPIO pin X as follows:

• Set the field IO_MUX_GPIOx_MCU_SEL to desired IO MUX function corresponding to GPIO pin X.
This is Function 1 (GPIO function), numeric value 1, for all pins.

• Set the IO_MUX_GPIOx_FUN_DRV field to the desired value for output strength (0 ~ 3). The higher
the drive strength, the more current can be sourced/sunk from the pin.

– 0: ~5 mA

– 1: ~10 mA

– 2: ~20 mA (default)

– 3: ~40 mA

• If using open drain mode, set/clear the IO_MUX_GPIOx_FUN_WPU and IO_MUX_GPIOx_FUN_WPD

bits to enable/disable the internal pull-up/pull-down resistors.

Espressif Systems 241 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Note:

1. The output signal from a single peripheral can be sent to multiple pins simultaneously.

2. The output signal can be inverted by setting GPIO_FUNCx_OUT_INV_SEL.

7.5.3 Simple GPIO Output

GPIO matrix can also be used for simple GPIO output. For this case, one GPIO pin can be configured to directly
output the desired value, without routing any peripheral output to this pin. This can be done as below:

• Set GPIO matrix GPIO_FUNCn_OUT_SEL with a special peripheral index 128 (0x80);

• Set the corresponding bit in GPIO_OUT_REG register to the desired GPIO output value.

Note:

• GPIO_OUT_REG[0] ~ GPIO_OUT_REG[30] correspond to GPIO0 ~ GPIO30 respectively. GPIO_OUT_REG[31] is

invalid.

• Recommended operation: use GPIO_OUT_W1TS/GPIO_OUT_W1TC to set or clear the register GPIO_OUT_REG.

7.5.4 Sigma Delta Modulated Output (SDM)

7.5.4.1 Functional Description

Four out of the 93 peripheral output signals (index: 83 ~ 86 in Table 7-2 support 1-bit second-order sigma delta
modulation. By default the output is enabled for these four channels. This Sigma Delta modulator can also
output PDM (pulse density modulation) signal with configurable duty cycle. The transfer function is:

H(z) = X(z)z−1 + E(z)(1-z−1 )2

E(z) is quantization error and X(z) is the input.

This modulator supports scaling down of IO MUX operating clock by divider 1 ~ 256:

• Set GPIO_EXT_SD_FUNCTION_CLK_EN to enable the modulator clock.

• Configure GPIO_EXT_SDn_PRESCALE (n = 0 ~ 3 for the four channels).

After scaling, the clock cycle is equal to one pulse output cycle from the modulator.

GPIO_EXT_SDn_IN is a signed number with a range of [-128, 127] and is used to control the duty cycle 1 of
PDM output signal.

• GPIO_EXT_SDn_IN = -128, the duty cycle of the output signal is 0%.

• GPIO_EXT_SDn_IN = 0, the duty cycle of the output signal is near 50%.

• GPIO_EXT_SDn_IN = 127, the duty cycle of the output signal is near 100%.

The formula for calculating PDM signal duty cycle is shown as below:

GP IO_EXT _SDn_IN + 128

Duty_Cycle =
256

Espressif Systems 242 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Note:
For PDM signals, duty cycle refers to the percentage of high level cycles to the whole statistical period (several pulse
cycles, for example, 256 pulse cycles).

7.5.4.2 SDM Configuration

The configuration of SDM is shown below:

• Route one of SDM outputs to a pin via GPIO matrix, see Section 7.5.2.

• Enable the modulator clock by setting GPIO_EXT_SD_FUNCTION_CLK_EN.

• Configure the divider value by setting GPIO_EXT_SDn_PRESCALE.

• Configure the duty cycle of SDM output signal by setting GPIO_EXT_SDn_IN.

7.6 Direct Input and Output via IO MUX

7.6.1 Overview
Some digital signals (SPI and JTAG) can bypass GPIO matrix for better high-frequency digital performance. In
this case, IO MUX is used to connect these pins directly to peripherals.

This option is less flexible than routing signals via GPIO matrix, as the IO MUX register for each GPIO pin can
only select from a limited number of functions, but high-frequency digital performance can be
improved.

7.6.2 Functional Description

Two fields must be configured in order to bypass GPIO matrix for peripheral input signals:

1. IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to the required pin function. For the list of pin
functions, please refer to Section 7.12.

2. Clear GPIO_SIGn_IN_SEL to route the input directly to the peripheral.

To bypass GPIO matrix for peripheral output signals, IO_MUX_GPIOn_MCU_SEL for the GPIO pin must be set to
the required pin function.

Note:
Not all signals can be directly connected to peripheral via IO MUX. Some input/output signals can only be connected
to peripheral via GPIO matrix.

7.7 LP IO MUX for Low Power and Analog Input/Output

7.7.1 Overview
ESP32-C6 provides eight GPIO pins with low power (LP) capabilities and analog functions. These pins can be
controlled by either IO MUX or LP IO MUX.

Espressif Systems 243 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

If controlled by LP IO MUX, these pins will bypass IO MUX and GPIO matrix for the use by ULP and peripherals
in LP system.

When configured as LP GPIOs, the pins can still be controlled by ULP or the peripherals in LP system during
chip Deep-sleep, and wake up the chip from Deep-sleep.

7.7.2 Low Power Capabilities

The pins with LP functions are controlled by LP_AON_GPIO_MUX_SEL[n] (n = GPIO0 ~ GPIO7) bit in register
LP_AON_GPIO_MUX_REG. By default, all bits in these registers are set to 0, routing all input/output signals via
IO MUX.

If LP_AON_GPIO_MUX_SEL[n] is set to 1, then input/output signals are controlled by LP IO MUX. In this mode,
LP_IO_GPIOn_REG is used to control the LP GPIO pins. See 7-4 for the LP functions of each LP GPIO pin. Note
that LP_IO_GPIOn_REG applies the LP GPIO pin numbering, not the GPIO pin numbering.

7.7.3 Analog Functions

When the pin is used for analog purpose, make sure this pin is left floating by configuring LP_IO_GPIOn_REG.
By such way, the external analog signal is directly connected to internal analog signal via GPIO pin. The
configuration is as follows:

• Set LP_AON_GPIO_MUX_SEL[n], to select LP IO MUX to route input and output signals.

• Clear LP_GPIO_GPIOn_FUN_IE, LP_GPIO_GPIOn_FUN_RUE, and LP_GPIO_GPIOn_FUN_RDE, to set the

pin floating.

• Configure LP_GPIO_GPIOn_FUN_SEL to 0, i.e., select Analog Function 0;

• Write 1 to the corresponding bit in LP_GPIO_ENABLE_W1TC, to clear output enable.

See Table 7-5 for analog functions of LP GPIO pins.

7.8 Pin Functions in Light-sleep

Pins may provide different functions when ESP32-C6 is in Light-sleep mode. If IO_MUX_GPIOn_SLP_SEL in
register IO_MUX_GPIOn_REG for a GPIO pin is set to 1, a different set of bits will be used to control the pin
when the chip is in Light-sleep mode.

Table 7-1. Bit Used to Control IO MUX Functions in Light-sleep Mode

Normal Execution Light-sleep Mode

IO MUX Function
OR IO_MUX_GPIOn_SLP_SEL = 0 AND IO_MUX_GPIOn_SLP_SEL = 1
Output Drive Strength IO_MUX_GPIOn_FUN_DRV IO_MUX_GPIOn_MCU_DRV
Pull-up Resistor IO_MUX_GPIOn_FUN_WPU IO_MUX_GPIOn_MCU_WPU
Pull-down Resistor IO_MUX_GPIOn_FUN_WPD IO_MUX_GPIOn_MCU_WPD
Input Enable IO_MUX_GPIOn_FUN_IE IO_MUX_GPIOn_MCU_IE
∗
Output Enable OEN_SEL from GPIO matrix IO_MUX_GPIOn_MCU_OE

Note:
If IO_MUX_GPIOn_SLP_SEL is set to 0, pin functions remain the same in both normal execution and in Light-sleep

Espressif Systems 244 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

mode. Please refer to Section 7.5.2 for how to enable output in normal execution.

7.9 Pin Hold Feature

Each GPIO pin (including the LP pins: GPIO0 ~ GPIO7) has an individual hold function controlled by an LP
register. When the pin is set to hold, the state is latched at that moment and will not change no matter how the
internal signals change or how the IO MUX/GPIO configuration is modified. Users can use the hold function for
the pins to retain the pin state through a core reset triggered by watchdog time-out or Deep-sleep
events.

To use this feature, follow the steps below:

• Digital pins (GPIO8 ~ GPIO30)

The Hold state of each digital pin is controlled by the result of OR operation of the pin’s Hold enable
signal and the global Hold enable signal.

– LP_AON_GPIO_HOLD0_REG[n] (n = 8 ~ 30), controls the Hold signal of each pin of GPIO8 ~

GPIO30.

– PMU_TIE_HIGH_HP_PAD_HOLD_ALL, controls the global Hold signal of all digital pins.

To use this feature, follow the steps below:

– To maintain pin input/output status in Deep-sleep mode, users can set

LP_AON_GPIO_HOLD0_REG[n] (where n = 8 ~ 30 corresponds to GPIO8 ~ GPIO30) to 1 before
powering down. To disable the hold function after the chip is woken up, users can set
LP_AON_GPIO_HOLD0_REG[n] to 0.

– Or users can set PMU_TIE_HIGH_HP_PAD_HOLD_ALL to maintain the input/output status of all

digital pins, and set PMU_TIE_LOW_HP_PAD_HOLD_ALL to disable the hold function of all digital
pins.

• LP pins (GPIO0 ~ GPIO7)

The Hold state of each LP pin is controlled by the result of OR operation of the pin’s Hold enable signal
and the global Hold enable signal.

– LP_AON_GPIO_HOLD0_REG[n] (n = 0 ~ 7), controls the Hold signal of each pin of GPIO0 ~ GPIO7.

– PMU_TIE_HIGH_LP_PAD_HOLD_ALL and PMU_TIE_LOW_LP_PAD_HOLD_ALL, control the global

Hold signal of all LP pins.

To use this feature, follow the steps below:

– Users can set LP_AON_GPIO_HOLD0_REG[n] (where n = 0 ~ 7 corresponds to GPIO0 ~ GPIO7) to 1

to hold the value of GPIOn, or set LP_AON_GPIO_HOLD0_REG[n] to 0 to disable the hold function
of GPIOn.

– Or users can set PMU_TIE_HIGH_LP_PAD_HOLD_ALL to hold the values of all LP pins, and set
PMU_TIE_LOW_LP_PAD_HOLD_ALL to disable the hold function of all LP pins.

7.10 Power Supplies and Management of GPIO Pins

Espressif Systems 245 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.10.1 Power Supplies of GPIO Pins

For more information on the power supply for GPIO pins, please refer to Pin Definition in ESP32-C6 Datasheet.
All the pins can be used to wake up the chip from Light-sleep mode, but only the pins (GPIO0 ~ GPIO7) in
VDDPST1 domain can be used to wake up the chip from Deep-sleep mode.

7.10.2 Power Supply Management

Each ESP32-C6 pin is connected to one of the two different power domains.

• VDDPST1: the input power supply for LP GPIOs

• VDDPST2: the input power supply for digital GPIOs

7.11 Peripheral Signal List

Table 7-2 shows the peripheral input/output signals via GPIO matrix.

Please pay attention to the configuration of the bit GPIO_FUNCn_OEN_SEL:

• GPIO_FUNCn_OEN_SEL = 1: the output enable is controlled by the corresponding bit n of

GPIO_ENABLE_REG:

– GPIO_ENABLE_REG = 0: output is disabled;

– GPIO_ENABLE_REG = 1: output is enabled;

• GPIO_FUNCn_OEN_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the
column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0” of Table 7-2. Note that the signals
such as SPIQ_oe can be 1 (1’d1) or 0 (1’d0), depending on the configuration of corresponding
peripherals. If it’s 1’d1 in column “Output enable signal when GPIO_FUNCn_OEN_SEL = 0”, it indicates
that once GPIO_FUNCn_OEN_SEL is cleared, the output signal is always enabled by default.

Note:
Signals are numbered consecutively, but not all signals are valid.
• Only the signals with a name assigned in the column “Input signal” in Table 7-2 are valid input signals.

• Only the signals with a name assigned in the column “Output signal” in Table 7-2 are valid output signals.

Espressif Systems 246 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
 Espressif Systems

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

Table 7-2. Peripheral Signals via GPIO Matrix

Signal Default Direct Input via Output enable signal when Direct Output
Input Signal Output Signal
No. value IO MUX GPIO_FUNCn_OEN_SEL = 0 via IO MUX
0 ext_adc_start 0 no ledc_ls_sig_out0 1’d1 no
1 - - - ledc_ls_sig_out1 1’d1 no
2 - - - ledc_ls_sig_out2 1’d1 no
3 - - - ledc_ls_sig_out3 1’d1 no
4 - - - ledc_ls_sig_out4 1’d1 no
5 - - - ledc_ls_sig_out5 1’d1 no
6 U0RXD_in 0 yes U0TXD_out 1’d1 yes
7 U0CTS_in 0 no U0RTS_out 1’d1 no
Submit Documentation Feedback

8 U0DSR_in 0 no U0DTR_out 1’d1 no

9 U1RXD_in 1 no U1TXD_out 1’d1 no
10 U1CTS_in 0 no U1RTS_out 1’d1 no
247

11 U1DSR_in 0 no U1DTR_out 1’d1 no

12 I2S_MCLK_in 0 no I2S_MCLK_out 1’d1 no
13 I2SO_BCK_in 0 no I2SO_BCK_out 1’d1 no
14 I2SO_WS_in 0 no I2SO_WS_out 1’d1 no
15 I2SI_SD_in 0 no I2SO_SD_out 1’d1 no
16 I2SI_BCK_in 0 no I2SI_BCK_out 1’d1 no
17 I2SI_WS_in 0 no I2SI_WS_out 1’d1 no
18 - - - I2SO_SD1_out 1’d1 no
ESP32-C6 TRM (Version 1.0)

19 usb_jtag_tdo_bridge 0 no usb_jtag_trst 1’d1 no

20 - - - - - -
21 - - - - - -
22 - - - - - -
23 - - - - - -

GoBack
24 - - - - - -
25 - - - - - -
 Espressif Systems

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Default Direct Input via Output enable signal when Direct Output
Input Signal Output Signal
No. value IO MUX GPIO_FUNCn_OEN_SEL = 0 via IO MUX
26 - - - - - -
27 - - - - - -
28 cpu_gpio_in0 0 no cpu_gpio_out0 cpu_gpio_out_oen0 no
29 cpu_gpio_in1 0 no cpu_gpio_out1 cpu_gpio_out_oen1 no
30 cpu_gpio_in2 0 no cpu_gpio_out2 cpu_gpio_out_oen2 no
31 cpu_gpio_in3 0 no cpu_gpio_out3 cpu_gpio_out_oen3 no
32 cpu_gpio_in4 0 no cpu_gpio_out4 cpu_gpio_out_oen4 no
33 cpu_gpio_in5 0 no cpu_gpio_out5 cpu_gpio_out_oen5 no
34 cpu_gpio_in6 0 no cpu_gpio_out6 cpu_gpio_out_oen6 no
Submit Documentation Feedback

35 cpu_gpio_in7 0 no cpu_gpio_out7 cpu_gpio_out_oen7 no

36 - - - - - -
37 - - - - - -
38 - - - - - -
248

39 - - - - - -
40 - - - - - -
41 - - - - - -
42 - - - - - -
43 - - - - - -
44 - - - - - -
45 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out I2CEXT0_SCL_oe no
46 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out I2CEXT0_SDA_oe no
ESP32-C6 TRM (Version 1.0)

47 parl_rx_data0 0 no parl_tx_data0 1’d1 no

48 parl_rx_data1 0 no parl_tx_data1 1’d1 no
49 parl_rx_data2 0 no parl_tx_data2 1’d1 no
50 parl_rx_data3 0 no parl_tx_data3 1’d1 no
51 parl_rx_data4 0 no parl_tx_data4 1’d1 no

GoBack
52 parl_rx_data5 0 no parl_tx_data5 1’d1 no
53 parl_rx_data6 0 no parl_tx_data6 1’d1 no
 Espressif Systems

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Default Direct Input via Output enable signal when Direct Output
Input Signal Output Signal
No. value IO MUX GPIO_FUNCn_OEN_SEL = 0 via IO MUX
54 parl_rx_data7 0 no parl_tx_data7 1’d1 no
55 parl_rx_data8 0 no parl_tx_data8 1’d1 no
56 parl_rx_data9 0 no parl_tx_data9 1’d1 no
57 parl_rx_data10 0 no parl_tx_data10 1’d1 no
58 parl_rx_data11 0 no parl_tx_data11 1’d1 no
59 parl_rx_data12 0 no parl_tx_data12 1’d1 no
60 parl_rx_data13 0 no parl_tx_data13 1’d1 no
61 parl_rx_data14 0 no parl_tx_data14 1’d1 no
62 parl_rx_data15 0 no parl_tx_data15 1’d1 no
Submit Documentation Feedback

63 FSPICLK_in 0 yes FSPICLK_out_mux FSPICLK_oe yes

64 FSPIQ_in 0 yes FSPIQ_out FSPIQ_oe yes
65 FSPID_in 0 yes FSPID_out FSPID_oe yes
66 FSPIHD_in 0 yes FSPIHD_out FSPIHD_oe yes
249

67 FSPIWP_in 0 yes FSPIWP_out FSPIWP_oe yes

68 FSPICS0_in 0 yes FSPICS0_out FSPICS0_oe yes

69 parl_rx_clk_in 0 no 1’d1 no
sdio_tohost_int_out
70 parl_tx_clk_in 0 no parl_tx_clk_out 1’d1 no
71 rmt_sig_in0 0 no rmt_sig_out0 1’d1 no
72 rmt_sig_in1 0 no rmt_sig_out1 1’d1 no
73 twai0_rx 1 no twai0_tx 1’d1 no
ESP32-C6 TRM (Version 1.0)

74 - - - twai0_bus_off_on 1’d1 no
75 - - - twai0_clkout 1’d1 no
76 - - - twai0_standby 1’d1 no
77 twai1_rx 1 no twai1_tx 1’d1 no
78 - - - twai1_bus_off_on 1’d1 no

GoBack
79 - - - twai1_clkout 1’d1 no
80 - - - twai1_standby 1’d1 no
 Espressif Systems

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Default Direct Input via Output enable signal when Direct Output
Input Signal Output Signal
No. value IO MUX GPIO_FUNCn_OEN_SEL = 0 via IO MUX
81 - - - - - -
82 - - - - - -
83 - - - gpio_sd0_out 1’d1 no
84 - - - gpio_sd1_out 1’d1 no
85 - - - gpio_sd2_out 1’d1 no
86 - - - gpio_sd3_out 1’d1 no
87 pwm0_sync0_in 0 no pwm0_out0a 1’d1 no
88 pwm0_sync1_in 0 no pwm0_out0b 1’d1 no
89 pwm0_sync2_in 0 no pwm0_out1a 1’d1 no
Submit Documentation Feedback

90 pwm0_f0_in 0 no pwm0_out1b 1’d1 no

91 pwm0_f1_in 0 no pwm0_out2a 1’d1 no
92 pwm0_f2_in 0 no pwm0_out2b 1’d1 no
93 pwm0_cap0_in 0 no - - -
250

94 pwm0_cap1_in 0 no - - -
95 pwm0_cap2_in 0 no - - -
96 - - - - - -
97 sig_in_func_97 0 no sig_in_func97 1’d1 no
98 sig_in_func_98 0 no sig_in_func98 1’d1 no
99 sig_in_func_99 0 no sig_in_func99 1’d1 no
100 sig_in_func_100 0 no sig_in_func100 1’d1 no
101 pcnt_sig_ch0_in0 0 no FSPICS1_out FSPICS1_oe yes
ESP32-C6 TRM (Version 1.0)

102 pcnt_sig_ch1_in0 0 no FSPICS2_out FSPICS2_oe yes

103 pcnt_ctrl_ch0_in0 0 no FSPICS3_out FSPICS3_oe yes
104 pcnt_ctrl_ch1_in0 0 no FSPICS4_out FSPICS4_oe yes
105 pcnt_sig_ch0_in1 0 no FSPICS5_out FSPICS5_oe yes
106 pcnt_sig_ch1_in1 0 no - - -

GoBack
107 pcnt_ctrl_ch0_in1 0 no - - -
108 pcnt_ctrl_ch1_in1 0 no - - -
 Espressif Systems

7 IO MUX and GPIO Matrix (GPIO, IO MUX)

Signal Default Direct Input via Output enable signal when Direct Output
Input Signal Output Signal
No. value IO MUX GPIO_FUNCn_OEN_SEL = 0 via IO MUX
109 pcnt_sig_ch0_in2 0 no - - -
110 pcnt_sig_ch1_in2 0 no - - -
111 pcnt_ctrl_ch0_in2 0 no - - -
112 pcnt_ctrl_ch1_in2 0 no - - -
113 pcnt_sig_ch0_in3 0 no - - -
114 pcnt_sig_ch1_in3 0 no SPICLK_out_mux SPICLK_oe yes
115 pcnt_ctrl_ch0_in3 0 no SPICS0_out SPICS0_oe yes
116 pcnt_ctrl_ch1_in3 0 no SPICS1_out SPICS1_oe no
117 - - - - - -
Submit Documentation Feedback

118 - - - - - -
119 - - - - - -
120 - - - - - -
121 SPIQ_in 0 yes SPIQ_out SPIQ_oe yes
251

122 SPID_in 0 yes SPID_out SPID_oe yes

123 SPIHD_in 0 yes SPIHD_out SPIHD_oe yes
124 SPIWP_in 0 yes SPIWP_out SPIWP_oe yes
125 - - - CLK_OUT_out1 1’d1 no
126 - - - CLK_OUT_out2 1’d1 no
127 - - - CLK_OUT_out3 1’d1 no
ESP32-C6 TRM (Version 1.0)

GoBack
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.12 IO MUX Functions List

Table 7-3 shows the IO MUX functions of each GPIO pin.

Table 7-3. IO MUX Functions List

GPIO Pin Name Function 0 Function 1 Function 2 Function 3 DRV Reset Notes
0 XTAL_32K_P GPIO0 GPIO0 — — 2 0 R
1 XTAL_32K_N GPIO1 GPIO1 — — 2 0 R
2 GPIO2 GPIO2 GPIO2 FSPIQ — 2 1 R
3 GPIO3 GPIO3 GPIO3 — — 2 1 R
4 MTMS MTMS GPIO4 FSPIHD — 2 1 R
5 MTDI MTDI GPIO5 FSPIWP — 2 1 R
6 MTCK MTCK GPIO6 FSPICLK — 2 1* R
7 MTDO MTDO GPIO7 FSPID — 2 1 R
8 GPIO8 GPIO8 GPIO8 — — 2 1 —
9 GPIO9 GPIO9 GPIO9 — — 2 3 —
10 GPIO10 GPIO10 GPIO10 — — 2 1 S1
11 GPIO11 GPIO11 GPIO11 — — 2 1 S1
12 GPIO12 GPIO12 GPIO12 — — 3 1 USB
13 GPIO13 GPIO13 GPIO13 — — 3 3 USB
14 GPIO14 GPIO14 GPIO14 — — 2 1 S0
15 GPIO15 GPIO15 GPIO15 — — 2 1 —
16 U0TXD U0TXD GPIO16 FSPICS0 — 2 4 —
17 U0RXD U0RXD GPIO17 FSPICS1 — 2 3 —
18 SDIO_CMD SDIO_CMD GPIO18 FSPICS2 — 2 3 —
19 SDIO_CLK SDIO_CLK GPIO19 FSPICS3 — 2 3 —
20 SDIO_DATA0 SDIO_DATA0 GPIO20 FSPICS4 — 2 3 —
21 SDIO_DATA1 SDIO_DATA1 GPIO21 FSPICS5 — 2 3 —
22 SDIO_DATA2 SDIO_DATA2 GPIO22 — — 2 3 —
23 SDIO_DATA3 SDIO_DATA3 GPIO23 — — 2 3 —
24 SPICS0 SPICS0 GPIO24 — — 2 3 S1, S2
25 SPIQ SPIQ GPIO25 — — 2 3 S1, S2
26 SPIWP SPIWP GPIO26 — — 2 3 S1, S2
27 VDD_SPI GPIO27 GPIO27 — — 2 0 S1, S2
28 SPIHD SPIHD GPIO28 — — 2 3 S1, S2
29 SPICLK SPICLK GPIO29 — — 2 3 S1, S2
30 SPID SPID GPIO30 — — 2 3 S1, S2

Drive Strength

“DRV” column shows the drive strength of each pin after reset:

• 0 - Drive current = ~5 mA

• 1 - Drive current = ~10 mA

• 2 - Drive current = ~20 mA

Espressif Systems 252 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

• 3 - Drive current = ~40 mA

Reset Configurations

“Reset” column shows the default configuration of each pin after reset:

• 0 - IE = 0 (input disabled)

• 1 - IE = 1 (input enabled)

• 2 - IE = 1, WPD = 1 (input enabled, pull-down resistor enabled)

• 3 - IE = 1, WPU = 1 (input enabled, pull-up resistor enabled)

• 4 - OE = 1, WPU = 1 (output enabled, pull-up resistor enabled)

• 1* - If EFUSE_DIS_PAD_JTAG = 1, the pin MTCK is left floating after reset, i.e., IE = 1. If

EFUSE_DIS_PAD_JTAG = 0, the pin MTCK is connected to internal pull-up resistor, i.e., IE = 1, WPU = 1.

Note:

• R - Pins in VDDPST1 domain, and part of them have analog functions, see Table 7-5.

• USB - GPIO12 and GPIO13 are USB pins. The pull-up value of the two pins are controlled by the pins’
pull-up value together with USB pull-up value. If any one of the pull-up value is 1, the pin’s pull-up resistor
will be enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP.

• S0 - For chip variants without an in-package flash, this pin can not be used.

• S1 - For chip variants with an in-package flash, this pin can not be used.

• S2 - For chip variants with an in-package flash, this pin can only be used to connect the in-package
flash, i.e., only Function 0 is available. For chip variants without an in-package flash, this pin can be used
as a normal pin, i.e., all the functions are available.

7.13 LP IO MUX Functions List

Table 7-4 shows the LP GPIO pins and how they correspond to GPIO pins and LP functions.

Table 7-4. LP IO MUX Functions List

LP Functions
LP GPIO No. GPIO No. GPIO Pin
0 1
0 0 XTAL_32K_P LP_GPIO0 lp_uart_dtrn1
1 1 XTAL_32K_N LP_GPIO1 lp_uart_dsrn1
2 2 GPIO2 LP_GPIO2 lp_uart_rtsn1
3 3 GPIO3 LP_GPIO3 lp_uart_ctsn1
4 4 MTMS LP_GPIO4 lp_uart_rxd1
5 5 MTDI LP_GPIO5 lp_uart_txd1
6 6 MTCK LP_GPIO6 lp_i2c_sda2
7 7 MTDO LP_GPIO7 lp_i2c_scl2
1 For the configuration of lp_uart_xx, please refer to Section: LP UART Controller in
Chapter 3 Low-Power CPU.
2 For the configuration of sar_i2c_xx, please refer to Section: LP I2C Controller in
Chapter 3 Low-Power CPU.

Espressif Systems 253 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Table 7-5 shows the LP GPIO pins and how they correspond to GPIO pins and analog functions.

Table 7-5. Analog Functions of IO MUX Pins

LP GPIO GPIO No.1 Pin Name Analog Function 0 Analog Function 1

No.1
0 0 XTAL_32K_P XTAL_32K_P ADC1_CH0
1 1 XTAL_32K_N XTAL_32K_N ADC1_CH1
2 2 GPIO2 - ADC1_CH2
3 3 GPIO3 - ADC1_CH3
4 4 MTMS - ADC1_CH4
5 5 MTDI - ADC1_CH5
6 6 MTCK - ADC1_CH6
- 12 GPIO122 USB_D- -
- 13 GPIO132 USB_D+ -
1 In this table, LP GPIO No. and GPIO No. are used, not the pin No.
2 GPIO12 and GPIO13 are not LP GPIO.

7.14 Event Task Matrix Function

In ESP32-C6 , GPIO supports ETM function, that is, the ETM task of GPIO can be triggered by the ETM event
of any peripheral, or the ETM task of any peripheral can be triggered by the ETM event of GPIO. For more
details about ETM, please refer to Chapter 11 Event Task Matrix (SOC_ETM). Only ETM tasks and ETM events
related to GPIO are introduced here.

The GPIO ETM provides eight task channels x (0 ~ 7). The ETM tasks that each task channel can receive
are:

• GPIO_TASK_CHx_SET: GPIO goes high when triggered;

• GPIO_TASK_CHx_CLEAR: GPIO goes low when triggered;

• GPIO_TASK_CHx_TOGGLE: GPIO toggle level when triggered.

Below is an example to configure task channel x to control GPIOy:

• Configure IO_MUX_GPIOy_MCU_SEL to 1, to select Function 1 listed in Table 7-3;

• Configure GPIO_ENABLE_REG[y] to 1;

• Configure GPIO_EXT_ETM_TASK_GPIOy_SEL to x;

• Set GPSD_ETM_TASK_GPIOy_EN, to enable ETM task channel x to control GPIOy.

Note:

• One task channel can be selected by one or more GPIOs.

• When two or three of the signals GPIO_TASK_CHx_SET, GPIO_TASK_CHx_CLEAR, and GPIO_TASK_CHx_

TOGGLE of the task channel x selected by GPIOy are valid at the same time, then GPIO_TASK_CHx_SET has the
highest priority, GPIO_TASK_CHx_CLEAR takes the second higher priority, and GPIO_TASK_CHx_TOGGLE has the
lowest priority.

• When GPIOy is controlled by ETM task channel, the values of GPIO_OUT_REG, GPIO_FUNCn_OUT_INV_SEL, and

Espressif Systems 254 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

GPIO_FUNCn_OUT_SEL may be modified by the hardware. For such reason, it’s recommended to reconfigure
these registers when the GPIO is free from the control of ETM task channel.

GPIO has eight event channels, and the ETM events that each event channel can generate are:

• GPIO_EVT_CHx_RISE_EDGE: Indicates that the output signal of the corresponding GPIO filter (see Figure
7-1) has a rising edge;

• GPIO_EVT_CHx_FALL_EDGE: Indicates that the output signal of the corresponding GPIO filter (see
Figure 7-1) has a falling edge;

• GPIO_EVT_CHx_ANY_EDGE: Indicates that the output signal of the corresponding GPIO filter (see Figure
7-1) is reversed.

The specific configuration of the event channel is as follows:

• Set GPIO_EXT_ETM_CHx_EVENT_EN to enable event channel x (0 ~ 7).

• Configure GPIO_EXT_ETM_CHx_EVENT_SEL to y (0 ~ 30), i.e., select one from the 31 GPIOs.

Note:
One GPIO can be selected by one or more event channels.

In specific applications, GPIO ETM events can be used to trigger GPIO ETM tasks. For example, event channel
0 selects GPIO0, GPIO1 selects task channel 0, and the GPIO_EVT_CH0_RISE_EDGE event is used to trigger
the GPIO_TASK_CH0_TOGGLE task. When a square wave signal is input to the chip through GPIO0, the chip
outputs a square wave signal with a frequency divided by 2 through GPIO1.

7.15 Register Summary

7.15.1 GPIO Matrix Register Summary
The addresses in this section are relative to GPIO base address provided in Table 5-2 in Chapter 5 System and
Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Note: For chip variants with an in-package flash, 22 GPIO pins are available, i.e., GPIO0 ~ GPIO9 and GPIO12 ~
GPIO23. For this case:

• Configuration Registers: can only be configured for GPIO0 ~ GPIO9 and GPIO12 ~ GPIO23.

• Pin Configuration Registers: only GPIO_PIN0_REG ~ GPIO_PIN9_REG and GPIO_PIN12_REG ~

GPIO_PIN23_REG are available.

• Input Configuration Registers: can only be configured for GPIO0 ~ GPIO9 and GPIO12 ~ GPIO23.

• Output Configuration Registers: only GPIO_FUNC0_OUT_SEL_CFG_REG ~

GPIO_FUNC9_OUT_SEL_CFG_REG and GPIO_PIN12_OUT_SEL_CFG_REG ~
GPIO_PIN23_OUT_SEL_CFG_REG are available.

Name Description Address Access

Configuration Registers

Espressif Systems 255 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Name Description Address Access

GPIO_OUT_REG GPIO output register 0x0004 R/W/SC/WTC
GPIO_OUT_W1TS_REG GPIO output set register 0x0008 WT
GPIO_OUT_W1TC_REG GPIO output clear register 0x000C WT
GPIO_ENABLE_REG GPIO output enable register 0x0020 R/W/WTC
GPIO_ENABLE_W1TS_REG GPIO output enable set register 0x0024 WT
GPIO_ENABLE_W1TC_REG GPIO output enable clear register 0x0028 WT
GPIO_STRAP_REG Strapping pin register 0x0038 RO
GPIO_IN_REG GPIO input register 0x003C RO
Interrupt Status Registers
GPIO_STATUS_REG GPIO interrupt status register 0x0044 R/W/WTC
GPIO_STATUS_W1TS_REG GPIO interrupt status set register 0x0048 WT
GPIO_STATUS_W1TC_REG GPIO interrupt status clear register 0x004C WT
GPIO_PCPU_INT_REG GPIO CPU interrupt status register 0x005C RO
GPIO_STATUS_NEXT_REG GPIO interrupt source register 0x014C RO
Pin Configuration Registers
GPIO_PIN0_REG GPIO0 configuration register 0x0074 R/W
GPIO_PIN1_REG GPIO1 configuration register 0x0078 R/W
GPIO_PIN2_REG GPIO2 configuration register 0x007C R/W
... ... ... ...
GPIO_PIN28_REG GPIO28 configuration register 0x00E4 R/W
GPIO_PIN29_REG GPIO29 configuration register 0x00E8 R/W
GPIO_PIN30_REG GPIO30 configuration register 0x00EC R/W
Input Configuration Registers
GPIO_FUNC0_IN_SEL_CFG_REG Configuration register for input signal 0 0x0154 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Configuration register for input signal 1 0x0158 R/W
GPIO_FUNC2_IN_SEL_CFG_REG Configuration register for input signal 2 0x015C R/W
... ... ... ...
GPIO_FUNC125_IN_SEL_CFG_REG Configuration register for input signal 125 0x0348 R/W
GPIO_FUNC126_IN_SEL_CFG_REG Configuration register for input signal 126 0x034C R/W
GPIO_FUNC127_IN_SEL_CFG_REG Configuration register for input signal 127 0x0350 R/W
Output Configuration Registers
GPIO_FUNC0_OUT_SEL_CFG_REG Configuration register for GPIO0 output 0x0554 varies
GPIO_FUNC1_OUT_SEL_CFG_REG Configuration register for GPIO1 output 0x0558 varies
GPIO_FUNC2_OUT_SEL_CFG_REG Configuration register for GPIO2 output 0x055C varies
... ... ... ...
GPIO_FUNC28_OUT_SEL_CFG_REG Configuration register for GPIO28 output 0x05C4 varies
GPIO_FUNC29_OUT_SEL_CFG_REG Configuration register for GPIO29 output 0x05C8 varies
GPIO_FUNC30_OUT_SEL_CFG_REG Configuration register for GPIO30 output 0x05CC varies
Version Register
GPIO_DATE_REG GPIO version register 0x06FC R/W
Clock Gate Register
GPIO_CLOCK_GATE_REG GPIO clock gate register 0x062C R/W

Espressif Systems 256 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.15.2 IO MUX Register Summary

The addresses in this section are relative to the IO MUX base address provided in Table 5-2 in Chapter 5
System and Memory.

Note: For chip variants with an in-package flash, only 22 GPIO pins are available, i.e., GPIO0 ~ GPIO9 and
GPIO12 ~ GPIO23. For this case, Configuration Registers of IO_MUX_GPIO10_REG ~ IO_MUX_GPIO11_REG and
IO_MUX_GPIO24_REG ~ IO_MUX_GPIO30_REG are not configurable.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

Configuration Registers
IO_MUX_PIN_CTRL_REG Clock output configuration register 0x0000 R/W
IO_MUX_GPIO0_REG IO MUX configuration register for GPIO0 0x0004 R/W
IO_MUX_GPIO1_REG IO MUX configuration register for GPIO1 0x0008 R/W
IO_MUX_GPIO2_REG IO MUX configuration register for GPIO2 0x000C R/W
IO_MUX_GPIO3_REG IO MUX configuration register for GPIO3 0x0010 R/W
IO_MUX_GPIO4_REG IO MUX configuration register for GPIO4 0x0014 R/W
IO_MUX_GPIO5_REG IO MUX configuration register for GPIO5 0x0018 R/W
IO_MUX_GPIO6_REG IO MUX configuration register for GPIO6 0x001C R/W
IO_MUX_GPIO7_REG IO MUX configuration register for GPIO7 0x0020 R/W
IO_MUX_GPIO8_REG IO MUX configuration register for GPIO8 0x0024 R/W
IO_MUX_GPIO9_REG IO MUX configuration register for GPIO9 0x0028 R/W
IO_MUX_GPIO10_REG IO MUX configuration register for GPIO10 0x002C R/W
IO_MUX_GPIO11_REG IO MUX configuration register for GPIO11 0x0030 R/W
IO_MUX_GPIO12_REG IO MUX configuration register for GPIO12 0x0034 R/W
IO_MUX_GPIO13_REG IO MUX configuration register for GPIO13 0x0038 R/W
IO_MUX_GPIO14_REG IO MUX configuration register for GPIO14 0x003C R/W
IO_MUX_GPIO15_REG IO MUX configuration register for GPIO15 0x0040 R/W
IO_MUX_GPIO16_REG IO MUX configuration register for GPIO16 0x0044 R/W
IO_MUX_GPIO17_REG IO MUX configuration register for GPIO17 0x0048 R/W
IO_MUX_GPIO18_REG IO MUX configuration register for GPIO18 0x004C R/W
IO_MUX_GPIO19_REG IO MUX configuration register for GPIO19 0x0050 R/W
IO_MUX_GPIO20_REG IO MUX configuration register for GPIO20 0x0054 R/W
IO_MUX_GPIO21_REG IO MUX configuration register for GPIO21 0x0058 R/W
IO_MUX_GPIO22_REG IO MUX configuration register for GPIO22 0x005C R/W
IO_MUX_GPIO23_REG IO MUX configuration register for GPIO23 0x0060 R/W
IO_MUX_GPIO24_REG IO MUX configuration register for GPIO24 0x0064 R/W
IO_MUX_GPIO25_REG IO MUX configuration register for GPIO25 0x0068 R/W
IO_MUX_GPIO26_REG IO MUX configuration register for GPIO26 0x006C R/W
IO_MUX_GPIO27_REG IO MUX configuration register for GPIO27 0x0070 R/W
IO_MUX_GPIO28_REG IO MUX configuration register for GPIO28 0x0074 R/W
IO_MUX_GPIO29_REG IO MUX configuration register for GPIO29 0x0078 R/W
IO_MUX_GPIO30_REG IO MUX configuration register for GPIO30 0x007C R/W
Version Register
IO_MUX_DATE_REG Version control register 0x00FC R/W

Espressif Systems 257 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.15.3 GPIO_EXT Register Summary

GPIO_EXT registers consist of SDM registers, Glitch Filter registers, and ETM registers.

The addresses in this section are relative to (GPIO base address + 0x0F00). GPIO base address is provided in
Table 5-2 in Chapter 5 System and Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

SDM Configure Registers
GPIO_EXT_SIGMADELTA0_REG Duty cycle configuration register for SDM 0x0000 R/W
channel 0
GPIO_EXT_SIGMADELTA1_REG Duty cycle configuration register for SDM 0x0004 R/W
channel 1
GPIO_EXT_SIGMADELTA2_REG Duty cycle configuration register for SDM 0x0008 R/W
channel 2
GPIO_EXT_SIGMADELTA3_REG Duty cycle configuration register for SDM 0x000C R/W
channel 3
GPIO_EXT_SIGMADELTA_MISC_REG MISC register 0x0024 R/W
Glitch Filter Configuration Registers
GPIO_EXT_GLITCH_FILTER_CH0_REG Glitch Filter configuration register for channel 0x0030 R/W
0
GPIO_EXT_GLITCH_FILTER_CH1_REG Glitch Filter configuration register for channel 0x0034 R/W
1
GPIO_EXT_GLITCH_FILTER_CH2_REG Glitch Filter configuration register for channel 0x0038 R/W
2
GPIO_EXT_GLITCH_FILTER_CH3_REG Glitch Filter configuration register for channel 0x003C R/W
3
GPIO_EXT_GLITCH_FILTER_CH4_REG Glitch Filter configuration register for channel 0x0040 R/W
4
GPIO_EXT_GLITCH_FILTER_CH5_REG Glitch Filter configuration register for channel 0x0044 R/W
5
GPIO_EXT_GLITCH_FILTER_CH6_REG Glitch Filter configuration register for channel 0x0048 R/W
6
GPIO_EXT_GLITCH_FILTER_CH7_REG Glitch Filter configuration register for channel 0x004C R/W
7
ETM Configuration Registers
GPIO_EXT_ETM_EVENT_CH0_CFG_REG ETM configuration register for channel 0 0x0060 R/W
GPIO_EXT_ETM_EVENT_CH1_CFG_REG ETM configuration register for channel 1 0x0064 R/W
GPIO_EXT_ETM_EVENT_CH2_CFG_REG ETM configuration register for channel 2 0x0068 R/W
GPIO_EXT_ETM_EVENT_CH3_CFG_REG ETM configuration register for channel 3 0x006C R/W
GPIO_EXT_ETM_EVENT_CH4_CFG_REG ETM configuration register for channel 4 0x0070 R/W
GPIO_EXT_ETM_EVENT_CH5_CFG_REG ETM configuration register for channel 5 0x0074 R/W
GPIO_EXT_ETM_EVENT_CH6_CFG_REG ETM configuration register for channel 6 0x0078 R/W
GPIO_EXT_ETM_EVENT_CH7_CFG_REG ETM configuration register for channel 7 0x007C R/W
GPIO_EXT_ETM_TASK_P0_CFG_REG GPIO selection register 0 for ETM 0x00A0 R/W

Espressif Systems 258 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Name Description Address Access

GPIO_EXT_ETM_TASK_P1_CFG_REG GPIO selection register 1 for ETM 0x00A4 R/W
GPIO_EXT_ETM_TASK_P2_CFG_REG GPIO selection register 2 for ETM 0x00A8 R/W
GPIO_EXT_ETM_TASK_P3_CFG_REG GPIO selection register 3 for ETM 0x00AC R/W
GPIO_EXT_ETM_TASK_P4_CFG_REG GPIO selection register 4 for ETM 0x00B0 R/W
GPIO_EXT_ETM_TASK_P5_CFG_REG GPIO selection register 5 for ETM 0x00B4 R/W
GPIO_EXT_ETM_TASK_P6_CFG_REG GPIO selection register 6 for ETM 0x00B8 R/W
GPIO_EXT_ETM_TASK_P7_CFG_REG GPIO selection register 7 for ETM 0x00BC R/W
Version Register
GPIO_EXT_VERSION_REG Version control register 0x00FC R/W

7.15.4 LP IO MUX Register Summary

The addresses in this section are relative to LP_IO base address provided in Table 5-2 in Chapter 5 System and
Memory.

The abbreviations given in Column Access are explained in Section Access Types for Registers.

Name Description Address Access

GPIO Configuration/Data Registers
LP_IO_OUT_REG LP GPIO output register 0x0000 R/W
LP_IO_OUT_W1TS_REG LP GPIO output set register 0x0004 WT
LP_IO_OUT_W1TC_REG LP GPIO output clear register 0x0008 WT
LP_IO_ENABLE_REG LP GPIO output enable register 0x000C R/W
LP_IO_ENABLE_W1TS_REG LP GPIO output enable set register 0x0010 WT
LP_IO_ENABLE_W1TC_REG LP GPIO output enable clear register 0x0014 WT
LP_IO_STATUS_REG LP GPIO interrupt status register 0x0018 R/W
LP_IO_STATUS_W1TS_REG LP GPIO interrupt status set register 0x001C WT
LP_IO_STATUS_W1TC_REG LP GPIO interrupt status clear register 0x0020 WT
LP_IO_IN_REG LP GPIO input register 0x0024 RO
LP_IO_PIN0_REG LP GPIO0 configuration register 0x0028 R/W
LP_IO_PIN1_REG LP GPIO1 configuration register 0x002C R/W
LP_IO_PIN2_REG LP GPIO2 configuration register 0x0030 R/W
LP_IO_PIN3_REG LP GPIO3 configuration register 0x0034 R/W
LP_IO_PIN4_REG LP GPIO4 configuration register 0x0038 R/W
LP_IO_PIN5_REG LP GPIO5 configuration register 0x003C R/W
LP_IO_PIN6_REG LP GPIO6 configuration register 0x0040 R/W
LP_IO_PIN7_REG LP GPIO7 configuration register 0x0044 R/W
GPIO LP Function Configuration Registers
LP_IO_GPIO0_REG LP IO MUX configuration register for GPIO0 0x0048 R/W
LP_IO_GPIO1_REG LP IO MUX configuration register for GPIO1 0x004C R/W
LP_IO_GPIO2_REG LP IO MUX configuration register for GPIO2 0x0050 R/W
LP_IO_GPIO3_REG LP IO MUX configuration register for GPIO3 0x0054 R/W
LP_IO_GPIO4_REG LP IO MUX configuration register for GPIO4 0x0058 R/W
LP_IO_GPIO5_REG LP IO MUX configuration register for GPIO5 0x005C R/W
LP_IO_GPIO6_REG LP IO MUX configuration register for GPIO6 0x0060 R/W

Espressif Systems 259 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Name Description Address Access

LP_IO_GPIO7_REG LP IO MUX configuration register for GPIO7 0x0064 R/W
LP_IO_STATUS_INT_REG LP GPIO interrupt source register 0x0068 RO
Version Register
LP_IO_DATE_REG Version control regiter 0x03FC R/W

7.16 Registers
7.16.1 GPIO Matrix Registers
The addresses in this section are relative to GPIO base address provided in Table 5-2 in Chapter 5 System and
Memory.

Register 7.1. GPIO_OUT_REG (0x0004)

G
RI
_O
TA
DA
UT_
_O
IO
GP

31 0

0x000000 Reset

GPIO_OUT_DATA_ORIG Configures the output value of GPIO0 ~ 30 output in simple GPIO output
mode.
0: Low level
1: High level
The value of bit0 ~ bit30 correspond to the output value of GPIO0 ~ GPIO30 respectively. Bit31
is invalid.
(R/W/SC/WTC)

Register 7.2. GPIO_OUT_W1TS_REG (0x0008)

S
1T
W
UT_
_O
IO
GP

31 0

0x000000 Reset

GPIO_OUT_W1TS Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
GPIO30.
0: Not set
1: The corresponding bit in GPIO_OUT_REG will be set to 1
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid. Recommended operation:
use this register to set GPIO_OUT_REG.
(WT)

Espressif Systems 260 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.3. GPIO_OUT_W1TC_REG (0x000C)

C
1T
_W
UT
_O
IO
GP
31 0

0x000000 Reset

GPIO_OUT_W1TC Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0
~ GPIO30 output.
0: Not clear
1: The corresponding bit in GPIO_OUT_REG will be cleared.
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid. Recommended operation:
use this register to clear GPIO_OUT_REG.
(WT)

Register 7.4. GPIO_ENABLE_REG (0x0020)

DA
TA
E_
BL
NA
_E
IO
GP

31 0

0x000000 Reset

GPIO_ENABLE_DATA Configures whether or not to enable the output of GPIO0 ~ GPIO30.

0: Not enable
1: Enable
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid.
(R/W/WTC)

Espressif Systems 261 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.5. GPIO_ENABLE_W1TS_REG (0x0024)

S
1T
_W
LE
B
NA
_E
IO
GP
31 0

0x000000 Reset

GPIO_ENABLE_W1TS Configures whether or not to set the output enable register

GPIO_ENABLE_REG of GPIO0 ~ GPIO30.
0: Not set
1: The corresponding bit in GPIO_ENABLE_REG will be set to 1
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid. Recommended operation:
use this register to set GPIO_ENABLE_REG.
(WT)

Register 7.6. GPIO_ENABLE_W1TC_REG (0x0028)

C
1T
E_W
BL
A
EN
O_
I
GP

31 0

0x000000 Reset

GPIO_ENABLE_W1TC Configures whether or not to clear the output enable register

GPIO_ENABLE_REG of GPIO0 ~ GPIO30.
0: Not clear
1: The corresponding bit in GPIO_ENABLE_REG will be cleared
Bit0 ~ bit30 are corresponding to GPIO0 ~ 30. Bit31 is invalid. Recommended operation: use
this register to clear GPIO_ENABLE_REG.
(WT)

Espressif Systems 262 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.7. GPIO_STRAP_REG (0x0038)

NG
PI
AP
)

TR
ed

_S
rv
se

IO
(re

GP
31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 Reset

GPIO_STRAPPING Represents the values of GPIO strapping pins.

• bit0 ~ bit1: invalid

• bit2: GPIO8

• bit3: GPIO9

• bit4: GPIO15

• bit5: MTMS

• bit6: MTDI

• bit7 ~ bit15: invalid

(RO)

Register 7.8. GPIO_IN_REG (0x003C)

T
EX
_N
TA
DA
I N_
I O_
GP

31 0

0x000000 Reset

GPIO_IN_DATA_NEXT Represents the input value of GPIO0 ~ GPIO30. Each bit represents a pin
input value:
0: Low level
1: High level
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid.
(RO)

Espressif Systems 263 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.9. GPIO_STATUS_REG (0x0044)

PT
RU
ER
NT
I
S_
TU
TA
_S
IO
GP
31 0

0x000000 Reset

GPIO_STATUS_INTERRUPT The interrupt status of GPIO0 ~ GPIO30, can be configured by the soft-
ware.

• Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid.

• Each bit represents the status of its corresponding GPIO:

– 0: Represents the GPIO does not generate the interrupt configured by

GPIO_PINn_INT_TYPE, or this bit is configured to 0 by the software.

– 1: Represents the GPIO generates the interrupt configured by GPIO_PINn_INT_TYPE,

or this bit is configured to 1 by the software.

(R/W/WTC)

Register 7.10. GPIO_STATUS_W1TS_REG (0x0048)

S
1T
W
S_
TU
TA
_S
IO
GP

31 0

0x000000 Reset

GPIO_STATUS_W1TS Configures whether or not to set the interrupt status register

GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO30.

• Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid.

• If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will
be set to 1.

• Recommended operation: use this register to set GPIO_STATUS_INTERRUPT.

(WT)

Espressif Systems 264 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.11. GPIO_STATUS_W1TC_REG (0x004C)

C
1T
W
S_
TU
TA
_S
IO
GP
31 0

0x000000 Reset

GPIO_STATUS_W1TC Configures whether or not to clear the interrupt status register

GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO30.

• Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid.

• If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will
be cleared.

• Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT.

(WT)

Register 7.12. GPIO_PCPU_INT_REG (0x005C)

NT
I
U_
CP
RO
_P
IO
GP

31 0

0x000000 Reset

GPIO_PROCPU_INT Represents the CPU interrupt status of GPIO0 ~ GPIO30. Each bit represents:
0: Represents CPU interrupt is not enabled, or the GPIO does not generate the interrupt config-
ured by GPIO_PINn_INT_TYPE.
1: Represents the GPIO generates an interrupt configured by GPIO_PINn_INT_TYPE after the CPU
interrupt is enabled.
Bit0 ~ bit30 are corresponding to GPIO0 ~ GPIO30. Bit31 is invalid. This interrupt status
is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of
GPIO_PINn_REG).
(RO)

Espressif Systems 265 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.13. GPIO_PINn_REG (n: 0-30) (0x0074+4*n)

LE

SS
S
AB

_D AS

PA
NC ER
EN

YP

BY
SY RIV
P_

PE

IO n_P 1_B
A

2_
EN

EU

TY

NC
T_

T_
AK

AD
_P SY
IN

IN
W
n_

n_

n_

n_
GP INn
d)

GP ed)

)
ed
IN

IN

IN

IN
ve

I
P

_P

_P

_P

_P
rv

rv
O_
r
se

se

se
IO

IO

IO

IO
I
(re

(re

(re
GP

GP

GP

GP
31 18 17 13 12 11 10 9 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0 0x0 0 0 0x0 0 0x0 Reset

GPIO_PINn_SYNC2_BYPASS Configures whether or not to synchronize GPIO input data on either

edge of IO MUX operating clock for the second-level synchronization.
0: Not synchronize
1: Synchronize on falling edge
2: Synchronize on rising edge
3: Synchronize on rising edge
(R/W)

GPIO_PINn_PAD_DRIVER Configures to select pin drive mode.

0: Normal output
1: Open drain output
(R/W)

GPIO_PINn_SYNC1_BYPASS Configures whether or not to synchronize GPIO input data on either

edge of IO MUX operating clock for the first-level synchronization.
0: Not synchronize
1: Synchronize on falling edge
2: Synchronize on rising edge
3: Synchronize on rising edge
(R/W)

GPIO_PINn_INT_TYPE Configures GPIO interrupt type.

0: GPIO interrupt disabled
1: Rising edge trigger
2: Falling edge trigger
3: Any edge trigger
4: Low level trigger
5: High level trigger
(R/W)

GPIO_PINn_WAKEUP_ENABLE Configures whether or not to enable GPIO wake-up function.

0: Disable
1: Enable
This function only wakes up the CPU from Light-sleep.
(R/W)

Continued on the next page...

Espressif Systems 266 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.13. GPIO_PINn_REG (n: 0-30) (0x0074+4*n)

Continued from the previous page...

GPIO_PINn_INT_ENA Configures whether or not to enable CPU interrupt or CPU non-maskable in-
terrupt.

• bit13: Configures whether or not to enable CPU interrupt:

0: Disable
1: Enable

• bit14: Configures CPU non-maskable interrupt:

0: Disable
1: Enable

• bit15 ~ bit17: invalid

(R/W)

Register 7.14. GPIO_STATUS_NEXT_REG (0x014C)

T
EX
_N
PT
RU
ER
NT
_I
US
AT
ST
O_
I
GP

31 0

0x000000 Reset

GPIO_STATUS_INTERRUPT_NEXT Represents the interrupt source signal of GPIO0 ~ GPIO30.

Bit0 ~ bit30 are corresponding to GPIO0 ~ 30. Bit31 is invalid. Each bit represents:
0: The GPIO does not generate the interrupt configured by GPIO_PINn_INT_TYPE.
1: The GPIO generates an interrupt configured by GPIO_PINn_INT_TYPE.
The interrupt could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and
any edge interrupt.
(RO)

Espressif Systems 267 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.15. GPIO_FUNCn_IN_SEL_CFG_REG (n: 0-127) (0x0154+4*n)

L
SE
V_

L
SE
IN
_I L
Cn SE
N_

N_
UN IN_

_I
Cn
_F _
IO IGn
)

UN
ed

GP _S

_F
rv
se

IO

IO
(re

GP

GP
31 8 7 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

GPIO_FUNCn_IN_SEL Configures to select a pin from the 31 GPIO pins to connect the input signal
n.
0: Select GPIO0
1: Select GPIO1
......
29: Select GPIO29
30: Select GPIO30
Or
0x38: A constantly high input
0x3C: A constantly low input
(R/W)

GPIO_FUNCn_IN_INV_SEL Configures whether or not to invert the input value.

0: Not invert
1: Invert
(R/W)

GPIO_SIGn_IN_SEL Configures whether or not to route signals via GPIO matrix.

0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in IO MUX.
1: Route signals via GPIO matrix.
(R/W)

Espressif Systems 268 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.16. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-30) (0x0554+4*n)

UT EL EL

EL
_O _S _S

_S

EL
C0 OEN INV

NV

_S
_I
UN 0_ _

UT
_F C EN
IO UN _O

_O
GP _F C0

C0
d)

IO U N

UN
ve

GP _F

_F
r
se

IO

IO
(re

GP

GP
31 11 10 9 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 Reset

GPIO_FUNCn_OUT_SEL Configures to select a signal Y (0 <= Y < 128) from 128 peripheral signals to
be output from GPIOn.
0: Select signal 0
1: Select signal 1
......
126: Select signal 126
127: Select signal 127
Or
128: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and output
enable.

For the detailed signal list, see Table 7-2.

(R/W/SC)

GPIO_FUNCn_OUT_INV_SEL Configures whether or not to invert the output value.

0: Not invert
1: Invert
(R/W/SC)

GPIO_FUNCn_OEN_SEL Configures to select the source of output enable signal.

0: Use output enable signal from peripheral.
1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG.
(R/W)

GPIO_FUNCn_OEN_INV_SEL Configures whether or not to invert the output enable signal.

0: Not invert
1: Invert
(R/W)

Espressif Systems 269 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.17. GPIO_CLOCK_GATE_REG (0x062C)

EN
K_
d)

L
ve

_C
r
se

IO
(re

GP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

GPIO_CLK_EN Configures whether or not to enable clock gate.

0: Not enable
1: Enable, the clock is free running.
(R/W)

Register 7.18. GPIO_DATE_REG (0x06FC)

E
)

AT
ed

_D
rv
se

IO
(re

GP

31 28 27 0

0 0 0 0 0x1907040 Reset

GPIO_DATE Version control register.

(R/W)

7.16.2 IO MUX Registers

The addresses in this section are relative to the IO MUX base address provided in Table 5-2 in Chapter 5
System and Memory.

Register 7.19. IO_MUX_PIN_CTRL_REG (0x0000)

T2
T3

T1
U

OU

U
_O

_O
K_
LK

LK
L
_C

_C

_C
)
ed

UX

UX

UX
rv
se

_M

_M

_M
(re

IO

IO

IO

31 15 14 10 9 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7 0xf 0xf Reset

IO_MUX_CLK_OUTx (x: 1 - 3) Configures the output clock for I2S.

0x0: Select CLK_OUT_outx for I2S output clock.
CLK_OUT_outx can be found in Table 7-2.
(R/W)

Espressif Systems 270 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.20. IO_MUX_GPIOn_REG (n: 0-30) (0x0004+4*n)

_G On CU PU

_M _S D
V
_ U
D
EL

V
_E

On LP P
DR

E
UN P
_M WP

CU EL
DR

IO UX PI _M _IE
UX GPI _M U_W
PI _S _W

_O
_S

PI _F _IE
IO X_G _F _W
ER

_M _ On U_
N_
U

U
_G On UN
On UN
LT

_M _ On C
_M _ On C
FU
M

IO UX PI _M
FI

UX GPI _F
n_

n_
On

_M _ On

IO UX On
IO

O
PI

IO UX PI

PI

IO UX PI
P

_M GP
_G

_G

G
G
G
)
ed

_M _

_M _
UX

UX

UX

IO UX
rv

U
se

_M

_M

_M

_M

_M
(re

IO

IO

IO

IO

IO
31 16 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 1 1 0 0 0 0 0 0 0 0 Reset

IO_MUX_GPIOn_MCU_OE Configures whether or not to enable the output of GPIOn in sleep mode.
0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_SLP_SEL Configures whether or not to enter sleep mode for GPIOn.

0: Not enter
1: Enter
(R/W)

IO_MUX_GPIOn_MCU_WPD Configure whether or not to enable pull-down resistor of GPIOn in sleep

mode.
0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_MCU_WPU Configures whether or not to enable pull-up resistor of GPIOn during

sleep mode.
0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_MCU_IE Configures whether or not to enable the input of GPIOn during sleep
mode.
0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_MCU_DRV Configures the drive strength of GPIOn during sleep mode.

0: ~5 mA
1: ~10 mA
2: ~20 mA
3: ~40 mA
(R/W)

IO_MUX_GPIOn_FUN_WPD Configures whether or not to enable pull-down resistor of GPIOn.

0: Disable
1: Enable
(R/W)

Continued on the next page...

Espressif Systems 271 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.20. IO_MUX_GPIOn_REG (n: 0-30) (0x0004+4*n)

Continued from the previous page...

IO_MUX_GPIOn_FUN_WPU Configures whether or not enable pull-up resistor of GPIOn.

0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_FUN_IE Configures whether or not to enable input of GPIOn.

0: Disable
1: Enable
(R/W)

IO_MUX_GPIOn_FUN_DRV Configures the drive strength of GPIOn.

0: ~5 mA
1: ~10 mA
2: ~20 mA
3: ~40 mA
(R/W)

IO_MUX_GPIOn_MCU_SEL Configures to select IO MUX function for this signal.

0: Select Function 0
1: Select Function 1
......
(R/W)

IO_MUX_GPIOn_FILTER_EN Configures whether or not to enable filter for pin input signals.
0: Disable
1: Enable
(R/W)

Register 7.21. IO_MUX_DATE_REG (0x00FC)

EG
_R
TE
DA
)
ed

_
UX
rv
se

_M
(re

IO

31 28 27 0

0 0 0 0 0x2006050 Reset

IO_MUX_DATE_REG Version control register.

(R/W)

Espressif Systems 272 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

7.16.3 GPIO_EXT Registers

The addresses in this section are relative to (GPIO base address + 0x0F00). GPIO base address is provided in
Table 5-2 in Chapter 5 System and Memory.

Register 7.22. GPIO_EXT_SIGMADELTAn_REG (n: 0-3) (0x0000+0x4*n)

E
AL
SC
RE

N
_P

I
n_
Dn

SD
_S

T_
d)

XT

X
ve

_E

_E
r
se

IO

IO
(re

GP

GP
31 16 15 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xff 0x0 Reset

GPIO_EXT_SDn_IN (n: 0 - 3) Configures the duty cycle of sigma delta modulation output.
(R/W)

GPIO_EXT_SDn_PRESCALE (n: 0 - 3) Configures the divider value to divide IO MUX operating

clock.
(R/W)

Register 7.23. GPIO_EXT_SIGMADELTA_MISC_REG (0x0024)

EN
_
LK
_C
ON
I
CT
F UN
D_
_S
IO d )

)
XT

ed
GP rve
_E

rv
se

se
(re

(re

31 30 29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

GPIO_EXT_SD_FUNCTION_CLK_EN Configures whether or not to enable the clock for sigma delta
modulation.
0: Not enable
1: Enable
(R/W)

Espressif Systems 273 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.24. GPIO_EXT_GLITCH_FILTER_CHn_REG (n: 0-7) (0x0030+0x4*n)

S
TH

M
RE

NU
ID

H
_W

_T

O_
W

_I
DO

DO

UT
IN

IN

N
IN
_W

_W

_E
n_
Hn

Hn

n
CH

CH
_C

_C

R_

R_
ER

ER

E
ILT

ILT

LT

LT
FI

FI
_F

_F

T_

T_
)

XT

XT
ed

X
E

_E

_E

_E
rv

O_
se

IO

IO

IO
I
(re

GP

GP

GP

GP
31 19 18 13 12 7 6 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0 Reset

GPIO_EXT_FILTER_CHn_EN Configures whether or not to enable channel n of Glitch Filter.

0: Not enable
1: Enable
(R/W)

GPIO_EXT_FILTER_CHn_INPUT_IO_NUM Configures to select the input GPIO for Glitch Filter.

0: Select GPIO0
1: Select GPIO1
......
29: Select GPIO29
30: Select GPIO30
(R/W)

GPIO_EXT_FILTER_CHn_WINDOW_THRES Configures the window threshold for Glitch Filter. The

window threshold should be less than or equal to GPIO_EXT_FILTER_CHn_WINDOW_WIDTH.
Measurement unit: IO MUX operating clock cycle
(R/W)

GPIO_EXT_FILTER_CHn_WINDOW_WIDTH Configures the window width for Glitch Filter. The effec-
tive value of window width is 0 ~ 62. 63 is a reserved value and cannot be used.
Measurement unit: IO MUX operating clock cycle
(R/W)

Espressif Systems 274 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.25. GPIO_EXT_ETM_EVENT_CHn_CFG_REG (n: 0-7) (0x0060+0x4*n)

L
N

E
_S
_E
NT

NT
VE

VE
E

_E
n_

Hn
CH

_C
ed M_

M
ET

T
_E
(re XT_
)

XT
ed

_E

_E
rv

rv
se

se
IO

IO
(re

GP

GP
31 8 7 6 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

GPIO_EXT_ETM_CHn_EVENT_SEL Configures to select GPIO for ETM event channel.

0: Select GPIO0
1: Select GPIO1
......
29: Select GPIO29
30: Select GPIO30
(R/W)

GPIO_EXT_ETM_CHn_EVENT_EN Configures whether or not to enable ETM event send.

0: Not enable
1: Enable
(R/W)

Espressif Systems 275 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.26. GPIO_EXT_ETM_TASK_P0_CFG_REG (0x00A0)

L
L

L
EN

EN
N

SE

SE
SE

N
SE
_E

_E
2_

2_

0_

0_
3_

1_
O3

O1
IO

IO

IO

IO

IO

IO
PI

PI
GP

GP

GP

GP

GP

GP
_G

_G
K_

K_

K_

K_

K_

K_
SK

K
AS

AS

AS

AS

AS

AS

AS
A
_T

_T

_T

_T

_T

_T

_T

_T
M

TM

TM

TM

TM

TM

TM
T

T
_E

_E

_E

_E

_E

_E

_E
T_
d)

)
XT

XT

XT

XT

XT

XT

XT
ed

ed

ed
EX
ve

_E

_E

_E

_E

_E

_E

_E
rv

rv

rv
O_
r
se

se

se

se
IO

IO

IO

IO

IO

IO

IO
I
(re

(re

(re

(re
GP

GP

GP

GP

GP

GP

GP

GP
31 28 27 25 24 23 20 19 17 16 15 12 11 9 8 7 4 3 1 0

0 0 0 0 0x0 0 0 0 0 0 0x0 0 0 0 0 0 0x0 0 0 0 0 0 0x0 0 Reset

GPIO_EXT_ETM_TASK_GPIOn_EN (n: 0 - 3) Configures whether or not to enable GPIOn to re-

sponse ETM task.
0: Not enable
1: Enable
(R/W)

GPIO_EXT_ETM_TASK_GPIOn_SEL (n: 0 - 3) Configures to select an ETM task channel for GPIOn.

0: Select channel 0
1: Select channel 1
......
7: Select channel 7
(R/W)

Espressif Systems 276 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.27. GPIO_EXT_ETM_TASK_P1_CFG_REG (0x00A4)

L
L

EN

EN
SE

SE

SE
N
SE

_E
_E

6_

6_

5_

4_

4_
7_

O5
O7
IO

IO

IO

IO

IO

IO
PI

PI
GP

GP

GP

GP

GP

GP
_G

_G
K_

K_

K_

K_

K_

K_
SK

K
AS

AS

AS

AS

AS

AS

AS
A
_T

_T

_T

_T

_T

_T

_T

_T
TM

TM

TM

TM

TM

TM

TM
T
_E

_E

_E

_E

_E

_E

_E
T_
)

)
XT

XT

XT

XT

XT

XT

XT
ed

ed

ed

ed
EX
_E

_E

_E

_E

_E

_E

_E
rv

rv

rv

rv
O_
se

se

se

se
IO

IO

IO

IO

IO

IO

IO
I
(re

(re

(re

(re
GP

GP

GP

GP

GP

GP

GP

GP
31 28 27 25 24 23 20 19 17 16 15 12 11 9 8 7 4 3 1 0

0 0 0 0 0x0 0 0 0 0 0 0x0 0 0 0 0 0 0x0 0 0 0 0 0 0x0 0 Reset

GPIO_EXT_ETM_TASK_GPIOn_EN (n: 4 - 7) Configures whether or not to enable GPIOn to re-

sponse ETM task.
0: Not enable
1: Enable
(R/W)

GPIO_EXT_ETM_TASK_GPIOn_SEL (n: 4 - 7) Configures to select an ETM task channel for GPIOn.

0: Select channel 0
1: Select channel 1
......
7: Select channel 7
(R/W)

Espressif Systems 277 ESP32-C6 TRM (Version 1.0)

Submit Documentation Feedback
7 IO MUX and GPIO Matrix (GPIO, IO MUX) GoBack

Register 7.28. GPIO_EXT_ETM_TASK_P2_CFG_REG (0x00A8)

EL
L

L
N

L
EN
SE

EN
N

SE
SE
_S

_E

_E
11_

1_

8_

8_
9_
10

10

O9
O1
IO

IO

IO

IO

IO

IO
PI

PI
GP

GP

GP

GP

GP

GP
_G

_G
K_

K_

K_

K_

K_

K_
SK

K
AS

AS

AS

AS

AS

AS

AS
A
_T

_T

_T

_T

_T

_T

_T

_T
M

TM

TM

TM

TM

TM

TM
T

T
_E

_E

_E

_E

_E

_E

_E

_E
)

)
XT

XT

XT

XT

XT

XT

XT

XT
ed

ed

ed

ed
_E

_E

_E

_E

_E

_E

_E

_E
rv<