Chapter 6

Test Compression

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What is this chapter about?

Introduce the basic concepts of test data compression Focus on stimulus compression and response compaction techniques Present and discuss commercial tools on test compression

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Test Compression
Introduction Test Stimulus Compression Test Response Compaction Industry Practices Concluding Remarks

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Introduction
Why do we need test compression?
Test data volume Test time Test pins

Why can we compress test data?

Deterministic test vector has dont care (Xs)

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Test data volume v.s. gate count

Volume of test data (Gb)
70 60 50 40 30 20 10 0 1 2 4 8 16

Test data volume increases with circuit size

32 64

Gate count (Mg)

(Source: Blyler, Wireless System Design, 2001)
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Test compression categories

Test Stimulus Compression
Code-based schemes Linear-decompression-based schemes Broadcast-scan-based schemes

Test Response Compaction

Space compaction Time compaction Mixed time and space compaction

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Architecture for test compression

Stimulus Response

Decompressor

Compressed Stimulus

Core

Compacted Response

Compactor

Low-Cost ATE

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Test stimulus compression

Code-based schemes Linear-decompression-based schemes Broadcast-scan-based schemes

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Test stimulus compression

Code-based schemes
Dictionary code (fixed-to-fixed) Huffman code (fixed-to-variable) Run-length code (variable-to-fixed) Golomb code (variable-to-variable)

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Code-based schemes
Dictionary code (fixed-to-fixed)

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Code-based schemes
Huffman code (fixed-to-variable)

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Code-based schemes
Huffman code (fixed-to-variable)

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Code-based schemes
Run-length code (variable-to-fixed)

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Code-based schemes
Golomb code (variable-to-variable)

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Code-based schemes
Golomb code (variable-to-variable)

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Test stimulus compression

Linear-decompression-based schemes
Combinational linear decompressors Fixed-length sequential linear decompressors Variable-length sequential linear decompressors Combined linear and nonlinear decompressors

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Linear-decompression-based schemes

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Linear-decompression-based schemes

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Linear-decompression-based schemes

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Linear-decompression-based schemes
Combinational linear decompressors

XOR Network

XOR Network

MISR
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XOR network: a 3-to-5 example

s1 s2 s3

o1 o2
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o3

o4

o5
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Linear-decompression-based schemes
Fixed-length sequential linear decompressors

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Linear-decompression-based schemes
Variable-length sequential linear decompressors
Can vary the number of free variables Better encoding efficiency More control logic and control information

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Linear-decompression-based schemes
Combined linear and nonlinear decompressors
Specified bits tend to be highly correlated Combine linear and nonlinear decompression together can achieve greater compression than either alone

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Test stimulus compression

Broadcast-scan-based schemes
Broadcast scan Illinois scan Multiple-input broadcast scan Reconfigurable broadcast scan Virtual scan

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Broadcast-scan-based schemes
Broadcast scan

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Generate patterns for broadcast scan

Force ATPG tool to generate patterns for broadcast scan

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Broadcast scan for a pipelined circuit

Broadcast scan for a pipelined circuit

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Broadcast-scan-based schemes
Illinois scan architecture

(a) Broadcast mode

(b) Serial chain mode

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Broadcast-scan-based schemes
Reconfigurable broadcast scan
Reduce the number of channels that are required Static reconfiguration
The reconfiguration can only be done when a new pattern is to be applied

Dynamic reconfiguration
The configuration can be changed while scanning in a pattern

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Broadcast-scan-based schemes
First configuration is: 1->{2,3,6}, 2->{7}, 3->{5,8}, 4->{1,4} Other configuration is: 1->{1,6}, 2->{2,4}, 3->{3,5,7,8}

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Broadcast-scan-based schemes
Block diagram of MUX network

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Broadcast-scan-based schemes
Virtual scan
Pure MUX and XOR networks are allowed No need to solve linear equations Dynamic compaction can be effectively utilized during the ATPG process Very little or no fault coverage loss

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Test response compaction

Space compaction Time compaction Mixed time and space compaction

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Test response compaction

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Taxonomy of various response compaction schemes

Compaction Schemes Zero-aliasing Compactor [Chakrabarty 1998] [Pouya 1998] Parity Tree [Karpovsky 1987] Enhanced Parity Tree [Sinanoglu 2003] X-Compact [Mitra 2004] q-Compactor [Han 2003] Convolutional Compactor [Rajski 2005] OPMISR [Barnhart 2002] Block Compactor [Wang 2003] i-Compact [Patel 2003] Compactor for SA [Wohl 2001] Scalable Selector [Wohl 2004] I Space Time CFS 36
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II CFI Linearity

III Nonlinearity

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Test response compaction

Space compaction
Zero-aliasing linear compaction X-compact X-blocking X-masking X-impact

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Space compaction
Zero-aliasing linear compaction

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An example of response graph

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Space compaction
X-compact
X-tolerant response compaction technique X-compact matrix Error masking

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Space compaction
X-compact

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Space compaction
X-compactor with 8 inputs and 5 outputs

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X-compact Matrix
SC1 SC2 SC3 SC4 S= SC5 SC6 SC7 SC8 O1 O2 O= O3 O4 O5

X S = O
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Space compaction
X-blocking (or X-bounding)
Xs can be blocked before reaching the response compactor Can ensure that no Xs will be observed May result in fault coverage loss Add area overhead and may impact delay

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Space compaction
Illustration of the x-blocking scheme

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Space compaction
X-masking
Xs can be masked off right before the response compactor Mask data is required to indicate when the masking should take place Mask date can be compressed
Possible compression techniques are weighted pseudorandom LFSR reseeding or run-length encoding

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Space compaction
An example of X-masking circuit

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Space compaction
X-impact
Simply use ATPG to algorithmically handle the impact of residual xs on the space compactor Without adding any extra circuitry

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Space compaction
Handling of X-impact

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Space compaction
Handling of aliasing

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Test response compaction

Time compaction
A time compactor uses sequential logic to compact test responses MISR is most widely adopted n-stage MISR can be described by specifying a characteristic polynomial of degree n

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Multiple-input signature register (MISR)

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Test response compaction

Mixed time and space compaction

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Industry practices
OPMISR+ Embedded Deterministic Test Virtual Scan and UltraScan Adaptive Scan ETCompression

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Industry solutions categories

Linear-decompression-based schemes
Two steps
ETCompression, LogicVision TestKompress, Mentor Graphics SOCBIST, Synopsys

Broadcast-scan-based schemes
Single step
SPMISR+, Cadence VirtualScan and UltraScan, SynTest DFT MAX, Synopsys
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Industry practices
OPMISR+
Cadence Roots in IBM s logic BIST and ATPG technology

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General scan architecture for OPMISR+

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Industry practices
Embedded Deterministic Test (TestKompress)
Mentor Graphics First commercially available on-chip test compression product

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EDT (TestKompression) architecture

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TestKompress stimuli compression

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TestKompress response compaction

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Industry practices
Virtual Scan and UltraScan
SynTest First commercial product based on the broadcast scan scheme using combinational logic for pattern decompression

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VirtualScan architecture

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UltraScan architecture

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Industry practices
Adaptive Scan
Synopsys Designed to be the next generation scan architecture

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Adaptive scan architecture

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Industry practices
ETCompression
LogicVision Built upon embedded logic test (ELT) technology

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ETCompression architecture

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Summary of industry practices

MISR: multiple-input signature register MUX: multiplexers PRPG: pseudo-random pattern generator TDDM: time-division demultiplexer TDM: time-division multiplexers XOR: exclusive-OR
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Concluding remarks
Test compression is
An effective method for reducing test data volume and test application time with relatively small cost An effective test structure for embedded hard cores Easy to implement and capable of producing high-quality tests Successfully as part of design flow

Need to unify different compression architectures

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