Project Assignment VLSI Design 4th year CSE
Summation date: Apr 20, 2024
SN Name sex Group Title Descriptions Remark
1 Awet Alemaayehu M G-1 Differential Design and simulating
2 Henok Mulugeta M Amplifire Sequential logic circuit using
3 Muleye Tsegay M VHDL
4 Kibrom Redae M
5 Rishane Mebrahtu F
6 Hermon H/selase M G-2 CMOS D – CMOS circuit design using
7 Berihu Araya F Latch SPICE (DC and Transient
8 Kibrom W/gewergs M Analysis)
9 Brhane Araya M
10 Emebet Kibrom F
11 Naod Yemane M G-3 CMOS CMOS circuit design using
12 Fillmon Tsehaye M Inverter SPICE (DC and Transient
13 Fillmon Mezgebe M Analysis)
14 Awet Equbiay M
15 Shambel Kiduis M
16 G/wahed Tafere M G-4 4 Adder FPGA Implementation
17 Medhaniye Kahsay M
18 Guesh Gebru M
19 Hayelom Teklay M
20 Brhane G/her M
21 Nebiyu Yohaness M G-5 CMOS NOR CMOS circuit design using
22 Maebel Niguse M gate SPICE (DC and Transient
23 Yohaness Hailemaryam M Analysis)
24 Yosef Tuemey M
25 Abel Tsegabu M
26 Syum Berigu M G-6 Shift Register Design sequential logic circuit
27 Nebeyat G/her M using VHDL
28 G/her Hailu M
29 Tesfaalem Tamene M
30 Ashenai G/hewot M
31 Amanial Yirgalem M G-7 CMOS CMOS circuit design using
32 Danay H/Maryam M NAND gate SPICE (DC and Transient
33 G/her Gunde M Analysis)
34 Fisseha Tesfay M
35 Tewestya T/haymanot M
36 Desalegn G/aher M G-8 Filip Flop Design and simulating
37 Danial Assefa M Sequential logic circuit using
38 G/medhin Yihaysh M VHDL
39 Yordanos Kelali F
40 Betelihem W/gebrial F
41 Shakir Ahmedsirag M G-9 Encoder and Design and Simulating
42 Dnial G/her M Decoder Combinational logic circuit
43 Mulat Tesfay M using VHDL
44 Yohaness Nguise M
45 Yaread Reta M
46 H/selasse Kiros M G-10 Multiplexer Design and Simulating
47 Mulugeta G/krstos M and De- Combinational logic circuit
48 Mhretab Yehdego M multiplexer using VHDL
49 Betelihem Hagos F
50
51 Abuboker Abriahim M G-11 Frequency Design and simulating
52 Henok Gebremedhin M Divider Sequential logic circuit using
53 Naod Tadess M VHDL
54 Yordanos Desalegn F
55
56 Teamr Yeheys M G-12 ALU Design and simulating
57 Esral Tesfay M Sequential logic circuit using
58 Sara Kelali F VHDL
59 Simret Tesfay F
60 Samuial Mezgebo M
61 Halefom Hailemichail M G-13 Counter Design and simulating
62 Kibrom G/ebrezigher M Sequential logic circuit using
63 Kisanet Teklay F Verilog HDL
64 Merha G/libanos M
65 Tsega W/gebrial F
