80386 Microprocessor

 Introduction to Protected Mode Memory Addressing

 Memory Paging Mechanism
 Introduction to 80386 Microprocessor
 The Memory System Special 80386 registers
 80386 Memory Management
 Virtual 80386 Mode

Introduction to 80386
 80386 family of microprocessor of INTEL Corporation is the first 32 bit version
of 8086 family.
 808386 was launched in October 1985, but full function chips were first
delivered in third quarter of 1986 (July - September).
 Used in aerospace technology.

Features of 80386
 Manufactured by Intel
 80386 is upgraded form of 8085, 8086, 80186 and 80286
 32 bits of ALU.
 32 bits of MPU (Memory Processing Unit).
 32 bits of data bus.
 32 bits of address bus
 2 speed versions -Single Speed – has 16 bits of data bus
Double Speed – has 32 bits of data bus
 Supports 3 level pipelining (Fetch, Decode & Execute)
 Has protection mechanism
 Supports multitasking
 Can have 64TB virtual memory by memory segmentation
 Supports Paging

Modes of 80386
 Real Mode
 Protected Mode
 Virtual Mode
 Pin Diagram of 80386 Microprocessor

 N/C: No connection pins are expected to be left open while connecting the
80386 in the circuit.
 VCC: These are system power supply lines.
 VSS: These return lines for the power supply.
 A31 – A2: These are upper 30 bit of the 32- bit address bus.
 D0 – D31: These 32 lines act as bidirectional data bus.
 INTR : Interrupt Request Pin
 ERROR#: The error input pin indicates to the CPU that the coprocessor has
encountered an error while executing its instruction.
 NMI: A valid request signal at the non-maskable interrupt request input pin.
 PEREQ: Processor extension request pin, output pin, fetches data word from
coprocessor.
 BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy
with the allocated task.
 RESET: A high at this input pin suspends the current operation and restart the
execution from the starting location.
 W/R# : Write / Read cycle
 Lock#: Output Pin, Prevents 80386 from coprocessor to use buses directly.
 D/C# : Data control output
 M/IO#: Differentiates memory / input output cycle.
 BED#, CLK2: The input pin provides the basic system clock timing for the
operation of 80386.
 BE0 to BE3: These are 4 byte enable lines BE0 to BE3. Using these 4 enable
signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously.
 READY#: The ready signals indicates to the CPU that the previous bus cycle
has been terminated and the bus is ready for the next cycle. The signal is used to
insert WAIT states in a bus cycle and is useful for interfacing of slow devices
with CPU.
 BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with
the 32 bit wide 80386 data bus.
 HOLD: If the bus hold input pin is enable the other bus masters to gain control
of the system bus if it is asserted.
 HLDA: The bus hold acknowledge output indicates that a valid bus hold request
has been received.
 ADS#: The address status output pin indicates the address bus and bus cycle
definition pins are carrying the respective valid signals. The 80383 does not
have any ALE signals and so this signals may be used for latching the address to
external latches.

80386 Memory Management

 Memory Management section of 8086 supports virtual memory, paging and four
levels of protection.
 80386 has 8 debug registers DR0-DR7 for hardware debugging and control.
 Paging concept was introduced to organize available physical memory in terms
of page size 4Kb each under segmented memory.
 Introduction to Protected Mode Memory Addressing
 All capabilities of 80386 are available for utilization in its protected mode of
operation.
 Protected mode is where Windows is operated.
 Supports all programs written for 80286 and 8086.
 Can address 4 Gb of physical memory and 64Tb of virtual mode.
 Protected mode allows use of additional instructions and addressing of 80386
 Allows microprocessor to access all data and programs located above 1Mb.
 Segment registers are present but segment address is not present so we use
selector.
 Selector selects a descriptor from descriptor table. (No. of descriptors = 2 x
8192 = 16384)
 Descriptor – describes memory segment (Location, Length, Access Rights).

Protected Mode Memory Addressing (Without Paging Unit)

Segment Descriptor
 Selector gets base address.
 Offset address is combined with base address to get linear address.
 Linear address is used to get physical address with help of memory operand and
segment base.
 Segment limit is up to 4 Gb.
 Linear address can be used as physical address.
 Protected Mode Memory Addressing (With Paging Mechanism)

 Page unit is a memory management unit enable (only in protected mode)

 When CPU Paging Mechanism is done on liner address we get physical address
and page frame address which points to memory operand.
 Each task is divided into pages with size 4kb each
Special 80386 Registers

1. Control Registers:

 These are 32 bit registers

 Control Registers are available in protection mode only
 CR0 – Indicates machine status word through flags.
 PE-Protection Enable bit: 1=Protected mode, 0=Real mode
  MP-Monitor Coprocessor: 1= Coprocessor present, 0=Coprocessor Absent
 EM-Emulation bit: 1=Emulation feature enabled
 TS-Task Switch: 1= Allow saving task context after task switch occurred
 ET-Extension Type: 1=coprocessor is 80387, 0=coprocessor is 80287
 PG-Paging Enable bit: 1=Paging Enabled, 0=Paging Disabled
 CR1 – Reserved by Intel
 CR2 – Read only register. Linear address of Page fault
 CR3 – Holds page address of page directory. Last 12 bits are 0.

2. Debug Registers:
 Used to remove error and faults during execution of program
 8 debug register – DR0 to DR7
 32 bit register each
 DR0 to DR7 total 8 debug registers
 DR0 to DR3 – Linear breakpoint
address 0 to 3
 DR4 and DR5 – Reserved by Intel
 DR6 – Break point status
 DR7 – Break point control

3. Test Registers:
TR6 – Test Control
TR7 – Test Status
 Paging Mechanism

 Convert linear address to physical address. (Linear address has 32 bits)

 CR3 gives base address of page fault.
 Page Directory: Contains 1024 entries, each pointing to a page table.
 Page Table: Contains 1024 entries, each pointing to a physical frame.
 Each entry in the page directory or table is 4 bytes (32 bits) wide
Architecture of 80386 Microprocessor

 Architecture of 80386 Microprocessor has 5 functional units

1. BIU (Bus Interface Unit)
 2. CFU (Code Fetch Unit)
3. IDU (Instruction Decode Unit)
4. EU (Execution Unit)
5. MMU (Memory Management Unit)

1. BIU (Bus Interface Unit)

 Connects 80386 with memory I/O
 Holds 32 bit bidirectional data bus as well as 32 bit address bus
 During instruction R/W, BIU generates signals for activating the data and
address bus in order to fetch the data from desired address.
2. CFU (Code Fetch Unit)
 When system needs instruction to perform next task CFU fetches the
instruction stored in memory
 To speed up the operation of 80386, this unit fetches the instruction in advance
and stores these instructions in queue.
3. IDU (Instruction Decode Unit)
 Decodes instruction stored in prefetch queue.
 Takes instruction bytes from the code prefetch queue and translates them into
microcode.
 Decoded instruction are then stored in the instruction queue. They are passed to
control section.
4. EU (Execution Unit)
 Instructions are provided to execution unit in order to execute instructions.
 EU has 32 bit ALU
 Also has 8 general purpose and 8 special purpose registers used to handle and
calculate offset address.
5. MMU (Memory Management Unit)
 Has 2 sub units
a) Segmentation Unit
 Offers protection mechanism in order to protect the code or data present in
memory from application programs.
 Every information has been given a privilege level (PL0 to PL3, PL0 has
highest priority and PL3 has lowest priority).
b) Paging Unit
 Supports multitasking
 Operates only in protected mode
 Changes linear address into physical address

Flag Register of Microprocessor 80386

 D0 to D11 flags are same as in 8085 and 8086

 IOPL – I/O Privilege levels. Shows priority levels (00 – High,..,11- low)
 NT – Nested Task ( Other task other than the current one, returns to current
task after performing nested task)
 RF – Resume Flag (Unnecessary debug breakpoint in program)
 VM – Virtual Mode (Used to run 8086 program in faster way)

Descriptors Tables
1. Global Descriptor Table (GDT)
 Descriptor – describes memory
segment (Location, Length, Access
Rights)
 There are 8192 Descriptors, each of 8
bytes
 Total size 64 kB
 48 bit GDTR is used
 Descriptor 0 is Null Descriptor
(Reserved by INTEL)
 GDTR selects any descriptor from GDT

2. Local Descriptor Table (GDT)

 Local Memory area shared by
tasks.
 LDT has 8192 descriptors
 Extension to GDT
 LDTR provides index of LDT
Descriptor in GDT.
 LDTR changes as task changes
 Virtual Mode of 80386
 Virtual mode of 8086 is also called as V86
 It is a dynamic mode i.e. processor can switch between V86 and protected
mode repeatedly and rapidly.
 Paging can be performed here (linear to physical)
 Processor enters V86 mode to perform 8086 programs and leaves to continue
execution of 80386 program in protected mode.