Date

Sinhgad Institutes
Assiqnment Noi-06

Q1 Ath neat circuit diagram explain current to valtage converter

Definiion:
The opanmp ckt which produces an autput valtage
praportionad to its input cument is called as on
T to V converter

Circuit diaqram:

Vo

i> The open loop qain Av of Ehe oP-AMP is very large

So as per the concept af virtual short
V
> Tnput impedance of the OP-AMP is very high.
3> Gain the inverting amplifier is qiven hy
Aup = -RE Vo
R, Vin.
Vo = - RE xVin 0
4> But Vheheo as the nan-inverting (4) terminal
is conneched to qround
>Thus the inverting terminal () aso is al qround pctential
l the entirt Ip valkage appers across Rr
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Sinhgad Institutes

Tin = Vin
R
Vin = Iin Ri
trom
Vo =-Rr Iin
Q2An -bit DAC Converter has o resolution of IomV/bit. Fnd
the analog Vo fox the Follouoing digital input
1000 O10
0001 0000
Given: Rescluion = 1O m/b n:
To Find: 1.Vo for l0001010 2. Vo FoT 00010000
Resolution = VEs
2n-1
l0x10-3 = Ves
VeS = 2.SS v/sB
Vo = 2.5ss (1x2-) +0+ 0+o}+(1x 2s) +o+(ix2-7)+o

Vo = ( 3746 Volts
Vo -38 Valts

2) Vo = 2-5S O+o+0+(x2-9) +o+0+0+o

Vo = 0.S93 Volts.
Vo O.16 Valts
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Sinhgad Institutes

0.3 th the helo of black diagraro _explain operation o PLL

Detine the term ock range"& <captut range"

TPhase

Companentsi
Phase detectoxPhase detectoy compats ilp Ereq R4
Feedhack freg fo' which is lp af VCo.
>law Pass Gller :-High e: Component Atho' is removed
by louw pass Cilker and difference frequency Cifo) is
amplified by erroY Gmp' and sent to VCo Cvoltage
Cantrol Oscillator)
1 The Pll ckt is basically used For tracking c
System. poticdar
2 The stoe of synchranization betueen the input &outpd
is called as the locked state In the locked state he
phase error between the Ilp ond p is minimum.
3 Thus the phose of the Op siqnal is locked to that af
the input siqnal hence the nome phase locked loop.
Lock Ronge:
) The lock onge of a PLL is deined as the range
inpat frequencies abaut the centre frequency over which
the loop maintains a lock.
The lock range is always symmehrically located with
respect to the centrR brequency of the CO.
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42
Sinhgad Institutes

Cophure Range:
The capture ronge is the ronge of out put Frequencies
kox uhich the initially nk unlocked loop coill ge
locked on on input signa
The cophure range also is Summetricaly locaed
albaut tae centre frequency of VCO
QCalculake the output frequency fo,lock range
capture Yange Afe of a PLL-IE Rr= loke Cr= 0.0lu
ilkr capacitor C= lOuf and Tnterna) resistance =3.6k
Assume ±V=lo.
Given: Rr= loke Cre 00af Cp=l0,Ra =3.6ke
D Outpud Frequency, o= 0.2S
RCT
0.25
t0x(0x 0-01 x 10-6

2 Lock ronge af = 8.o

Assuming V=20 Vlts
8x 250O t|000 Hz
20

Lock range i IsOO Hz to 3s0O Hz

Capture range, Afe = +
2T x3-6xIo Ce
+
1000
21 x 3-6x |ox 10x\06
Ofe = t 6s H2
Capture range 2433-S H2 to 2566-5 Hz
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|Sinhgad Institutes

QADrauw neot circuit diagram of VolBage controlled ascillotox

(Vco) and derive expression kor ouBput Hrequency

Ra

The VCo generates an outpu frequency that is

directly proportional to ite input voltage
DA commonlu available VCO in the TC foznm is
signetics NE/SE SK6
3 The constant current Soureelsink hlack is used
to charge and discharge he extremely onnected
timing capacitor C7 linearly.
to 2(Vee- % Vee)
RrCr Vec
1
4R1Cr
fo = O.25
RC
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429
Sinhgad Institutes

Q5 Oraw ckt diagram of R-2R laddey DAC ond write

its output eq.
Diagram.

2R

Applying nodal analysis at node A

VA VA -Ve O
R
..3VA t 2VA -2 Ve = 0
2R

Bo
(mse) Ve = 5VA/2O

Applying nadal analysis at nade B

+ Ve -(-Ve) Ve-VA = 0
2R 2R R
4Ve + VR -2VA =0
2R
VA = 2V8 + Ve

Puting Ve in eg". O
VA =2SVA
2
+ Ve2
. VA SVA + VR 2
.VA= -VR
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Sinhgad Institutes

p voltage of Complete. setup will be

R
M= Va

Csl Draw ckt diagram of binay_ weighted DAC and wite

its p eg.

Vo

-VA

Here T, = I +I, t.... In

2'R 2°R 2°R

Ve b2 4 ba2*+.tb, 2

Vo= IoRE = Ve Lb, 2" 2

+b tba2
R
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Sinhgad Institutes

a Draw ckt diagram of frequency mulBilier using PL and

explain its operation.
A requency
Erequency Tt
mulliplier generaBes mutiples of the inpud
consists of PLL uith a
divider in the lb path frequency
Diagcam
Phase JAmp' Low pOss VCO
Camparator Alter fo= NG
N
N Netuprk
(Arequencydivider)

3 cydes

fo =3f;

DFrcq. divider divides the op of VCO by factors_ of N'.

Phase detector Campares oith the divideclfa and
adjusts VCo to maintain the lock
Hence, the Fo is N'times the Ei
4 The lo) _poss iler is used to filkr the error
transferred Volkae
from the cimp'
 265.22
Hz 1 =fe
2X10x10x
\o-6 \/ 2Tt RCa V 2T
S3.04x103 x21T
=S3-04
kHz ft
VEE Vec-
20
xlo3
8x132.6
kHz 132.6 to=
(os /0-00lx x10-6 x0-01 12xIo x2Tt
lox[o-6
R,C 2T
-10V =
VEE
Ve= 12ke, R= uf
0-00l C3= l0Mf =Ca, 0.0laf C=Given:
-Va-10V
5
2
cincuit qiven the
requency tor unningferange capture and
anget lack and fo Calcre
ulate Q
Institutes Sinhgad
Date
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Sinhgad nstitutes

s Explain with a neat diagrou). oorking Vto I convertox

@
Luith grounded load ond derive the eg of Load crent IL
’ DThe Vta I convertor aith qraunded load converts
valBage input into a current output while keeping
Che emincl of the R qraunded.

-o Vo=2V;

L
LOAD

This circuit oorks on theprinciple af negative feedlback

o the opamp tohich tries to keepthe VolBage difkrence
betweenits input termin als zero.
) Hence the Vi is dropped aCrOss. R ond Vo drops
across Rc
V
R
|4 T is the current Elouwing Hhrough R where R= Re
12I= Vo
R
. I = Vi Re
Ri R
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Sinhgad Institutes

Froro the eqn we con say that IL is

to Vi and inversely propoxtiona to RLproportiona
Q1o Draw and explain frequency shift keying (ESK)
using IC 565 demodulator
FSk is o method of digitel modulation that uses
diferent .Corrier frequencies to represent binary datatuo.
The Carrier Frequencies te tepreseet
to the logic state of ilp signal change according.
qenerake FSK usiog IC565, the ip binarysiqna is
applied to VCO that produces two diferent frequencies
with respect to 0' and state
To demodulate ESk using IC565., the
recieyer ESk
signal is applied to ilp PLL which locks the and
tracks it blw tuo possible hreguencies with a coespandisg
DC shifE at its olp

-Vec N.C
Ip Phase
N.C
2Detec tor
N.C
N.C
Phase comparator VCo ilp Vco +Vec
5
Ref op Tirning capacitor
7 Amgpl Timing Resistors
VCO contro) Vg
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Sinbgad Institutes

QThe o/p of s -bit ADC with al 1s when Vi=5

find its: Resolution and Digital o/p_ cade if Vi=l-7 V
Given: Vic = 5V No. af bits = &
Resalution =2=2= 256 levels
Digita) p= V x (29-1) (h= reference yta)

Maximunn digital p forADC is

Then D: 1-7 255 = §7: 48 87
Converting 87 to binag Oloto

Q13 Deine Lock range, capture ronge and Free

running
Frequency and explain transfer characBeristics of PÍL
Free running frequenty: Tis the type of Frequency
of VCO where there is no ilp signal or the ip siqna
is outside the lock Faee rOnge of PLL. fe is determinec
by the follouoing formuwa:
fe =
2T VLC

Tronsfer charackeristics af PIL:

Capture range: This is the range of F for which the
PLL can acquin phase lock from on ini tially unlocked
state Capture range is smaller then lock range of
depends on loap gain and loop klkr Band width of
the PLL
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Sinhgad lInstitutes

Lock Tangei T is the of f for which the PlL

range
Canmaintain phase lock once it is achieved. The
lock range is larger than capture range and depends
Cn hreerunning requency and phase cetector
characBerishics o PLL.
Out at range : TH is the range o ip frequencies or
which the PLL connat achieye or maintain phase
lodk PlL op Frequency will either be equal' to f
0scillates. aroundit

Q. I3] Nrite shoxti hotes on the applications of PlL as

requeEncy muliplier t
DPLL is a /b Sustem that con lock into the phase and
Frtquency af an ilp igna.
By inserting a brequency dividler ino VCO Qutpud and
phase comparatox ipthe PUL can qenerahe an op
Signal ith o Frtquency that is a multiple and
divider rotio 'N).
fo= N;
) This woy PlL produces hiqh freq clock signa frarm
lous-Ert relerence signal.
a FM demadulatoy:
PLL can be used os an EM demodulator by tracking
the phase 4 rtquency Variations oF a camier signal
PLL adjusts Vco freq so that it matches the freg of
Fm signa). The error Signal is then ilter by the lou
pass FlBer and used to_ control VCo.
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|SinhgadInstitutes

Q.3 Drauw V to I converter with floating load and explaio.

with p equation.

The Vta T convertor canverts an ip volBage into.

a proportianal output Current hile the RL is not
connected to qYound. Tt is cument series Flb amp.
The basic principleok this ee circuit is to use an
opamo to maintuin a constanto wtg acrOSS the
resistor which deternmines the Ta.
Voltage eg for ilp loop i
V;= Vid + VE
As A' is large Vid=0
V;= VE
Vi= RIo
I, Vi
R
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Sinhgad lnstitutes

is DraL) and explain successive_approximaBian AlD converter

Gucteoghe approritnat tocl, CIaclkL

reqjstoy

tse) Ouzput

OAC

D This type of ADC apgrates by successively dividing the

voltoge range by half
D MsBis initially sel to with other bits as '000'.
Ihe digital equivadent vtg is compatd with unknawn
analag ip voltage
s) T analag pis greater than digital equivclant valtage
MsB is retined as ' and second Ms& is set to
T Step Qis followed to decide rehention or resetting
the second MsB..

Advantagesi
Small Conversion ime
>Converion time is constant,ie independent df amplttucde
ofVA'

Disadvantagesi
> Ckt is complex.
> Conyersian time is morethan that in Flash type
ADC.
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Sinhgad Institutes

Q Fox IC 565, give exprtssion of free tunning treq, lock

range and capBure range.
Fe unning
fo Q:3frequency
RiG
where Rand C are exteYnal resisbance and capacitance
Lock range
V= Sum o absolute values of Ve cund -Ve
voltages (Vee and - VEe) supply
Capturx range 2
2F
R, a
where Ra is internal resisbanceof 3-6 kn and C.
is external capacitor
Q17 Desian o PLL cixcuit using 565 TC to get free
running frequen cy 45 kHzlock range 2kHz and
capture ronge lo0Hz Assume Vec =loV, -VeE -lOV.
fo = 4.5 kHz Fe= lo0Ha Vec =IoV,
-VEE =-IoV
fo = 0:3.
R,C
RiCi = 0.3 0-3 66-67 x I0-6
to 4sOo
Solving for R and G
R= 3-53 k
G= 100nf
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Sinhgad Institutes

2T x2x|0
3-5xI0 x (o0

C = 359uf
Circutt:

3.6k
|Ohose Jem p
Amo
Tle 2 o Ndetector Ref olp
Comporator

VCO oloo VCO

VM

4V V