LAB - 1

Aim: To simulate and synthesize all the logic gates using Verilog HDL

module lab1(a,b,and_out,or_out,not_out,nand_out,xor_out,xnor_out,nor_out);

input a,b;
output and_out,or_out,not_out,nand_out,xor_out,xnor_out,nor_out;
assign and_out=a&b;
assign or_out=a|b;
assign not_out=~a;
assign nand_out=~(a&b);
assign xor_out=a^b;
assign xnor_out=~(a^b);
assign nor_out=~(a|b);
endmodule

module lab1_tb();
reg a,b;
wire and_out,or_out,not_out,nand_out,xor_out,xnor_out,nor_out;
lab1 uut(a,b,and_out,or_out,not_out,nand_out,xor_out,xnor_out,nor_out);
initial begin
a=0;b=0;#10;
a=0;b=1;#10;
a=1;b=0;#10;
a=1;b=1;#10;
#10 $finish;
end
endmodule

LAB - 2

(A) Design of Half adder

module half_add(a,b,sum,carry);
input a, b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

module half1_tb();
reg a,b;
wire sum,carry;
half_add dut(.a(a) , .b(b) , .sum(sum) ,.carry(carry));
initial begin
a=0;b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1; b=1;
#10 $finish;
end
endmodule

(B)Design of a Full Adder Using Different Modeling Styles in Verilog and Simulation

(a) Gate-level Modeling:

module lab2a( a, b, cin, sum, carry );

input a,b,cin;

output sum,carry;

wire sum1, carry1, carry2;

// Gate-level implementation using XOR and AND gates

xor (sum1, a, b); // sum1 = a ⊕ b

xor (sum, sum1, cin); // sum = sum1 ⊕ cin

and (carry1, a, b); // carry1 = a ⋅ b

and (carry2, sum1, cin); // carry2 = sum1 ⋅ cin

or (carry, carry1, carry2); // carry = carry1 + carry2

Endmodule
module lab2a_tb();

reg a, b, cin;

wire sum, carry;

// Instantiate the Full Adder (Gate-level)

lab2a uut (.a(a), .b(b), .cin(cin), .sum(sum), .carry(carry));

initial begin

a = 1'b0; b = 1'b0; cin = 1'b0; #10;

a = 1'b0; b = 1'b0; cin = 1'b1; #10;

a = 1'b0; b = 1'b1; cin = 1'b0; #10;

a = 1'b0; b = 1'b1; cin = 1'b1; #10;

a = 1'b1; b = 1'b0; cin = 1'b0; #10;

a = 1'b1; b = 1'b0; cin = 1'b1; #10;

a = 1'b1; b = 1'b1; cin = 1'b0; #10;

a = 1'b1; b = 1'b1; cin = 1'b1; #10;

#10 $finish;

end

Endmodule
(b) Dataflow Modeling:

module lab2a( a, b, cin, sum, carry );

input a,b,cin;

output sum,carry;

// Dataflow modeling using Boolean expressions

assign sum = (a ^ b) ^ cin; // sum = (A ⊕ B) ⊕ Cin

assign carry = (a & b) | (cin & (a ^ b)); // carry = (A ⋅ B) + (Cin ⋅ (A ⊕ B))

endmodule

© Behavioral Modeling:

module lab2a( a, b, cin, sum, carry );

input a,b,cin;

output reg sum,carry;

// Behavioral modeling using procedural block

 always @(*) begin

sum = (a ^ b) ^ cin; // Sum calculation

carry = (a & b) | (cin & (a ^ b)); // Carry calculation

end

endmodule

© To design full adder using half adder and simulate the design

module full_adder1 (

input A, B, Cin,

output Sum, Cout

);

wire sum1, carry1, carry2;

half_adder ha1 (

.A(A),

.B(B),

.Sum(sum1),

.Carry(carry1)

);

half_adder ha2 (

.A(sum1),

.B(Cin),

.Sum(Sum),

.Carry(carry2)

);

assign Cout = carry1 | carry2;

endmodule

module half_adder (

input A, B,
 output Sum, Carry

);

assign Sum = A ^ B;

assign Carry = A & B;

endmodule
LAB - 3

(A)Design of a 2 to 4 Decoder Using Dataflow Modeling in Verilog

TRUTH TABLE

module decoder_2_4c(

input A0,A1,E,

output D3,D2,D1,D0

);

assign D0 = E && !A0 && !A1;

assign D2 = E && A0 && !A1;

assign D1 = E && !A0 && A1;

assign D3 = E && A0 && A1;

endmodule

module decoder_2_4_tb;

reg E,A0,A1;

wire D3,D2,D1,D0;

decoder_2_4c dut(.E(E),.A0(A0),.A1(A1),.D0(D0),.D1(D1),.D2(D2),.D3(D3));

initial

begin
 A0 = 1'bx; A1 =1'bx; E = 1'b0;

#10 A0 = 1'b0; A1 =1'b0; E = 1'b1;

#10 A0 = 1'b0; A1 =1'b1; E = 1'b1;

#10 A0 = 1'b1; A1 =1'b0; E = 1'b1;

#10 A0 = 1'b1; A1 =1'b1; E = 1'b1;

#10 $finish;

end

Endmodule

(B) To design 2 to 4 decoder using case statement (behavior level)

module decoder_2_to_4 (

input wire A1, A0, EN,

output reg Y0, Y1, Y2, Y3

);

// Behavioral modeling using case statement

always @(*) begin

// Initialize outputs to zero

Y0 = 1'b0;

Y1 = 1'b0;

Y2 = 1'b0;

Y3 = 1'b0;

if (EN) begin

case ({A1, A0}) // Combine inputs into a 2-bit vector

2'b00: Y0 = 1'b1; // When A1 = 0, A0 = 0

 2'b01: Y1 = 1'b1; // When A1 = 0, A0 = 1

2'b10: Y2 = 1'b1; // When A1 = 1, A0 = 0

2'b11: Y3 = 1'b1; // When A1 = 1, A0 = 1

default: begin

Y0 = 1'b0;

Y1 = 1'b0;

Y2 = 1'b0;

Y3 = 1'b0;

end

endcase

end

end

endmodule
Lab - 4
1. Design of 8x3 encoder and simulate the design.

module encoder(y0,y1,y2,y3,y4,y5,y6,y7,a,b,c);

input y0,y1,y2,y3,y4,y5,y6,y7;

output a,b,c;

assign a=y4|y5|y6|y7;

assign b=y2|y3|y6|y7;

assign c=y1|y3|y5|y7;

endmodule

module testbench();

reg y0,y1,y2,y3,y4,y5,y6,y7;

wire a,b,c;

encoder uut(y0,y1,y2,y3,y4,y5,y6,y7,a,b,c);

initial begin

y0=1; y1=0; y2=0; y3=0; y4=0; y5=0; y6=0; y7=0;

#10 y0=0; y1=1; y2=0; y3=0; y4=0; y5=0; y6=0; y7=0;

#10 y0=0; y1=0; y2=1; y3=0; y4=0; y5=0; y6=0; y7=0;

#10 y0=0; y1=0; y2=0; y3=1; y4=0; y5=0; y6=0; y7=0;

#10 y0=0; y1=0; y2=0; y3=0; y4=1; y5=0; y6=0; y7=0;

#10 y0=0; y1=0; y2=0; y3=0; y4=0; y5=1; y6=0; y7=0;

#10 y0=0; y1=0; y2=0; y3=0; y4=0; y5=0; y6=1; y7=0;

#10 y0=0; y1=0; y2=0; y3=0; y4=0; y5=0; y6=0; y7=1;

#10 $finish;

end

endmodule

LAB - 5

1. Design of 2x1 & 4x1 multiplexer & Demultiplexer and simulate the design

(A) 2x1 multiplexer

module mux2_to_1(a,b,s,y );

input a,b,s;

output y;

assign y=s?a:b;

Endmodule
module mux2_to_1_tb();

reg a, b, s;

wire y;

mux2_to_1 uut (.a(a), .b(b), .s(s), .y(y));

initial begin

a = 1'b0; b = 1'b0; s = 1'b0;

#10 a = 1'b0; b = 1'b1; s = 1'b1;

#10 a = 1'b1; b = 1'b0; s = 1'b0;

#10 a = 1'b1; b = 1'b1; s = 1'b1;

#10 $finish;

end

endmodule

(B) 4x1 multiplexer

module Mux4(A,B,C,D,S,Z);

input A,B,C,D;

input [0:1]S;

output reg Z;
 always @(*) begin

case(S)

2'b00: Z = A;

2'b01: Z = B;

2'b10: Z = C;

2'b11: Z = D;

default: Z = 2'bxx;

endcase

end

endmodule

module Mux4_tb( );

reg A,B,C,D;

reg[0:1]S;

wire Z;

Mux4 uut(A,B,C,D,S,Z);

initial begin

S = 2'b00; A = 1'b0; B = 1'bx; C = 1'bx; D = 1'bx;

#10 S = 2'b00; A = 1'b1; B = 1'bx; C = 1'bx; D = 1'bx;

#10 S = 2'b01; A = 1'bx; B = 1'b0; C = 1'bx; D = 1'bx;

#10 S = 2'b01; A = 1'bx; B = 1'b1; C = 1'bx; D = 1'bx;

#10 S = 2'b10; A = 1'bx; B = 1'bx; C = 1'b0; D = 1'bx;

#10 S = 2'b10; A = 1'bx; B = 1'bx; C = 1'b1; D = 1'bx;

 #10 S = 2'b11; A = 1'bx; B = 1'bx; C = 1'bx; D = 1'b0;

#10 S = 2'b11; A = 1'bx; B = 1'bx; C = 1'bx; D = 1'b1;

#10 $finish; $stop;

end

endmodule

© Design of 2x1 Demultiplexer and simulate the design

module demux2x1_dataflow (

input wire d,

input wire sel,

output wire y0,

output wire y1

);

assign y0 = (~sel) & d;

assign y1 = sel & d;

endmodule

module tb_demux2x1_dataflow;

reg d;
 reg sel;

wire y0, y1;

demux2x1_dataflow uut (

.d(d),

.sel(sel),

.y0(y0),

.y1(y1)

);

initial begin

d = 1; sel = 0; #10;

d = 1; sel = 1; #10;

d = 0; sel = 0; #10;

d = 0; sel = 1; #10;

$finish;

end

endmodule

(d) Design of 4x1 Demultiplexer and simulate the design

module demux4x1_dataflow (
 input wire d, // Input data

input wire [1:0] sel, // Select lines

output wire y0, // Output 0

output wire y1, // Output 1

output wire y2, // Output 2

output wire y3 // Output 3

);

assign y0 = (~sel[1] & ~sel[0]) & d;

assign y1 = (~sel[1] & sel[0]) & d;

assign y2 = ( sel[1] & ~sel[0]) & d;

assign y3 = ( sel[1] & sel[0]) & d;

endmodule

module tb_demux4x1_dataflow;

reg d;

reg [1:0] sel;

wire y0, y1, y2, y3;

demux4x1_dataflow uut (

.d(d),

.sel(sel),

.y0(y0),

.y1(y1),
 .y2(y2),

.y3(y3)

);

initial begin

d = 1; sel = 2'b00; #10;

d = 1; sel = 2'b01; #10;

d = 1; sel = 2'b10; #10;

d = 1; sel = 2'b11; #10;

d = 0; sel = 2'b00; #10;

d = 0; sel = 2'b01; #10;

d = 0; sel = 2'b10; #10;

d = 0; sel = 2'b11; #10;

$finish;

end

endmodule
LAB - 6

(a) To design and simulate Verilog coding for 8x1 multiplexer using 2x1
multiplexer

module mux2x1(a,b,s,y);

input a,b,s;

output y;

assign y=s?a:b;

endmodule

module mux8x1 (

input wire [7:0] d, // 8 inputs

input wire [2:0] s, // 3 select lines

output wire y // Output

);

wire y0, y1, y2, y3, y4, y5;

mux2x1 mux0 (.a(d[0]), .b(d[1]), .s(s[0]), .y(y0));

mux2x1 mux1 (.a(d[2]), .b(d[3]), .s(s[0]), .y(y1));

mux2x1 mux2 (.a(d[4]), .b(d[5]), .s(s[0]), .y(y2));

mux2x1 mux3 (.a(d[6]), .b(d[7]), .s(s[0]), .y(y3));

mux2x1 mux4 (.a(y0), .b(y1), .s(s[1]), .y(y4));

mux2x1 mux5 (.a(y2), .b(y3), .s(s[1]), .y(y5));

mux2x1 mux6 (.a(y4), .b(y5), .s(s[2]), .y(y));

endmodule
module tb_mux8x1;

reg [7:0] d; // 8 inputs

reg [2:0] s; // 3 select lines

wire y; // Output

mux8x1 uut (

.d(d),

.s(s),

.y(y)

);

initial begin

// Display the inputs and output

$monitor("d=%b, sel=%b, y=%b", d, s, y);

d = 8'b11011011; s = 3'b000; #10;

d = 8'b11011011; s = 3'b001; #10;

d = 8'b11011011; s = 3'b010; #10;

d = 8'b11011011; s = 3'b011; #10;

d = 8'b11011011; s = 3'b100; #10;

d = 8'b11011011; s = 3'b101; #10;

d = 8'b11011011; s= 3'b110; #10;

d = 8'b11011011; s= 3'b111; #10;

$finish;

end

endmodule
(b) To design and simulate Verilog coding for 8x1 multiplexer using case/ if else
statement (behavior level)

module lab6b(

input wire [7:0] d, // 8 inputs

input wire [2:0] sel, // 3 select lines

output reg y

);

always @(*) begin

if (sel == 3'b000)

y = d[0];

else if (sel == 3'b001)

y = d[1];

else if (sel == 3'b010)

y = d[2];

else if (sel == 3'b011)

y = d[3];

else if (sel == 3'b100)

y = d[4];

else if (sel == 3'b101)

y = d[5];
 else if (sel == 3'b110)

y = d[6];

else if (sel == 3'b111)

y = d[7];

else

y = 1'b0;

end

endmodule

module tb_mux8x1_if;

reg [7:0] d;

reg [2:0] sel;

wire y;

lab6b uut (

.d(d),

.sel(sel),

.y(y)

);

initial begin

d = 8'b11010101; sel = 3'b000; #10;

d = 8'b11010101; sel = 3'b001; #10;

d = 8'b11010101; sel = 3'b010; #10;

 d = 8'b11010101; sel = 3'b011; #10;

d = 8'b11010101; sel = 3'b100; #10;

d = 8'b11010101; sel = 3'b101; #10;

d = 8'b11010101; sel = 3'b110; #10;

d = 8'b11010101; sel = 3'b111; #10;

$finish;

end

endmodule

©To design and simulate Verilog coding for 8x1 Demultiplexer:using 2x1
Demultiplexer:

module demux2x1_dataflow (

input wire d,

input wire sel,

output wire y0,

output wire y1

);

assign y0 = (~sel) & d;

assign y1 = sel & d;

endmodule

module demux8x1 (

input wire d, input

wire [2:0] sel,

output wire y0,

 output wire y1,

output wire y2,

output wire y3,

output wire y4,

output wire y5,

output wire y6,

output wire y7

);

wire w0, w1, w2, w3;

demux2x1_dataflow demux0 (

.d(d),

.sel(sel[2]),

.y0(w0),

.y1(w1)

);

demux2x1_dataflow demux1 (

.d(w0),

.sel(sel[1]),

.y0(w2),

.y1(w3)

);

demux2x1_dataflow demux2 (

.d(w1),

.sel(sel[1]),

.y0(w4),

.y1(w5)

);

demux2x1_dataflow demux3 (

.d(w2),
 .sel(sel[0]),

.y0(y0),

.y1(y1)

);

demux2x1_dataflow demux4 (

.d(w3),

.sel(sel[0]),

.y0(y2),

.y1(y3)

);

demux2x1_dataflow demux5 (

.d(w4),

.sel(sel[0]),

.y0(y4),

.y1(y5)

);

demux2x1_dataflow demux6 (

.d(w5),

.sel(sel[0]),

.y0(y6),

.y1(y7)

);

endmodule
module tb_demux8x1;

reg d;

reg [2:0] sel;

wire y0, y1, y2, y3, y4, y5, y6, y7;

demux8x1 uut (

.d(d),

.sel(sel),

.y0(y0),

.y1(y1),

.y2(y2),

.y3(y3),

.y4(y4),

.y5(y5),

.y6(y6),

.y7(y7)

);

initial begin

d = 1; sel = 3'b000; #10;

d = 1; sel = 3'b001; #10;

d = 1; sel = 3'b010; #10;

d = 1; sel = 3'b011; #10;

 d = 1; sel = 3'b100; #10;

d = 1; sel = 3'b101; #10;

d = 1; sel = 3'b110; #10;

d = 1; sel = 3'b111; #10;

$finish;

end

endmodule

(d) To design and simulate Verilog coding for 8x1 Demultiplexer using case/ if
else statement (behavior level)

module demux8x1_case (

input wire d,

input wire [2:0] sel,

output reg y0,

output reg y1,

output reg y2,

output reg y3,

 output reg y4,

output reg y5,

output reg y6,

output reg y7

);

always @(*) begin

y0 = 0;

y1 = 0;

y2 = 0;

y3 = 0;

y4 = 0;

y5 = 0;

y6 = 0;

y7 = 0;

case (sel)

3'b000: y0 = d;

3'b001: y1 = d;

3'b010: y2 = d;

3'b011: y3 = d;

3'b100: y4 = d;

3'b101: y5 = d;

3'b110: y6 = d;

3'b111: y7 = d;

default: ;

endcase

end

endmodule
module tb_demux8x1_case;

reg d;

reg [2:0] sel;

wire y0, y1, y2, y3, y4, y5, y6, y7;

demux8x1_case uut (

.d(d),

.sel(sel),

.y0(y0),

.y1(y1),

.y2(y2),

.y3(y3),

.y4(y4),

.y5(y5),

.y6(y6),

.y7(y7)

);

initial begin

d = 1;

sel = 3'b000; #10;

sel = 3'b001; #10;

sel = 3'b010; #10;

sel = 3'b011; #10;

sel = 3'b100; #10;

 sel = 3'b101; #10;

sel = 3'b110; #10;

sel = 3'b111; #10;

d = 0;

sel = 3'b000; #10;

sel = 3'b001; #10;

sel = 3'b010; #10;

sel = 3'b011; #10;

sel = 3'b100; #10;

sel = 3'b101; #10;

sel = 3'b110; #10;

sel = 3'b111; #10;

$finish; // End simulation

end

endmodule
LAB - 7

Design of 4 bit binary to gray converter & Gray to Binary Code Converter using Verilog
and simulate the design.

(A) 4 bit binary to gray converter

module binary_to_gray (

input [3:0] binary,

output [3:0] gray

);

assign gray[3] = binary[3];

assign gray[2] = binary[3] ^ binary[2];

assign gray[1] = binary[2] ^ binary[1];

assign gray[0] = binary[1] ^ binary[0];

endmodule

module binary_to_gray_tb();
 reg [3:0] binary;

wire [3:0] gray;

binary_to_gray uut(.binary(binary),.gray(gray));

always

begin

binary = 4'b0000 ; #10;

binary = 4'b0001 ; #10;

binary = 4'b0010 ; #10;

binary = 4'b0100 ; #10;

binary = 4'b1000 ; #10;

binary = 4'b1111 ; #10;

binary = 4'b1100 ; #10;

$finish;

end

Endmodule
(B)Gray to Binary Code Converter

module gray_to1_binary (

input wire [3:0] gray,

output wire [3:0] binary

);

assign binary[3] = gray[3];

assign binary[2] = binary[3] ^ gray[2];

assign binary[1] = binary[2] ^ gray[1];

assign binary[0] = binary[1] ^ gray[0];

endmodule

module gray_to_binary_tb1;

reg [3:0] gray;

wire [3:0] binary;

gray_to1_binary uut (

.gray(gray),

.binary(binary)

);
 initial begin

gray= 4'b0000; #10;

gray= 4'b0001; #10;

gray= 4'b0011; #10;

gray= 4'b0010; #10;

gray= 4'b0110; #10;

gray= 4'b0111; #10;

gray= 4'b0101; #10;

$finish;

end

endmodule