UNIT 1

8085 Processor: Detailed Notes

1. Hardware Architecture and Pinouts

Hardware Architecture Overview:

 The Intel 8085 microprocessor is an 8-bit microprocessor.

 It consists of three main sections: Arithmetic and Logic Unit (ALU), Timing and Control
Unit, and Registers.
 ALU performs arithmetic and logical operations, Timing and Control Unit manages the
timing and control signals, and Registers store data temporarily.

Pinouts:

1. Address Bus (AD0-AD7, A8-A15): These pins carry the addresses of memory locations
during the execution of an instruction or while fetching or storing data.
2. Data Bus (D0-D7): These pins carry data between the microprocessor and the memory
or I/O devices.
3. Control and Status Signals (RD, WR, IO/M, S0, S1, S2, INT, HOLD, HLDA,
RESET): These signals control the operation of the microprocessor and provide status
information.
4. Power Supply and Clock Signals (Vcc, Vss, CLK): These pins provide power and
clock signals to the microprocessor.

2. Functional Building Blocks of Processor

 Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations on data.
 Registers (Accumulator, B, C, D, E, H, L): Stores data temporarily.
 Program Counter (PC): Stores the address of the next instruction to be fetched.
 Stack Pointer (SP): Points to the top of the stack.
 Instruction Register (IR): Holds the current instruction being executed.
 Flag Register (FLAGS): Holds flags indicating status of arithmetic operations.

3. Memory Organization

 Address Space: 8085 has a 16-bit address bus, capable of addressing 64KB of memory.
 Memory Organization: Divided into two parts - 8KB for I/O and 56KB for memory
mapped devices.
 Addressing Modes: Direct, Immediate, Register, Indirect, and Implicit.

4. I/O Ports and Data Transfer Concepts

  I/O Ports: Addressed by IN and OUT instructions.
 Data Transfer: MOV, MVI instructions for data transfer.
 Timing Diagram: Shows synchronization of all operations of 8085. Uses clock pulses.

5. Timing Diagram

 Timing and Control Unit (TCU): Provides time sequencing to all operations.
 Machine Cycle: Set of operations.

6. Interrupts

 Interrupts: Initiated by external devices and program execution.

Programming of 8085 Processor: Detailed Notes

1. Instruction Format and Addressing Modes

 Instruction Format: Opcode, Operand.

 Addressing Modes: Immediate, Direct, Register, Register Indirect.

2. Assembly Language Format

 Mnemonics: Short codes.

 Data Transfer, Data Manipulation & Control Instructions: MOV, MVI, LXI, LDA,
STA, ADD, SUB, INR, DCR, etc.

3. Programming Concepts

 Loop Structure with Counting & Indexing: Using loops with counters and index
registers (BC, DE, HL).

Example:

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MVI C, 10 ; initialize counter
LOOP:
MOV A, B ; do something
INX B ; increment index
DCR C ; decrement counter
JNZ LOOP ; loop until counter is zero

 Look Up Table: Using tables for fast retrieval.

Example:

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 LDA TABLE ; load data from lookup table

 Subroutine Instructions & Stack: CALL, RET, RST for subroutines.

Example:

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CALL SUBROUTINE ; call subroutine
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SUBROUTINE:
; subroutine code
RET ; return from subroutine

4. Stack

 Stack: Implemented using the stack pointer (SP).

 Push and Pop Operations: PUSH, POP.

Conclusion

The Intel 8085 microprocessor is a versatile processor suitable for a wide range of applications,
from simple control systems to complex data processing tasks. Understanding its hardware
architecture, instruction set, and programming concepts allows developers to leverage its
capabilities effectively.

UNIT 2

8086 Architecture:

1. 8086 Architecture

Functional Diagram:

 The 8086 microprocessor is a 16-bit microprocessor.

 It consists of the following functional units:
o Bus Interface Unit (BIU): Controls the flow of data and addresses between the
processor and memory.
o Execution Unit (EU): Executes instructions fetched by the BIU and performs
arithmetic and logic operations.
o Registers: AX, BX, CX, DX, SI, DI, BP, SP, IP, CS, DS, SS, ES, FLAGS.
o Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations.
Register Organization:

 Data Registers (AX, BX, CX, DX): Used for general data operations.
 Pointer Registers (SP, BP, SI, DI): Used for addressing.
 Index Registers (SI, DI): Used for indexed addressing.
 Segment Registers (CS, DS, SS, ES): Point to different segments of memory.
 Status and Control Registers (IP, FLAGS): IP holds the address of the next instruction,
FLAGS holds status flags.

Memory Segmentation:

 Segmentation: Memory is divided into segments, each 64KB in size.

 Segment Registers (CS, DS, SS, ES): Combined with an offset to form a physical
address.

Programming Model:

 Data Registers: AX, BX, CX, DX (general data).

 Pointer and Index Registers: SP, BP, SI, DI (addressing).
 Segment Registers: CS, DS, SS, ES (segmentation).
 IP (Instruction Pointer): Points to the next instruction to be executed.
 FLAGS: Status flags (carry, zero, sign, overflow, etc.).

Memory Addresses:

 Logical Address: Generated by combining a segment register with an offset.

 Physical Address: Result of converting a logical address via segmentation.

Physical Memory Organization:

 Physical Address Space: 1MB (20-bit address bus).

 Memory Organization: Divided into segments of 64KB.
 Real Mode: Uses 20-bit addressing (1MB).
 Protected Mode: Supports up to 4GB of addressable memory.

Architecture of 8086:

 Bus Interface Unit (BIU): Manages data and addresses between the processor and
memory.
 Execution Unit (EU): Executes instructions fetched by the BIU.
 Registers: AX, BX, CX, DX, SI, DI, BP, SP, IP, CS, DS, SS, ES, FLAGS.
 Arithmetic and Logic Unit (ALU): Performs arithmetic and logical operations.
 Control and Timing Signals: Responsible for synchronization and control.

Signal Descriptions of 8086:

  CLK: Clock input.
 MN/MX: Minimum/Maximum mode selection.
 RD, WR: Read/Write signals.
 ALE: Address latch enable.
 HOLD, HLDA: Hold and Hold Acknowledge.
 INTA: Interrupt acknowledge.
 RESET: Resets the microprocessor.

Interrupts of 8086:

 Interrupts: Initiated by internal and external devices.

 Types: Hardware (INT) and Software (INT n, INTO, INT 3).

Instruction Set and Assembly Language Programming of 8086: Detailed Notes

1. Instruction Formats

 Instruction Formats:
o One-byte Instructions: MOV, ADD, SUB, etc.
o Two-byte Instructions: JMP, CALL, etc.
o Three-byte Instructions: MOVS, CMPS, etc.

2. Addressing Modes

 Addressing Modes:
o Immediate: MOV AX, 1234h.
o Direct: MOV AX, [1234h].
o Register: MOV AX, BX.
o Indexed: MOV AX, [BX+SI].
o Based: MOV AX, [BX+1234h].
o Stack: PUSH AX, POP AX.

3. Instruction Set

 Data Transfer: MOV, XCHG, PUSH, POP.

 Arithmetic: ADD, SUB, INC, DEC.
 Logical: AND, OR, XOR, NOT.
 Control Transfer: JMP, JZ, JNZ, CALL, RET.
 String Instructions: MOVS, CMPS, SCAS, LODS, STOS.
 Flag Control: CLC, STC, CLI, STI.

4. Assembler Directives

 Directives:
o DB, DW, DD: Define Byte, Word, Double Word.
o SEGMENT, ENDS: Define segment.
 o ASSUME: Assign segment registers.

5. Macros

 Macros: Reusable code sequences defined using MACRO and ENDM.

6. Simple Programs

 Logical Instructions: AND, OR, XOR.

 Branch Instructions: JMP, JZ, JNZ.
 Call Instructions: CALL, RET.
 Sorting: Bubble sort, selection sort.
 String Manipulations: Copy, compare, search

UNIT III

Overview of 8051 Microcontroller

Overview:

 The 8051 microcontroller is an 8-bit microcontroller.

 Developed by Intel, it became widely popular and has been manufactured by several
companies.
 It includes CPU, RAM, ROM, I/O ports, timers, and serial communication ports on a
single chip.
 It's used in embedded systems, industrial applications, and consumer electronics.

Architecture of 8051 Microcontroller

Architecture:

 CPU: 8-bit ALU, 8-bit accumulator (Acc).

 Registers: B (B register), R0 to R7 (General-purpose registers).
 Timers/Counters: Two 16-bit timers/counters (T0 and T1).
 Interrupts: External, timer, and serial communication interrupts.
 I/O Ports: 4 I/O ports (P0 to P3).
 Serial Communication: UART for serial communication.
 Memory: ROM, RAM, and Special Function Registers (SFRs).
 Clock: Requires an external crystal oscillator for operation.

I/O Ports of 8051 Microcontroller

I/O Ports:

 P0, P1, P2, P3: 8-bit bidirectional ports.

  Port Modes: Input, Output, and Open-drain.
 Port Pins: Can be individually configured.
 Special Function Registers (SFRs): Control and monitor port operations.

Memory Organization of 8051 Microcontroller

Memory Organization:

 Program Memory (ROM): Stores the program code.

 Data Memory (RAM): Stores data and variables.
 Special Function Registers (SFRs): Control and status registers.

Addressing Modes of 8051 Microcontroller

Addressing Modes:

 Immediate: MOV A, #data.

 Direct: MOV A, address.
 Register: MOV A, R0.
 Indirect: MOV A, @R0.
 Relative: JMP label.

Instruction Set of 8051 Microcontroller

Instruction Set:

 Data Transfer: MOV, XCH, PUSH, POP.

 Arithmetic: ADD, SUB, INC, DEC.
 Logical: ANL, ORL, XRL.
 Branching: JMP, JZ, JNZ, JC, JNC.
 Bit Manipulation: SETB, CLR, CPL.
 Timer/Counter Control: TL0, TH0, TL1, TH1.
 Serial Communication: MOV, SETB, CLR.

8051 Real-Time Control: Detailed Notes

Programming Timer Interrupts

Timer Interrupts:

 Timer Registers: TH0, TL0, TH1, TL1.

 Timer Modes: Mode 0 (13-bit timer), Mode 1 (16-bit timer), Mode 2 (8-bit auto-reload
timer).
 Programming Steps:
1. Initialize timer mode and reload value.
2. Enable timer interrupt.
 3. Implement ISR to handle timer overflow.

Programming External Hardware Interrupts

External Interrupts:

 Interrupt Source: External hardware interrupt pin (INT0, INT1).

 Programming Steps:
1. Configure interrupt pin as input.
2. Enable external interrupt.
3. Implement ISR to handle the interrupt.

Programming the Serial Communication Interrupts

Serial Communication Interrupts:

 Interrupt Source: Receive (RI) and Transmit (TI) interrupt flags.

 Programming Steps:
1. Initialize serial communication.
2. Enable serial interrupts (RI, TI).
3. Implement ISR to handle receive and/or transmit operations.

Programming 8051 Timers and Counters

Timers and Counters:

 Timers: T0, T1 (16-bit timers).

 Counters: T0, T1 (external count input).
 Programming Steps:
1. Configure timer mode (mode 0, 1, or 2).
2. Set initial value and reload value.
3. Start the timer.
4. Implement ISR to handle timer overflow or external count events.

UNIT IV

/O and Memory Interface: Detailed Notes

1. 8251 - USART (Universal Synchronous/Asynchronous Receiver/Transmitter)

Overview:

 Function: Provides serial communication capability (RS232).

 Modes: Synchronous and Asynchronous.
  Registers: Data register, control register, status register.
 Operations: Transmitting and receiving serial data.
 Programming: Set control registers, handle interrupts.

2. 8257 - Direct Memory Access (DMA) Controller

Overview:

 Function: Transfers data between memory and I/O devices without CPU intervention.
 Channels: Multiple DMA channels (usually 4).
 Registers: Control and status registers for each channel.
 Programming: Initialize DMA channels, transfer data.

3. 8259 - Programmable Interrupt Controller (PIC)

Overview:

 Function: Manages and prioritizes interrupts.

 Modes: Cascade mode for handling more than 8 interrupts.
 Registers: Initialization and interrupt request registers.
 Programming: Set interrupt masks, handle interrupts.

4. LCD - Liquid Crystal Display

Overview:

 Function: Displays alphanumeric characters and symbols.

 Interfacing: Uses control lines and data lines.
 Commands: Clear display, move cursor, write character.
 Programming: Send commands and data to display.

5. 8279 - Keyboard Display Interface

Overview:

 Function: Interfaces keyboards and displays.

 Modes: Scanning and debounce for keyboards.
 Registers: Status, control, and data registers.
 Programming: Scan keyboard, display data on LED display.

6. External Memory (RAM, ROM) Interface

Overview:

 Function: Expands 8051 memory using external RAM and ROM.

 Modes: Address and data bus interfacing.
  Memory Selection: Chip select signals.
 Programming: Access data and program stored in external memory.

7. ADC (Analog-to-Digital Converter) Interface to 8051

Overview:

 Function: Converts analog signals to digital data.

 Types: Single channel, multi-channel.
 Registers: Control and data registers.
 Programming: Start conversion, read digital data.

8. DAC (Digital-to-Analog Converter) Interface to 8051

Overview:

 Function: Converts digital data to analog signals.

 Types: Voltage output, current output.
 Registers: Data registers, control registers.
 Programming: Write digital data, output analog signal.

Serial Communication and Bus Interface: Detailed Notes

1. Serial Communication Standards

Standards:

 RS232: Older standard, asynchronous communication.

 RS485: Differential standard, used for long-distance communication.
 UART: Universal Asynchronous Receiver/Transmitter.

2. Serial Data Transfer Scheme

Scheme:

 Asynchronous: Start bit, data bits, stop bit.

 Synchronous: Clock signal, data bits.
 Baud Rate: Speed of data transfer.

3. On-Board Communication Interfaces

a. I2C Bus (Inter-Integrated Circuit)

 Function: Multi-master, multi-slave serial bus.

 Signals: SDA (Data), SCL (Clock).
 Addressing: 7-bit or 10-bit addressing.
b. SPI Bus (Serial Peripheral Interface)

 Function: Master-slave, full-duplex synchronous serial communication.

 Signals: MISO (Master In Slave Out), MOSI (Master Out Slave In), SCK (Clock), SS
(Slave Select).
 Modes: 0, 1, 2, 3 (different clock polarities and phases).

c. UART (Universal Asynchronous Receiver/Transmitter)

 Function: Asynchronous serial communication.

 Signals: TXD (Transmit Data), RXD (Receive Data).
 Baud Rate: Configurable baud rates.

4. External Communication Interfaces

a. RS232

 Function: Standard for serial communication.

 Signals: TXD, RXD, RTS, CTS, DTR, DSR, DCD.
 Voltage Levels: +/- 12V for communication.

b. USB (Universal Serial Bus)

 Function: High-speed serial communication.

 Types: USB 1.1, USB 2.0, USB 3.0, USB 3.1.
 Protocols: Device classes (HID, Mass Storage, etc.).

UNIT V

ARM Architecture: Detailed Notes

ARM Processor Fundamentals

Overview:

 ARM (Advanced RISC Machine) is a family of RISC (Reduced Instruction Set

Computer) architectures.
 ARM processors are widely used in embedded systems, smartphones, and tablets due to
their power efficiency and performance.
 Versions: ARMv7, ARMv8 (64-bit), and newer versions.

Architecture:
  RISC Design: Simple instructions, uniform instruction length (32-bit), and pipelined
execution.
 Instruction Set: Thumb (16-bit) and ARM (32-bit) instruction sets.

Components:

 Processor Core: Arithmetic Logic Unit (ALU), Registers, Control Unit.

 Memory: RAM, ROM, Flash Memory.
 Peripherals: Timers, GPIO, UART, SPI, I2C.
 System Bus: AMBA (Advanced Microcontroller Bus Architecture).

ARM Architecture - Registers, CPSR, Pipeline

Registers:

 General Purpose Registers: R0-R15 (R0-R7 are also banked).

 Special Registers: CPSR (Current Program Status Register), SPSR (Saved Program
Status Register).
 Mode Registers: FIQ, IRQ, Supervisor, Abort, Undefined.

CPSR (Current Program Status Register):

 Flags: Negative, Zero, Carry, Overflow.

 Modes: User, FIQ, IRQ, Supervisor, Abort, Undefined.
 Control: Thumb state, Interrupts enabled/disabled, Condition code flags.

Pipeline:

 Three-Stage Pipeline: Fetch, Decode, Execute.

 Fetch: Instruction fetched from memory.
 Decode: Decoding the fetched instruction.
 Execute: Executing the instruction.

Exceptions and Interrupts, Interrupt Vector Table

Exceptions and Interrupts:

 Types: Reset, Undefined Instruction, Software Interrupt, Prefetch Abort, Data Abort,
IRQ, FIQ.
 Handling: Mode switching, saving context (registers), jumping to handler.

Interrupt Vector Table:

 Location: Fixed location in memory (0x00000000 or 0xFFFF0000).

 Structure: Entry for each interrupt/exception.
 Contents: Address of interrupt handler routine.
ARM Instruction Set - Data Processing, Branch Instructions, Load-Store Instructions

Data Processing Instructions:

 ALU Operations: ADD, SUB, AND, ORR, EOR.

 Shift and Rotate: LSL, LSR, ASR, ROR.
 Comparison: CMP, CMN.
 Conditional Execution: Conditional suffixes (EQ, NE, GE, LT, etc.).

Branch Instructions:

 Unconditional Branch: B, BL.

 Conditional Branch: BEQ, BNE, BGT, BLE, etc.
 Link/Branch with Link: BL, BX.

Load-Store Instructions:

 Load: LDR (Load Register), LDM (Load Multiple).

 Store: STR (Store Register), STM (Store Multiple).
 Byte and Half-word Access: LDRB, LDRH, STRB, STRH.

Software Interrupt Instructions:

 SWI (Software Interrupt): Generate a software interrupt (system call).

Program Status Register (PSR) Instructions:

 CPS (Change Program Status): Change mode or interrupt flags.

 MRS (Move to Register from PSR): Read CPSR or SPSR.
 MSR (Move to PSR from Register): Write CPSR or SPSR.

Loading Constants:

 LDR with Immediate Value: LDR Rd, =constant.

 PC-relative Load: LDR Rd, [PC, #offset].

Conditional Execution:

 Suffixes: EQ (equal), NE (not equal), GE (greater or equal), LT (less than), etc.

 Example: ADDNE R0, R1, R2 ; Add R1 and R2 only if not equal.

Introduction to Thumb Instructions

Thumb Instructions:

 Overview: 16-bit instruction set for code density and power efficiency.
  Compatibility: Thumb instructions are a subset of ARM instructions.
 Advantages: Reduced code size, faster execution on processors with limited memory
bandwidth.
 Thumb-2: Combines Thumb and ARM instructions for enhanced performance.

Diagram:

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+----------------------------------+
| ARM Instruction Set |
| |
| 32-bit instructions |
+----------------------------------+
| Thumb Instruction Set |
| |
| 16-bit instructions |
+----------------------------------+

Advanced ARM Processors: Detailed Notes

Introduction to Cortex Processor and its Architecture

Overview:

 Cortex: Series of ARM processor cores designed for a range of applications.

 Cortex-A (Application Processors): High-performance for smartphones, tablets.
 Cortex-R (Real-time Processors): Real-time applications like automotive, industrial
control.
 Cortex-M (Microcontroller Processors): Low-power, embedded systems.

Architecture:

 Pipeline: In-order, pipelined execution.

 Caches: L1 and optionally L2 caches for performance.
 NEON SIMD (Single Instruction, Multiple Data): Advanced SIMD for multimedia
and signal processing.

OMAP Processor and its Architecture

Overview:

 OMAP (Open Multimedia Applications Platform): Family of ARM-based processors

developed by Texas Instruments.
 Applications: Used in mobile phones, tablets, and other multimedia devices.
 Architecture: Integrates ARM CPU cores with multimedia accelerators and peripherals.

Key Features:
  ARM Cortex-A8 Core: High-performance ARM core.
 PowerVR GPU: Graphics processing unit for multimedia applications.
 Peripherals: Camera interface, USB, audio, and video codecs.
 Memory Interfaces: DDR RAM, NAND Flash.

Diagram:

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+-----------------------------------------------------------+
| OMAP Processor |
+-----------------------------------------------------------+
| ARM Cortex-A8 Core | PowerVR GPU | Multimedia Peripherals |
| | | (Camera, USB, Audio, |
| | | Video Codecs) |
| | | |
+-----------------------------------------------------------+

Conclusion

Understanding ARM architecture and its various processor families is crucial for designing
efficient and optimized embedded systems and applications. The ARM instruction set, along
with its modes, registers, and pipeline, provides developers with powerful tools to create
versatile and high-performance solutions. Cortex and OMAP processors extend these capabilities
further with enhanced features and peripherals, catering to a wide range of applications from
mobile devices to real-time embedded systems. Mastering these concepts and architectures
enables developers to harness the full potential of ARM-based processors for their applications.