Indian Institute of Technology (IIT-Bombay)
AUTUMN Semester, 2024
COMPUTER SCIENCE AND ENGINEERING
CS231: Digital Logic Design + Computer Architecture Lab
Lab 2
Full Marks: 100
Time allowed: (3 + ϵ) hours
Students who do not follow the naming convention will be awarded no marks.
1. In this assignment, you need to create a Ripple-Carry-Adder (RCA) following the instructions given
below:
1. First create a module called half adder. You are only allowed to use basic gates and assign state-
ments.
Module name = ”half adder”
input a, b : the numbers to be added
output S, cout : S is the sum and cout is the carry bit.
2. Next, create a module called full adder by instantiating the half adder module and maybe a few
basic gates. Once again, you are only allowed to use basic gates and assign statements.
Module name = ”full adder”
input a, b : the numbers to be added
input cin : the input carry bit
output S, cout : S is the sum and cout is the output carry bit.
3. Create your RCA using your full adder module. The length of the adder will be decided by a
parameter N , which you need to define. Also, you need to use generate statement to construct
your adder. An example of how to do parameterized design and use generate statements is given
in Figure. 1. The module name should be rca Nbit.
4. Write a proper testbench tb rca 32bit.v and test the 32-bit version of your adder.
2. This question asks you to create a Carry-Lookahead-Adder (CLA). The goal is to design a 4-bit CLA
and use that to generate a 16-bit CLA adder in a hierarchical manner.
1. First design the 4-bit CLA module named CLA 4bit. Clearly specify the logic equation of
the lookahead carry signals (C1 , C2 , C3 , C4 ) in terms of generate (G0 , G1 , G2 , G3 ) and propagate
(P0 , P1 , P2 , P3 signals.
2. Now, use these 4-bit CLAs to generate a 16-bit CLA (module name : CLA 16bit). Note that you
are not supposed to cascade the blocks as discussed in the class. Instead, we follow a
different design style. Here, you need to generate the carry-in for each 4-bit CLA block using a
lookahead carry unit (a module named lookahead carry unit 16 bit). For that, first modify your
4-bit CLA module to generate block propagate and block generate signals (P, G) (module name :
CLA 4bit P G). The equations for block propagate and generate signals are as follows:
P = P0 P1 P2 P3 , G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0
Figure 1: Example of Parameterized Modules and Generate Statements
. Observe that, we can also write C4 = G + P C0 . This is supposed to be an output of your
lookahead carry unit. Similarly, we can calculate C8 and C1 2, and finally, the C1 6, all from block
propagate and block generate signals for each 4-bit CLA. A diagram is given in Figure 2:
3. Finally, design a 32-bit CLA (module name : CLA 32bit) by extending the above mentioned philos-
ophy. You will need to create a module for 32 bit lookahead carry called lookahead carry unit 32 bit
Maintain the naming convention of the modules.
3. In this question, you are asked to design a combinational multiplier (of 16 bit numbers) using Karatsuba’s
algorithm. Follow the Wikipedia document provided to understand the algorithm.
1. Your design has to be fully hierarchical and structural, i.e., you cannot use anything more than
module instantiation and assign statements.
2. You cannot use any multiplier or adder/subtractor unless it is structurally designed.
3. If you need to use any multiplier (designed by you structurally), it should only be multiplying
numbers whose bit-width is a power of 2. No marks will be given if you are using anything else.
4. Submit the design module and testbench in separate files. Strictly follow the naming convention.
5. Module name : karatsuba 16, input parameters X[15:0], Y[15:0] and output Z[31:0] = X×Y
Figure 2: 16-bit hierarchical CLA
Figure 3: Submission Format
