Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

LM5134 Single 7.6-A Peak Current Low-Side Gate Driver With a PILOT Output
1 Features 3 Description
1• 7.6-A and 4.5-A Peak Sink and Source Drive The LM5134 is a high-speed single low-side driver
Current for Main Output capable of sinking and sourcing 7.6-A and 4.5-A peak
currents. The LM5134 has inverting and noninverting
• 820-mA and 660-mA Peak Sink and Source inputs that give the user greater flexibility in
Current for PILOT Output controlling the FET. The LM5134 features one main
• 4-V to 12.6-V Single-Power Supply output, OUT, and an extra gate drive output, PILOT.
• Matching Delay Time Between Inverting and Non- The PILOT pin logic is complementary to the OUT
Inverting Inputs pin, and can be used to drive a small MOSFET
located close to the main power FET. This
• TTL/CMOS Logic Inputs configuration minimizes the turnoff loop and reduces
• Up to 14-V Logic Inputs (Regardless of VDD the consequent parasitic inductance. It is particularly
Voltage) useful for driving high-speed FETs or multiple FETs
• –40°C to 125°C Junction Temperature Range in parallel. The LM5134 is available in the 6-pin
SOT-23 package and the 6-pin WSON package with
an exposed pad to aid thermal dissipation.
2 Applications
• Motor Drivers Device Information(1)
• Solid-State Power Controllers PART NUMBER PACKAGE BODY SIZE (NOM)
• Power Factor Correction Converters SOT-23 (6) 2.90 mm × 1.60 mm
LM5134
WSON (6) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Noninverting Input Inverting Input

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 12
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 8 Application and Implementation ........................ 14
4 Revision History..................................................... 2 8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 3 9 Power Supply Recommendations...................... 17
6.1 Absolute Maximum Ratings ...................................... 3 10 Layout................................................................... 18
6.2 ESD Ratings.............................................................. 3 10.1 Layout Guidelines ................................................. 18
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 18
6.4 Thermal Information .................................................. 4 10.3 Power Dissipation ................................................. 19
6.5 Electrical Characteristics .......................................... 4 11 Device and Documentation Support ................. 20
6.6 Switching Characteristics .......................................... 6 11.1 Community Resources.......................................... 20
6.7 Typical Characteristics .............................................. 8 11.2 Trademarks ........................................................... 20
7 Detailed Description ............................................ 12 11.3 Electrostatic Discharge Caution ............................ 20
7.1 Overview ................................................................. 12 11.4 Glossary ................................................................ 20
7.2 Functional Block Diagram ....................................... 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 18

2 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

5 Pin Configuration and Functions

DBV Package, NGG Package

6-Pin SOT-23, 6-Pin WSON
Top View

VDD 1 6 IN

PILOT 2 5 INB

OUT 3 4 VSS

Pin Functions
PIN
I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
Locally decouple to VSS using low ESR/ESL capacitor located as
VDD 1 — Gate drive supply
close as possible to the IC.
Gate drive output for an external Connect to the gate of a small turnoff MOSFET with a short, low
PILOT 2 O
turnoff FET inductance path. The turnoff FET provides a local turnoff path.
Connect to the gate of the power FET with a short, low inductance
Gate drive output for the power
OUT 3 O path. A gate resistor can be used to eliminate potential gate
FET
oscillations.
VSS 4 — Ground All signals are referenced to this ground.
INB 5 I Inverting logic input Connect to VSS when not used.
IN 6 I Non-inverting logic input Connect to VDD when not used.
It is recommended that the exposed pad on the bottom of the
package be soldered to ground plane on the PC board, and that
EP EP — Exposed Pad
ground plane extend out from beneath the IC to help dissipate
heat.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD to VSS −0.3 14
Pin voltage V
IN, INB to VSS −0.3 14
Junction temperature, TJ 150 °C
Storage temperature, Tstg −55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Gate drive supply, VDD 4 12.6 V
Operating junction temperature –40 125 °C

6.4 Thermal Information

LM5134
THERMAL METRIC (1) DBV (SOT-23) NGG (WSON) UNIT
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 105.9 51 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.1 47 °C/W
RθJB Junction-to-board thermal resistance 21 25.3 °C/W
ψJT Junction-to-top characterization parameter 1.2 0.6 °C/W
ψJB Junction-to-board characterization parameter 20.5 24.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 5.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

TJ = 25°C, VDD = 12 V, unless otherwise specified. Minimum and Maximum limits are ensured through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only. (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD VDD operating voltage TJ = –40°C to +125°C 4 12.6 V
TJ = 25°C 3.6
UVLO VDD undervoltage lockout VDD rising V
TJ = –40°C to +125°C 3.25 4
VDD undervoltage lockout
0.36 V
hysteresis
VDD undervoltage lockout
VDD rising 500 ns
to main output delay time
TJ = 25°C 0.8
IDD VDD quiescent current IN = INB = VDD mA
TJ = –40°C to +125°C 2
OUTPUT
VDD = 10 V, IOUT = TJ = 25°C 0.15
Ω
–100 mA TJ = –40°C to +125°C 0.45
RON-DW Main output resistance –
(SOT23-6) pulling down TJ = 25°C 0.2
VDD = 4.5 V, IOUT =
Ω
–100 mA TJ = –40°C to +125°C 0.5
VDD = 10 V, IOUT = TJ = 25°C 0.2
Ω
–100 mA TJ = –40°C to +125°C 0.5
RON-DW Main output resistance –
(WSON) pulling down TJ = 25°C 0.25
VDD = 4.5 V, IOUT =
Ω
–100 mA TJ = –40°C to +125°C 0.55
Power-off pulldown
VDD = 0 V, IOUT = –10 mA 1.5 10 Ω
resistance
Power-off pulldown clamp
VDD = 0 V, IOUT = –10 mA 0.7 1 V
voltage
Peak sink current CL = 10,000 pF 7.6 A

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
4 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

Electrical Characteristics (continued)

TJ = 25°C, VDD = 12 V, unless otherwise specified. Minimum and Maximum limits are ensured through test, design, or
statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference
purposes only.(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 10 V, TJ = 25°C 0.7
Ω
RON-UP Main output resistance - IOUT = 50 mA TJ = –40°C to +125°C 1.3
(SOT23-6) pulling up VDD = 4.5 V, TJ = 25°C 1
Ω
IOUT = 50 mA TJ = –40°C to +125°C 1.9
VDD = 10 V, TJ = 25°C 0.75
Ω
RON-UP Main output resistance - IOUT = 50 mA TJ = –40°C to +125°C 1.2
(WSON) pulling up VDD = 4.5 V, TJ = 25°C 1.14
Ω
IOUT = 50 mA TJ = –40°C to +125°C 1.85
Peak source current CL = 10,000 pF 4.5 A
PILOT
VDD = 10 V, TJ = 25°C 3.7
Ω
PILOT output resistance – IOUT = –100 mA TJ = –40°C to +125°C 9
RONP-DW
pulling down VDD = 4.5 V, TJ = 25°C 4.7
Ω
IOUT = –100 mA TJ = –40°C to +125°C 12
Peak sink current CL = 330 pF 820 mA
VDD = 10 V, TJ = 25°C 6
Ω
PILOT output resistance – IOUT = 50 mA TJ = –40°C to +125°C 11
RONP-UP
pulling up VDD = 4.5 V, TJ = 25°C 10.7
Ω
IOUT = 50 mA TJ = –40°C to +125°C 20
Peak source current CL = 330 pF 660 mA
LOGIC INPUT
LM5134A, TJ = –40°C to +125°C 0.67 × VDD
VIH Logic 1 input voltage V
LM5134B, TJ = –40°C to +125°C 2.4
LM5134A, TJ = –40°C to +125°C 0.33 × VDD
VIL Logic 0 input voltage V
LM5134B, TJ = –40°C to +125°C 0.8
LM5134A 0.9
VHYS Logic-input hysteresis V
LM5134B 0.68
TJ = 25°C 0.001
Logic-input current INB = VDD or 0 µA
TJ = –40°C to +125°C 10
THERMAL RESISTANCE
SOT23-6 90 °C/W
θJA Junction to ambient
WSON-6 60 °C/W

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FOR VDD = +10 V
CL = 1000 pF 3
tR OUT rise time CL = 5000 pF 10 ns
CL = 10,000 pF 20
CL = 1000 pF 2
tF OUT fall time CL = 5000 pF 4.7 ns
CL = 10,000 pF 7.2
TJ = 25°C 17
OUT turnon propagation
tD-ON CL = 1000 pF TJ = –40°C to ns
delay 40
+125°C
TJ = 25°C 12
OUT turnoff propagation
tD-OFF CL = 1000 pF TJ = –40°C to ns
delay 25
+125°C
Main output break-before-
2.5 ns
make time
tPR PILOT rise time CL = 330 pF 5.3 ns
tPF PILOT fall time CL = 330 pF 3.9 ns
OUT turnoff to PILOT turnon
tPD-ON CL = 330 pF 4.2 ns
propagation delay
PILOT turnoff to OUT turnon
tPD-OFF CL = 330 pF 6.4 ns
propagation delay
FOR VDD = +4.5 V
CL = 1000 pF 5
tR Rise time CL = 5000 pF 14 ns
CL = 10,000 pF 24
CL = 1000 pF 2.3
tF Fall time CL = 5000 pF 5.4 ns
CL = 10,00 0pF 7.2
TJ = 25°C 26
OUT turnon propagation
tD-ON CL = 1000 pF TJ = –40°C to ns
delay 50
+125°C
TJ = 25°C 20
OUT turnoff propagation
tD-OFF CL = 1000 pF TJ = –40°C to ns
delay 45
+125°C
Main output break-before-
4.2 ns
make time
tPR PILOT rise time CL = 330 pF 9.6 ns
tPf PILOT fall time CL = 330 pF 3.7 ns
OUT turnoff to PILOT turnon
tPD-ON CL = 330 pF 7.5 ns
propagation delay
PILOT turnoff to OUT turnon
tPD-OFF CL = 330 pF 11.8 ns
propagation delay

6 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

50% 50%

IN

tD-ON tD-OFF

90%

OUT
10%

tR tF

tPD-OFF tPD-ON

PILOT 90%

10%

tPF tPR

Figure 1. Timing Diagram — Noninverting Input

INB

50% 50%

tD-ON tD-OFF

90%

OUT
10%

tR tF

tPD-OFF tPD-ON

PILOT 90%

10%

tPF tPR

Figure 2. Timing Diagram — Inverting Input

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

6.7 Typical Characteristics

Figure 3. OUT Source Current vs OUT Voltage Figure 4. OUT Sink Current vs OUT Voltage

Figure 5. OUT Peak Source Current vs VDD Voltage Figure 6. OUT Peak Sink Current vs VDD Voltage

Figure 7. PILOT Source Current vs PILOT Voltage Figure 8. PILOT Sink Current vs PILOT Voltage

8 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

Typical Characteristics (continued)

Figure 9. PILOT Peak Source Current vs VDD Voltage Figure 10. PILOT Peak Sink Current vs VDD Voltage

Figure 11. OUT Turnon Propagation Delay vs VDD Figure 12. OUT Turnoff Propagation Delay vs VDD

Figure 13. OUT Turnoff to PILOT Turnon Propagation Delay Figure 14. PILOT Turnoff to OUT Turnon Propagation Delay
vs VDD vs VDD

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

Typical Characteristics (continued)

Figure 15. Supply Current vs OUT Capacitive Load Figure 16. Supply Current vs PILOT Capacitive Load

Figure 17. Supply Current vs Frequency Figure 18. Quiescent Current vs Temperature

Figure 19. LM5134A Input Threshold vs Temperature Figure 20. LM5134A Input Threshold vs Temperature

10 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

Typical Characteristics (continued)

Figure 21. LM5134B Input Threshold vs Temperature Figure 22. LM5134B Input Threshold vs Temperature

Figure 23. UVLO Threshold vs Temperature

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

7 Detailed Description

7.1 Overview
The LM5134 is a single low-side gate driver with one main output, OUT, and a complementary output PILOT.
The OUT pin has high 7.6-A and 4.5-A peak sink and source current and can be used to drive large power
MOSFETs or multiple MOSFETs in parallel. The PILOT pin has 820-mA and 660-mA peak sink and source
current, and is intended to drive an external turnoff MOSFET, as shown in Functional Block Diagram. The
external turnoff FET can be placed close to the power MOSFETs to minimize the loop inductance, and therefore
helps eliminate stray inductance induced oscillations or undesired turnon. This feature also provides the flexibility
to adjust turnon and turnoff speed independently.

7.2 Functional Block Diagram

VDD

UVLO

IN OUT
DRIVER

INB
VSS
PILOT

VSS

7.3 Feature Description

When using the external turnoff switch, it is important to prevent the potential shoot-through between the external
turnoff switch and the LM5134 internal pullup switch. The propagation delay, TPD-ON and TPD-OFF, has been
implemented in the LM5134 between the PILOT and the OUT pins, as depicted in the timing diagram. The turnon
delay TPD-ON is designed to be shorter than the turnoff delay TPD-OFF because the rising time of the external
turnoff switch can attribute to the additional delay time. It is also desirable to minimize TPD-ON to favor the fast
turnoff of the power MOSFET.
The LM5134 offers both inverting and noninverting inputs to satisfy requirements for inverting and non-inverting
gate drive signals in a single device type. Inputs of the LM5134 are TTL and CMOS Logic compatible and can
withstand input voltages up to 14 V regardless of the VDD voltage. This allows inputs of the LM5134 to be
connected directly to most PWM controllers.
The LM5134 includes an Undervoltage Lockout (UVLO) circuit. When the VDD voltage is below the UVLO
threshold voltage, the IN and INB inputs are ignored, and if there is sufficient VDD voltage, the OUT is pulled
low. In addition, the LM5134 has an internal PNP transistor in parallel with the output NMOS. Under the UVLO
condition, the PNP transistor will be on and clamp the OUT voltage below 1 V. This feature ensures the OUT
remains low even with insufficient VDD voltage.

7.4 Device Functional Modes

Table 1 lists the logic options for the device and Table 2 lists the device truth table.

12 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

Table 1. Input/Output Options

BASE PART NUMBER LOGIC INPUT
LM5134A CMOS
LM5134B TTL

Table 2. Truth Table

IN INB OUT PILOT
L L L H
L H L H
H L H L
H H L H

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

High-current gate-driver devices are required in switching power applications for a variety of reasons. To affect
fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power-semiconductor devices. Further,
gate drivers are indispensable when there are times that the PWM controller cannot directly drive the gates of
the switching devices. With advent of digital power, this situation is often encountered because the PWM signal
from the digital controller is often a 3.3-V logic signal, which is not capable of effectively turning on a power
switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to
fully turn on the power device and minimize conduction losses. Because traditional buffer-drive circuits based on
NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, lack level-shifting
capability, the circuits prove inadequate with digital power.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers can also perform
other tasks, such as minimizing the effect of high-frequency switching noise by locating the high-current driver
physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates,
and reducing power dissipation and thermal stress in controllers by moving gate-charge power losses into itself.
Finally, emerging wide-bandgap power-device technologies, such as GaN based switches capable of supporting
very high switching frequency operation, are driving special requirements in terms of gate-drive capability. These
requirements include operation at low VDD voltages (5 V or lower), low propagation delays, and availability in
compact, low-inductance packages with good thermal capability. In summary, gate-driver devices are extremely
important components in switching power combining benefits of high-performance, low cost, component count
and board space reduction with a simplified system design.

8.2 Typical Application

Figure 24. Application Schematic

14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

Typical Application (continued)

8.2.1 Design Requirements
When selecting the proper gate driver device for an end application, some design considerations must first be
evaluated to make the most appropriate selection. Among these considerations are input-to-output configuration,
the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independent
enable and disable functions, propagation delay, power dissipation, and package type.

Table 3. Design Parameters

PARAMETER EXAMPLE VALUE
Input-to-output logic Noninverting
Input threshold type Logic level
VDD bias supply voltage 10 V (minimum), 113 V (nominal), 15 V (peak)
Peak source and sink currents Minimum 1.65-A source, minimum 1.65-A sink
Enable and disable function Yes, required
Propagation delay Maximum 40 ns or less

8.2.2 Detailed Design Procedure

8.2.2.1 Input-to-Output Logic

The design should specify which type of input-to-output configuration should be used. If turning on the power
MOSFET when the input signal is in high state is preferred, then the noninverting configuration must be selected.
If turning off the power MOSFET when the input signal is in high state is preferred, the inverting configuration
must be chosen. The LM5134 device can be configured in either an inverting or noninverting input-to-output
configuration, using the IN– or IN+ pins, respectively. To configure the device for use in inverting mode, tie the
IN+ pin to VDD and apply the input signal to the IN– pin. For the noninverting configuration, tie the IN– pin to
GND and apply the input signal to the IN+ pin.

8.2.2.2 Input Threshold Type

The type of controller used determines the input voltage threshold of the gate driver device. The LM5134B device
features a TTL and CMOS-compatible input threshold logic, with wide hysteresis. The threshold voltage levels
are low voltage and independent of the VDD supply voltage, which allows compatibility with both logic-level input
signals from microcontrollers, as well as higher-voltage input signals from analog controllers.
The LM5134A device features higher voltage thresholds for greater noise immunity, and controllers with higher
drive voltages.
See Electrical Characteristics for the actual input threshold voltage levels and hysteresis specifications for the
LM5134 device.

8.2.2.3 VDD Bias Supply Voltage

The bias supply voltage applied to the VDD pin of the device should never exceed the values listed in
Recommended Operating Conditions. However, different power switches demand different voltage levels to be
applied at the gate terminals for effective turnon and turnoff. With an operating range from 4 V to 12 V, the
LM5134 device can be used to drive a variety of power switches, such as Si MOSFETs (for example,
VGS = 4.5 V, 10 V, 12 V), BJTs, and wide-band gap power semiconductors (such as GaN, certain types of which
allow no higher than 6 V to be applied to the gate terminals).

8.2.2.4 Peak Source and Sink Currents

Generally, to minimize switching power losses, the switching speed of the power switch during turnon and turnoff
should be as fast as possible. However, very fast transitions on the Drain node voltage can lead to unwanted
emissions for EMI, and the turnon speed is often deliberately slowed down by placing a series resistor between
the Drive output and MOSFET gate to reduce these emissions.

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

The speed at which the drain node rises during turnoff is typically dictated by the current in the inductor at
turnoff, and thus is not dependent on the turnoff current of the drive circuit. However, depending on the amount
of current flowing through the drain to gate capacitance of the MOSFET as the drain voltage rises and the
impedance to ground of the drive circuit, it is possible for the gate voltage to exceed the threshold voltage of the
FET and turn the FET back on, known as a false turnon.
For these reasons, turn the FET off as fast as possible. The LM5134 allows the flexibility of different turnon and
turnoff speeds, and avoids false turnon by providing a pilot output to drive a small pulldown MosFET, which can
be placed close to the main FET and reduces the impedance from gate to ground on turnoff.
Using the example of a power MOSFET, the system requirement for the switching speed is typically described in
terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dV/dt). For example, the
system requirement might state that a SPP20N60C3 power MOSFET must be turned on with a dV/dt of 20 V/ns
or higher, under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC converter
application. This type of application is an inductive hard-switching application, and reducing switching power
losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET
turnon event (from 400 V in the OFF state to V DS(on) in on state) must be completed in approximately 20 ns or
less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (QGD parameter
in SPP20N60C3 power MOSFET data sheet = 33 nC typical) is supplied by the peak current of gate driver.
According to the power MOSFET inductive switching mechanism, the gate-to-source voltage of the power
MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage
of the power MOSFET, VGS(TH). To achieve the targeted dV/dt, the gate driver must be capable of providing the
QGD charge in 20 ns or less. In other words, a peak current of 1.65 A (= 33 nC / 20 ns) or higher must be
provided by the gate driver. The LM5134 gate driver is capable of providing 4.5-A peak sourcing current, which
exceeds the design requirement and has the capability to meet the switching speed needed. The 2.7x overdrive
capability provides an extra margin against part-to-part variations in the QGD parameter of the power MOSFET,
along with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency
versus EMI optimizations.
However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will have a
definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to limit the
dI/dt of the output current pulse of the gate driver. To illustrate this, consider output current pulse waveform from
the gate driver to be approximated to a triangular profile, where the area under the triangle ( ½ × I PEAK × time)
would equal the total gate charge of the power MOSFET (QG parameter in SPP20N60C3 power MOSFET
datasheet = 87 nC typical). If the parasitic trace inductance limits the dI/dt, then a situation may occur in which
the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG
required for the power MOSFET switching. In other words, the time parameter in the equation would dominate
and the I PEAK value of the current pulse would be much less than the true peak current capability of the device,
while the required QG is still delivered. Because of this, the desired switching speed may not be realized, even
when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. Thus,
placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with
minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver.
The LM5134 is capable of driving a small FET local to the Gate of the main MOSFET to reduce the impact of this
parasitic inductance and achieve the high dV/dt required on turnoff. The nominal gate voltage plateau of the
SPP20N60C3 is given as 5.5 V. Thus to achieve the required sink current of 1.65 A would require an Rds_on of
3.3 Ω for the pilot FET. Lower on resistance gives further margin in the turnoff speed as described above, and
reduces the potential for false turnon.

8.2.2.5 Enable and Disable Function

Certain applications demand independent control of the output state of the driver, without involving the input
signal. A pin offering an enable and disable function achieves this requirement. The LM5134 device offers two
input pins, IN+ and IN – , both of which control the state of the output as listed in Table 2. Based on whether an
inverting or noninverting input signal is provided to the driver, the appropriate input pin can be selected as the
primary input for controlling the gate driver. The other unused input pin can be used for the enable and disable
functionality. If the design does not require an enable function, the unused input pin can be tied to either the VDD
pin (in case IN+ is the unused pin), or GND (in case IN – is unused pin) to ensure it does not affect the output
status.

16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

8.2.2.6 Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used, and the acceptable level of pulse distortion to the system. The LM5134 device features industry best-in-
class 17-ns (typical) propagation delays, which ensure very little pulse distortion and allow operation at very high
frequencies. See Electrical Characteristics for the propagation and switching characteristics of the LM5134
device.

8.2.2.7 PILOT MOSFET Selection

In general, a small-sized 20-V MOSFET with logic level gates can be used as the external turnoff switch. To
achieve a fast switching speed and avoid the potential shoot-through, select a MOSFET with the total gate
charge less than 3 nC. Verify that no shoot-through occurs for the entire operating temperature range. In
addition, a small Rds(on) is preferred to obtain the strong sink current capability. The power losses of the PILOT
MOSFET can be estimated in Equation 1.
Pg = 1/2 × Qgo × VDD × FSW
where
• Qgo is the total input gate charge of the power MOSFET (1)

8.2.3 Application Curves

Figure 25. OUT Turnoff to PILOT Turnon Propagation Figure 26. PILOT Turnoff to OUT Turnon Propagation
Delay vs VDD Delay vs VDD

9 Power Supply Recommendations

A low ESR/ESL ceramic capacitor must be connected close to the IC, between VDD and VSS pins to support the
high peak current being drawn from VDD during turnon of the FETs. Place the VDD decoupling capacitor on the
same side of the PC board as the driver. The inductance of via holes can impose excessive ringing on the IC
pins.

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

10 Layout

10.1 Layout Guidelines

Attention must be given to board layout when using LM5134. Some important considerations include:
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the FETs gate into a minimal physical area. This will decrease the loop inductance and minimize
noise issues on the gate.
2. To reduce the loop inductance, the driver should be placed as close as possible to the FETs. The gate trace
to and from the FETs are recommended to be placed closely side by side, or directly on top of one another.
3. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form a LCR
resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp
the ringing.

10.2 Layout Example

Figure 27. LM5134 Layout Example

18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 LM5134
www.ti.com SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

10.3 Power Dissipation

It is important to keep the power consumption of the driver below the maximum power dissipation limit of the
package at the operating temperature. The total power dissipation of the LM5134 is the sum of the gate charge
losses and the losses in the driver due to the internal CMOS stages used to buffer the output as well as the
power losses associated with the quiescent current.
The gate charge losses include the power MOSFET gate charge losses as well as the PILOT FET gate charge
losses and can be calculated as follows:
Pg = (Qgo + Qgp) × VDD × FSW (2)
Or
Pg = (Co + Cp) × VDD2 × FSW
where
• Fsw is switching frequency
• Qgo is the total input gate charge of the power MOSFET
• Qgp is the total input gate charge of the PILOT MOSFET (3)
Co and Cp are the load capacitance at OUT and PILOT outputs respectively. It should be noted that due to the
use of an external turnoff switch, part of the gate charge losses are dissipated in the external turnoff switch.
Therefore, the actual gate charge losses dissipated in the LM5134 is less than predicted by the above
expressions. However, they are a good conservative design estimate.
The power dissipation associated with the internal circuit operation of the driver can be estimated with the
characterization curves of the LM5134. For a given ambient temperature, the maximum allowable power losses
of the IC can be defined using Equation 4.
P = (TJ – TA) / θJA
where
• P is the total power dissipation of the driver (4)

Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: LM5134
LM5134
SNVS808C – MAY 2012 – REVISED FEBRURARY 2016 www.ti.com

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

Product Folder Links: LM5134

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM5134AMF/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SK7A

LM5134AMFX/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SK7A

LM5134ASD/NOPB ACTIVE WSON NGG 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5134A

LM5134ASDX/NOPB ACTIVE WSON NGG 6 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5134A

LM5134BMF/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SK7B

LM5134BMFX/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SK7B

LM5134BSD/NOPB ACTIVE WSON NGG 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5134B

LM5134BSDX/NOPB ACTIVE WSON NGG 6 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5134B

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5134AMF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5134AMFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5134ASD/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM5134ASDX/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM5134BMF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5134BMFX/NOPB SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5134BSD/NOPB WSON NGG 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM5134BSDX/NOPB WSON NGG 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5134AMF/NOPB SOT-23 DBV 6 1000 208.0 191.0 35.0
LM5134AMFX/NOPB SOT-23 DBV 6 3000 208.0 191.0 35.0
LM5134ASD/NOPB WSON NGG 6 1000 208.0 191.0 35.0
LM5134ASDX/NOPB WSON NGG 6 4500 367.0 367.0 35.0
LM5134BMF/NOPB SOT-23 DBV 6 1000 208.0 191.0 35.0
LM5134BMFX/NOPB SOT-23 DBV 6 3000 208.0 191.0 35.0
LM5134BSD/NOPB WSON NGG 6 1000 208.0 191.0 35.0
LM5134BSDX/NOPB WSON NGG 6 4500 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA
NGG0006A

SDE06A (Rev A)

www.ti.com
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated