SEM.
_3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
Experiment
1 Date:
OBJECTIVE:
(a) Verify mesh analysis and nodal analysis using KVL and KCL in given circuit
diagram.
(b) To observe response of Resistor, Inductor and Capacitor to DC as well as AC. Prove
Voltage and current divider.
Apparatus:
• Resistors, Inductors, Capacitors.
• Variable Power supply, Function generator
• Breadboard, Digital Multimeter, connecting wires and probes.
Theory:
V1 1 V2 3 V3 5
1 Vpk 1 Vpk L1 1 Vpk C1
1kHz R1 1kHz 1kHz
0° 0° 0°
2 4 6
Figure a. Resistor, Inductor and Capacitor connected with a.c. supplies
Resistors, Inductors and Capacitors are passive devices it means they should be
excited by other active sources. These devices are lumped, linear and passive devices.
Voltage and current division:
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
SEM._3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
R1
R2
V
By Ohm’s law
V =V1 +V2 = iR1 + iR2 = i(R1 + R2)
So I = V/(R1 + R2)
Thus V2 = iR2 = VR2/(R1 + R2)
So V2 = (R2/(R1 + R2))V
R2
R1
I1
Current flowing through R2 is
IR2 = V / R2 = i( R1 ||R2 )/R2 = i R1 /(R1 + R2)
And similarly
IR1 = i R2/ (R1 + R2)
Kirchhoff’s Voltage law (KVL):
The algebraic sum of voltage around any closed path is zero
Or more compactly
𝑁
∑ 𝑉𝑛 = 0
𝑛=1
Kirchhoff’s Current law (KCL):
The algebraic sum of current entering any node is zero
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
SEM._3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
Or more compactly
𝑁
∑ 𝑖𝑛 = 0
𝑛=1
KCL is independent of the nature of elements connected to node.
KVL is independent of the nature of elements present in loop.
KCL + Ohm’s law = nodal analysis
KVL + Ohm’s law = mesh analysis
Representation of circuit diagram in solder less bread board is shown in below figure.
Circuit Diagram:
Circuit Diagram:
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
SEM._3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
Observation table :
Sr.No. Actual Theoretical value of Practical value of current
Resistor current across resistor across resistor value
value value
1 15Ω 0.4 A 0.5 A
2 12Ω 0.2 A 0.17A
3 15Ω 0.2 A 0.33 A
Procedure:
✓ Connect circuit diagram as shown in figure.
✓ Apply source voltages by using power supply.
✓ Measure the voltage across each of resistor and from that find the current
through them.
✓ Calculate the current through each circuit element theoretically.
✓ Compare the theoretical result with practical one.
Conclusion:
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
SEM._3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
Rubric wise marks obtained:
Parameters Attendance Basic Capability Output Submission Total
in lab knowledge of doing
of topic task
Marks
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
SEM._3_BATCH-___
ENROLLMENT NO.______________
GOVERNMENT ENGINEERING COLLEGE
BHAVNAGAR (021) -364002
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT
FACULTY NAME: DR. JANAK TRIVEDI
NETWORK THEORY (3131103) LAB
