Advance Processors

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1. Define the Following.

Ans - Microprocessor: It is a multipurpose, programmable device that accepts digital data as input, processes
it according to instructions stored in its memory, and provides results as output.
- Assembler: An assembler or macro-assembler generally forms a part of the operating
system. Which translates a assembly language program into machine language
program.
- Debugger: It is a program which allows user to test and debug programs. All computers
including microprocessor provide debugging facility. To detect errors a program
can be tested in single steps. Each step of the program is executed and tested.
The debugger allows the user to examine the contents of registers and memory
locations after each step of execution. This also provides facility to insert
breakpoint in the programs.
- Linker: A large program is divided in smaller programs known as modules. A linker is a
program which links smaller programs together to form a large program. While
developing a program subroutines, which are stored in library file, are frequently
used in the program. The linker also links these subroutines with the main
program.
- Stack: The stack is an area of memory identified by the programmer for temporary
storage of information having LIFO structure.
- Subroutine: A subroutine is a group of instructions that will be used repeatedly in different
locations of the program.
- Instruction: An instruction is a binary pattern designed inside a microprocessor to perform a
specific function
- Opcode: selects the operation performed by the microprocessor
- Operand: The data on which the operation is to be performed as well as the result of an
operation.
- Interrupt: Interrupt is a change of path in program execution caused by hardware request,
software execution or internal processor error.
- ISR: A small program or a routine that when executed services the corresponding
interrupting source is called ISR.
- Bus: A group of lines, pins or signals having common function is teamed as bus.
- Clock The processing speed of microprocessor depends upon the clock frequency.
Frequency: Program execution speed is determined by this parameter (number of
instructions/sec).

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2. Introduction to 8086 microprocessor OR Features of 8086 microprocessor

Ans General Features:
➢ 8086 is a 16-bit processor, which implies that
- 16-bit data bus
- 16-bit ALU, that perform 16-bit operation at the same time
- 16-bit registers
➢ Speed of processor
➢ There are three versions based on the frequency of operation
8086 -> 5MHz (5 million cycles per second)
8086 -> 8MHz (8 million cycles per second)
8086 -> 10MHz (10 million cycles per second)
➢ 8086 has a 20 bit address bus can access up to 220 memory locations.( 220=1048576 bytes =1 MB)
➢ It can support up to 64K I/O ports. (216 I/O ports-> 216=65536 bytes=64 Kb)
➢ In 8086 two Unit works in parallel:
- Bus Interface Unit (BIU)
- Execution Unit (EU)
➢ 8086 has 256 vectored interrupt.
➢ 8086 contains powerful instruction set , that supports Multiply and Divide operation (this operation
were not possible in previous versions of 8086)
➢ 8086 can perform operation on bit, byte (8-bit), word (16-bit) or string types of data.
Special Features:
➢ 8086 is a pipelined processor
➢ 8086 is two staged pipelined architecture:
i. Fetch Stage: It pre-fetch up to 6 bytes of instruction and store them in the queue.
ii. Execute stage: Executes the instruction
➢ 8086 can operate in 2 modes
i. Minimum mode: A system with only one processor i.e.8086
ii. Maximum mode: A system with multiple processors.
e.g. 8086 + math co-processor(8087),
8086+ I/O processor (8089),
Multiple 8086 processors
➢ 8086 uses memory bank
- In 8086 entire data is not stored in single sequential memory of 1MB.
- The memory is divided into two banks of 512KB each.
i. Lower Bank/ Even Bank: Stores the data types at even locations (0,2,4…)
ii. Higher Bank/ Odd Bank: Stores the data types at odd locations (1,3,5…)
➢ 8086 uses memory segmentation
- Segmentation means dividing memory into logical components.
- In 8086 memory is divided into 16 segments of capacity 216 bytes each and used as code, stack,
data and extra segment

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3. Explain 8086 Architecture

OR State the function of components of 8086 internal architecture.
Ans The Block diagram for the internal architecture of 8086 is as follows:-

- In 8086 CPU is divided into two independent functional parts BIU and EU.
- Dividing the work between these two units’ speeds up the processing.
➢ BIU (Bus Interface Unit)
Components of BIU
- Instruction queue
It holds the instruction bytes of the next instruction to be executed by EU
- Segment Registers
Four 16-bit register that provides powerful memory management mechanism
ES (extra segment), CS (code segment), SS (stack segment) , DS (data segment).
The size of each register is 64kb.
- Instruction pointer (IP)
Register that holds 16-bit address or offset of next code byte within code segment
- Address Generation and bus control
Generation of 20-bit physical address

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Task carried out by BIU

- Fetch instruction from memory
- Read/ Write instruction from / to the memory
- Input/ Output (I/O) of data from / to peripheral ports
- Write the data to memory.
- Address generation for memory reference
- Queuing of instruction (The instruction bytes are transferred to the instruction queue)
- Thus, BUI handles all transfer of data and address on the buses for Execution unit.
- BIU works in synchronous with machine cycles
➢ EU (Execution Unit)
Components of EU
- ALU (Arithmetic logic Unit)
Contains 16-bit ALU, that performs add, subtract, increment, decrement, compliment,
shift binary numbers, AND, OR, XOR etc.
- CU (Control Unit)
Directs internal operation
- Flag Register
16-bit flag register
EU contains 9 active flags
- General Purpose Registers (GPR)
EU has 4 general purpose 16-bit register
i.e. AX, BX, CX, DX
each register is the combination of two 8-bit register
AH, AL, BH, BL, CH, CL, DH, DL where ‘L’ means Lower byte and ‘H’ means higher byte.
- Index Register
16-bit Register is SI (source index) and DI (destination index).
Both the register are used for string related operation and for moving block of memory
from one location to the other.
- Pointers
16-bit Register.
i.e. SP (stack pointer), BP (base pointer)
BP : is used when we need to pass parameter through stack
SP: It always points to the top of the stack. Used for sequential access of stack
segment.
- Decoder (instruction decoder)
Translates the instruction fetched from into series of action which EU carries out
Task carried out by EU
- Decodes the instruction
- It executes instructions ( executes decoded instructions)
- Tells BIU from where to fetch the instruction

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- Decodes instruction (decode the fetched instruction)

- EU takes care of performing operation on the data
- EU is also known as execution heart of the processor
4. Explain 8086 Registers
Ans The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer as
follows:-
General Purpose Register
1. AX: - Accumulator register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX.
- AX works as an intermediate register in memory and I/O operation.
- Accumulator is used for the instruction such as MUL and DIV.
2. BX: - Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX.
- BX register usually contains a data pointer used for based, based indexed or register indirect
addressing.
3. CX: - Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. Count register can be used in Loop, shift/rotate instructions and
as a counter in string manipulation.
4. DX: - Data register can be used together with AX register to execute MUL and DIV instruction.
- Data register can be used as a port number in I/O operations.
Segment Register
Types of Segment registers are as follows:-
1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment
of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data
Segment by an offset address or the content of other register that holds the offset address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the
destination data
Pointer Registers
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively.
1. Stack Pointer (SP): SP is a 16-bit register pointing to program stack in stack segment.
2. Base Pointer (BP): BP is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
3. Instruction Pointer (IP): IP is a 16-bit register pointing to next instruction to be executed.

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Index registers
The Index Registers are as follows:-
1. Source Index (SI): SI is a 16-bit register used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions.
2. Destination Index (DI) : DI is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data addresses in string manipulation instructions.
Flag Registers
1. The 16-bit flag register of 8086 contains 9 active flags (six conditional & 3 control flags), other 7
flags are undefined.
2. Status Flags: It indicates certain condition that arises during the execution. They are controlled by
the processor.
3. Control Flags: It controls certain operations of the processor. They are deliberately set/ reset by the
user.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF

U- Undefined CF- Carry Flag

TF- Trap Flag PF- Parity Flag
IF- Interrupt Flag AF- Auxiliary Flag
DF- Direction Flag ZF- Zero Flag
OF- Overflow Flag SF- Sign Flag
The Flag Registers are classified as follows :-

Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
4. Trap Flag (TF):
- It is used for single step control.
- It allows user to execute one instruction of a program at a time for debugging.
- When trap flag is set, program can be run in single step mode.
5. Interrupt Flag (IF):
- It is an interrupt enable/disable flag.
- If it is set, the mask able interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
- It can be set by executing instruction sit and can be cleared by executing CLI instruction.

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6. Direction Flag (DF):

- It is used in string operation.
- If it is set, string bytes are accessed from higher memory address to lower memory address.
- When it is reset, the string bytes are accessed from lower memory address to higher memory
address.
Status Flag
1. Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also
used in multiple-precision arithmetic.
2. Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e.
D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag.
This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD
conversion.
3. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.
4. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
5. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.
6. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. OF=1 indicates that the
result has exceeded the capacity of machine.
5. Explain Addressing modes of 8086
Ans When 8086 executes an instruction, it performs the specified function on data. These data are called its
operands and may be part of the instruction, reside in one of the internal registers of the microprocessor,
stored at an address in memory or held at an I/O port, to access these different types of operands,
the 8086 is provided with various addressing modes.
There are 12 addressing modes in 8086 as follows:-
1. Immediate Mode
- If a source operand is part of the instruction instead of the contents of a register or memory location,
it represents what is called the immediate operand.
- In other word it is constant data contained in an instruction
- If source operand is the part of instruction rather than register or memory, then referred as
immediate addressing mode.
- Operand = address field
- E.g. MOV AL, 05H; instruction copies immediate number 05H to AL register
- Immediate data may be 8-bits or 16-bits in length
Instruction

Opcode Immediate Operand

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Advantage:
- Operand can be accessed quickly as they are directly available in instruction queue.
- No need of External bus or bus-cycles to obtain data.
- No memory reference to fetch data
- Comparatively Faster execution
Limitation:
- The operand can only be used as a source operand.
- Value of the operand will remain Constant
2. Register Addressing Mode
- The operand is stored in one of the CPU register.
- Register may be used as source operand or destination operand or both
- E.g. ADD r1, r2; adding r1 and r2 and store the result in r2
E.g. MOV AX,BX ; move value from BX to AX register
Advantage:
- This mode is normally preferred, as the execution of instruction is faster and compact, because all
the registers reside on the same chip.
- Therefore, data transfer is within the chip and no External bus is required.
Limitation:
- Number of CPU registers are limited

3. Direct Addressing Mode

- Address field of Instruction contains address of operand
Benefit:
- Single memory reference is required to access data
- No additional calculations to work out effective address
Equation: Physical Address PA ={starting address of Segment Register } + {Direct memory address}

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E.g.
MOV [30540], TEMP; moving value of TEMP to memory location [30540]
DS=3060 and direct memory address=0030
3 0 6 0 0 (‘0’ is added to LSB by BIU)
+ 0 0 3 0 ( direct address)

3 0 6 3 0 (physical address)
-

4. Register Indirect Addressing

In this addressing mode effective address of memory is calculated from base register (BX) or index
register (SI, DI), specified in the instruction. Then it is added to the segment register to generate physical
address.
Equation: Physical Address PA ={starting address of Segment Register } + { [BX] or index register }

E.g. MOV [DI], BX; value of BX is moved to the memory location specified in DI
MOV [BX], AX ; value of AX is moved to the memory location specified in BX

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Benefit:
- Large address space
Limitation:
- Slower access, as multiple memory accesses is needed to find operand.
5. Based Addressing Mode
When memory is accessed PA is computed from BX and DS, when the stack is accessed PA is computed
from BP and SS.

Equation:
PA ={starting address of Segment Register } + { [BX] or [BP] }+ (8 or 16 bit) displacement
E.g. MOV AL, TEMP [BX]; segment register address+ BX+ offset
MOV AL, TEMP [BP]; segment register address+ BP+ offset
Assume DS=3060, BX=0050 and displacement=08
3 0 6 0 0 H (starting address of segment register)
+ 0 0 5 0 H(base register)
+ 0 8 H(offset)

3 0 6 5 8 H(physical address)
6. Indexed Addressing Mode
- In this addressing mode offset address is added to index register and finally the sum is added to
segment register.
- E.g. MOV BH, TEMP [SI] ; TEMP is the offset address
Equation:
PA ={starting address of Segment Register } + { [SI] or [DI] }+ (8 or 16 bit) displacement
Assume DS=3060, SI=0050 and displacement=08
3 0 6 0 0 H (starting address of segment register)
+ 0 0 5 0 H (Source Index)
+ 0 8 H (offset)

3 0 6 5 8 H (physical address)

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7. Based Indexed Addressing Mode

- This mode generates the effective address, which is sum of Base address +Index Address + (8 or 16
bit) displacement address.
- This sum is added to segment register to generate effective address.
- E.g. MOV CX, TEMP[BX] [SI]
Equation: PA ={starting address of Segment Register } + {[BX] or [BP]}+({ [SI] or [DI] }+ (8 or 16
bit) displacement

Assume DS=5000, BX=3000, SI=0400 and displacement=08

5 0 0 0 0 H (starting address of segment register)
+ 3 0 0 0 H (base register)
+ 0 4 0 0 H (Source Index)
+ 0 8 H (offset)

5 3 4 0 8 H (physical address)

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8. String Addressing Mode

The string instructions automatically assume SI to point to the first byte or word of the source operand
and DI to point to the first byte or word of the destination operand. The contents of SI and DI are
automatically incremented (by clearing DF to 0 by CLD instruction) to point to the next byte or word.
Source address : 20500, assume it contains 38
PA : [DS] + [SI] = 20000+0500=20500
Destination address : [ES] + [DI] = 40000+0300
After executing MOV SI, DI
[40300] = 38
[SI] = 0501 incremented
[DI] = 03
9. Relative addressing mode:
Relative address means ‘relative to IP (Instruction Pointer)’.
Example : JNC START ; jump to label if no carry is generated
- If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START,
otherwise the next instruction is executed.
- Displacement is calculated on the basis of next location to be executed.
10. Implied addressing mode:
Instructions using this mode have no operands.
E.g. CLC; which clears carry flag to zero.
STC; set the carry flag
11. I/O mode (direct) :
Port number is an 8 bit immediate operand.
Example : OUT 05 H, AL
Outputs value of AL to 8 bit port 05 H
IN and OUT instructions are allowed to use only AL or AX registers.
12. I/O mode (indirect):
I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH.
The port number is taken from DX.
Example 1 : IN AL, DX
IN and OUT instructions are allowed to use only AL or AX registers.

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6. Draw and explain 8086 pin diagram

Ans The 8086 pins and signals are shown as follows:

- Total number of pins in 8086 = 40 pins

- The 8086 operates in single processor or multiprocessor configuration to achieve high performance.
- The 8086 signals can be categorized in six groups
1 Power Supply pins [3] GND1, GND2, VCC
2 Clock Related pins[3] CLK, RESET, READY
3 Interrupt Related pins[3] NMI, INTR, INTA
4 Address and Data pins [21] AD0-AD15, A16/S3- A19/S6, BHE/S7
5 Control pins [3] TEST, MN/MX, RD
6 Mode Multiplexed pins [8] HOLD, HLDA, WR, M/IO, DT/R, DEN, ALE,
INTA
➢ Power Supply pins
i. GND1, GND2 - Ground signal (Vss)
ii. VCC - It is a power supply input signal and +5V DC is supplied through this pin.
➢ Clock Related pins
i. CLK
- Input signal
- Generates clock signals that synchronize the operation of processor.
ii. RESET
- It is an active high input signal
- When high, microprocessor enters into reset state and Terminates activity of processor

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- Clears PSW, IP, DS,SS,ES, and the instruction queue

- CS to FFFF; IP to 0000H; SS to 0000H; DS to 0000H; PSW to 0000H
- Processor requires 4 clock cycle to reset. Thus RESET signal must be 1 for at least 4 clock cycles
iii. READY
- It is an active high input signal
- This is an acknowledgement signal from I/O devices or memory.
- When READY = high; it indicates that the device is ready to transfer data.
=low; microprocessor is in wait state.
➢ Interrupt Related pins
i. NMI
- It is an active high input signal
- It is a non-mask able interrupt signal.
- It is an edge triggered interrupt.
ii. INTR
- It is an active high input signal
- It is an interrupt request signal.
iii. INTA
- It is an active low output signal.
- This is an interrupt acknowledge signal.
- When microprocessor receives INTR signal, it acknowledges the interrupt by generating this
signal.
➢ Address and Data pins
i. AD0-AD15 (bidirectional)
- These lines are multiplexed bidirectional address/data bus.
- During T1, they carry lower order 16-bit address and in the remaining clock cycles, they carry
16-bit data.
- AD0-AD7 carry lower order byte of data and AD8-AD15 carry higher order byte of data.
- During T1 machine cycle, when ALE=1, then Address bus gets enabled, else Data bus will get
enabled.
ii. A16/S3- A19/S6 (unidirectional)
- These lines are multiplexed and unidirectional address and status bus.
- During T1, they carry higher order 4-bit address.
- In the remaining clock cycles, they carry status signals.
- S5 gives the status of Interrupt Flag (IF)
- S6 goes low, when 8086 controls the shared system bus.

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- S3 and S4 indicates the segment register as shown below:-

S4 S3 Register
0 0 ES
0 1 SS
1 0 CS
1 1 DS
iii. BHE/S7
- BHE stands for Bus High Enable.
- Active low output signal.
- BHE signal is used to indicate the transfer of data over higher order data bus (D8 – D15).
- 8-bit I/O devices use this signal.
- S7 is reserved for future development.
➢ Control Pins
i. TEST
- Active low input signal.
- It is used to test the status of math coprocessor 8087.
- The BUSY pin of 8087 is connected to this pin of 8086.
- If low, execution continues, else microprocessor is in wait state.
ii. MN/MX
- Input signal
- 8086 works in two modes:
- Minimum Mode [Active high input signal]
- Maximum Mode [ Active low input signal]
- If MN/MX is high, it works in minimum mode.
- If MN/MX is low, it works in maximum mode.
- Pins 24 to 31 issue two different sets of signals.
- One set of signals is issued when CPU operates in minimum mode.
- Other set of signals is issued when CPU operates in maximum mode.
iii. RD (READ)
- It is an active low output signal.
- It is a read signal used for read operation.
- When the signal is low, then read from memory or I/O
➢ Mode Multiplexed pins
i. INTA (QS1)
- It is an active low output signal.
- This is an interrupt acknowledge signal.
- When microprocessor receives INTR signal, it acknowledges the interrupt by generating this signal.
ii. ALE(QS0)
- It is an active high output signal and remains high during T1 state.

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- This is an Address Latch Enable signal.

- It indicates that valid address is available on bus AD0 – AD15
iii. DEN (S0)
- It is an active low output signal
- This is a Data Enable signal
- This signal is used to enable the transceiver
- Transceiver is used to separate the data from the address/data bus
iv. DT/R (S1)
- This is a Data Transmit/Receive signal.
- When it is high= >data is transmitted out ,low=>data is received in
v. M/IO(S2)
- This signal is issued by the microprocessor to distinguish memory access from I/O access.
- When it is high=> memory is accessed.
- low=> I/O devices are accessed
Operation carried out by Maximum mode (pin 26, 27, 28)
S2 S1 S0 Machine Language
0 0 0 Interrupt acknowledgement
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 HALT
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

vi. LOCK (WR)

- It is an active low output signal.
- This signal indicates that other processors should not ask CPU (8086) to hand over the system
bus.
- When it goes low, all interrupts are masked and HOLD request is not granted.
- Thus the master bus controller can’t take control over the system bus, till the instruction gets
completed.
- This pin is activated by using LOCK prefix on any instruction.
- WR: It is an active low output signal. It is used to write data in memory or output signal,
depending on status of M/IO signal.
vii. HOLD (RQ/GT0)
- It is an active high input signal.
- When DMA controller needs to use address/data bus, it sends a request to the CPU through this
pin.
- When microprocessor receives HOLD signal, it issues HLDA signal to the DMA controller.

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viii. HLDA (RQ/GT1)

- It is an active high output signal.
- It is a Hold Acknowledge signal.
- It is issued after receiving the HOLD signal.
ix. RQ/GT0 and RQ/GT1 For maximum mode (pin 30 and 31)
- These are Request/Grant bi-directional pins.
- Other processors request the CPU through these lines to release the system bus.
- After receiving the request, CPU sends acknowledge signal on the same lines.
- RQ/GT0 has higher priority than RQ/GT1

7. Explain Minimum mode of 8086 in detail.

Ans - In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1.
- In this mode, all the control signals are given out by the microprocessor chip itself.
- There is a single microprocessor in the minimum mode system. The remaining components in the
system are latches, transceivers, clock generator, memory and I/O devices.
- Some type of chip selection logic may be required for selecting memory or I/O devices, depending
upon the address map of the system.

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- Block diagram for Minimum mode of 8086 is shown below:-

Figure: Minimum Mode of 8086

Timing Diagram
- The working of the minimum mode configuration system can be better described in terms of the
timing diagrams rather than qualitatively describing the operations.
- T-State: One clock period is referred to as a T-State. An operation takes an integer number of T-
States.

- CPU Bus Cycle: A bus cycle consists of 4 or more T-States.

- Since a memory read or write should be complete within one bus-cycle (4-CLK pulses, T1 -T4),
related timing states as follows:
- T1 (1st clock pulse)- starts the bus cycle. Actions include setting control signals to give the
required logic values for IO/M, ALE, DT/R and a valid address onto the address bus.
- T2 - the RD or WR control signals are issued, DEN is asserted and in the case of a write, data is
put onto the data bus.
- The DEN turns on the data bus buffers to connect the CPU to the external data bus.
- The READY input to the CPU is sampled at the end of T2 and if READY is low, wait state (TW) is
inserted before T3 begins.
- T3 - this clock period is provided to allow memory to access the data. If the bus cycle is a read

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cycle, the data bus is sampled at the end of T3 or the 3rd clock pulse of the bus-cycle.
- T4 - all bus signals are deactivated in preparation for the next clock cycle.
- The 8088 also finishes sampling the data (in a read cycle) in this period.
- For the write cycle, the trailing edge of the WR signal transfers data to the memory.
- Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read
cycle and the second is the timing diagram for write cycle shown below.

Figure: Read Cycle of Minimum Mode Figure: Write Cycle of Minimum Mode
Read Cycle
To complete the minimum-mode memory-read bus-cycle, the required control signals with appropriate
active logic levels are :
- IO/M = ‘logic 0’, to select memory interface
- MN/MX = ‘logic 1’, to select minimum-mode of operation
- DT/R = ‘logic 0’, to activate the data-receive mode of ‘Data-bus-buffer’
- Valid Physical-address of memory-location via address-bus (A19 to A0)
- ALE-pulse, to latch the valid Physical-address
- RD = ‘logic 0’, to initiate reading data into CPU. Note, WR = ’logic 1’
- DEN = ‘0’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
- Reset RD=DEN=’logic1’, to END the read-bus-cycle.
Write Cycle
To complete the minimum-mode memory-write bus-cycle, the required control signals with appropriate
active logic levels are :
- IO/M = ‘logic 0’, to select memory interface
- MN/MX = ‘logic 1’, to select minimum-mode of operation
- DT/R = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus-buffer’
- Valid Physical-address of memory-location via address-bus (A19 to A0)
- ALE-pulse, to latch the valid Physical-address.
- WR = ‘logic 0’, to initiate memory data writing. Note, RD = ’logic 1’
- DEN = ‘0’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
- Reset WR=DEN=’logic1’, to END the write-bus-cycle.
-

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8. Explain Maximum mode of 8086 in detail.

Ans - In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type
8087 or another processor is interfaced with 8086.
- The Memory, Address Bus, Data Buses are shared resources between the processors.
- The control signals for Maximum mode of operation are generated by the Bus Controller chip
8788.
- Block diagram for Maximum mode of 8086 is shown below:-

Figure: Maximum Mode of 8086

- In Maximum mode, for multiprocessor environment WR, IO/M, DT/R, DEN, ALE, INTA signals are
not available. Instead available signals are as follows:-
MRDC (memory read command)
MWRT (memory write command)
IORC (I/O read command)
IOWC (I/O write command)
INTA (interrupt acknowledge)

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- The below table shows the Operation carried out by Maximum Mode.
S2 S1 S0 Machine Language
0 0 0 Interrupt acknowledgement
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 HALT
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
Table: Operation carried out by Maximum Mode

Figure: Read Cycle of Maximum Mode Figure: Write Cycle of Maximum Mode
Read Cycle
To complete the minimum-mode memory-read bus-cycle, the required control signals with appropriate
active logic levels are :
- IO/M = ‘logic 0’, to select memory interface
- MN/MX = ‘logic 0’, to select maximum-mode of operation
- DT/R = ‘logic 0’, to activate the data-receive mode of ‘Data-bus-buffer’
- Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
- ALE-pulse, to latch the valid Physical-address.
- Proper status code S0 to S2 (as shown in table of slide 8) is generated by
- CPU to initiate data reading (MRDC) from the desired memory bank
- DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
- Reset MRDC and DEN signals to END the read-bus-cycle

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Write Cycle
To complete the maximum-mode memory-write bus-cycle, the required control signals with appropriate
active logic levels are :
- IO/M = ‘logic 0’, to select memory interface
- MN/MX = ‘logic 0’, to select maximum-mode of operation
- DT/R = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus-buffer’
- Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
- ALE-pulse, to latch the valid Physical-address.
- Proper status code S0 to S2 (as shown in table of slide 8) is generated by
- CPU to initiate data writing (MRTC) from the desired memory bank
- DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
- Reset MRTC and DEN signals to END the read-bus-cycle
9. Differentiate minimum and maximum mode of 8086.
Ans Maximum Mode
i. When MN/MX (bar) low 8086 is in maximum mode.
ii. There are multiple processors in the system
iii. Maximum mode unique signals
Name Function
RQ/GT Request/ Grant bus access control
0,1
LOCK Bus priority lock control
Status Bus cycle status
QS 0,1 Instruction queue status

iv. In maximum mode interfacing, master/slave and multiplexing and several such control signals
are required.
v. In maximum mode a bus controller is required to produce control signals. This bus controller
produces MEMRDC, MEMWRC, IORDC, IOWRC, ALE, DEN, DT/R control signals.
vi. Maximum mode operation control signals must be generated externally requires an additional
external bus controller 8288. Thus maximum mode operation is more expensive.
Minimum Mode
i. When MN/MX (bar) high 8086 is in minimum mode.
ii. There is only one processor in the system minimum mode.
iii. In minimum mode no interfacing or master/slave signals is required.
iv. In minimum mode direct RD WR signals can be used. No bus controller required. A simple de-
multiplexer would do the job of producing the control signals.
Minimum mode operation is less expensive as all the control signal is generated for the
input/output and memory by processor itself.

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v. Minimum mode unique signals

Name Function
HOLD Hold request
HLDA Hold acknowledge
WR Write control
IO/M Input output/ memory control
DT/R Data transmit/ receive
DEN Data enable
Status Status line
ALE Address Latch Enable
INTA Interrupt acknowledge
10. Explain Memory bank. Briefly explain ODD and EVEN bank concept in 8086.
Ans - A memory bank is a designated section of computer memory used for storing data.
- In 8086 there is 20 bit address bus, so it can address 1,048,576 addresses. At each address we
can store 8 bit address (1-byte)but if want to write a word(16-bit)into a memory segment to
store data in byte form then we write the data in two consecutive memory address which are
even(low) and odd(high) memory.
- The 8086 memory address space can be viewed as a sequence of one million bytes in which any
byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit
data element.
- There is no constraint on byte or word address boundaries.
- The address space is physically connected to a 16-bit data bus by dividing the address space into
two 8-bit banks of up to 512K bytes each.
Even Memory bank
- One bank is connected to the lower half of the 16-bit data bus (D0 – D7) and contains even
address bytes. i.e., when A0 bit is low, the bank is selected.
- To access memory bytes from Even address, information is transferred over the lower half of the
data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even address
bank.
Odd Memory bank
- The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd
address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected.
- To access memory byte from an odd address information, is transferred over the higher half of
the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high
to disable the lower memory bank.

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Figure: Memory Bank

16. What is the minimum and maximum size of a segment in 8086? How are they computed?
Ans - In 8086 microprocessor the total memory addressing capability is 1 mega bytes.
- For representing 1MB there are minimum 4 hex digits are required i.e., 20 bits, but 8086 has
fourteen 16-bit registers. That is there are no registers for representing 20 bit address. So, the
total memory is divided into 16 logical segments and each segment capacity is 64 KB (kilo bytes).
- That is 16*64kb=1 MB. So, for representing 64 kb only 16 bit register is sufficient.
- Therefore, Size of segments is from minimum 64KB to maximum 1MB.
17. Explain Memory Models in 8086
Ans The Memory models used in 8086 are as follows:-
- Tiny: Code and data combined must be less than 64K
- Small: Code <=64K and Data<= 64K
- Medium: Data<=64K code any size multiple code segment
- Compact: Code<=64K data any size multiple data segment
- Large: Code>64K and data>64K multiple code and data segment
- Huge: Same as the Large except that individual section can be > 64K

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