// Code your design here
module registerfile #(xlen = 32)(
input clk, reset_n,
input wire [$clog2(xlen)-1:0] src1_addr, //all 3 from decoder to register file
input wire [$clog2(xlen)-1:0] src2_addr,
input wire [$clog2(xlen)-1:0] dest_addr,
output wire [xlen-1:0] operand_a, //both from register file to execution
output wire [xlen-1:0] operand_b,
input wire [xlen-1:0] write_data, // from execution to register file(data for
destination
input reg wr_en); // Execution to register file
reg [31:0] reg_file[31:0];
assign operand_a = (src1_addr == 0) ? 32'b0 : reg_file[src1_addr]; // Send Src 1
& 2 value to Execution
assign operand_b = (src2_addr == 0) ? 32'b0 : reg_file[src2_addr];
always@(posedge clk) begin
if(wr_en && dest_addr != 0)
reg_file[dest_addr] = write_data;
else
reg_file[dest_addr] = 32'b0;
// wr_en = 0;
end
endmodule
***********************************************************************************
***************************************
***************************************************Testbench***********************
***************************************
***********************************************************************************
***************************************
// Code your testbench here
// or browse Examples
module tb_registerfile;
// Parameters
localparam xlen = 32;
localparam addr_width = $clog2(xlen);
// Inputs
reg clk;
reg reset_n;
reg [addr_width-1:0] src1_addr;
reg [addr_width-1:0] src2_addr;
reg [addr_width-1:0] dest_addr;
reg [xlen-1:0] write_data;
reg wr_en;
// Outputs
wire [xlen-1:0] operand_a;
wire [xlen-1:0] operand_b;
// Instantiate the register file module
registerfile #(.xlen(xlen)) dut (
.clk(clk),
.reset_n(reset_n),
.src1_addr(src1_addr),
.src2_addr(src2_addr),
.dest_addr(dest_addr),
.operand_a(operand_a),
.operand_b(operand_b),
.write_data(write_data),
.wr_en(wr_en)
);
// Clock generation
always #5 clk = ~clk;
// Test procedure
initial begin
// Initialize inputs
clk = 0;
reset_n = 0;
src1_addr = 0;
src2_addr = 0;
dest_addr = 0;
write_data = 0;
wr_en = 0;
// Reset the register file
#10 reset_n = 1; // De-assert reset after 10 time units
// Test 1: Write to register 1 and read back from it
#10;
wr_en = 1;
dest_addr = 5; // Write to register 5
write_data = 32'hA5A5A5A5;
#10;
wr_en = 0; // Disable write
src1_addr = 5; // Read from register 5
src2_addr = 5;
#10;
$display("Register 5 value: operand_a = %h, operand_b = %h", operand_a,
operand_b);
if (operand_a !== 32'hA5A5A5A5 || operand_b !== 32'hA5A5A5A5) begin
$display("Error: Register 5 readback mismatch!");
end
// Test 2: Write to register 10 and read back from it
#10;
wr_en = 1;
dest_addr = 10; // Write to register 10
write_data = 32'h5A5A5A5A;
#10;
wr_en = 1; // Disable write
src1_addr = 10; // Read from register 10
src2_addr = 10;
#10;
$display("Register 10 value: operand_a = %h, operand_b = %h", operand_a,
operand_b);
if (operand_a !== 32'h5A5A5A5A || operand_b !== 32'h5A5A5A5A) begin
$display("Error: Register 10 readback mismatch!");
end
// Test 3: Attempt to write to register 0 (should not write anything)
#10;
wr_en = 1;
dest_addr = 0; // Attempt to write to register 0
write_data = 32'hFFFFFFFF;
#10;
wr_en = 0; // Disable write
src1_addr = 0; // Read from register 0
src2_addr = 0;
#10;
$display("Register 0 value: operand_a = %h, operand_b = %h", operand_a,
operand_b);
if (operand_a !== 32'h0 || operand_b !== 32'h0) begin
$display("Error: Register 0 should always read back as 0!");
end
// Finish the simulation
#10;
$finish;
end
endmodule
