Operating System Bcs401 Complete Notes
Operating System Bcs401 Complete Notes
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OS UNIT 1 - best notes unit 1 operating system student
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Operating System (OS) Unit-2
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Complete Unit- 3 (OS) - Operating System Unit 3 Full Notes
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Downloaded by Arman Ali ([email protected])
lOMoARcPSD|30415125
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OS UNIT 4 - Very well explained notes of Operating System
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Numerical on Paging
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*Note: 210 = 1K, 220 = 1M, 230 = 1G, 240 = 1T, 250 = 1P
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Type 01 Numerical: Address to Space/Memory Translation
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*Note: The total size of memory (to find) depends upon two values:
1. Number of locations the memory has (2n); where n is no of address bits
2. Size of Memory Location (if Size of Location is not given in question,
then by default we take it as 1Byte (1B) as our system is Byte Addressable.)*
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Now, Size of memory = no. of memory locations x size of memory location
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= 214 x 1B = 24 x 210 x 1B = 16 x 1K x 1B = 16KB (ans)
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Q3. An address of 22 bits can support memory of how much size, when the size
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of memory location is 2B?
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Sol:
Given Data:
No. of address bits (n) = 22bits
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Type 02 Numerical: Space/Memory to Address Translation
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*Note: As we have seen above, the total size of memory depends upon two
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values:
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1. Number of locations the memory has (2n); where n (to find) is no of
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address bits
2. Size of Memory Location (if Size of Location is not given in question,
then by default we take it as 1Byte (1B) as our system is Byte Addressable.)*
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Size if memory = 32KB
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Size of memory location = 1B (by default, as it’s not given in question)
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Now, Size of memory = no. of memory locations x size of memory location
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Therefore,
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no. of memory locations (2n) = size of memory/size of memory location
= 32KB/1B = 32K = 25 x 210 = 215
Therefore n = 15bits (ans)
Q3. A memory of 256 MB can support an address of how many bits?
Sol:
Given Data:
Size if memory = 256MB
Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 256MB/1B = 256M = 28 x 220 = 228
Therefore n = 28bits (ans)
Q4. A memory of 16 GB can support an address of how many bits, when the size
of location is 4B?
Sol:
Given Data:
Size if memory = 16 GB
Size of memory location = 4B
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
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= 16 GB/4B = 4G = 22 x 230 = 232
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Therefore n = 32bits (ans)
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Types 03 Numericals: To find number of Pages (Sec Memory) and
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number of Frames (Main Memory) from Logical Address, Physical
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Address and Page Size.
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Steps to solve the numerical
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1. Find the size of Secondary Memory using given Logical Address (LA)
bits (numerical type 01)
2. Find the size of Main Memory using given Physical Address (PA) bits
(numerical type 01)
3. Using given Page Size, find the bits of instruction offset (d) of Logical
Address and Physical Address. (d is same in both address)
4. Using d, find the bits of p in Logical Address and f in Physical Address
5. Using the bits of p and d, find the number of pages and frames.
Q1. When LA= 24 bits, PA = 16bits and Page Size= 1KB, find the total
number of pages and frames in the system.
Sol.
Step 01: To find the size of Secondary Memory using given Logical
Address (LA) bits.
No. of LA bits (n) = 24bits
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= 216 x 1B = 26 x 210 x 1B = 64 x 1K x 1B = 64KB
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Step 03: Using given Page Size, find the bits of instruction offset (d) of
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Logical Address and Physical Address. (d is same in both address)
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Page Size (size of memory) = 1KB
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Size of memory location = 1B (by default, as it’s not given in question)
Now, Size of memory = no. of memory locations x size of memory location
Therefore,
no. of memory locations (2n) = size of memory/size of memory location
= 1KB/1B = 1K = 210
Therefore n = 10bits
i.e. d = n = 10bits
now the value of d in LA and also in PA is same i.e. 10bits
Step 04: Using d, find the bits of p in Logical Address and f in Physical
Address
w.k.t, LA= p+d
Therefore, p= LA-d = 24-10 bits = 14 bits
Also, w.k.t, PA= f+d
Therefore, f= PA-d = 16-10 bits = 6 bits
Step 05: Using the bits of p and d, find the number of pages and frames.
Now, p=14 bits
Therefore, no of pages (no. of locations) = 2p = 214 = 24 x 210 = 16K no of pages
approx. (ans)
Now, f=6 bits
Therefore, no of frames (no. of locations) = 2f = 26 = 64 no of frames approx.
(ans)
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Q2. When LA= 33 bits, PA = 24bits and Page Size= 2KB, find the total number
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of pages and frames in the system.
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Sol.
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Step 01: To find the size of Secondary Memory using given Logical
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Address (LA) bits.
No. of LA bits (n) = 33bits
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i.e. d = n = 11bits
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now the value of d in LA and also in PA is same i.e. 11bits
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Step 04: Using d, find the bits of p in Logical Address and f in Physical
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Address
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w.k.t, LA= p+d
Therefore, p= LA-d = 33-11 bits = 22 bits
Also, w.k.t, PA= f+d
Therefore, f= PA-d = 24-11 bits = 13 bits
Step 05: Using the bits of p and d, find the number of pages and frames.
Now, p=22 bits
Therefore, no of pages (no. of locations) = 2 p = 222 = 22 x 220 = 4M no of pages
approx. (ans)
Now, f=13 bits
Therefore, no of frames (no. of locations) = 2f = 213 = 23 x 210 = 8K no of frames
approx. (ans)
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Types 04 Numerical: To find the total space/memory wasted in
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maintaining the page table for all processes in the system or a
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single process in the system (*NOT IN SYLLABUS* only for
GATE)
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Refer https://www.youtube.com/watch?v=NMtHuK2i2dc
Types 05 Numerical: To find the size of process using the size of
Page Table system (*NOT IN SYLLABUS* only for GATE)
Refer https://www.youtube.com/watch?v=gRzwXIRG1Dc
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Paging Diagram
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Translation Lookaside Buffer (TLB) in Paging ES
In Operating System (Memory Management Technique: Paging), for each process page table
will be created, which will contain Page Table Entry (PTE). This PTE will contain information
like frame number (The address of main memory where we want to refer), and some other
useful bits (e.g., valid/invalid bit, dirty bit, protection bit etc.). This page table entry (PTE) will
tell where in the main memory the actual page is residing.
Now the question is where to place the page table, such that overall access time (or reference
time) will be less.
The problem initially was to fast access the main memory content based on address generated
by CPU (i.e. logical/virtual address). Initially, some people thought of using registers to store
page table, as they are high-speed memory so access time will be less.
The idea used here is, place the page table entries in registers, for each request generated from
CPU (virtual address), it will be matched to the appropriate page number of the page table,
which will now tell where in the main memory that corresponding page resides. Everything
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seems right here, but the problem is register size is small (in practical, it can accommodate
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maximum of 0.5k to 1k page table entries) and process size may be big hence the required page
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table will also be big (let’s say this page table contains 1M entries), so registers may not hold
all the PTE’s of Page table. So this is not a practical approach.
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To overcome this size issue, the entire page table was kept in main memory. But the problem
here is two main memory references are required:
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1. To find the frame number
2. To go to the address specified by frame number
To overcome this problem a high-speed cache is set up for page table entries called a
Translation Lookaside Buffer (TLB). Translation Lookaside Buffer (TLB) is nothing but a
special cache used to keep track of recently used transactions. TLB contains page table entries
that have been most recently used. Given a virtual address, the processor examines the TLB if
a page table entry is present (TLB hit), the frame number is retrieved and the real address is
formed. If a page table entry is not found in the TLB (TLB miss), the page number is used to
index the process page table. TLB first checks if the page is already in main memory, if not in
main memory a page fault is issued then the TLB is updated to include the new page entry.
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4. Corresponding frame number is retrieved, which now tells where in the main memory
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page lies.
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5. The TLB is updated with new PTE (if space is not there, one of the replacement
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technique comes into picture i.e. either FIFO, LRU or MFU etc.).
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Effective memory access time (EMAT): TLB is used to reduce effective memory access
time as it is a high speed associative cache.
EMAT = h*(c+m) + (1-h)*(c+2m) where h*(c+m) refers t0 TLB HIT and (1-h)*(c+2m)
refers to TLB MISS
where, h = hit ratio of TLB
m = Memory access time
c = TLB access time
Numerical on TLB
Q1. If memory access time is 400µs and TLB access time is 50µs and TLB hit%
is 90%. Find the average instruction access time and effective memory access
time.
Sol.
Given:
m= 400µs, c= 50µs, h= 0.9
If TLB is not present,
Then Total memory access time = 2 x m = 2 x 400µs = 800 µs (*solve only if
asked*)
If TLB is present,
Then Effective memory access time (EMAT) = h*(c+m) + (1-h)*(c+2m)
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Difference between Segmentation and Paging
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Sr. Key Paging Segmentation
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No.
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Memory Size In Paging, a process address In Segmentation, a process
space is broken into fixed address space is broken in
1
sized blocks called pages. varying sized blocks called
sections.
Data Storage Page table stores the page Segmentation table stores the
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data. segmentation data.
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UNIT 04
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Page Replacement Algorithm – Numerical
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Q1. Consider the following page reference string 3,2,1,3,4,1,6,2,4,3,4,2,1,4,5,2,1,3,4. How
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many page faults would occur assuming three frames are made available for FIFO, LRU, and
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optimal page replacement algorithm?
Frames 3 2 1 3 4 1 6 2 4 3 4 2 1 4 5 2 1 3 4
0 3 3 3 3 4 4 4 4 4 3 3 3 3 3 5 5 5 5 4
1 2 2 2 2 2 6 6 6 6 4 4 4 4 4 2 2 2 2
2 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 3 3
Page * * * * * *
Hit
- Page which has not been used for the longest time is replaced.
FRAME 3 2 1 3 4 1 6 2 4 3 4 2 1 4 5 2 1 3 4
0 3 3 3 3 3 3 6 6 6 3 3 3 1 1 1 2 2 2 4
1 2 2 2 4 4 4 2 2 2 2 2 2 2 5 5 5 3 3
2 1 1 1 1 1 1 4 4 4 4 4 4 4 4 1 1 1
Page * * * * *
Hit
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Optimal Page Replacement Algorithm
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- Replace the page that will not be used for the longest time.
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- Has the lowest page fault.
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FRAME 3 2 1 3 4 1 6 2 4 3 4 2 1 4 5 2 1 3 4
0 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5
1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3
2 1 1 1 1 6 6 6 3 3 3 1 1 1 1 1 1 4
Page * * * * * * * * *
Hit
1
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Q2. Consider the following page reference string 1,2,3,4,2,1,5,6,2,1,2,3,7,6,3,2,1,2,3,6. How
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many page faults would occur assuming three frames are made available for FIFO, LRU, and
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optimal page replacement algorithm?
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FIFO: First In First Out Page Replacement Algorithm
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- Oldest page in the memory will be replaced.
- Has the highest page fault rate.
Frames 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
0 1 1 1 4 4 4 4 6 6 6 6 3 3 3 3 2 2 2 2 6
1 2 2 2 2 1 1 1 2 2 2 2 7 7 7 7 1 1 1 1
2 3 3 3 3 5 5 5 1 1 1 1 6 6 6 6 6 3 3
Page * * * *
Hit
- Page which has not been used for the longest time is replaced.
FRAME 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
0 1 1 1 4 4 4 5 5 5 1 1 1 7 7 7 2 2 2 2 2
1 2 2 2 2 2 2 6 6 6 6 3 3 3 3 3 3 3 3 3
2 3 3 3 1 1 1 2 2 2 2 2 6 6 6 1 1 1 6
Page * * * * *
Hit
- Replace the page that will not be used for the longest time.
- Has the lowest page fault.
-
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FRAME 1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2 1 2 3 6
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0 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 6
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1 2 2 2 2 2 2 2 2 2 2 2 7 7 7 2 2 2 2 2
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2 3 4 4 4 5 6 6 6 6 6 6 6 6 6 1 1 1 1
Page * * * * * * * * *
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Hit
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Total Page Hit = 9
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Q3. How many page faults would occur for the following reference string for four page
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frames using LRU and FIFO algorithms: 1,2,3,4,5,5,3,4,1,6,7,8,7,8,9,7,8,9,5,4,5,4,2.
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FIFO: First In First Out Page Replacement Algorithm
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- Oldest page in the memory will be replaced.
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- Has the highest page fault rate.
Frames 1 2 3 4 5 5 3 4 1 6 7 8 7 8 9 7 8 9 5 4 5 4 2
0 1 1 1 1 5 5 5 5 5 5 5 8 8 8 8 8 8 8 8 8 8 8 2
1 2 2 2 2 2 2 2 1 1 1 1 1 1 9 9 9 9 9 9 9 9 9
2 3 3 3 3 3 3 3 6 6 6 6 6 6 6 6 6 5 5 5 5 5
3 4 4 4 4 4 4 4 7 7 7 7 7 7 7 7 7 4 4 4 4
Page * * * * * * * * * *
Hit
- Page which has not been used for the longest time is replaced.
Frames 1 2 3 4 5 5 3 4 1 6 7 8 7 8 9 7 8 9 5 4 5 4 2
0 1 1 1 1 5 5 5 5 5 6 6 6 6 6 6 6 6 6 5 5 5 5 5
1 2 2 2 2 2 2 2 1 1 1 1 1 1 9 9 9 9 9 9 9 9 9
2 3 3 3 3 3 3 3 3 7 7 7 7 7 7 7 7 7 4 4 4 4
3 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 2
Page * * * * * * * * * *
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Q4. Consider a main memory with five page frames and the following sequence of page
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references: 3, 8, 2, 3, 9, 1, 6, 3, 8, 9, 3, 6, 2, 1, 3. which one of the following is true with
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respect to page replacement policies First-In-First-out (FIFO) and Least Recently Used
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(LRU)?
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A. Both incur the same number of page faults
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B. FIFO incurs 2 more page faults than LRU
C. LRU incurs 2 more page faults than FIFO
D. FIFO incurs 1 more page faults than LRU
Q7. Consider the following page reference string 5,4,3,2,1,4,3,5,4,3,2,1,5. How many page
faults would occur assuming three frames are made available for FIFO page replacement
algorithm? Would the FIFO page replacement algorithm suffer from Belady’s Anomaly if
number of frames increase from three to four? Justify.
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OS UNIT-5
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