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VLSI Design & Verification Course

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SHIREESHA.R
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54 views4 pages

VLSI Design & Verification Course

Uploaded by

SHIREESHA.R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Professi onal Devel opm ent Course on VLSI Design & Verificati on (Full-time)

APRICUS SYSTEMS offers the 15-week full time (Monday - Friday, 9am - 6pm) Professional
Development Course for recent graduates and post-graduates in Electronics / Electrical /
Telecommunication engineering. This program is specifically designed with an objective to provide
a sound platform for the students and prepare them for a successful career in the fields of VLSI
Design and verification.

The APRICUS SYSTEMS offers the right blend of classroom teaching, quality hands-on training
from 'concept-to- project', covering design methodology using industry standard tools and practices.
The course includes a project work as well.

Placement assistance is provided to those who complete all modules of this course and a pre -
placement test.

Course Duration: 15 Weeks Course Structure and Outline


Mod. Module Title What You Learn

P  Introduction to VLSI
(15 Days) Advanced Digital
System Design
 VLSI Design Flow

 Introduction to Digital Electronics

 Universal Logic Elements

 Combinational Circuits - Design and Analysis

 Arithmetic Circuits

 Data processing Circuits

 Sequential Circuits - Design and Analysis

 Latches and Flip flops

 Shift Registers and Counters

 Memories – ROM and RAM

 Finite State Machine & Sequence detection


 Introduction To HDL

 Design methodology

C1  Logical operators
Verilog
(15 Days)
 Data types

 System tasks

 Compiler directives

 Gate level modeling

 Data flow modeling

 Behavioral modeling

 Blocking and Non-Blocking assignments

 Time scale precession

 Conditional statements

 Delays

 Tasks and functions

 Finite State Machine


 System Verilog Vs Verilog

 Data Types

 Arrays

C2  Procedural Statements and Control Flow


System Verilog
(45 Days)
 Processes threads

 Tasks and Functions

 Classes

 Randomization

 Constraints

 IPC

 Assertions

 Coverage

 Verification process and Testbench


 UVM hierarchy

 Sequence item
C3 UVM
(30 Days)  Sequence

 Sequencer

 Driver Sequencer Handshake

 Driver

 Config DB

 Agent

 Phases

 Monitor

 Scoreboard

 Environment

 Test

 Top

 TLM Ports
Integrated
in the Course Project Design and Verification
course

Note:
1) The contents listed above is a representative outline and is subject to change at short notice in
compliance with the current industry demands
2) Legend: P# - Primer Module, C# - Core Module

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