Design of Sequential Circuits
Dr. P Sasipriya
Associate Professor
Introduction
Block diagram of Sequential Circuit
Inputs Outputs
Combinational Circuits
Memory
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Memory
• Cross coupled inverter holds the data.
• When we want to write a new data we can go for force writing by
implementing 2 input gate with external input.
• External input will change the data stored in latch
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Latches vs Flip-flop
There are two types of memory elements based on the type of
triggering that is suitable to operate it.
➢Latches
➢Flip-flops
Latches operate with enable signal, which is level sensitive.
Whereas, flip-flops are edge sensitive.
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NOR based SR
S R Q Q’(t)
R
Q 1 0 1 0
0 1 0 1
0 0 Q Q’
1 1 Indeterminate
Q’
S
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SR latch using compound CMOS logic
R
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NAND based SR Latch
S’ S’ R’ Q Q’(t)
Q
1 0 0 1
0 1 1 0
1 1 Q Q’
0 0 Indeterminate
R’ Q’
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SR Latch with Enable/ SR Flip-Flop
E S R Q Q’
1 1 0 1 0
1 0 1 0 1
1 0 0 Q Q’
1 1 1 Indeterminate
0 X X Q Q’
E is Enable signal activated with Logic ‘1’.
When it is logic ‘0’ , the latch is deactivated and maintains the same state.
E can also be Clock Pulse and this latch can be called as positive level triggered Latch
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SR Flipflop using NAND gates
E S R Q Q’
1 1 0 1 0
1 0 1 0 1
1 0 0 Q Q’
1 1 1 Indeterminate
0 X X Q Q’
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D latch
E’ D Q Q’(t)
0 0 0 1
0 1 1 0
1 X Q Q’
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Thank You
