MEMORY
MANAGEMENT
Monali Mahajan
Department of Computer Engg.
K.K.Wagh Institute of Engineering Education & Research
Nashik
Objectives
To study memory management feature of 80386DX
Outcomes
To make use of memory management features of 80386DX
Memory Management
Prerequisites
Memory Organization
The physical memory of an 80386 system is organized as a sequence of 8-bit bytes
Each byte is assigned a unique address that ranges from zero to a maximum of 2 32-1
The model of memory organization can range between the following extremes:
1. A "flat" address space consisting of a single array of up to 4 gigabytes
2. A segmented address space consisting of a collection of up to 16,383 linear address spaces of
up to 4 gigabytes each
Memory Management
Contd…
The "Flat" Model
In a "flat" model of memory organization, has a single array of up to 232 bytes
A pointer into this flat address space is a 32-bit ordinal number that may range from 0 to 232-1
Memory Management
Contd…
The Segmented Model
The address space is viewed as by an applications program is a much larger space of up to 2 46 bytes
A pointer into this flat address space is a 32-bit ordinal number that may range from 0 to 232-1
The processor maps the 64 terabyte logical address space onto the physical address space by the
address translation
Applications programmers view the logical address space of the 80386 as a collection of up to
16,383 one-dimensional subspaces, each with a specified length
Each of these linear subspaces is called a segment
Segment sizes may range from one byte up to a maximum of 2 32 bytes
Memory Management
Contd…
A complete pointer in this address space consists of two parts:
1. A segment selector, which is a 16-bit field that identifies a segment
2. An offset, which is a 32-bit ordinal that addresses to the byte level within a segment
Memory Management
Memory Management
The 80386 transforms logical into physical address in two steps:
1. Segment translation in which a logical address are converted to a linear address
2. Page translation in which a linear address is converted to a physical address
Memory Management
Segment Translation
Logical address into a linear address translation
Memory Management
Contd…
To perform this translation, the processor uses the following data structures:
1. Descriptors
2. Descriptor tables
3. Selectors
4. Segment Registers
Memory Management
Descriptors
The segment descriptor provides the processor with the data it needs to map a logical
address into a linear address
Memory Management
Contd…
Segment-descriptor contains following fields :
BASE: Defines the location of the segment within the 4 gigabyte linear address space
LIMIT: Defines the size of the segment. The processor interprets the limit field in one of two
ways, depending on the setting of the granularity bit:
1. In units of one byte, to define a limit of up to 1 megabyte
2. In units of 4 Kilobytes, to define a limit of up to 4 gigabytes
Granularity bit: Specifies the units with which the LIMIT field is interpreted
TYPE: Distinguishes between various kinds of descriptors
DPL (Descriptor Privilege Level): Used by the protection mechanism
Segment-Present bit: If this bit is zero, the descriptor is not valid for use in address transformation
Accessed bit: The processor sets this bit when the segment is accessed
Memory Management
Descriptor Tables
Segment descriptors are stored in two kinds of descriptor
table
1. The global descriptor table (GDT)
2. A local descriptor table (LDT)
A descriptor table is a memory array of 8-byte entries that
contain descriptors
A descriptor table is variable in length and may contain up
to 8192 (213) descriptors
The first entry of the GDT (INDEX=0) is not used by
the processor
The processor locates the GDT and the current LDT in
memory by means of the GDTR and LDTR registers
Memory Management
Selectors
The selector portion of a logical address identifies a descriptor by specifying a descriptor
table and indexing a descriptor within that table
The selector contains the following fields:
1. Index: Selects one of 8192 descriptors in a descriptor table
2. Table Indicator: Specifies to which descriptor table the selector refers
3. Requested Privilege Level: Used by the protection mechanism
Memory Management
Segment Registers
The 80386 stores information from descriptors in segment registers
Memory Management
Objective and Outcomes
Objective
Memory paging mechanism
Outcomes
Exhibit skill of assembly language programming for the application
Classify processor architectures
Content
Paging
Linear to physical address translation
Paging mechanism
Page Directory Base Register
Page table
Page Table Entry
Translation Lookaside Buffer(TLB)
Paging
The address space may be large physical address space, or paging may be used to simulate
using a small amount of RAM and some disk storage
In paging, address generated by segment address translation is not valid
Linear address is translated into its corresponding physical address. The process is called “page
translation”
Component of paging mechanism
Page Directory
Page table
Page Frame or Page
4KB
Linear to physical address translation
Segment address translation unit converts logical address to 32 bit linear address
31 22 21 12 11 0
DIR PAGE Field OFFSET Field
There are 3 fields in linear address
DIR i. e. Directory Field(10 bits): Used to lookup into directory table
PAGE Field(10 Bits): Used to lookup into Page Table
OFFSET Field(12 Bits): Used to select a location from page frame
Paging mechanism
31 22 21 12 11 0
DIR PAGE Field OFFSET Field
PAGE TABLE
PAGE DIRECTORY
PAGE FRAME
PG TBL ENTRY PHYSICAL
DIR ENTRY ADDRESS
CR3
Paging mechanism (Example)
31 22 21 12 11 0
DIR PAGE Field OFFSET Field
PAGE TABLE
PAGE DIRECTORY
PAGE FRAME
BOOK ACTUAL LINE
PG TBL ENTRY SUB
DIR ENTRY CHAPTE POINT PHYSICAL
R ADDRESS
CR3
Page Directory Base Register
CR2 is used to store the 32 bit linear address of page fault
CR3 (page Directory Physical Base Address Register) stores the physical starting address of
Page Directory
Page table
A page table is simply an array of 32-bit page specifiers
Upper 20 bit page frame address is concatenated with the lower 12 bits of the linear address to
form the physical address
Page tables can be shared between tasks and swapped to disks.
Page Table Entry
31 12 11 0
U R
PAGE FRAME ADDRESS 31…12 AVAIL 0 0 D A 00 / / P
S W
P i. e. Present
If the bit is set, the page is actually in physical memory at the moment
If P=0 in either level of page tables when an attempt is made to use a page-table entry for address translation, the
processor signals a page exception
R/W i. e. Read/ Write
If the bit is set, the page is read/write. Otherwise when it is not set, the page is read-only
Page Table Entry
U/S i. e. User/Supervisor
If set page can be accessed by all
If not supervisor can access it
D i. e. Cache Disabled
The processor sets the dirty bit in the second-level page table to one before a write to an address covered by that
page table entry
The dirty bit in directory entries is undefined
A i. e. Access
The processor sets the corresponding accessed bits in both levels of page tables to one before a read or write
operation to a page
Page Table Entry
AVAIL(Available)
These bits are available with user
Page frame address
Physical address of page table
