TARUR, eptt- of cCE, ETE- Nov.

2),2023 s ee, (B)

DsP TiME: 2h% 23 Minnt, Ma Mank,s

H(z)= + + L + + |
) fnd the latia ealiahim
H(e)= -2

Q.2 Tranfw the uto a

lanyh Ms (ogns) -2
+
kysten H()=
I-+
potumine the sttestone t )=)
8y. fnd the
ady)2
DET.

6-s4) find the bodes bonhan md Atfawoty

a ffth rde

it) =()" (n43)

1h) u
 MALAVIYANATIONAL INSTITUTE OF TECHNOLOGY JAIPUR302017
B.Tech. DEGREE VSEMESTER (ECE), End Term Examination, 2d December, 2023
Roll No..22NERSH..
SUB. CODE &TITLE: ECT306, VLSITesting & Testability
DATE: 2.12.2023 TIME: 11:00 PM to 01:30 PM MAX. MARKS: 50

Note- Please solve all parts of a question in continuation only.

1 Write short notes on any four (4.5X4)
a SCOAP Measures
bCheck point theorem 18
&Fault simulations techniques
d. Critical path tracing
e. PODEM Algorithm
2 Use 9 Value method for test pattern generation for vS-a-0 fault in the
circuit following 8

V
W & 1D o
+
C1
H
-Z
CK 4
b What is the need of scan chain based testing?
C. HowWa fast speed scanchain testing clock can be generated. 4
3 a, Use LFSR for signature analysis for the following single
11010101
input bit pattern 7

P()= l+x*+a*+
b, Discuss memory fault models and their testing methods. 5
Write short notes on any one
1. Test pattern generation for BIST
Compression techniques for BIST(Ypes)
3. Explain BIST
general architecture and its working.
 Malaviya National Institute of Technology, Jaipur
Department of Electronics and Communication Engineering
End Term Examination
ECT303: Optical Communication Systens B.Tech., VSem.
Duration: 150 minutes, Full Marks: 50 28-11-2023, 11:00 AM to 01:30 PM
Answer all Qucstions. Make suitable assumptions if required.
1. Discuss the significance of the threshold condition for LASER action (8]
ruby laser contains a crystal of length 3 cm with a refractive index of 1.75. The peak emission
wavelength from the device is 0.60 m. Deternine the nunber of longitudinal modes and their froqucncy
separation. (5]
3. Discuss the parameters (Quantum efficiency, Responsivity, Long-wavelength cutoff) that define the per
formance of the photodetector. 6)
4. Explain the construction and working of PIN photodiode l4l
5. Aphotodiode has aquantum efficiency of G0% when photons of energy 2 x10-9 Jare incident upon
it.obtain
at what wavelength is the photodiode operating? Calculate the incident optical power required to
a photoc°rent of 3 uA. also, calculate the Responsivity. (2+2+1]

6. Discuss the effect of different types of noises n optical receivers. [101

7. Discuss the ccessity of wavelength couversio escribe differcnt types of waveleugth converters. (4+8
PoECS Fifth Semester (ECE)End Term Examination
Subject: DigitalCommunication System (ECT 303)
FDate of Examination: 20/11/ 2023 Max Marks - 60 Time- 2.30 Hours
Attempt allthe questions in sequence preferably
Q.1. Explain briefly:
a) The term matched filter is often used synonymously with correlator receiver. How is
that possible when
their mathematical operations are different. Explain
b)List the benefits and drawbacks of Nyquist pulse shaping.
) Define jamming margin?. Specify the significance of jamming margin equal to 18 dB.
d} What is the difference between fast hopping and slowhopping FHSS systems? Explain with diagram
e) Draw a correlation type demodulator that decomposes the received signal and the noise into N
dimensional vectors. 2x5
Q2 a) Explain MSK modulation by drawing proper waveforms of it and describe a method to recover the
baséband signal in MSK. 6
b) A 1000 bps binary information data signal is required to be transmitted in half duplex mode using
binary FSK technique. If the separation between two carrier frequencies is 3000 Hz, determine the baud and
the minimum bandwidth of the FSK signal. 4
Q.3a) Explain the DS-CDMA and FH spread spectrum systems in detail with the help of block diagrams.
4
b) Apseudo random (PN)Sequence is generated using a feedback K-shift register with four number of
memory elements. The chip rate is 10' chips per second. Find the PN sequence period and the chip duration
of the PN sequence generated. 3
An FHSS system employs a total bandwidthof 400 MHz and an individual channel bandwidth of 100
3
Hz What is the minimum number of PN bits required for each frequency hop?.
Q.4.a) Derive a detailed expression for calculating the impulse response of amatched filter. 5
b) The received signal in a binary communication System that employs antipoal signal is
r() - s() +n() where s) is drawn below and n(t) is AWGN with power spectral density Ng2 W/Hz.
A
S(t)

2 >t
() Sketch the impulse response of the filter matched to s(t). (ii) Sketch the output of the matched filter to
the input s(t). (iii) Determine the BER asa function of Aand No. 5
Q.5. a).Explain the maximal length linear shift register method to generate PN sequence and discuss the
basi properties of linear shift register sequences.
b) Explain the basic principle and structure of arate receiver with the help of asuitable diagram. What
are the advantages and disadvantages of RAKE receivcr used in CDMA phone receiver? 5
Q.6 a) What is a Zero Forcing Equalizer?. Derive the appropriate mathematical expressions ofits
tap gains by following the equalizer analysis. 5
b) It is desired that the information data rate of 30.9 kbpS needto be propagated through a 3.1 KHz band
noise free communications channel. Determine the optimum number. of signaling elements per bit to be
transmitted to achieve it. 5
 Malaviya National Institute of Technology Jaipur
Department of ECE
END Semester Examination

All the Questions are Digital CMOS IC (ECT 304) Total Marks: 50
Compulsory Time: 2 hrs. and 30 minutes

Derive the expression of dissipated power in CMOS

inverter. Also, write theCOT 5
expression of power delay product.
2. Evaluate the oxide capacitances of MOSFET in different region of
operations. COT
Also, draw the corresponding oxide capacitance vs.
gate to source voltage
characteristics by indicating different region of opcrations.
3. Draw the stick diagram and layout of 3 input CMOS
NAND gate. CO4 3+3
4. Design a full adder using minimum number of CMOS inverter logic. CO3
5. (Design and explain the operation of SR Latch Circuit. CO3 4+4
(b) Write a short note on Master Slavebased JK- Flip Flop.
6. (a) Write a short note on pipelined NORA CMOS system.
(bUsing Transmission gate design a 4:l multiplexcr circuit. CO3+C023+3+4
(c) Explain the behavior offbistable element with proper circuit
diagram and VTC
curve. A lso, show the stable and unstable points on VTC.
7 Design acarTy look ahead adder circuit using domino CMOS logic.
CO4
8. Write a short note on SRAM and DRAM.
COS 4
9. Consider asymmetric CMOS inverter with supply voltage (VDD) = 5 Vand
C02 2
thresholdvoltagc (Vn) = 0.7 V. Estimate thc valucs of high state noisc
margin
(NMH) and low state noise margin (NML).
 Malaviya National Institute ofTechnology Jaipur
Department of ECE
MID Semester Examination (Date: 01/10/2022)
Digital CMOS IC(ECT 304) Total Marks: 30
Allthe Questions are Compulsory Time: 1 hrs. and 30 minutes

Show schematically the opcration of MOSFET under accumulation, depletion, and CO1 5
inversion modes. IDraw the corresponding energy band diagrams.
Evaluate the oxide capacitances of MOSFET in different region of operations. Also, CO1
Draw the corresponding oxide capacitance vs. gate to source voltage
characteristics
by indicating different region of operations.
3 Explain the operation of CMOS inverter and drawits voltage transfer characteristics CO3 4+1
by indicating different regions. Define the terms Von, VoL., ViL, VIH.
4, (a) Derive the expression of high to low propagation delay for CMOS inverter circuit. CO2
4+1
(b Consider a symmetric CMOS inverter with supply voltage (VDD) = 5 V and
threshold voltage (Vn) =0.7 V. Estimate the values of high state noise margin (NM1u)
and low state noise margin (NML).

5. Design the CMOScircuit for the following two cases: CO3 5

Case 1: The output of atwo input logic gate is low logic only when both inputs are
high logic.

Case 2: The output of a two input logic gate is low logic if both the inputs
are either
low or high logic.
6. sá) Design a 4:1 multiplexer using
transmission gate. CO3+CO1 3+2
(b The drain and gate terminal of N-MOSFET is shorted such that gate to source
voltage (Vgs) isequal to drain to source voltage (Vas) and
threshold voltage (Vi) 0.5
V. The drain current (lá) is 0.5 mA at
Vos 1 V. Estimate the value of Ia for Vgs =1.5
V.