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CALD Lab Assignment # 4

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20 views3 pages

CALD Lab Assignment # 4

Uploaded by

mchips2000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Bahria University, Islamabad

Department of Software Engineering

CALD Lab (Fall-2024)


Teacher: Engr. Aamir

Student : Muhammad Jibran


Enrollment : 01-131232-062

Lab: 4
Date: 10-10-2024

Comments:

Signature
Muhammad Jibran CALD Engr. Aamir
01-131232-062 Lab # 04 Dept of SE, BUIC

Lab No: 4 - Implementation of a Half Adder and a Full Adder using Gates
Introduction
Design and verify the logic circuit of Half adder and Full adder using logic gates.
Tools Used
Digital Logic Electrical Trainer

Lab Task:
Screenshot

Truth Tables:
a. Half Adder:

Input Output

A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

2
Muhammad Jibran CALD Engr. Aamir
01-131232-062 Lab # 04 Dept of SE, BUIC

b. Full Adder:

Input Output

A B C Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Conclusion
From this lab, we learnt about full adders and half adders and how they work.

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