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Verilog Modules for Logic Design

Verilog notes of and module operation for alu

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RRSS2023
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10 views3 pages

Verilog Modules for Logic Design

Verilog notes of and module operation for alu

Uploaded by

RRSS2023
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

---------------

module andd(

output reg y,

input a,b

);

always @(a&&b)begin

if(a==1'b1 && b==1'b1)begin

y=1'b1;

end

else begin

y=1'b0;

end

end

endmodule

--------------

module tb;

reg a,b;

wire y;

andd andd1(y,a,b);

initial

begin

$dumpfile("file.vcd");
$dumpvars(1);

a=0;b=0;

#5

a=0;b=1;

#5

a=1;b=0;

#5

a=1;b=1;

#5

$finish;

end

endmodule
module Barrel_Shifter (

input wire [4:0] shift_val,

input wire [31:0] data_in,

input wire [1:0] shift_ctrl,

output wire [31:0] shifted_out

);

wire [31:0] t1, t2, t3;

assign t1 = (shift_ctrl[0] == 1'b0) ? ({data_in[31:shift_val], {shift_val{1'b0}}}) : // Logical


Left

({{shift_val{1'b0}}, data_in[shift_val-1:0]}); // Logical Right

assign t2 = (shift_ctrl[1:0] == 2'b00) ? t1 : // Unsigned (Logical)

($signed(temp1) >>> shift_val); // Signed (Arithmetic)

assign shifted_out = (shift_ctrl[1] == 1'b0) ? t2 : // Unsigned

({t2[31], t2[31:1]}); // Signed

endmodule

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