CS42L52 F2m

DRAFTv1
3/1/13 CS42L52
Low-Power, Stereo CODEC with Headphone and Speaker Amps
Stereo CODEC Class D Stereo/Mono Speaker Amplifier
 High Performance Stereo ADC and DAC  No External Filter Required
– 99 dB (ADC), 98 dB (DAC) Dyn. Range (A-wtd)  High-power Stereo Output at 10% THD+N
– -88 dB THD+N – 2 x 1.00 W into 8  @ 5.0 V
 Flexible Stereo Analog Input Architecture – 2 x 550 mW into 8  @ 3.7 V
– 4:1 Analog Input MUX – 2 x 230 mW into 8  @ 2.5 V
– Analog Input Mixing  High-power Mono Output at 10% THD+N
– Analog Passthrough with Volume Control – 1 x 1.90 W into 4  @ 5.0 V
– Analog Programmable Gain Amplifier (PGA) – 1 x 1.00 W into 4  @ 3.7 V
– 1 x 350 mW into 4  @ 2.5 V
 Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression  Direct Battery-powered Operation
– Programmable Threshold and Attack/Release – Battery Level Monitoring and Compensation
Rates  81% Efficiency at 800 mW
 Dual MIC Inputs  Phase-aligned PWM Output Reduces Idle
– Differential or Single-ended Channel Current
– +16 dB to +32 dB with 1-dB step Mic Pre-  Spread Spectrum Modulation
Amplifiers  Low Quiescent Current
– Programmable, Low-noise MIC Bias Levels Stereo Headphone Amplifier
 Digital Signal Processing Engine  Ground-centered Outputs
– Bass and Treble Tone Control, De-emphasis – No DC-Blocking Capacitors Required
– Master Vol. and Independent PCM SDIN + ADC – Integrated Negative Voltage Regulator
SDOUT Mix Volume Control  High-power Output at -75 dB THD+N
– Soft-Ramp and Zero-Cross Transitions – 2 x 23 mW Into 16  @ 1.8 V
– Programmable Peak-detect and Limiter – 2 x 44 mW Into 16  @ 2.5 V
– Beep Generator w/Full Tone Control (Features continued on page 2)
+1.65 V to +2.63 V +1.65 V to +2.63 V +1.60 V to +5.25 V

Analog Supply Digital Supply Battery
Summing Battery Level Monitoring & Compensation
Programmable + Stereo/Mono
-
Gain Amps
Pulse-Width Full-Bridge
+
Modulator Speaker

-
(PWM) Outputs
ALC
Beep
Class D Amps
1
Left 2 Left HP/Line
3
Inputs 4 Multi-bit Volume, Mono
Mono mix,
Output
1  ADC Swap, Mix
Limiter, Bass,
Treble Adjust
Right 2 Multi-bit
Inputs 3
4
 DAC Ground-Centered
Amps
HPF Right HP/Line

 ALC Output
Speaker/HP
+16 to +32 dB Diff./
S.E. MIC Pre-Amps Control Port Serial Audio Port -VHP +VHP
Switch
MIC Bias Level Shifter Charge Pump +1.65 V to +2.63 V

Headphone Supply
Selectable +1.65 V to +2.63 V

+1.65 V to +3.47 V 2 Reset Serial Audio
I C Control Analog Supply
Bias Voltage Interface Supply Input/Output
Copyright  Cirrus Logic, Inc. 2013 MAR ’13

(All Rights Reserved)
http://www.cirrus.com DS680F2
3/1/13
CS42L52
System Features General Description
 12, 24, and 27 MHz Master Clock Support in The CS42L52 is a highly integrated, low-power stereo CO-
Addition to Typical Audio Clock Rates DEC with headphone and Class D speaker amplifiers. The
 High-performance 24-bit Converters CS42L52 offers many features suitable for low-power, porta-
– Multi-bit Delta-Sigma Architecture ble system applications.
– Very Low 64Fs Oversampling Clock Reduces The ADC input path allows independent channel control of a
Power Consumption number of features. Input summing amplifiers mix and select
line-level and/or microphone-level inputs for each channel.
 Low-power Operation The microphone input path includes a selectable programma-
– Stereo Analog Passthrough: 10 mW @ 1.8 V ble-gain pre-amplifier stage and a low-noise MIC bias voltage
– Stereo Playback: 14 mW @ 1.8 V supply. A PGA is available for line or microphone inputs and
– Stereo Rec. and Playback: 23 mW @ 1.8 V provides analog gain with soft-ramp and zero-cross transi-
tions. The ADC also features a digital volume control with soft
 Variable Power Supplies ramp transitions. A programmable ALC and Noise Gate mon-
– 1.8 V to 2.5 V Digital and Analog itor the input signals and adjust the volume levels
– 1.6 V to 5 V Class D Amplifier appropriately. To conserve power, the ADC may be bypassed
– 1.8 V to 2.5 V Headphone Amplifier while still allowing full analog volume control.
– 1.8 V to 3.3 V Interface Logic The DAC output path includes a digital signal processing en-
gine with various fixed-function controls. Tone Control
 Power-down Management
provides bass and treble adjustment of four selectable corner
– ADC, DAC, CODEC, MIC Pre-Amplifier, PGA, frequencies. The Digital Mixer provides independent volume
Headphone Amplifier, Speaker Amplifier control for both the ADC output and PCM input signal paths,
 Analog and Digital Routing/Mixes: as well as a master volume control. Digital Volume controls
– Line/Headphone Out = Analog In (ADC may be configured to change on soft-ramp transitions while
Bypassed) the analog controls can be configured to occur on every zero
crossing. The DAC also includes de-emphasis, limiting func-
– Line/Headphone/Speaker tions and a BEEP generator, delivering tones selectable
Out = ADC + Digital In across a range of two full octaves.
– Digital Out = ADC + Digital In
The stereo headphone amplifier is powered from a separate
– Internal Digital Loopback positive supply and the integrated charge pump provides a
– Mono Mixes negative supply. This allows a ground-centered, analog output
 Flexible Clocking Options with a wide signal swing and eliminates external DC-blocking
capacitors.
– Master or Slave Operation
– High-impedance Digital Output Option (for easy The Class D stereo speaker amplifier does not require an
MUXing between CODEC and other data external filter and provides the high-efficiency amplification re-
quired by power-sensitive portable applications. The speaker
sources)
amplifier may be powered directly from a battery while the in-
– Quarter-speed Mode - (i.e. allows 8 kHz Fs ternal DC supply monitoring and compensation provides a
while maintaining a flat noise floor up to 16 kHz) constant gain level as the battery’s voltage decays.
– 4 kHz to 96 kHz Sample Rates
In addition to its many features, the CS42L52 operates from a
 I²C™ Control Port Operation low-voltage analog and digital core making it ideal for portable
 Headphone/Speaker Detection Input systems that require extremely low power consumption in a
minimal amount of space.
 Pop and Click Suppression
The CS42L52 is available in a 40-pin QFN package in Com-
Applications mercial (-40 to +85 °C) grade. The CS42L52 Customer
 Digital Voice Recorders, Digital Cameras, and Demonstration board is also available for device evaluation
Camcorders and implementation suggestions. Refer to “Ordering Informa-
tion” on page 81 for complete ordering information.
 PDA’s
 Personal Media Players
 Portable Game Consoles
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CS42L52
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8
1.1 I/O Pin Characteristics .................................................................................................................... 10
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 12
RECOMMENDED OPERATING CONDITIONS ................................................................................... 12
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 12
ANALOG INPUT CHARACTERISTICS ................................................................................................ 13
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14
ANALOG OUTPUT CHARACTERISTICS ............................................................................................ 15
ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 16
PWM OUTPUT CHARACTERISTICS .................................................................................................. 17
HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 18
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS ..................................................................... 19
COMBINED DAC INTERPOLATION AND ONCHIP ANALOG FILTER RESPONSE .......................... 19
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 20
SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 21
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 22
DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS ................................................ 22
POWER CONSUMPTION .................................................................................................................... 23
4. APPLICATIONS ................................................................................................................................... 24
4.1 Overview ......................................................................................................................................... 24
4.1.1 Basic Architecture ................................................................................................................. 24
4.1.2 Line and MIC Inputs .............................................................................................................. 24
4.1.3 Line and Headphone Outputs ............................................................................................... 24
4.1.4 Speaker Driver Outputs ......................................................................................................... 24
4.1.5 Fixed Function DSP Engine .................................................................................................. 24
4.1.6 Beep Generator ..................................................................................................................... 24
4.1.7 Power Management .............................................................................................................. 24
4.2 Analog Inputs ................................................................................................................................. 25
4.2.1 MIC Inputs ............................................................................................................................. 26
4.2.2 Automatic Level Control (ALC) .............................................................................................. 26
4.2.3 Noise Gate ............................................................................................................................ 27
4.3 Analog Outputs .............................................................................................................................. 28
4.3.1 Beep Generator ..................................................................................................................... 29
4.3.2 Limiter .................................................................................................................................... 30
4.4 Analog In to Analog Out Passthrough ............................................................................................ 31
4.4.1 Overriding the ADC Power Down .......................................................................................... 31
4.4.2 Overriding the PGA Power Down .......................................................................................... 32
4.5 PWM Outputs ................................................................................................................................. 32
4.5.1 Mono Speaker Output Configuration ..................................................................................... 32
4.5.2 VP Battery Compensation ..................................................................................................... 33
4.5.2.1 Maintaining a Desired Output Level ........................................................................... 33
4.6 Serial Port Clocking ........................................................................................................................ 33
4.7 Digital Interface Formats ................................................................................................................ 35
4.7.1 DSP Mode ............................................................................................................................. 35
4.8 Initialization ..................................................................................................................................... 36
4.9 Recommended Power-up Sequence .............................................................................................. 37
4.10 Recommended Power-Down Sequence ...................................................................................... 37
4.11 Required Initialization Settings ..................................................................................................... 37
4.12 Control Port Operation .................................................................................................................. 38
4.12.1 I²C Control ........................................................................................................................... 38
4.12.2 Memory Address Pointer (MAP) .......................................................................................... 39
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4.12.2.1 Map Increment (INCR) ............................................................................................. 39
5. REGISTER QUICK REFERENCE ........................................................................................................ 40
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 42
6.1.1 Chip I.D. (Read Only) ............................................................................................................ 42
6.1.2 Chip Revision (Read Only) .................................................................................................... 42
6.2 Power Control 1 (Address 02h) ...................................................................................................... 42
6.2.1 Power Down ADC Charge Pump .......................................................................................... 42
6.2.2 Power Down PGAx ................................................................................................................ 42
6.2.3 Power Down ADCx ................................................................................................................ 43
6.2.4 Power Down .......................................................................................................................... 43
6.3.1 Power Down ADC Override ................................................................................................... 43
6.3.2 Power Down MICx ................................................................................................................. 43
6.3.3 Power Down MIC Bias .......................................................................................................... 43
6.4.1 Headphone Power Control .................................................................................................... 44
6.4.2 Speaker Power Control ......................................................................................................... 44
6.5 Clocking Control (Address 05h) ...................................................................................................... 44
6.5.1 Auto-Detect ........................................................................................................................... 44
6.5.2 Speed Mode .......................................................................................................................... 45
6.5.3 32kHz Sample Rate Group ................................................................................................... 45
6.5.4 27 MHz Video Clock .............................................................................................................. 45
6.5.5 Internal MCLK/LRCK Ratio ................................................................................................... 45
6.5.6 MCLK Divide By 2 ................................................................................................................. 46
6.6 Interface Control 1 (Address 06h) .................................................................................................. 46
6.6.1 Master/Slave Mode ............................................................................................................... 46
6.6.2 SCLK Polarity ........................................................................................................................ 46
6.6.3 ADC Interface Format ........................................................................................................... 46
6.6.4 DSP Mode ............................................................................................................................. 46
6.6.5 DAC Interface Format ........................................................................................................... 47
6.6.6 Audio Word Length ................................................................................................................ 47
6.7 Interface Control 2 (Address 07h) .................................................................................................. 47
6.7.1 SCLK equals MCLK .............................................................................................................. 47
6.7.2 SDOUT to SDIN Digital Loopback ......................................................................................... 47
6.7.3 Tri-State Serial Port Interface ................................................................................................ 48
6.7.4 Speaker/Headphone Switch Invert ........................................................................................ 48
6.7.5 MIC Bias Level ...................................................................................................................... 48
6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h) ....................... 48
6.8.1 ADC Input Select ................................................................................................................... 48
6.8.2 PGA Input Mapping ............................................................................................................... 49
6.9 Analog and HPF Control (Address 0Ah) ......................................................................................... 49
6.9.1 ADCx High-Pass Filter .......................................................................................................... 49
6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 49
6.9.3 Ch. x Analog Soft Ramp ........................................................................................................ 49
6.9.4 Ch. x Analog Zero Cross ....................................................................................................... 49
6.10 ADC HPF Corner Frequency (Address 0Bh) ................................................................................ 50
6.10.1 HPF x Corner Frequency .................................................................................................... 50
6.11 Misc. ADC Control (Address 0Ch) ................................................................................................ 50
6.11.1 Analog Front-End Volume Setting B=A ............................................................................... 50
6.11.2 Digital MUX ......................................................................................................................... 50
6.11.3 Digital Sum .......................................................................................................................... 50
6.11.4 Invert ADC Signal Polarity ................................................................................................... 51
6.11.5 ADC Mute ............................................................................................................................ 51
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6.12 Playback Control 1 (Address 0Dh) ............................................................................................... 51
6.12.1 Headphone Analog Gain ..................................................................................................... 51
6.12.2 Playback Volume Setting B=A ............................................................................................ 51
6.12.3 Invert PCM Signal Polarity .................................................................................................. 52
6.12.4 Master Playback Mute ......................................................................................................... 52
6.13 Miscellaneous Controls (Address 0Eh) ........................................................................................ 52
6.13.1 Passthrough Analog ............................................................................................................ 52
6.13.2 Passthrough Mute ............................................................................................................... 52
6.13.3 Freeze Registers ................................................................................................................. 52
6.13.4 HP/Speaker De-emphasis ................................................................................................... 53
6.13.5 Digital Soft Ramp ................................................................................................................ 53
6.13.6 Digital Zero Cross ................................................................................................................ 53
6.14 Playback Control 2 (Address 0Fh) ................................................................................................ 54
6.14.1 Headphone Mute ................................................................................................................. 54
6.14.2 Speaker Mute ...................................................................................................................... 54
6.14.3 Speaker Volume Setting B=A .............................................................................................. 54
6.14.4 Speaker Channel Swap ....................................................................................................... 54
6.14.5 Speaker MONO Control ...................................................................................................... 54
6.14.6 Speaker Mute 50/50 Control ............................................................................................... 54
6.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h) ............................................ 55
6.15.1 MIC x Select ........................................................................................................................ 55
6.15.2 MICx Configuration .............................................................................................................. 55
6.15.3 MICx Gain ........................................................................................................................... 55
6.16 PGAx Vol. and ALCx Transition Ctl.:
ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h) .............................................................. 55
6.16.1 ALCx Soft Ramp Disable ..................................................................................................... 55
6.16.2 ALCx Zero Cross Disable .................................................................................................... 56
6.16.3 PGAx Volume ...................................................................................................................... 56
6.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h) ................. 57
6.17.1 Passthrough x Volume ........................................................................................................ 57
6.18 ADCx Volume Control: ADCAVOL (Address 16h) and ADCBVOL (Address 17h) ....................... 57
6.18.1 ADCx Volume ...................................................................................................................... 57
6.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h) ........................................ 58
6.19.1 ADC Mixer Channel x Mute ................................................................................................. 58
6.19.2 ADC Mixer Channel x Volume ............................................................................................. 58
6.20 PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh) ...................................... 58
6.20.1 PCM Mixer Channel x Mute ................................................................................................ 58
6.20.2 PCM Mixer Channel x Volume ............................................................................................ 58
6.21 Beep Frequency and On Time (Address 1Ch) ............................................................................. 59
6.21.1 Beep Frequency .................................................................................................................. 59
6.21.2 Beep On Time ..................................................................................................................... 60
6.22 Beep Volume and Off Time (Address 1Dh) .................................................................................. 60
6.22.1 Beep Off Time ..................................................................................................................... 60
6.22.2 Beep Volume ....................................................................................................................... 61
6.23 Beep and Tone Configuration (Address 1Eh) ............................................................................... 61
6.23.1 Beep Configuration .............................................................................................................. 61
6.23.2 Beep Mix Disable ................................................................................................................ 61
6.23.3 Treble Corner Frequency .................................................................................................... 62
6.23.4 Bass Corner Frequency ...................................................................................................... 62
6.23.5 Tone Control Enable ........................................................................................................... 62
6.24 Tone Control (Address 1Fh) ......................................................................................................... 62
6.24.1 Treble Gain .......................................................................................................................... 62
6.24.2 Bass Gain ............................................................................................................................ 63
6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h) .................................... 63
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6.25.1 Master Volume Control ........................................................................................................ 63
6.26 Headphone Volume Control: HPA (Address 22h) and HPB (Address 23h) ................................. 63
6.26.1 Headphone Volume Control ................................................................................................ 63
6.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h) .................................. 64
6.27.1 Speaker Volume Control ..................................................................................................... 64
6.28 ADC and PCM Channel Mixer (Address 26h) .............................................................................. 64
6.28.1 PCM Mix Channel Swap ..................................................................................................... 64
6.28.2 ADC Mix Channel Swap ...................................................................................................... 64
6.29 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 65
6.29.1 Limiter Maximum Threshold ................................................................................................ 65
6.29.2 Limiter Cushion Threshold .................................................................................................. 65
6.29.3 Limiter Soft Ramp Disable ................................................................................................... 65
6.29.4 Limiter Zero Cross Disable .................................................................................................. 66
6.30 Limiter Control 2, Release Rate (Address 28h) ............................................................................ 66
6.30.1 Peak Detect and Limiter ...................................................................................................... 66
6.30.2 Peak Signal Limit All Channels ........................................................................................... 66
6.30.3 Limiter Release Rate ........................................................................................................... 66
6.31 Limiter Attack Rate (Address 29h) ................................................................................................ 67
6.31.1 Limiter Attack Rate .............................................................................................................. 67
6.32 ALC Enable and Attack Rate (Address 2Ah) ................................................................................ 67
6.32.1 ALCx Enable ....................................................................................................................... 67
6.32.2 ALC Attack Rate .................................................................................................................. 67
6.33 ALC Release Rate (Address 2Bh) ................................................................................................ 68
6.33.1 ALC Release Rate ............................................................................................................... 68
6.34 ALC Threshold (Address 2Ch) ..................................................................................................... 68
6.34.1 ALC Maximum Threshold .................................................................................................... 68
6.34.2 ALC Minimum Threshold ..................................................................................................... 69
6.35 Noise Gate Control (Address 2Dh) ............................................................................................... 69
6.35.1 Noise Gate All Channels ..................................................................................................... 69
6.35.2 Noise Gate Enable .............................................................................................................. 69
6.35.3 Noise Gate Threshold and Boost ........................................................................................ 70
6.35.4 Noise Gate Delay Timing .................................................................................................... 70
6.36 Status (Address 2Eh) (Read Only) ............................................................................................... 70
6.36.1 Serial Port Clock Error (Read Only) .................................................................................... 70
6.36.2 DSP Engine Overflow (Read Only) ..................................................................................... 71
6.36.3 PCMx Overflow (Read Only) ............................................................................................... 71
6.36.4 ADCx Overflow (Read Only) ............................................................................................... 71
6.37 Battery Compensation (Address 2Fh) .......................................................................................... 71
6.37.1 Battery Compensation ......................................................................................................... 71
6.37.2 VP Monitor ........................................................................................................................... 71
6.37.3 VP Reference ...................................................................................................................... 72
6.38 VP Battery Level (Address 30h) (Read Only) ............................................................................... 72
6.38.1 VP Voltage Level (Read Only) ............................................................................................ 72
6.39 Speaker Status (Address 31h) (Read Only) ................................................................................. 72
6.39.1 Speaker Current Load Status (Read Only) ......................................................................... 72
6.39.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 73
6.40 Charge Pump Frequency (Address 34h) ...................................................................................... 73
6.40.1 Charge Pump Frequency .................................................................................................... 73
7. ANALOG PERFORMANCE PLOTS .................................................................................................... 74
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 74
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 76
8.1 Auto Detect Enabled .................................................................................................................... 76
8.2 Auto Detect Disabled .................................................................................................................... 76
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 77
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9.1 Power Supply and Grounding ......................................................................................................... 77
9.2 QFN Thermal Pad .......................................................................................................................... 77
10. ADC AND DAC DIGITAL FILTERS .................................................................................................. 78
11. PARAMETER DEFINITIONS .............................................................................................................. 79
12. PACKAGE DIMENSIONS .................................................................................................................. 80
THERMAL CHARACTERISTICS .......................................................................................................... 80
13. ORDERING INFORMATION .............................................................................................................. 81
14. REFERENCES .................................................................................................................................... 81
15. REVISION HISTORY .......................................................................................................................... 81
LIST OF TABLES
Table 1. MCLK, LRCK Quick Decode ....................................................................................................... 34
LIST OF FIGURES
Figure 1. Typical Connection Diagram ...................................................................................................... 11
Figure 2. Headphone Output Test Load .................................................................................................... 18
Figure 3. Serial Audio Interface Timing ..................................................................................................... 20
Figure 4. Control Port Timing - I²C ............................................................................................................ 21
Figure 5. Analog Input Signal Flow ........................................................................................................... 25
Figure 6. Single-Ended MIC Configuration ............................................................................................... 26
Figure 7. Differential MIC Configuration .................................................................................................... 26
Figure 8. ALC ............................................................................................................................................ 27
Figure 9. Noise Gate Attenuation .............................................................................................................. 27
Figure 10. DSP Engine Signal Flow .......................................................................................................... 28
Figure 11. PWM Output Stage .................................................................................................................. 29
Figure 12. Analog Output Stage ................................................................................................................ 29
Figure 13. Beep Configuration Options ..................................................................................................... 30
Figure 14. Peak Detect and Limiter ........................................................................................................... 31
Figure 15. Battery Compensation ............................................................................................................. 33
Figure 16. I²S Format ................................................................................................................................ 35
Figure 17. Left-Justified Format ................................................................................................................ 35
Figure 18. Right-Justified Format (DAC only) ........................................................................................... 35
Figure 19. DSP Mode Format) .................................................................................................................. 36
Figure 20. Control Port Timing, I²C Write .................................................................................................. 38
Figure 21. Control Port Timing, I²C Read .................................................................................................. 39
Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16  load) ................................................... 74
Figure 26. ADC Passband Ripple ............................................................................................................. 78
Figure 27. ADC Stopband Rejection ......................................................................................................... 78
Figure 28. ADC Transition Band ............................................................................................................... 78
Figure 29. ADC Transition Band (Detail) ................................................................................................... 78
Figure 30. DAC Passband Ripple ............................................................................................................. 78
Figure 31. DAC Stopband ......................................................................................................................... 78
Figure 32. DAC Transition Band ............................................................................................................... 78
Figure 33. DAC Transition Band (Detail) ................................................................................................... 78
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1. PIN DESCRIPTIONS
SPKR/HP
SDOUT
RESET
DGND
MCLK
LRCK
SCLK
SDIN
VD
VL
40
38
36
39
37
35
34
33
32
31
SDA 1 30 AIN1B
SCL 2 29 AIN1A
AD0 3 28 AFILTB
SPKR_OUTA+ 4 27 AFILTA
VP 5
GND/Thermal Pad
26 AIN2B
SPKR_OUTA- 6 25 AIN2A
SPKR_OUTB+ 7
Top-Down (Through-Package) View
24 AIN3B/MIC2-/MIC1B
40-Pin QFN Package
VP 8 23 AIN3A/MIC1-/MIC1A
SPKR_OUTB- 9 22 AIN4B/MIC2+/MIC2B
-VHPFILT 10 21 AIN4A/MIC1+/MIC2A
12
14
16
17
18
19
20
11
13
15
HP/LINE_OUTA
VQ
AGND
HP/LINE_OUTB
FLYN
FILT+
VA
MICBIAS
+VHP
FLYP
Pin Name # Pin Description

SDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.
SCL 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0 3 Address Bit 0 (Input) - Chip address bit 0.
SPKR_OUTA+ 4
SPKR_OUTA- 6
PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.
SPKR_OUTB+ 7
SPKR_OUTB- 9
5
VP Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.
8
Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge
-VHPFILT 10
pump that provides the negative rail for the headphone/line amplifiers.
Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly-
FLYN 11
ing capacitor.
Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying
FLYP 12
capacitor.
Positive Analog Power for Headphone (Input) - Positive voltage rail and power for the internal
+VHP 13
headphone amplifiers and inverting charge pump.
HP/LINE_OUTB, A 14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.
VA 16 Analog Power (Input) - Positive power for the internal analog section.
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AGND 17 Analog Ground (Input) - Ground reference for the internal analog section.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
FILT+ 18
cuits.
VQ 19 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical charac-
MICBIAS 20
teristics are specified in the DC Electrical Characteristics table.
AIN4A,B 21,22
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
AIN3A,B 23,24
MIC1+,- 21,23
Differential Microphone Inputs (Input) - Differential stereo microphone inputs.
MIC2+,- 22,24
MIC2A,B 21,22
Single-Ended Microphone Inputs (Input) - Single-ended stereo microphone inputs.
MIC1A,B 23,24
AIN2A,B 25,26
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
AIN1A,B 29,30
AFILTA,B 27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for the ADC inputs.
Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
SPKR/HP 31
and/or headphone outputs.
RESET 32 Reset (Input) - The device enters a low power mode when this pin is driven low.
Digital Interface Power (Input) - Determines the required signal level for the serial audio inter-
VL 33
face and host control port.
VD 34 Digital Power (Input) - Positive power for the internal digital section.
DGND 35 Digital Ground (Input) - Ground reference for the internal digital section.
SDOUT 36 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MCLK 37 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 38 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
LRCK 40
the serial audio data line.
Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
GND/Thermal Pad -
dissipation.
DS680F2 9
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1.1 I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power Pin Name I/O Internal Driver Receiver

Supply Connections
RESET Input - - 1.65 V - 3.47 V, with Hysteresis
AD0 Input - - 1.65 V - 3.47 V, with Hysteresis
SCL Input - - 1.65 V - 3.47 V, with Hysteresis
SDA Input/ - 1.65 V - 3.47 V, CMOS/Open 1.65 V - 3.47 V, with Hysteresis
Output Drain
MCLK Input - - 1.65 V - 3.47 V
VL LRCK Input/ Weak Pullup 1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
Output (~1 M)
SCLK Input/ Weak Pullup 1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V
Output (~1 M)
SDOUT Output Weak Pullup 1.65 V - 3.47 V, CMOS
(~1 M)
SDIN Input - - 1.65 V - 3.47 V
VA SPKR/HP Input - - 1.65 V - 2.63 V
SPKR_OUTA+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTA- Output - 1.6 V - 5.25 V Power MOSFET -
VP
SPKR_OUTB+ Output - 1.6 V - 5.25 V Power MOSFET -
SPKR_OUTB- Output - 1.6 V - 5.25 V Power MOSFET -
10 DS680F2
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2. TYPICAL CONNECTION DIAGRAM
+1.8 V to +2.5 V +1.8 V to +2.5 V
1 µF 0.1 µF 0.1 µF 0.1 µF 1 µF
See Note 5
VD VA +VHP
Line Level Out
47 k
Left & Right
0.022 µF
Note 1
FLYP 51.1 
HP/LINE_OUTB
1 µF ** Headphone Out
FLYN HP/LINE_OUTA Left & Right
51.1 
0.022 µF
Note 2
-VHPFILT SPKR/HP
1 µF **
VP +1.6 V to
+5 V Stereo Speakers
CS42L52 0.1 µF 10 µF
* *Use low ESR ceramic capacitors. SPKR_OUTA+

SPKR_OUTA-
VP
0.1 µF
SPKR_OUTB+
MCLK SPKR_OUTB-
SCLK Note 4
LRCK AIN1A Left 1
1800 pF * 100  1 µF
SDIN 100 k
Digital Audio Analog
Processor SDOUT 1800 pF
*
Input 1
100  100 k
RESET AIN1B Right 1
1 µF
SCL
SDA AIN2A Left 2
1800 pF * 100  1 µF
100 k
AD0 Analog
1800 pF Input 2
* 100 k
100 
AIN2B Right 2
1 µF
2 k 2 k
MIC1- Note 7
+1.8 V to +3.3 V VL
AIN3A/MIC1A
0.1 µF 1 µF
Microphone 1
MIC1+
AIN4A/MIC2A
1 µF 100 k
Notes:
1. Recommended values for the default charge pump switching Mic-Level
MICBIAS Inputs
frequency. The required capacitance follows an inverse RL
relationship with the charge pump’s switching frequency. When 0.1 µF Note 6
increasing the switching frequency, the capacitance may
decrease; when lowering the switching frequency, the RL
capacitance must increase. MIC2+
2. Larger capacitance reduces the ripple on the internal AIN4B/MIC2B
1 µF 100 k
amplifier’s supply. This may reduce the distortion at higher
output power levels. Microphone 2
3. Additional bulk capacitance may be added to improve PSRR
at low frequencies. MIC2-
4. These capacitors serve as a charge reservoir for the internal AIN3B/MIC1B Note 7
1 µF
switched capacitor ADC modulators. They are only needed
when the PGA (Programmable Gain Amplifier) is bypassed. Note 3
5. Series resistance in the path of the power supplies must be
AGND
avoided. Any voltage drop on VHP will directly impact the
negative charge pump supply (-VHPFILT) and clip the audio * *
output. 150 pF 150 pF 1 µF 10 µF
6. The value of RL, a current-limiting resistor used with electret AFILTA
condenser microphones, is dictated by the microphone AFILTB
cartridge.
7. The negative terminal of the MICx inputs connects to the VQ
ground pin of the microphone cartridge. Gain is applied only to FILT+
the positive terminal.
DGND
* Capacitors must be C0G or equivalent
Figure 1. Typical Connection Diagram
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3. CHARACTERISTIC AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS

AGND=DGND=0 V, All voltages with respect to ground.
Parameters Symbol Min Max Units
DC Power Supply
Analog VA 1.65 2.63 V
Headphone Amplifier +VHP 1.65 2.63 V
Speaker Amplifier VP 1.60 5.25 V
Digital VD 1.65 2.63 V
Serial/Control Port Interface VL 1.65 3.47 V
Ambient Temperature Commercial - CNZ TA -40 +85 C
ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V; All voltages with respect to ground.
DC Power Supply Analog VA, VHP -0.3 3.0 V
Speaker VP -0.3 6.0 V
Digital VD -0.3 3.0 V
Serial/Control Port Interface VL -0.3 4.0 V
Input Current (Note 1) Iin - ±10 mA
External Voltage Applied to Analog Input (Note 2) VIN AGND-0.3 VA+0.3 V
External Voltage Applied to Analog Output VIN -VHP - 0.3 +VHP + 0.3 V
External Voltage Applied to Digital Input (Note 2) VIND -0.3 VL+ 0.3 V
Ambient Operating Temperature (power applied) TA -50 +115 °C
Storage Temperature Tstg -65 +150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
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ANALOG INPUT CHARACTERISTICS
Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; All
Supplies = VA; TA = +25C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise speci-
fied; “Required Initialization Settings” on page 37 written on power up.
VA = 2.5V VA = 1.8V
Parameters Min Typ Max Min Typ Max Unit
Analog In to ADC (PGA bypassed)
Dynamic Range A-weighted 93 99 - 90 96 - dB
unweighted 90 96 - 87 93 - dB
Total Harmonic Distortion + Noise -1 dBFS - -86 -80 - -84 -78 dB
-20 dBFS - -76 - - -73 - dB
-60 dBFS - -36 -30 - -33 -27 dB
Analog In to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted 92 96 - 89 95 - dB
PGA Setting: +12 dB A-weighted 85 91 - 82 88 - dB
Total Harmonic Distortion + Noise
PGA Setting: 0 dB -1 dBFS - -88 -82 - -86 -80 dB
-60 dBFS - -33 -27 - -32 -26 dB
PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB
Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted - 86 - - 83 - dB
unweighted - 83 - - 80 - dB
PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB
Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC
Dynamic Range
PGA Setting: 0 dB A-weighted - 76 - - 74 - dB
PGA Setting: 0 dB -2 dBFS - -74 - - -71 - dB
Other Characteristics
DC Accuracy
Interchannel Gain Mismatch - 0.2 - - 0.2 - dB
Gain Drift - ±100 - - ±100 - ppm/°C
Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB
Input
Interchannel Isolation - 90 - - 90 - dB
HP Amp to Analog Input Isolation RL = 10 k - 100 - - 100 - dB
(Note 3) RL = 16  - 70 - - 70 - dB
Speaker Amp to Analog Input Isolation - 60 - - 60 - dB
Full-scale Input Voltage ADC 0.73•VA 0.769•VA 0.83•VA 0.73•VA 0.769•VA 0.83•VA Vpp
PGA (0 dB) 0.73•VA 0.770•VA 0.83•VA 0.73•VA 0.770•VA 0.83•VA Vpp
PGA (+12 dB) 0.194•VA 0.194•VA Vpp
MIC (+16 dB) 0.115•VA 0.115•VA Vpp
MIC (+32 dB) 0.019•VA 0.019•VA Vpp
Input Impedance (Note 4) ADC - 20 - - 20 - k
PGA - 39 - - 39 - k
MIC - 50 - - 50 - k
3. Measured with DAC delivering full-scale output into specified load.
4. Measured between analog input and AGND.
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ADC DIGITAL FILTER CHARACTERISTICS
Parameters (Note 5) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4948 Fs
Passband Ripple -0.09 - 0.17 dB
Stopband 0.6 - - Fs
Stopband Attenuation 33 - - dB
Total Group Delay - 7.6/Fs - s
High-Pass Filter Characteristics (48 kHz Fs)
Frequency Response -3.0 dB - 3.6 - Hz
-0.13 dB - 24.2 - Hz
Phase Deviation @ 20 Hz - 10 - Deg
Passband Ripple - - 0.17 dB
Filter Settling Time - 105/Fs 0 s
5. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 29 on
page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
HPF parameters are for Fs = 48 kHz.
14 DS680F2
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ANALOG OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25C;
Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 k CL = 10 pFfor the line output
(see Figure 2); Test load RL = 16  CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011; “Required Initial-
ization Settings” on page 37 written on power up.
VA = 2.5 V VA = 1.8 V
Parameters (Note 6) Min Typ Max Min Typ Max Unit
RL = 10 k
Dynamic Range
18- to 24-Bit A-weighted 92 98 - 89 95 - dB
16-Bit A-weighted - 96 - - 93 - dB
18- to 24-Bit 0 dB - -86 -80 - -88 -82 dB
-20 dB - -75 - - -72 - dB
-60 dB - -35 -29 - -32 -26 dB
16-Bit 0 dB - -86 - - -88 - dB
-20 dB - -73 - - -70 - dB
-60 dB - -33 - - -30 - dB
RL = 16 
Dynamic Range
18- to 24-Bit A-weighted 92 98 - 89 95 - dB
16-Bit A-weighted - 96 - - 93 - dB
18- to 24-Bit 0 dB - -75 -69 - -75 -69 dB
-20 dB - -75 - - -72 - dB
-60 dB - -35 -29 - -32 -26 dB
16-Bit 0 dB - -75 - - -75 - dB
-20 dB - -73 - - -70 - dB
-60 dB - -33 - - -30 - dB
Other Characteristics for RL = 16  or 10 k
Output Parameters Modulation Index (MI) - 0.6787 - - 0.6787 -
(Note 7) Analog Gain Multiplier (G) - 0.6047 - - 0.6047 -
Full-scale Output Voltage (2•G•MI•VA) (Note 7) See “Line Output Voltage Level Characteristics” on Vpp
page 19
Full-scale Output Power (Note 7) See “Headphone Output Power Characteristics” on page 18
Interchannel Isolation (1 kHz) 16  - 80 - - 80 - dB
10 k - 95 - - 93 - dB
Speaker Amp to HP Amp Isolation - 80 - - 80 - dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°C
AC Load Resistance (RL) (Note 8) 16 - - 16 - - 
Load Capacitance (CL) (Note 8) - - 150 - - 150 pF
6. One (least-significant bit) LSB of triangular PDF dither is added to data.

7. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain” on page 51. High gain settings at certain VA and VHP supply levels may cause clipping when the
audio signal approaches full-scale, maximum power output, as shown in Figures 22 - 25 on page 75.
DS680F2 15
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CS42L52
8. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re-
quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-
mended 150 pF can cause the internal op-amp to become unstable.
ANALOG PASSTHROUGH CHARACTERISTICS

Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter; PGA and
HP/Line Gain = 0 dB; All Supplies = VA; TA = +25C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz;
“Required Initialization Settings” on page 37 written on power up.
VA = 2.5 V VA = 1.8 V
Parameters Min Typ Max Min Typ Max Unit
Analog In to HP/Line Amp (ADC is powered down)
RL = 10 k
Dynamic Range A-weighted - -96 - - -94 - dB
unweighted - -93 - - -91 - dB
Total Harmonic Distortion + Noise -1 dBFS - -70 - - -70 - dB
-20 dBFS - -73 - - -71 - dB
-60 dBFS - -33 - - -31 - dB
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
RL = 16 
Dynamic Range A-weighted - -96 - - -94 - dB
unweighted - -93 - - -91 - dB
Total Harmonic Distortion + Noise -1 dBFS - -70 - - -70 - dB
-20 dBFS - -73 - - -71 - dB
-60 dBFS - -33 - - -31 - dB
Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp
Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp
Output Power - 32 - - 17 - mW
Passband Ripple - 0/-0.3 - - 0/-0.3 - dB
16 DS680F2
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CS42L52
PWM OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement
Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 for stereo full-bridge, RL = 4 for mono parallel
full-bridge; VD = VL = VA = VHP = 1.8 V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz; “Required Initialization
Settings” on page 37 written on power up. (Note 9)
Parameters (Note 10) Symbol Conditions Min Typ Max Units
VP = 5.0 V
Power Output per Channel PO
Stereo Full-Bridge THD+N < 10% - 1.00 - Wrms
THD+N < 1% - 0.80 - Wrms
Mono Parallel Full-Bridge THD+N < 10% - 1.90 - Wrms
THD+N < 1% - 1.50 - Wrms
Total Harmonic Distortion + Noise THD+N
Stereo Full-Bridge PO = 0 dBFS = 0.8W - 0.52 - %
Mono Parallel Full-Bridge PO = -3 dBFS = 0.75 W - 0.10 - %
PO = 0 dBFS = 1.5 W - 0.50 - %
Dynamic Range DR
Stereo Full-Bridge PO = -60 dBFS, A-Weighted - 91 - dB
PO = -60 dBFS, Unweighted - 88 - dB
Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted - 91 - dB
VP = 3.7 V
THD+N < 1% - 0.45 - Wrms
THD+N < 1% - 0.84 - Wrms
Stereo Full-Bridge PO = 0 dBFS = 0.43 W - 0.54 - %
PO = 0 dBFS = 0.81 W - 0.45 - %
Dynamic Range DR
VP =2.5 V
THD+N < 1% - 0.19 - Wrms
THD+N < 1% - 0.35 - Wrms
Stereo Full-Bridge PO = 0 dBFS = 0.18 W - 0.50 - %
PO = 0 dBFS = 0.35 W - 0.43 - %
Dynamic Range DR
MOSFET On Resistance RDS(ON) VP = 5.0V, Id = 0.5 A - 600 - m
DS680F2 17
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CS42L52
Parameters (Note 10) Symbol Conditions Min Typ Max Units
Efficiency  VP = 5.0 V, PO = 2 x 0.8 W, RL = 8  - 81 - %
Output Operating Peak Current IPC - - 1.5 A
VP Input Current During Reset IVP RESET, pin 32, is held low - 0.8 5.0 µA
9. The PWM driver should be used in captive speaker systems only.
10. Optimal PWM performance is achieved when MCLK > 12 MHz.
HEADPHONE OUTPUT POWER CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Frequency = 48 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16  CL = 10 pF (see Figure 2); “Required Initialization Settings”
on page 37 written on power up.
Parameters VA = 2.5V VA = 1.8V Unit

Min Typ Max Min Typ Max
AOUTx Power Into RL = 16 
HP_GAIN[2:0] Analog Gain (G) VHP
000 0.3959 1.8 V - 14 - - 7 - mWrms
2.5 V - 14 - - 7 - mWrms
001 0.4571 1.8 V - 19 - - 10 - mWrms
2.5 V - 19 - - 10 - mWrms
010 0.5111 1.8 V - 23 - - 12 - mWrms
2.5 V - 23 - - 12 - mWrms
011 (default) 0.6047 1.8 V (Note 11) - 17 - mWrms
2.5 V - 32 - - 17 - mWrms
100 0.7099 1.8 V (Note 11) - 23 - mWrms
2.5 V - 44 - - 23 - mWrms
101 0.8399 1.8 V (Note 7), Figure 22 on page 74 mWrms
2.5 V - 32 - mWrms
110 1.0000 1.8 V (Note 7, 11) See Figures 22 and 23 on page 74 mWrms
2.5 V mWrms
111 1.1430 1.8 V mWrms
2.5 V mWrms
11. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 
0.022 F
C R
L L
AGND
Figure 2. Headphone Output Test Load
18 DS680F2
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CS42L52
LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz
to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 k CL = 10 pF (see Figure 2); “Required Initialization Settings” on
page 37 written on power up.
Parameters VA = 2.5V VA = 1.8V Unit
Min Typ Max Min Typ Max
AOUTx Voltage Into RL = 10 k
HP_GAIN[2:0] Analog VHP
Gain (G)
000 0.3959 1.8 V - 1.34 - - 0.97 - Vpp
2.5 V - 1.34 - - 0.97 - Vpp
001 0.4571 1.8 V - 1.55 - - 1.12 - Vpp
2.5 V - 1.55 - - 1.12 - Vpp
010 0.5111 1.8 V - 1.73 - - 1.25 - Vpp
2.5 V - 1.73 - - 1.25 - Vpp
011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 Vpp
2.5 V 1.95 2.05 2.15 - 1.48 - Vpp
100 0.7099 1.8 V - 2.41 - - 1.73 - Vpp
2.5 V - 2.41 - - 1.73 - Vpp
101 0.8399 1.8 V - 2.85 - 2.05 Vpp
2.5 V - 2.85 - - 2.05 - Vpp
110 1.0000 1.8 V - 3.39 - - 2.44 - Vpp
2.5 V - 3.39 - - 2.44 - Vpp
111 1.1430 1.8 V (See (Note 11) - 2.79 - Vpp
2.5 V - 3.88 - - 2.79 - Vpp
COMBINED DAC INTERPOLATION AND ONCHIP ANALOG FILTER RESPONSE

Parameters (Note 12) Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corner 0 - 0.4780 Fs
to -3 dB corner 0 - 0.4996 Fs
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 13) 50 - - dB
Group Delay - 9/Fs - s
De-emphasis Error Fs = 32 kHz - - +1.5/+0 dB
Fs = 44.1 kHz - - +0.05/-0.25 dB
Fs = 48 kHz - - -0.2/-0.4 dB
12. Response is clock dependent and scales with Fs. Note that the response plots (Figures 30 and 33 on
page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Measurement Bandwidth is from Stopband to 3 Fs.
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SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.
RESET pin Low Pulse Width (Note 14) 1 - ms
MCLK Frequency (Note 15) (See “Serial Port Clock- MHz
ing” on page 33)
MCLK Duty Cycle 45 55 %
Slave Mode
Input Sample Rate (LRCK) Fs (See “Serial Port Clock- kHz
ing” on page 33)
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP - 64•Fs Hz
SCLK Duty Cycle 45 55 %
LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns
LRCK Edge to SDOUT MSB Output Delay td(MSB) - 52 ns
SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns
SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th 20 - ns
Master Mode
Output Sample Rate (LRCK) All Speed Modes Fs (See “Serial Port Clock- Hz
ing” on page 33)
LRCK Duty Cycle 45 55 %
SCLK Frequency SCLK=MCLK mode 1/tP - 12.0000 MHz
MCLK=12.0000 MHz 1/tP - 68•Fs Hz
all other modes 1/tP - 64•Fs Hz
SCLK Duty Cycle 45 55 %
LRCK Edge to SDOUT MSB Output Delay td(MSB) - 52 ns
SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns
SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th 20 - ns
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 76 for typical MCLK frequencies.
//
LRCK
//
ts(LK-SK) tP
//
SCLK
//
td(MSB) th(SK-SDO) ts(SDO-SK)
//
SDOUT MSB MSB-1
//
ts(SD-SK) th
//
SDIN MSB MSB-1
//
Figure 3. Serial Audio Interface Timing
20 DS680F2
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SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF.
Parameters Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz
RESET Rising Edge to Start tirs 550 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 16) thdd 0 - µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc - 1 µs
Fall Time SCL and SDA tfc - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling tack 300 1000 ns
16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Repeated
Stop Start Start Stop
SDA
t buf t hdst t high t tf
hdst t susp
SCL
t t t sud t sust tr
low hdd
Figure 4. Control Port Timing - I²C
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CS42L52
DC ELECTRICAL CHARACTERISTICS
AGND = 0 V; All voltages with respect to ground.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage - 0.5•VA - V
Output Impedance - 23 - k
DC Current Source/Sink - - 1 A
MIC BIAS Characteristics
Nominal Voltage BIASLVL[2:0] = 000 - 0.5•VA - V
BIASLVL[2:0] = 001 - 0.6•VA - V
BIASLVL[2:0] = 010 - 0.7•VA - V
BIASLVL[2:0] = 011 - 0.8•VA - V
BIASLVL[2:0] = 100 - 0.83•VA - V
BIASLVL[2:0] = 101 - 0.91•VA - V
DC Output Current - - 1 mA
Power Supply Rejection Ratio (PSRR) 1 kHz - 50 - dB
Power Supply Rejection Ratio Characteristics
PSRR @1 kHz (Note 17) PGA to ADC - 44 - dB
ADC - 60 - dB
DAC (HP and Line Amps) - 60 - dB
PSRR @60 Hz (Note 17) PGA to ADC(Note 18) - 22 - dB
ADC - 42 - dB
DAC (HP and Line Amps) - 60 - dB
PSRR @217 Hz Full-Bridge PWM Outputs - 56 - dB
17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
18. The PGA is biased with VQ, created from a resistor divider from the VA supply. Increasing the capaci-
tance on VQ will also increase the PSRR at low frequencies. A 10 µF capacitor on VQ improves the
PSRR to 42 dB.
DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS

Parameters (Note 19) Symbol Min Max Units
Input Leakage Current Iin - ±10 A
Input Capacitance - 10 pF
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 A) VOH VL - 0.2 - V
Low-Level Output Voltage (IOL = 100 A) VOL - 0.2 V
High-Level Input Voltage VL = 1.65 V 0.85•VL - V
VL = 1.8 V 0.77•VL - V
VIH
VL = 2.0 V 0.68•VL - V
VL > 2.0 V 0.65•VL - V
Low-Level Input Voltage VIL - 0.30•VL V
19. See “I/O Pin Characteristics” on page 10 for serial and control port power rails.
22 DS680F2
3/1/13
CS42L52
POWER CONSUMPTION See (Note 20).
Power Ctl. Registers Typical Current (mA)
Operation 02h 03h 04h
iVHP iVA iVD iVL iVP Total
PDN_SPKB[1:0]
PDN_SPKA[1:0]
PDN_MICBIAS
PDN_HPB[1:0]
PDN_HPA[1:0]
VL=3.3V VP=3.7V Power
PDN_PGAB
PDN_PGAA
PDN_ADCB
PDN_ADCA
(Note 23)
PDN_MICB
PDN_MICA
(mWrms)
PDN
V
1 Off (Note 21) x x x x x x x x x x x x 1.8 0.00 0.00 0.00 0.00
0.00 0.00
2.5 0.00 0.00 0.00 0.00
2 Standby (Note 22) x x x x 1 x x x x x x x 1.8 0.00 0.00 0.01 0.02
0.00 0.00
2.5 0.00 0.00 0.02 0.05
3 Mono Record ADC 1 1 1 0 0 1 1 1 11 11 11 11 1.8 0.00 1.67 2.32 7.24
0.03 0.00
2.5 0.00 1.87 3.72 14.05
PGA to ADC 1 0 1 0 0 1 1 1 11 11 11 11 1.8 0.00 2.1 2.31 7.99
0.03 0.00
2.5 0.00 2.3 3.72 15.13
MIC to PGA to ADC 1 0 1 0 0 1 0 0 11 11 11 11 1.8 0.00 3.48 2.32 10.49
(with Bias) 0.03 0.00
2.5 0.00 3.71 3.72 18.65
MIC to PGA to ADC 1 0 1 0 0 1 0 1 11 11 11 11 1.8 0.00 3.15 2.32 9.90
(no Bias) 0.03 0.00
2.5 0.00 3.37 3.73 17.83
4 Stereo Record ADC 1 1 0 0 0 1 1 1 11 11 11 11 1.8 0.00 2.31 2.37 8.48
0.03 0.00
2.5 0.00 2.53 3.82 15.95
PGA to ADC 0 0 0 0 0 1 1 1 11 11 11 11 1.8 0.00 3.18 2.37 10.04
0.03 0.00
2.5 0.00 3.42 3.81 18.15
MIC to PGA to ADC 0 0 0 0 0 0 0 1 11 11 11 11 1.8 0.00 5.32 2.37 13.90
(no Bias) 0.03 0.00
2.5 0.00 5.57 3.81 23.53
5 Mono Playback to Headphone 1 1 1 1 0 1 1 1 10 11 11 11 1.8 1.59 1.99 2.72 11.36
0.01 0.00
2.5 2.07 2.62 4.27 22.43
6 Mono Playback to Speaker 1 1 1 1 0 1 1 1 11 11 10 10 1.8 0.00 0.20 4.42 12.05
0.01 1.00
2.5 0.00 0.22 6.77 21.21
7 Stereo Playback to Headphone 1 1 1 1 0 1 1 1 10 10 11 11 1.8 2.77 2.00 2.91 13.84
0.01 0.00
2.5 3.27 2.63 4.28 25.48
8 Stereo Playback to Speaker 1 1 1 1 0 1 1 1 11 11 10 10 1.8 0.00 0.20 4.38 11.98
0.01 1.00
2.5 0.00 0.22 6.80 21.28
9 Stereo Passthrough to Head- 1 1 1 1 0 1 1 1 10 10 11 11 1.8 2.79 1.91 1.06 10.39
phone 0.01 0.00
2.5 3.18 2.14 1.81 17.85
10 Mono Record and Playback 1 0 1 0 0 1 1 1 11 10 11 11 1.8 1.77 3.95 4.28 18.05
PGA in (no MIC) to Mono HP 0.03 0.00
2.5 2.13 4.77 6.63 33.90
11 Phone Monitor 1 0 1 0 0 1 0 0 11 10 11 11 1.8 1.76 5.33 4.28 20.52
MIC (w/bias) in to Mono Out 0.03 0.00
2.5 2.15 6.19 6.69 37.65
12 Stereo Record and Playback 0 0 0 0 0 1 1 1 10 10 11 11 1.8 2.76 5.05 4.64 22.46
PGA in (no MIC) to St. HP Out 0.03 0.00
2.5 3.21 5.90 7.17 40.78
13 Stereo Rec. and Full Playback 0 0 0 0 0 1 1 1 10 10 10 10 1.8 3.49 5.24 7.20 32.47
PGA (no MIC) to St. HP and SPK 0.03 1.00
2.5 3.95 6.10 10.46 55.07
20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample
rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode
and master/slave operation. “Required Initialization Settings” on page 37 written on power up.
21. RESET pin 25 held LO, all clocks and data lines are held LO.
22. RESET pin 25 held HI, all clocks and data lines are held HI.
23. VL current will slightly increase in master mode.
DS680F2 23
3/1/13
CS42L52
4. APPLICATIONS
4.1 Overview
4.1.1 Basic Architecture
The CS42L52 is a highly integrated, low-power, 24-bit audio CODEC comprised of a stereo analog-to-
digital converter (ADC), a stereo digital-to-analog converter (DAC), a digital PWM modulator and two full-
bridge power back-ends. The ADC and DAC are designed using multibit delta-sigma techniques - the
DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where Fs is equal to the
system sample rate.
The different clock rates maximize power savings while maintaining high performance. The PWM modu-
lator operates at a fixed frequency of 384 kHz. The power FETs are configured for either stereo full-bridge
or mono parallel full-bridge output. The CODEC operates in one of four sample rate speed modes: Quar-
ter, Half, Single, and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) de-
rived from an input Master Clock (MCLK).
4.1.2 Line and MIC Inputs

The analog input portion of the CODEC allows selection from and configuration of multiple combinations
of stereo and microphone (MIC) sources. Eight line inputs with an option for two balanced MIC inputs, a
MIC bias output, and a Programmable Gain Amplifier (PGA) comprise the analog front-end.
4.1.3 Line and Headphone Outputs

The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone
and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale
output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and al-
lows the amplifier to deliver more power to headphone loads at lower supply voltages.
4.1.4 Speaker Driver Outputs

The Class D power amplifiers drive 8 ohm (stereo) and 4 ohm (mono) speakers directly, without the need
for an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency
loss associated with an external regulator. Battery level monitoring and compensation maintains a steady
output as battery levels fall. NOTE: The CS42L52 should only be used in captive speaker systems where
the outputs are permanently tied to the speaker terminals.
4.1.5 Fixed Function DSP Engine

The fixed-function digital signal processing engine processes both the PCM serial input data and ADC
output data, allowing a mix between the two. Independent volume control, left/right channel swaps, mono
mixes, tone control, and limiting functions also comprise the DSP engine.
4.1.6 Beep Generator

The beep generator delivers tones at select frequencies across approximately two octave major scales.
With independent volume control, beeps may be configured to occur continuously, periodically, or at sin-
gle time intervals.
4.1.7 Power Management

Three control registers provide independent power-down control of the ADC, DAC, PGA, MIC pre-amp,
MIC bias, Headphone, and Speaker outputs, allowing operation in select applications with minimal power
consumption.
24 DS680F2
3/1/13
CS42L52
4.2 Analog Inputs
ADCAMUTE HPFRZA = PGAASEL[5:1]

PDN_ADCA
DIGSFT HPFA INV_ADCA
DIGZC HPFA_CF[1:0] PDN_CHRG
ADCAVOL[7:0] AIN1A
+24/-96dB
1dB steps AIN2A
Gain Adjust ADC
AIN3A/MIC1-/
ADCASEL[2:0]
 MIC1A
AIN4A/ MIC1+/
DIGSUM [1:0] ALCA MIC2A
ALCASRDIS
ALCAZCDIS PDN_PGAA
PCM Serial Interface
PGAAVOL[5:0] Refer to
ADCB=A “M IC Inputs”
ALCARATE[5:0]
ANLGSFTA
Swap/ ALCRRATE[5:0] NGALL
ALC Noise Gate ANLGZCA
Mix MAX[2:0]
` NG
THRESH[3:0]
BIASLVL[2:0]
PDN_BIAS
PDN_PGAB MICBIAS
DIGM IX M IN[2:0] NGDELAY[1:0] PGABVOL[5:0]
ADCB=A Refer to
ALCB ANLGSFTB “M IC Inputs”
ALCBSRDIS ANLGZCB
ALCBZCDIS AIN4B/ MIC2+/
MIC2B
ADCBSEL[2:0]
Gain Adjust ADC

 AIN3B/MIC2-/
MIC1B
ADCBM UTE AIN2B
DIGSFT
DIGZC
ADCBVOL[7:0] HPFRZB PDN_ADCB AIN1B
+24/-96dB HPB INV_ADCB
1dB steps HPFB_CF[1:0] PDN_CHRG
= PGABSEL[5:1]
ANALOG PASS THRU TO

TO DSP Engine
HEADPHONE AM PLIFIER M UX
FROM DSP ENGINE
Figure 5. Analog Input Signal Flow
Referenced Control Register Location

Analog Front End
PDN_PGAx ......................... “Power Down PGAx” on page 42
PGAxVOL[5:0]..................... “PGAx Volume” on page 56
ADCB=A .............................. “Analog Front-End Volume Setting B=A” on page 50
ANLGSFTx .......................... “Ch. x Analog Soft Ramp” on page 49
ANLGZCx ............................ “Ch. x Analog Zero Cross” on page 49
ADCxSEL[2:0] ..................... “ADC Input Select” on page 48
PGAxSEL5,4,3,2,1 .............. “PGA Input Mapping” on page 49
BIASLVL[2:0] ....................... “MIC Bias Level” on page 48
PDN_BIAS........................... “Power Down MIC Bias” on page 43
PDN_ADCx ......................... “Power Down ADCx” on page 43
PDN_CHRG ........................ “Power Down ADC Charge Pump” on page 42
INV_ADCx ........................... “Invert ADC Signal Polarity” on page 51
HPFRZx............................... “ADCx High-Pass Filter Freeze” on page 49
HPFx ................................... “ADCx High-Pass Filter” on page 49
HPFx_CF[1:0]...................... “HPF x Corner Frequency” on page 50
ADCxOVFL.......................... “ADCx Overflow (Read Only)” on page 71
Digital Volume
ADCxMUTE......................... “ADC Mute” on page 51
ADCxVOL............................ “ADCx Volume” on page 57
ALCx.................................... “ALCx Enable” on page 67
ALCxSRDIS......................... “ALCx Soft Ramp Disable” on page 55
ALCxZCDIS......................... “ALCx Zero Cross Disable” on page 56
ALCARATE[5:0]................... “ALC Attack Rate” on page 67
ALCRRATE[5:0] .................. “ALC Release Rate” on page 68
MAX[2:0].............................. “ALC Maximum Threshold” on page 68
MIN[2:0]............................... “ALC Minimum Threshold” on page 69
NGALL................................. “Noise Gate All Channels” on page 69
NG ....................................... “Noise Gate Enable” on page 69
THRESH[3:0]....................... “Noise Gate Threshold and Boost” on page 70
NGDELAY[1:0] .................... “Noise Gate Delay Timing” on page 70
Miscellaneous
DIGSUM[1:0] ....................... “Digital Sum” on page 50
DIGMUX .............................. “Digital MUX” on page 50
DS680F2 25
3/1/13
CS42L52
4.2.1 MIC Inputs
The input pins 21, 22, 23, and 24 accept stereo line-level or microphone signals. For microphone inputs,
either single-ended or differential configuration is allowed, providing programmable pre-amplification of
low-level signals. In the single-ended configuration, an internal MUX chooses one of two stereo sets (se-
lection is made independently on channels A and B). In the differential configuration, an internal voltage
follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection
above the MICxGAIN setting. The pre-amps are biased to VQ in both configurations.
MICAGAIN[4:0] MICAGAIN[4:0]
-
23 VQ - 23 -
MIC1A MIC1- +
21 + 16..32 dB/ to summing + 16..32 dB/ to summing
21
MIC2A 1 dB steps PGA A MIC1+ 1 dB steps PGA A
MICASEL
MICBGAIN[4:0]
MICBGAIN[4:0]
-
24 -
MIC1B 24 VQ - MIC2- +
+ 16..32 dB/ to summing
22
+ 16..32 dB/ to summing MIC2+ 22 1 dB steps PGA B
MIC2B 1 dB steps PGA B
MICBSEL
MICACFG=’1'b PDN_MICA=’0'b
MICACFG=’0'b PDN_MICA=’0'b MICBCFG=’1'b PDN_MICB=’0'b
MICBCFG=’0'b PDN_MICB=’0'b
Note: Output to PGA = (MIC + - MIC -)*gain + MIC -
Figure 6. Single-Ended MIC Configuration Figure 7. Differential MIC Configuration

MICxCFG ............................ “MICx Configuration” on page 55
PDN_MICx .......................... “Power Down MICx” on page 43
MICxGAIN ........................... “MICx Gain” on page 55
4.2.2 Automatic Level Control (ALC)

When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum (MAX) threshold settings, and responds by applying attenuation as neces-
sary to maintain the resulting level below the MAX threshold. To apply this attenuation, the ALC first low-
ers the PGA gain settings and then increases the digital attenuation levels. All attenuation is applied at a
programmable attack rate.
When input signal levels fall below the minimum (MIN) threshold, the ALC responds by removing any at-
tenuation that it has previously applied until all ALC-applied attenuation has been removed or until the
MAX threshold is again crossed. To remove this attenuation, the ALC first decreases the digital attenua-
tion levels and then increases the PGA gain. All attenuation is removed at a programmable release rate.
It should be noted that the ALC is applied independently to channels A and B with one exception: the input
signals on both channels A and B must be below the MIN threshold in order for the ALC attenuation to be
released on channel B.
Attack and release rates are affected by the ADC soft-ramp/zero-cross settings and sample rate, Fs. ALC
soft-ramp and zero-cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers.
Notes:
1. When ALC x is enabled and the PGAxVOL[5:0] is set above 12 dB, the ADCxVOL[7:0] should not be
set below 0 dB.
2. The maximum realized gain must be set in the PGAxVOL register. The ALC will only apply the gain
set in the PGAxVOL.
3. The ALC maintains the output signal between the MIN/MAX thresholds. As input signal level changes,
the level-controlled output may not always be the same but always falls within the thresholds.
26 DS680F2
3/1/13
CS42L52

PGAxVOL[5:0 “PGAx Vol. and ALCx Transition Ctl.: ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h)” on
MAX[2:0], MIN[2:0] page 55
“ALC Threshold (Address 2Ch)” on page 68
In p u t (b e fo re A L C )
M A X [2 :0 ]
M IN [2 :0 ]
b e lo w fu ll s ca le
b e lo w fu ll s ca le
A LC
R e sp o n se
P G A G a in a n d /o r
A tte n u a to r
O u tp u t
(a fte r A L C )
M A X [2 :0 ]
M IN [2 :0 ]
b e lo w fu ll sca le
b e lo w fu ll sc a le
R R A T E [5 :0 ] A R A T E [5 :0
]
Figure 8. ALC
4.2.3 Noise Gate

The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Note: Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC
pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied,
the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Noise Gate Controls............ “Noise Gate Control (Address 2Dh)” on page 69
Output
(dB)
=1
EN
G
N
-52 dB
Maximum Attenuation*
-64 dB
=0
EN
G
N
-80 dB
Input (dB)
-96 -40
THRESH[2:0]
Figure 9. Noise Gate Attenuation
DS680F2 27
3/1/13
CS42L52
4.3 Analog Outputs
INPUTS FROM ADCA
and ADCB
Fixed Function DSP LIMARATE[7:0]

LIMRRATE[7:0]
MSTAVOL[7:0] LMAX[2:0]
AMIXAMUTE MSTBVOL[7:0] CUSH[2:0]
AMIXBMUTE +12dB/-102dB LIMSRDIS
AMIXAVOL[6:0] 0.5dB steps LIMZCDIS
AMIXBVOL[6:0] LIMIT
+12dB/-51.5dB
0.5dB steps Chnl Vol.
Limiter
VOL Settings PWM
Modulator
PMIXAMUTE
PMIXBMUTE Channel
PMIXAVOL[6:0] ADCASWAP[1:0] Peak
Swap ADCBSWAP[1:0]
PMIXBVOL[6:0] Detect
PCM Serial Interface
PCMASWAP[1:0]
+12dB/-51.5dB
PCMBSWAP[1:0]
0.5dB steps
 
Bass/
Channel
Demph VOL VOL Treble/
Swap
Control
DEEMPH INV_PCMA
INV_PCMB TC_EN
MSTAMUTE BASS_CF[1:0]
BPVOL[4:0]
MSTBMUTE TREB_CF[1:0] DAC
DIGSFT BASS[3:0]
OFFTIME[2:0]
0dB/-50dB DIGZC TREB[3:0]
ONTIME[3:0]
2.0dB steps PLYBCKB=A +12.0dB/-10.5dB
FREQ[3:0]
BEEP[1:0] 1.5dB steps
BEEPMIXDIS Beep VOL
Generator
Digital Mix to ADC

Serial Interface
Figure 10. DSP Engine Signal Flow

DSP
DEEMPH ............................. “HP/Speaker De-emphasis” on page 53
PMIXxMUTE........................ “PCM Mixer Channel x Mute” on page 58
PMIXxVOL[6:0].................... “PCM Mixer Channel x Volume” on page 58
INV_PCMx........................... “Invert PCM Signal Polarity” on page 52
PCMxSWAP[1:0] ................. “PCM Mix Channel Swap” on page 64
AMIXxMUTE........................ “ADC Mixer Channel x Mute” on page 58
AMIXxVOL[6:0].................... “ADC Mixer Channel x Volume” on page 58
ADCxSWAP[1:0].................. “ADC Mix Channel Swap” on page 64
MSTxVOL[7:0]..................... “Master Volume Control” on page 63
MSTxMUTE......................... “Master Playback Mute” on page 52
DIGSFT ............................... “Digital Soft Ramp” on page 53
DIGZC ................................. “Digital Zero Cross” on page 53
PLYBCKB=A........................ “Playback Volume Setting B=A” on page 51
TC_EN................................. “Tone Control Enable” on page 62
BASS_CF[1:0] ..................... “Bass Corner Frequency” on page 62
TREB_CF[1:0] ..................... “Treble Corner Frequency” on page 62
BASS[3:0]............................ “Bass Gain” on page 63
TREB[3:0]............................ “Treble Gain” on page 62
LIMIT ................................... “Peak Detect and Limiter” on page 66
LIMSRDIS ........................... “Limiter Soft Ramp Disable” on page 65
LIMZCDIS............................ “Limiter Zero Cross Disable” on page 66
LMAX[2:0]............................ “Limiter Maximum Threshold” on page 65
CUSH[2:0] ........................... “Limiter Cushion Threshold” on page 65
LIMARATE[7:0].................... “Limiter Attack Rate” on page 67
LIMRRATE[7:0] ................... “Limiter Release Rate” on page 66
28 DS680F2
3/1/13
CS42L52
BATTCMP
VPREF[3:0]
VPLVL[7:0]
SPKAMUTE HPAMUTE PDN_HPA[1:0]
SPKBMUTE HPBMUTE PDN_HPB[1:0]
MUTE50/50 Battery HPA_VOL[7:0]
SPKMONO Compensation HPB_VOL[7:0] HPGAIN[2:0]
SPKSWAP +0dB/-102dB
SPKB=A 0.5dB steps
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB A
0.5dB steps from DSP
VOL DAC
HP/Line
Engine
+ A Outputs
- B
from DSP PWM Gate
VOL + B
Engine Modulator Drive Analog Passthru
- from PGA
VOL Charge
Pump
PASSTHRUA
PDN_SPKA[1:0]
Speaker PASSTHRUB
PDN_SPKB[1:0] Outputs PASSAMUTE
PASSBMUTE
PASSAVOL[7:0] CHGFREQ[3:0]
Short PASSBVOL[70]
+12dB/-60dB
Circuit 0.5dB steps
SPKASHRT (uses PGA)
SPKBSHRT
Figure 11. PWM Output Stage Figure 12. Analog Output Stage

PWM Control
SPKxMUTE ......................... “Speaker Mute” on page 54
MUTE50/50 ......................... “Speaker Mute 50/50 Control” on page 54
SPKMONO .......................... “Speaker MONO Control” on page 54
SPKxVOL[7:0] ..................... “Speaker Volume Control” on page 64
SPKSWAP........................... “Speaker Channel Swap” on page 54
SPKB=A .............................. “Speaker Volume Setting B=A” on page 54
BATTCMP ........................... “Battery Compensation” on page 71
VPREF[3:0] ......................... “VP Reference” on page 72
VPLVL[7:0] .......................... “VP Voltage Level (Read Only)” on page 72
PDN_SPKx[1:0]................... “Speaker Power Control” on page 44
SPKxSHRT.......................... “Speaker Current Load Status (Read Only)” on page 72

Analog Output
HPxMUTE ........................... “Headphone Mute” on page 54
HPxVOL[7:0] ....................... “Headphone Volume Control” on page 63
PDN_HPx[1:0] ..................... “Headphone Power Control” on page 44
HPGAIN[2:0]........................ “Headphone Analog Gain” on page 51
PASSTHRUx ....................... “Passthrough Analog” on page 52
PASSxMUTE ....................... “Passthrough Mute” on page 52
PASSxVOL[7:0] ................... “Passthrough x Volume” on page 57
CHGFREQ .......................... “Charge Pump Frequency” on page 73
4.3.1 Beep Generator

The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple, and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note: The Beep is generated before the limiter and may affect desired limiting performance. If the lim-
iter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep vol-
ume, DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.
DS680F2 29
3/1/13
CS42L52
BEEP[1:0] = CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on
'11' until BEEP is cleared.
BEEP[1:0] = MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)

'10' and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
BEEP is cleared.
BEEP[1:0] = SINGLE-BEEP: Beep turns on at a

'01' configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
BPVOL[4:0] ...
FREQ[3:0]
ONTIME[3:0] OFFTIME[2:0]
Figure 13. Beep Configuration Options

MSTxVOL[7:0]..................... “Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h)” on page 63
PMIXxVOL[6:0] ................... “PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh)” on page 58
OFFTIME[2:0] ..................... “Beep Off Time” on page 60
ONTIME[3:0] ....................... “Beep On Time” on page 60
FREQ[3:0] ........................... “Beep Frequency” on page 59
BEEP[1:0]............................ “Beep Configuration” on page 61
BEEPMIXDIS ...................... “Beep Mix Disable” on page 61
BPVOL[4:0] ......................... “Beep Volume” on page 61
4.3.2 Limiter
When enabled, the limiter monitors the digital input signal before the DAC and PWM modulators, detects
when levels exceed the maximum threshold settings, and lowers the master volume at a programmable
attack rate below the maximum threshold. When the input signal level falls below the maximum threshold,
the AOUT volume returns to its original level set in the Master Volume Control register at a programmable
release rate. Attack and release rates are affected by the DAC soft-ramp/zero-cross settings and sample
rate, Fs. Limiter soft-ramp and zero-cross dependency may be independently enabled/disabled.
Notes:
1. Recommended settings: Best limiting performance may be realized with the fastest attack and
slowest release setting with soft ramp enabled in the control registers. The MIN bits allow the user to
set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound
as the limiter attacks and releases.
2. The Limiter maintains the output signal between the MIN and MAX thresholds. As the digital input
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
Limiter Controls ................... “Limiter Control 2, Release Rate (Address 28h)” on page 66, “Limiter Attack Rate (Address 29h)” on page 67
Master Volume Control........ “Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h)” on page 63
30 DS680F2
3/1/13
CS42L52
In p u t
M A X [2 :0 ]
L im ite r
A T T A C K /R E L E A S E S O U N D
C U S H IO N
V o lu m e
O u tp u t
(a fte r L im ite r)
C U S H [2 :0 ]
M A X [2 :0 ]
A R A T E [5 :0 ] R R A T E [5 :0 ]
Figure 14. Peak Detect and Limiter

4.4 Analog In to Analog Out Passthrough
The CS42L52 accommodates analog routing of the analog input signal directly to the headphone amplifiers.
This feature is useful in applications that utilize an FM tuner where audio recovered over-the-air must be
transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This analog
passthrough path reduces power consumption and is immune to modulator switching noise that could
interfere with some tuners.
4.4.1 Overriding the ADC Power Down

To accommodate automatic activation of the speaker amplifier when the SPK/HP_SW switch pin chang-
es, the CS42L52 provides the option to automatically power up the ADC whenever the analog signal must
route to the digital PWM modulator, regardless of the PDN_ADC bit. Refer to the table below for details
on how this ADC power-down override functions in accordance with the state of the speaker channels.
The shaded cells represent normal ADC operation when passthrough is disabled.
PDN_ADC PASSTHRU PDN_OVRD Speaker Channel ADC Status

0 x x x Powered UP
0 x x Powered DOWN
0 x Powered DOWN
1
1 OFF Powered DOWN
1
ON Powered UP
When PASSTHRU and PDN_OVRD are enabled, turning the speaker channel ON (by writing ‘11’b to SP-
Kx_PDN[1:0] or by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically
disable the ADCx_PDN in order to convert the analog input to a digital signal for the PWM modulator. This
allows automatic analog input routing to the speaker amplifiers.
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CS42L52

PDN_ADCx ......................... “Power Down ADCx” on page 43
PASSTHRU......................... “Passthrough Analog” on page 52
PDN_OVRD ........................ “Power Down ADC Override” on page 43
SPKx_PDN[1:0]................... “Speaker Power Control” on page 44
4.4.2 Overriding the PGA Power Down

To accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin
changes, the CS42L52 will automatically power up the PGA whenever passthrough is enabled, regard-
less of the PDN_PGA setting. Refer to the table below for details on how this PGA power-down override
functions in accordance with the state of the headphone channels. The shaded cells represent normal
PGA operation when passthrough is disabled.
PDN_PGA PASSTHRU HP Channel PGA Status

0 x x Powered UP
0 x Powered DOWN
1 OFF Powered DOWN
1
ON Powered UP
When passthrough is enabled, turning the headphone channel ON (by writing ‘11’b to HPx_PDN[1:0] or
by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the
PGAx_PDN in order to transmit the analog signal to the headphone.
PDN_PGAx ......................... “Power Down PGAx” on page 42
PASSTHRU......................... “Passthrough Analog” on page 52
HPx_PDN[1:0]..................... “Headphone Power Control” on page 44
4.5 PWM Outputs

Note: The PWM speaker amplifiers should not be used in the 384x MCLK modes (18.4320 and
16.9344 MHz).
4.5.1 Mono Speaker Output Configuration

The CS42L52 accommodates a stereo as well as a mono speaker output configuration. In mono mode
the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speak-
er. Refer to the table below for pin mapping in mono configuration.
Speaker Output
Pin SPKMONO=0 SPKMONO=1
SPKSWAP=0 SPKSWAP=1 SPKSWAP=0 SPKSWAP=1
4 SPKOUTA+ SPKOUTB+ SPKOUTA+ SPKOUTB+
6 SPKOUTA- SPKOUTB- SPKOUTA+ SPKOUTB+
7 SPKOUTB+ SPKOUTA+ SPKOUTA- SPKOUTB-
9 SPKOUTB- SPKOUTA- SPKOUTA- SPKOUTB-
SPKMONO.......................... “Speaker MONO Control” on page 54
SPKSWAP........................... “Speaker Channel Swap” on page 54
32 DS680F2
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4.5.2 VP Battery Compensation
The CS42L52 provides the option to maintain a desired power output level, independent of the VP supply.
When enabled, this feature works by monitoring the voltage on the VP supply and reducing the attenua-
tion on the speaker outputs when VP voltage levels fall.
Note: The internal ADC that monitors the VP supply operates from the VA supply. Calculations are
based on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.
4.5.2.1 Maintaining a Desired Output Level

Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expect-
ed VP supply range (MAX relative to MIN). The CS42L52 then gradually reduces the attenuation as the
VP supply drops from its maximum level, maintaining a nearly constant power output.
Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)

1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.
2. Set the reference VP supply (VPREF) to 4.5 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges.
Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)

1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.
2. Set the reference VP supply (VPREF) to 5.0 V.
3. Enable battery compensation (BATTCMP).
The CS42L52 automatically adjusts the output level as the battery discharges. Refer to Figure 15 on page
33. In this example, the VP supply changes over a wide range, illustrating the accuracy of the CS42L52’s
battery compensation.
-6
Battery Compensated
-8
PWM Output Level
PWM Output Level (dB)
-10
-12
Uncompensated
-14 PWM Output
-16 Level
-18
-20
-22
-24
4.9 4.6 4.3 4 3.7 3.4 3.1 2.8 2.5 2.2 1.9 1.6
VP Supply (V)
Figure 15. Battery Compensation
VPREF ................................ “VP Reference” on page 72
SPKxVOL ............................ “Speaker Volume Control” on page 64
4.6 Serial Port Clocking

The CODEC serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
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input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
M/S “Master/Slave Mode” on page 46
Register 05h “Clocking Control (Address 05h)” on page 44
Register 06h “Interface Control 1 (Address 06h)” on page 46
MCLK Sample Rate, SPEED[1:0] 32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2

(MHz) Fs (kHz) (AUTO=’0’b)
8.0000 11 1 0 00 0
12.0000 11 0 0 00 0
16.0000 10 1 0 00 0
12.2880 24.0000 10 0 0 00 0
32.0000 01 1 0 00 0
48.0000 01 0 0 00 0
96.0000 00 0 0 00 0
11.0250 11 0 0 00 0
22.0500 10 0 0 00 0
11.2896
44.1000 01 0 0 00 0
88.2000 00 0 0 00 0
8.0000 11 1 0 00 0
12.0000 11 0 0 00 0
18.4320
16.0000 10 1 0 00 0
(Slave
24.0000 10 0 0 00 0
Mode
32.0000 01 1 0 00 0
ONLY)
48.0000 01 0 0 00 0
96.0000 00 0 0 00 0
8.0182 11 0 0 10 0
16.9344
11.0250 11 0 0 00 0
(Slave
22.0500 10 0 0 00 0
Mode
44.1000 01 0 0 00 0
ONLY)
88.2000 00 0 0 00 0
8.0000 11 1 0 01 0
11.0294 11 0 0 11 0
12.0000 11 0 0 01 0
16.0000 10 1 0 01 0
22.0588 10 0 0 11 0
12.0000 24.0000 10 0 0 01 0
32.0000 01 1 0 01 0
44.1176 01 0 0 11 0
48.0000 01 0 0 01 0
88.2353 00 0 0 11 0
96.0000 00 0 0 01 0
8.0000 11 1 0 01 1
11.0294 11 0 0 11 1
12.0000 11 0 0 01 1
16.0000 10 1 0 01 1
22.0588 10 0 0 11 1
24.0000 24.0000 10 0 0 01 1
32.0000 01 1 0 01 1
44.1176 01 0 0 11 1
48.0000 01 0 0 01 1
88.2353 00 0 0 11 1
96.0000 00 0 0 01 1
Table 1. MCLK, LRCK Quick Decode
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CS42L52
MCLK Sample Rate, SPEED[1:0] 32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2
(MHz) Fs (kHz) (AUTO=’0’b)
8.0000 11 1 1 01 0
12.0000 11 0 1 01 0
24.0000 10 0 1 01 0
32.0000 01 1 1 01 0
27.0000 44.1176 01 0 1 11 0
48.0000 01 0 1 01 0
11.0294 11 0 1 11 0
22.0588 10 0 1 11 0
16.0000 10 1 1 01 0
Table 1. MCLK, LRCK Quick Decode
4.7 Digital Interface Formats

The serial port operates in standard I²S, Left-justified, Right-justified (DAC only), or DSP Mode digital inter-
face formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the
rising edge of SCLK.
LRCK
L eft C h a n n el R ig ht C h a n n el
SCLK
SDIN MSB LS B M SB LS B MSB

SDOUT
AOUTA / AINxA AOUTB / AINxB
Figure 16. I²S Format
LRCK
L eft C h a n n el R ig ht C h a n n el
SCLK
SDIN MSB LS B M SB LS B MSB

SDOUT
AOUTA / AINxA AOUTB / AINxB
Figure 17. Left-Justified Format
LRCK L e ft C h a n n e l R ig h t C h a n n e l
SCLK
SDIN MSB LSB MSB LS B
AO UTL AO UTR
Audio W ord Length (AW L)
Figure 18. Right-Justified Format (DAC only)
4.7.1 DSP Mode

In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edge after the frame sync
rising edge. The right channel immediately follows the left channel.
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CS42L52
1/fs
LRCK
SCLK
SDIN L SB MSB L eft C h a n n el LS B M SB R ig ht C h a n n el LSB M SB
HP/LINE OUTA HP/LINE OUTB

Audio Word Length (AWL)
Figure 19. DSP Mode Format)
When configuring the 16-bit SDOUT word length with an 8 kHz sample rate in master mode and when
SCLK is set equal to MCLK, perform the following write sequences:
Register commands ONLY when entering DSP 16-bit, 8 kHz Fs, SCLK=MCLK, master mode:
Register[Bits] Value Description
1 0x0C[1:0] 0x03 Mute the ADC outputs to ensure no audible artifacts are transmitted when changing modes.
2 Refer to Section 4.10 Follow the recommended power down sequence for the HP and PWM outputs.
3 0x02[0] 0x01 Power down the CODEC.
4 0x05[7:0] 0x72 Enable 8 kHz Fs for MCLK=12.000 MHz.
5 0x06[7:0] 0x93 Enable DSP 16-bit master mode.
6 0x07[6] 0x01 Enable SCLK=MCLK.
7 0x33[6] 0x01 Undisclosed register command for enabling mode mentioned above.
8 Refer to Section 4.9 Follow the recommended power up sequence for the HP and PWM outputs.
9 0x02[0] 0x00 Power up the CODEC.
10 0x0C[1:0] 0x00 Unmute the ADC outputs.
Register commands when exiting DSP 16-bit, 8 kHz Fs, SCLK=MCLK, master mode:
Register[Bits] Value Description
1 0x0C[1:0] 0x03 Mute the ADC outputs to ensure no audible artifacts are transmitted when changing modes.
2 Refer to Section 4.10 Follow the recommended power down sequence for the HP and PWM outputs.
3 0x02[0] 0x01 Power down the CODEC.
4 0x05[7:0] 0x20 Enable 48 kHz Fs for MCLK = 12.2880 MHz or re-establish original settings.
5 0x06[7:0] 0x00 Enable Left-Justified 24-bit slave mode or re-establish original settings.
6 0x07[6] 0x00 Disable SCLK=MCLK or re-establish original settings.
7 0x33[6] 0x00 Undisclosed register command for disabling mode mentioned above.
8 Refer to Section 4.9 Follow the recommended power up sequence for the HP and PWM outputs.
9 0x02[0] 0x00 Power up the CODEC.
10 0x0C[1:0] 0x00 Unmute the ADC outputs.
4.8 Initialization
The CODEC enters a Power-down state on initial power-up. The interpolation and decimation filters, delta-
sigma and PWM modulators, and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device remains in Power-down state until the RESET pin is brought high. The control port is accessible
once RESET is high and the desired register settings can be loaded per the descriptions in the Section 6.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-
ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MC-
LK/LRCK frequency ratio and normal operation begins.
36 DS680F2
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CS42L52
4.9 Recommended Power-up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high.
3. The default state of the PDN bit is 1. Load the desired register settings while keeping the PDN bit set
to 11.
4. Load the required initialization settings listed in Section 4.11.
5. Apply MCLK at the appropriate frequency, as discussed in Section 4.6. SCLK may be applied or set to
master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.
6. Set the PDN bit to 0.
7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10 Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the CODEC in standby:
1. Mute the DACs, PWM outputs and ADCs.
2. Disable soft ramp and zero cross volume transitions.
3. Set the PDN bit to 1.
4. Wait at least 100 µs.
The CODEC will be fully powered down after this 100 µs delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 µs must be implemented after step 3 to avoid premature disruption
of the CODEC’s power down sequence.
A disruption in the CODEC’s power down sequence (i.e. removing the MCLK signal before this 100 µs
delay) has consequences on both the headphone and speaker amplifiers: The charge pump may stop
abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the last
state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the CODEC’s power down sequence may also cause clicks and pops on the output
of the DACs as the modulator holds the last output level before the MCLK signal was removed.
5. Optionally, MCLK may be removed at this time.
6. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
7. Power Supply Removal (Option 1): Switch power supplies to a high impedance state.
8. Power Supply Removal (Option 2): To minimize pops when the power supplies are pulled to ground, a
discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M resistor
and a 2.2 µF capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds. A 1 M resistor
on FILT+ reduces the full scale input/output voltage by approximately 0.25 dB.
After step 5, wait the required time for FILT+ to ramp to ground before pulling VA to ground.
4.11 Required Initialization Settings

The current and thresholds required for various sections in the CODEC must be adjusted by implementing
the initialization settings shown below after power-up sequence step 3. All performance and power con-
sumption measurements were taken with the following settings:
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CS42L52
1. Write 0x99 to register 0x00.
2. Write 0xBA to register 0x3E.
4. Write 1 to bit 7 in register 0x32.
5. Write 00 to bit 7 in register 0x32.
4.12 Control Port Operation

The control port is used to access the registers, allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates using an I²C interface with the CODEC acting as a slave device.
4.12.1 I²C Control

SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 pin
sets the LSB of the chip address; ‘0’ when connected to DGND, ‘1’ when connected to VL. This pin may
be driven by a host controller or directly connected to VL or DGND. The AD0 pin state is sensed and the
LSB of the chip address is set upon the release of the RESET signal (a low-to-high transition).
The signal timings for a read and write cycle are shown in Figure 20 and Figure 21. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising tran-
sition of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte
sent to the CS42L52 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a
read, low for a write).
The upper 6 bits of the address field are fixed at 100101. To communicate with the CS42L52, the chip
address field, which is the first byte sent to the CS42L52, should match 100101 followed by the setting of
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP), which selects the register to be read or written. If the operation is a read,
the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the CS42L52 after each input byte is read and is input to the CS42L52 from
the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1 DATA +n
SDA 1 0 0 1 0 1 AD0 0 INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
ACK ACK ACK ACK

START STOP
Figure 20. Control Port Timing, I²C Write
38 DS680F2
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CS42L52
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
STOP
CHIP ADDRESS (WRITE) MAP BYTE CHIP ADDRESS (READ) DATA DATA +1 DATA + n
SDA 1 0 0 1 0 1 AD0 0 INCR 6 5 4 3 2 1 0 1 0 0 1 0 1 AD0 1 7 0 7 0 7 0

ACK ACK ACK ACK NO
START START ACK
STOP
Figure 21. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 21, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.

Send 10010100 (chip address and write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Send stop condition, aborting write.
Send start condition.
Send 10010101 (chip address and read operation).
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.12.2 Memory Address Pointer (MAP)

The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.12.2.1 Map Increment (INCR)

The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-in-
crement after each byte is read or written, allowing block reads or writes of successive registers.
DS680F2 39
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CS42L52
5. REGISTER QUICK REFERENCE
Default values are shown below the bit names. Unless otherwise specified, all “Reserved” bits must maintain their
default values.
Adr. Function 7 6 5 4 3 2 1 0
01h ID CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0
p 42 1 1 1 0 0 x x x
02h Power Ctl 1 PDN_CHRG Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
p 42 0 0 0 0 0 0 0 1
03h Power Ctl 2 Reserved Reserved Reserved OVRDB OVRDA PDN_MICB PDN_MICA PDN_BIAS
p 43 0 0 0 0 0 1 1 1
04h Power Ctl 3 PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0
p 44 0 0 0 0 0 1 0 1
05h Clocking Ctl AUTO SPEED1 SPEED0 32kGROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2
p 44 1 0 1 0 0 0 0 0
06h Interface Ctl 1 M/S INV_SCLK ADCDIF DSP DACDIF1 DACDIF0 AWL1 AWL0
p 46 0 0 0 0 0 0 0 0
07h Interface Ctl 2 Reserved SCLK=MCLK DIGLOOP 3ST_SP INV_SWCH BIASLVL2 BIASLVL1 BIASLVL0
p 47 0 0 0 0 0 0 0 0
08h Input A Select ADCASEL2 ADCASEL1 ADCASEL0 PGAASEL5 PGAASEL4 PGAASEL3 PGAASEL2 PGAASEL1
p 48 1 0 0 0 0 0 0 1
09h Input B Select ADCBSEL2 ADCBSEL1 ADCBSEL0 PGABSEL5 PGABSEL4 PGABSEL3 PGABSEL2 PGABSEL1
p 48 1 0 0 0 0 0 0 1
0Ah Analog, HPFB HPFRZB HPFA HPFRZA ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA
p 49 HPF Ctl 1 0 1 0 0 1 0 1
0Bh ADC HPF Cor- Reserved Reserved Reserved Reserved HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0
p 50 ner Freq. 0 0 0 0 0 0 0 0
0Ch Misc. ADC Ctl ADCB=A DIGMIX DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADCBMUTE ADCAMUTE
p 50 0 0 0 0 0 0 0 0
0Dh Playback Ctl 1 HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE
p 51 0 1 1 0 0 0 0 0
0Eh Misc. Ctl PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC
p 52 0 0 0 0 0 0 1 0
0Fh Playback Ctl 2 HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50
p 54 0 0 0 0 0 0 0
10h MICA Amp Ctl Reserved MICASEL MICACFG MICAGAIN4 MICAGAIN3 MICAGAIN2 MICAGAIN1 MICAGAIN0
p 55 0 0 0 0 0 0 0 0
11h MICB Amp Ctl Reserved MICBSEL MICBCFG MICBGAIN4 MICBGAIN3 MICBGAIN2 MICBGAIN1 MICBGAIN0
p 55 0 0 0 0 0 0 0 0
12h PGAA Vol, Misc ALCASRDIS ALCAZCDIS PGAAVOL5 PGAAVOL4 PGAAVOL3 PGAAVOL2 PGAAVOL1 PGAAVOL0
p 55 0 0 0 0 0 0 0 0
13h PGAB Vol, Misc ALCBSRDIS ALCBZCDIS PGABVOL5 PGABVOL4 PGABVOL3 PGABVOL2 PGABVOL1 PGABVOL0
p 55 0 0 0 0 0 0 0 0
14h Passthru A Vol PASSAVOL7 PASSAVOL6 PASSAVOL5 PASSAVOL4 PASSAVOL3 PASSAVOL2 PASSAVOL1 PASSAVOL0
p 57 0 0 0 0 0 0 0 0
15h Passthru B Vol PASSBVOL7 PASSBVOL6 PASSBVOL5 PASSBVOL4 PASSBVOL3 PASSBVOL2 PASSBVOL1 PASSBVOL0
p 57 0 0 0 0 0 0 0 0
16h ADCA Vol ADCAVOL7 ADCAVOL6 ADCAVOL5 ADCAVOL4 ADCAVOL3 ADCAVOL2 ADCAVOL1 ADCAVOL0
p 57 0 0 0 0 0 0 0 0
17h ADCB Vol ADCBVOL7 ADCBVOL6 ADCBVOL5 ADCBVOL4 ADCBVOL3 ADCBVOL2 ADCBVOL1 ADCBVOL0
p 57 0 0 0 0 0 0 0 0
18h ADCMIXA Vol AMIXAMUTE AMIXAVOL6 AMIXAVOL5 AMIXAVOL4 AMIXAVOL3 AMIXAVOL2 AMIXAVOL1 AMIXAVOL0
p 58 1 0 0 0 0 0 0 0
19h ADCMIXB Vol AMIXBMUTE AMIXBVOL6 AMIXBVOL5 AMIXBVOL4 AMIXBVOL3 AMIXBVOL2 AMIXBVOL1 AMIXBVOL0
p 58 1 0 0 0 0 0 0 0
1Ah PCMMIXA Vol PMIXAMUTE PMIXAVOL6 PMIXAVOL5 PMIXAVOL4 PMIXAVOL3 PMIXAVOL2 PMIXAVOL1 PMIXAVOL0
p 58 0 0 0 0 0 0 0 0
40 DS680F2
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CS42L52
Adr. Function 7 6 5 4 3 2 1 0
1Bh PCMMIXB Vol PMIXBMUTE PMIXBVOL6 PMIXBVOL5 PMIXBVOL4 PMIXBVOL3 PMIXBVOL2 PMIXBVOL1 PMIXBVOL0
p 58 0 0 0 0 0 0 0 0
1Ch BEEP Freq, FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
p 59 On Time 0 0 0 0 0 0 0 0
1Dh BEEP Vol, OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
p 60 Off Time 0 0 0 0 0 0 0 0
1Eh BEEP, BEEP1 BEEP0 BEEPMIXDIS TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
p 61 Tone Cfg. 0 0 0 0 0 0 0 0
1Fh Tone Ctl TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
p 62 1 0 0 0 1 0 0 0
20h Master A Vol MSTAVOL7 MSTAVOL6 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1 MSTAVOL0
p 63 0 0 0 0 0 0 0 0
21h Master B Vol MSTBVOL7 MSTBVOL6 MSTBVOL5 MSTBVOL4 MSTBVOL3 MSTBVOL2 MSTBVOL1 MSTBVOL0
p 63 0 0 0 0 0 0 0 0
22h Headphone A HPAVOL7 HPAVOL6 HPAVOL5 HPAVOL4 HPAVOL3 HPAVOL2 HPAVOL1 HPAVOL0
p 63 Volume 0 0 0 0 0 0 0 0
23h Headphone B HPBVOL7 HPBVOL6 HPBVOL5 HPBVOL4 HPBVOL3 HPBVOL2 HPBVOL1 HPBVOL0
p 63 Volume 0 0 0 0 0 0 0 0
24h Speaker A SPKAVOL7 SPKAVOL6 SPKAVOL5 SPKAVOL4 SPKAVOL3 SPKAVOL2 SPKAVOL1 SPKAVOL0
p 64 Volume 0 0 0 0 0 0 0 0
25h Speaker B SPKBVOL7 SPKBVOL6 SPKBVOL5 SPKBVOL4 SPKBVOL3 SPKBVOL2 SPKBVOL1 SPKBVOL0
p 64 Volume 0 0 0 0 0 0 0 0
26h Channel Mixer PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 ADCASWP1 ADCASWP0 ADCBSWP1 ADCBSWP0
p 64 and Swap 0 0 0 0 0 0 0 0
27h Limit Ctl 1, LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS
p 65 Thresholds 0 0 0 0 0 0 0 0
28h Limit Ctl 2, LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0
p 66 Release Rate 0 1 1 1 1 1 1 1
29h Limiter Attack Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0
p 67 Rate 1 1 0 0 0 0 0 0
2Ah ALC Ctl 1, ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0
p 67 Attack Rate 0 0 0 0 0 0 0 0
2Bh ALC Release Reserved Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0
p 68 Rate 0 0 1 1 1 1 1 1
2Ch ALC Thresh- ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALCMIN0 Reserved Reserved
p 68 olds 0 0 0 0 0 0 0 0
2Dh Noise Gate Ctl NGALL NG NGBOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
p 69 0 0 0 0 0 0 0 0
2Eh Overflow and Reserved SPCLKERR DSPBOVFL DSPAOVFL PCMAOVFL PCMBOVFL ADCAOVFL ADCBOVFL
p 70 Clock Status 0 0 0 0 0 0 0 0
2Fh Battery Com- BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0
p 71 pensation 0 0 0 0 0 0 0 0
30h VP Battery VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0
p 72 Level 0 0 0 0 0 0 0 0
31h Speaker Status Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved
p 72 0 0 0 0 0 0 0 0
32h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 1 1 1 0 1 1
33h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
34h Charge Pump CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved
p 73 Frequency 0 1 0 1 1 1 1 1
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6. REGISTER DESCRIPTION
All registers are read/write except for the Chip I.D. and Revision Register and Interrupt Status Register, which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description. Unless otherwise specified, all “Reserved” bits must
maintain their default value.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
7 6 5 4 3 2 1 0
CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0
6.1.1 Chip I.D. (Read Only)

I.D. code for the CS42L52.
CHIPID[4:0] Device
11100 CS42L52
6.1.2 Chip Revision (Read Only)

CS42L52 revision level.
REVID[2:0] Revision Level
000 A0
001 A1
010 B0
011 B1
6.2 Power Control 1 (Address 02h)

7 6 5 4 3 2 1 0
PDN_CHRG Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN
6.2.1 Power Down ADC Charge Pump

Configures the power state of the ADC charge pump.
PDN_CHRG ADC Charge Pump Status
0 Powered Up
1 Powered Down
6.2.2 Power Down PGAx

Configures the power state of PGA channel x.
PDN_PGAx PGA Status
0 Powered Up (ONLY when the ADC or the analog passthru is used)
1 Powered Down
Application “Analog In to Analog Out Passthrough” on page 31
Notes:
1. The CS42L52 employs a scheme for controlling the power to the PGA when PASSTHRU (“Passthrough
Analog” on page 52) is enabled. Refer to the referenced application for more information.
2. This bit should be used in conjunction with ADCxSEL and PGAxSEL bits to determine the analog
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input path. The PGAxSEL bits may be used to isolate the input signal(s) from the PGA outputs. When
the PGA is powered down, no input should be selected. Refer to “ADC Input Select” on page 48 and
“PGA Input Mapping” on page 49 for the required settings.
6.2.3 Power Down ADCx

Configures the power state of ADC channel x.
PDN_ADCx ADC Status
0 Powered Up
1 Powered Down
Notes:
1. The CS42L52 employs a scheme for controlling the power to the ADC when PASSTHRU
(“Passthrough Analog” on page 52) and PDN_OVRD (“Power Down ADC Override” on page 43) are
enabled. Refer to the referenced application.
6.2.4 Power Down

Configures the power state of the entire CODEC.
PDN CODEC Status
0 Powered Up
1 Powered Down

7 6 5 4 3 2 1 0
Reserved Reserved Reserved OVRDB OVRDA PDN_MICB PDN_MICA PDN_BIAS
6.3.1 Power Down ADC Override

Configures an override of the power down control for ADCx.
OVRDx PDN_ADC Override
0 Disable
1 Enable
6.3.2 Power Down MICx

Configures the power state of the microphone pre-amplifier for channel x.
PDN_MICx MIC Pre-Amp Status
0 Powered Up
1 Powered Down
Application “MIC Inputs” on page 26
6.3.3 Power Down MIC Bias

Configures the power state of the microphone bias circuit.
PDN_BIAS MIC Bias Status
0 Powered Up
1 Powered Down
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7 6 5 4 3 2 1 0
PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0
6.4.1 Headphone Power Control

Configures how the SPKR/HP pin, 31, controls the power for the headphone amplifier.
PDN_HPx[1:0] Headphone Status
Headphone channel is ON when the SPKR/HP pin, 31, is LO.
00
Headphone channel is OFF when the SPKR/HP pin, 31, is HI.
Headphone channel is ON when the SPKR/HP pin, 31, is HI.
01
Headphone channel is OFF when the SPKR/HP pin, 31, is LO.
10 Headphone channel is always ON.
11 Headphone channel is always OFF.
6.4.2 Speaker Power Control

Configures how the SPKR/HP pin, 31, controls the power for the speaker amplifier.
PDN_SPKx[1:0] Speaker Status
Speaker channel is ON when the SPKR/HP pin, 31, is LO.
00
Speaker channel is OFF when the SPKR/HP pin, 31, is HI.
Speaker channel is ON when the SPKR/HP pin, 31, is HI.
01
Speaker channel is OFF when the SPKR/HP pin, 31, is LO.
10 Speaker channel is always ON.
11 Speaker channel is always OFF.
6.5 Clocking Control (Address 05h)

7 6 5 4 3 2 1 0
AUTO SPEED1 SPEED0 32k_GROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2
6.5.1 Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a
slave.
AUTO Auto-detection of Speed Mode
0 Disabled
1 Enabled
Application: “Serial Port Clocking” on page 33
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
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6.5.2 Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for
LRCK and SCLK in master mode.
Slave Mode Master Mode
SPEED[1:0]
Serial Port Speed MCLK/LRCK Ratio SCLK/LRCK Ratio
00 Double-Speed Mode (DSM - 50 kHz -100 kHz Fs) 128 64
01 Single-Speed Mode (SSM - 4 kHz -50 kHz Fs) 256 64
10 Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs) 512 64
11 Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs) 1024 64
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on
page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 44) is enabled.
6.5.3 32kHz Sample Rate Group

Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
32kGROUP 8 kHz, 16 kHz or 32 kHz sample rate?
0 No
1 Yes
6.5.4 27 MHz Video Clock

Specifies whether or not the external MCLK frequency is 27 MHz
VIDEOCLK 27 MHz MCLK?
0 No
1 Yes
6.5.5 Internal MCLK/LRCK Ratio

Configures the internal MCLK/LRCK ratio.
RATIO[1:0] Internal MCLK Cycles per LRCK SCLK/LRCK Ratio in Master Mode
00 128 64
01 125 62
10 132 66
11 136 68
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6.5.6 MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
MCLKDIV2 MCLK signal into CODEC
0 No divide
1 Divided by 2
Note: In slave mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 44) is disabled.
6.6 Interface Control 1 (Address 06h)

7 6 5 4 3 2 1 0
M/S INV_SCLK ADCDIF DSP DACDIF1 DACDIF0 AWL1 AWL0
6.6.1 Master/Slave Mode

Configures the serial port I/O clocking.
M/S Serial Port Clocks
0 Slave (input ONLY)
1 Master (output ONLY)
6.6.2 SCLK Polarity

Configures the polarity of the SCLK signal.
INV_SCLK SCLK Polarity
0 Not Inverted
1 Inverted
6.6.3 ADC Interface Format

Configures the digital interface format for data on SDOUT.
ADCDIF ADC Interface Format
0 Left Justified
1 I²S
Application: “Digital Interface Formats” on page 35
6.6.4 DSP Mode

Configures a data-packed interface format for both the ADC and DAC.
DSP DSP Mode
0 Disabled
1 Enabled
Application: “DSP Mode” on page 35
Notes:
1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 47).
2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode
is enabled.
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6.6.5 DAC Interface Format
Configures the digital interface format for data on SDIN.
DACDIF[1:0] DAC Interface Format
00 Left Justified, up to 24-bit data
01 I²S, up to 24-bit data
10 Right Justified
11 Reserved
Application: “Digital Interface Formats” on page 35
Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
page 47).
6.6.6 Audio Word Length

Configures the audio sample word length used for the data into SDIN and out of SDOUT.
Audio Word Length
AWL[1:0]
DSP Mode Right Justified (DAC ONLY)
00 32-bit data 24-bit data
Application: “DSP Mode” on page 35
Note: When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
6.7 Interface Control 2 (Address 07h)

7 6 5 4 3 2 1 0
Reserved SCLK=MCLK DIGLOOP 3ST_SP INV_SWCH BIASLVL2 BIASLVL1 BIASLVL0
6.7.1 SCLK equals MCLK

Configures the SCLK signal source for master mode.
SCLK=MCLK Output SCLK
0 Re-timed signal, synchronously derived from MCLK
1 Non-retimed, MCLK signal
Note: This bit is only valid for MCLK = 12.0000 MHz.
6.7.2 SDOUT to SDIN Digital Loopback

Configures an internal loops the signal on the SDOUT pin to SDIN.
DIGLOOP Internal Loopback
0 Disabled; SDOUT internally disconnected from SDIN
1 Enabled; SDOUT internally connected to SDIN
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6.7.3 Tri-State Serial Port Interface
Determines the state of the serial port drivers.
Serial Port Status
3ST_SP
Slave Mode Master Mode
0 Serial Port clocks are inputs and SDOUT is output Serial Port clocks and SDOUT are outputs
1 Serial Port clocks are inputs and SDOUT is HI-Z Serial Port clocks and SDOUT are HI-Z
Notes:
1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.
2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.
6.7.4 Speaker/Headphone Switch Invert

Determines the control signal polarity of the SPK/HP_SW pin.
INV_SWCH SPK/HP_SW pin 6 Control
0 Not inverted
1 Inverted
6.7.5 MIC Bias Level

Sets the output voltage level on the MICBIAS output pin.
BIASLVL[2:0] Output Bias Level
000 0.5 x VA
001 0.6 x VA
010 0.7 x VA
011 0.8 x VA
100 0.83 x VA
101 0.91 x VA
110 Reserved
111 Reserved
6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)
7 6 5 4 3 2 1 0
ADCASEL2 ADCASEL1 ADCASEL0 PGAASEL5 PGAASEL4 PGAASEL3 PGAASEL2 PGAASEL1
6.8.1 ADC Input Select

Selects the specified analog input signal into ADCx.
ADCxSEL[2:0] Selected Input to ADCx
000 AIN1x
001 AIN2x
010 AIN3x
011 AIN4x
100 PGAx - Use PGAxSEL bits (“PGA Input Mapping” on page 49) to select input channels
101 Reserved
110 Reserved
111 Reserved
Application: “Analog Inputs” on page 25
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6.8.2 PGA Input Mapping
Selects one or sums/mixes the analog input signal into the PGA. Each bit of the PGAx_SEL[5:1] word
corresponds to individual channels (i.e. PGAx_SEL1 selects AIN1x, PGAx_SEL2 selects AIN2x, etc.).
PGAxSEL[5:1] Selected Input to PGAx (Examples)
00000 No inputs selected
00001 AIN1x
00010 AIN2x
00100 AIN3x
01000 AIN4x
MICx; for single-ended MIC inputs, use MICxSEL (“MIC x Select” on page 55) to select MIC 1 or MIC 2; for
10000
differential MIC inputs, enable MICxCFG (“MICx Configuration” on page 55)
10001 MICx + AIN1x
10011 MICx + AIN1x + AIN2x
Note: Table does not show all possible combinations.
6.9 Analog and HPF Control (Address 0Ah)

7 6 5 4 3 2 1 0
HPFB HPFRZB HPFA HPFRZA ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA
6.9.1 ADCx High-Pass Filter

Configures the internal high-pass filter after ADCx.
HPFx High Pass Filter Status
0 Disabled
1 Enabled
6.9.2 ADCx High-Pass Filter Freeze

Configures the high pass filter’s digital DC subtraction and/or calibration after ADCx.
HPFRZx High Pass Filter Digital Subtraction
0 Continuous DC Subtraction
1 Frozen DC Subtraction
6.9.3 Ch. x Analog Soft Ramp

Configures an incremental volume ramp from the current level to the new level at the specified rate.
ANLGSFTx Volume Changes Affected Analog Volume Controls
0 Do not occur with a soft ramp MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”
1 Occur with a soft ramp on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
Ramp Rate: 1/2 dB every 16 LRCK cycles
6.9.4 Ch. x Analog Zero Cross

Configures when the signal level changes occur for the analog volume controls.
ANLGZCx Volume Changes Affected Analog Volume Controls
Do not occur on a zero cross-
0 MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”
ing
on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
1 Occur on a zero crossing
Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
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6.10 ADC HPF Corner Frequency (Address 0Bh)
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0
6.10.1 HPF x Corner Frequency

Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF).
HPFx_CF[1:0] HPF Corner Frequency Setting (Fs=48 kHz)
00 Normal setting as specified in “ADC Digital Filter Characteristics” on page 14
01 119 Hz
10 236 Hz
11 464 Hz
6.11 Misc. ADC Control (Address 0Ch)

7 6 5 4 3 2 1 0
ADCB=A DIGMUX DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADCBMUTE ADCAMUTE
6.11.1 Analog Front-End Volume Setting B=A

Configures independent or ganged volume control and muting of the analog front end.
ADCB=A Single Volume Control Affected Volume Controls
0 Disabled ADCxVOL[7:0] (“ADCx Volume” on page 57),
ADCxMUTE (“ADC Mute” on page 51),
ALC and Limiter Attack/Release (page 66 to page 68)
1 Enabled MICxGAIN[4:0] (“MICx Gain” on page 55),
PGAxVOL[5:0] (“PGAx Volume” on page 56),
PASSxVOL[7:0] (“Passthrough x Volume” on page 57)
6.11.2 Digital MUX

Selects the signal source for the ADC serial port
DIGMUX SDOUT Signal Source
0 ADC
1 DSP
6.11.3 Digital Sum

Configures a mix/swap of ADCA and ADCB.
Serial Output Signal
DIGSUM[1:0]
Left Channel Right Channel
00 ADCA ADCB
01 (ADCA + ADCB)/2 (ADCA + ADCB)/2
10 (ADCA - ADCB)/2 (ADCA - ADCB)/2
11 ADCB ADCA
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6.11.4 Invert ADC Signal Polarity
Configures the polarity of the ADC signal.
INV_ADCx ADC Signal Polarity
0 Not Inverted
1 Inverted
6.11.5 ADC Mute

Configures a digital mute on ADC channel x.
ADCxMUTE ADC Mute
0 Disabled
1 Enabled
Note: When the ADCxMUTE bit is enabled, the PGA will automatically apply 6 dB of attenuation.
6.12 Playback Control 1 (Address 0Dh)

7 6 5 4 3 2 1 0
HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE
6.12.1 Headphone Analog Gain

Selects the gain multiplier for the headphone/line outputs.
HPGAIN[2:0] Headphone/Line Gain Setting (G)
000 0.3959
001 0.4571
010 0.5111
011 0.6047
100 0.7099
101 0.8399
110 1.000
111 1.1430
Note: Refer to “Line Output Voltage Level Characteristics” on page 19 and “Headphone Output Power
Characteristics” on page 18.
6.12.2 Playback Volume Setting B=A

Configures independent or ganged volume control of all playback channels.
PLYBCKB=A Single Volume Control Affected Volume Controls
0 Disabled HPxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),
AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
1 Enabled MSTxVOL[7:0] (“Master Volume Control” on page 63),
HPxVOL[7:0] (“Headphone Volume Control” on page 63)
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6.12.3 Invert PCM Signal Polarity
Configures the polarity of the digital input signal.
INV_PCMx PCM Signal Polarity
0 Not Inverted
1 Inverted
6.12.4 Master Playback Mute

Configures a digital mute on the master volume control for channel x.
MSTxMUTE Master Mute
0 Not Inverted
1 Inverted
Note: The muting function is affected by the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC
(“Digital Zero Cross” on page 53) bits.
6.13 Miscellaneous Controls (Address 0Eh)

7 6 5 4 3 2 1 0
PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC
6.13.1 Passthrough Analog

Configures an analog passthrough from the PGA inputs to the headphone/line outputs.
PASSTHRUx Analog In Routed to HP/Line Output
0 Disabled
1 Enabled
Notes:
1. The Passthrough volume control is realized using a combination of the PGA volume control settings
(“PGAx Volume” on page 56) and the headphone amplifier volume control settings (hidden). When
passthrough is enabled and the PGA to ADC path is selected, the signal seen by the ADC will change
depending on the passthrough volume setting.
6.13.2 Passthrough Mute

Configures an analog mute on the channel x analog in to analog out passthrough.
PASSxMUTE Passthrough Mute
0 Disabled
1 Enabled
6.13.3 Freeze Registers

Configures a hold on all register settings.
FREEZE Control Port Status
0 Register changes take effect immediately
Modifications may be made to all control port registers without the changes taking effect until after the
1
FREEZE is disabled.
Notes:
1. Use this bit only to synchronize run-time controls, such as volume and mute, during normal operation.
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Using this bit before the relevant circuitry begins normal operation could cause the change to take
effect immediately, ignoring the FREEZE bit.
6.13.4 HP/Speaker De-emphasis

Configures a 15s/50s digital de-emphasis filter response on the headphone/line and speaker outputs.
DEEMPHASIS Control Port Status
0 Disabled
1 Enabled
6.13.5 Digital Soft Ramp

Configures an incremental volume ramp from the current level to the new level at the specified rate.
DIGSFT Volume Changes Affected Digital Volume Controls
0 Do not occur with a soft ramp MSTxMUTE (“Master Playback Mute” on page 52),
HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),
ADCxVOL[7:0] (“ADCx Volume” on page 57),
AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
1 Occur with a soft ramp MSTxVOL[7:0] (“Master Volume Control” on page 63),
HPxVOL[7:0] (“Headphone Volume Control” on page 63),
SPKxVOL[7:0] (“Speaker Volume Control” on page 64),
ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
Ramp Rate: 1/8 dB every LRCK cycle
Note: When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed
to occur with a soft ramp only when bits 7 and 6 in register 29h are set to ‘00’b.
6.13.6 Digital Zero Cross

Configures when the signal level changes occur for the digital volume controls.
DIGZC Volume Changes Affected Digital Volume Controls
Do not occur on a zero cross- MSTxMUTE (“Master Playback Mute” on page 52),
0
ing AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),
PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),
MSTxVOL[7:0] (“Master Volume Control” on page 63),
1 Occur on a zero crossing ALC and Limiter Attack/Release (page 66 to page 68)
Beep Volume (“Beep Volume” on page 61)
Notes:
1. If the signal does not encounter a zero crossing, the requested volume change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate).
2. The zero cross function is independently monitored and implemented for each channel.
3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is enabled.
4. When the DIGZC bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to
occur on a zero cross only if bits 7 and 6 in register 29h are set to '00'b
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6.14 Playback Control 2 (Address 0Fh)
7 6 5 4 3 2 1 0
HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50
6.14.1 Headphone Mute

Configures a digital mute on headphone channel x.
HPxMUTE Headphone Mute
0 Disabled
1 Enabled
6.14.2 Speaker Mute

Configures a digital mute on speaker channel x.
SPKxMUTE Speaker Mute
0 Disabled
1 Enabled
6.14.3 Speaker Volume Setting B=A

Configures independent or ganged volume control of the speaker output.
SPKB=A Single Volume Control Affected Volume Controls
0 Disabled SPKxMUTE (“Speaker Mute” on page 54),
1 Enabled SPKxVOL[7:0] (“Speaker Volume Control” on page 64)
6.14.4 Speaker Channel Swap

Configures a channel swap on the speaker channels.
SPKSWAP Speaker Output
0 Channel A
1 Channel B
Application: “Mono Speaker Output Configuration” on page 32
6.14.5 Speaker MONO Control

Configures a parallel full-bridge output for the speaker channels.
SPKMONO Parallel Full Bridge Output
0 Disabled
1 Enabled
Application: “Mono Speaker Output Configuration” on page 32
6.14.6 Speaker Mute 50/50 Control

Configures how the speaker channels mute.
MUTE50/50 Speaker Mute 50/50
0 Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.
Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is
1
enabled.
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6.15 MICx Amp Control:MIC A (Address 10h) and MIC B (Address 11h)
7 6 5 4 3 2 1 0
Reserved MICxSEL MICxCFG MICxGAIN4 MICxGAIN3 MICxGAIN2 MICxGAIN1 MICxGAIN0
6.15.1 MIC x Select

Selects one of two single-ended MIC inputs on channel x.
MICxSEL MIC x Selection
0 MIC 1x
1 MIC 2x
Application: “MIC Inputs” on page 26
6.15.2 MICx Configuration

Configures the input topology for MICx.
MICxCFG MIC Input Topology
0 Single-Ended
1 Differential
6.15.3 MICx Gain

Sets the gain of the microphone pre-amplifier.
MICxGAIN[4:0] Gain
1 1111 32 dB
... ...
1 0000 32 dB
0 1111 30.5 dB
0 1110 30 dB
... ...
0 0000 16 dB
Step Size: 1 dB (unless otherwise noted)
6.16 PGAx Vol. and ALCx Transition Ctl.:

ALC, PGA A (Address 12h) and ALC, PGA B (Address 13h)
7 6 5 4 3 2 1 0
ALCxSRDIS ALCxZCDIS PGAxVOL5 PGAxVOL4 PGAxVOL3 PGAxVOL2 PGAxVOL1 PGAxVOL0
6.16.1 ALCx Soft Ramp Disable

Configures an override of the analog soft ramp setting.
ALCxSRDIS ALC Soft Ramp Disable
0 OFF; ALC Attack Rate is dictated by the ANLGSFT (“Ch. x Analog Soft Ramp” on page 49) setting
1 ON; ALC volume changes take effect in one step, regardless of the ANLGSFT setting.
Application: “Automatic Level Control (ALC)” on page 26
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6.16.2 ALCx Zero Cross Disable
Configures an override of the analog zero cross setting.
ALCxZCDIS ALC Zero Cross Disable
0 OFF; ALC Attack Rate is dictated by the ANLGZC (“Ch. x Analog Zero Cross” on page 49) setting
1 ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting.
6.16.3 PGAx Volume

Sets the volume/gain of the Programmable Gain Amplifier (PGA).
PGAxVOL[5:0] Volume
01 1111 12 dB
... ...
01 1000 12 dB
... ...
00 0001 +0.5 dB
00 0000 0 dB
11 1111 -0.5 dB
... ...
10 1000 -6.0 dB
... ...
10 0000 -6.0 dB
Step Size: 0.5 dB
Note: The PGAxVOL bits are ignored when the PASSTHRUx bit (“Passthrough Analog” on page 52) is
enabled.
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6.17 Passthrough x Volume: PASSAVOL (Address 14h) and PASSBVOL (Address 15h)
7 6 5 4 3 2 1 0
PASSxVOL7 PASSxVOL6 PASSxVOL5 PASSxVOL4 PASSxVOL3 PASSxVOL2 PASSxVOL1 PASSxVOL0
6.17.1 Passthrough x Volume

Sets the volume/gain of the signal routed from the PGA to the headphone/line output.
PASSxVOL[7:0] Gain
0111 1111 12 dB
... ...
0001 1000 12 dB
... ...
0000 0001 +0.5 dB
0000 0000 0 dB
11111 1111 -0.5 dB
... ...
1000 1000 -60.0 dB
... ...
1000 0000 -60.0 dB
Step Size: 0.5 dB (approximate)
Application: “Analog In to Analog Out Passthrough” on page 31
Notes:
1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 52) is disabled.
2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD,
and 0xB9 are not guaranteed to be monotonic.
6.18 ADCx Volume Control: ADCAVOL (Address 16h) and ADCBVOL (Address 17h)
7 6 5 4 3 2 1 0
ADCAVOL7 ADCAVOL6 ADCAVOL5 ADCAVOL4 ADCAVOL3 ADCAVOL2 ADCAVOL1 ADCAVOL0
6.18.1 ADCx Volume

Sets the volume of the ADC signal out the serial data output (SDOUT).
ADCxVOL[7:0] Volume
0111 1111 24 dB
... ...
0001 1000 24 dB
... ...
0000 0000 0 dB
1111 1111 -1.0 dB
1111 1110 -2.0 dB
... ...
1010 0000 -96.0 dB
... ...
1000 0000 -96.0 dB
Step Size: 1.0 dB
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6.19 ADCx Mixer Volume: ADCA (Address 18h) and ADCB (Address 19h)
7 6 5 4 3 2 1 0
AMIXxMUTE AMIXxVOL6 AMIXxVOL5 AMIXxVOL4 AMIXxVOL3 AMIXxVOL2 AMIXxVOL1 AMIXxVOL0
6.19.1 ADC Mixer Channel x Mute

Configures a digital mute on the ADC mix in the DSP.
AMIXxMUTE ADC Mixer Mute
0 Disabled
1 Enabled
6.19.2 ADC Mixer Channel x Volume

Sets the volume/gain of the ADC mix in the DSP.
AMIXxVOL[6:0] Volume
001 1000 +12.0 dB
... ...
000 0001 +0.5 dB
000 0000 0 dB
111 1111 -0.5 dB
... ...
001 1001 -51.5 dB
Step Size: 0.5 dB
6.20 PCMx Mixer Volume: PCMA (Address 1Ah) and PCMB (Address 1Bh)
7 6 5 4 3 2 1 0
PMIXxMUTE PMIXxVOL6 PMIXxVOL5 PMIXxVOL4 PMIXxVOL3 PMIXxVOL2 PMIXxVOL1 PMIXxVOL0
6.20.1 PCM Mixer Channel x Mute

Configures a digital mute on the PCM mix from the serial data input (SDIN) to the DSP.
PMIXxMUTE PCM Mixer Mute
0 Disabled
1 Enabled
6.20.2 PCM Mixer Channel x Volume

Sets the volume/gain of the PCM mix from the serial data input (SDIN) to the DSP.
PMIXxVOL[6:0] Volume
001 1000 +12.0 dB
... ...
000 0001 +0.5 dB
000 0000 0 dB
111 1111 -0.5 dB
... ...
001 1001 -51.5 dB
Step Size: 0.5 dB
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6.21 Beep Frequency and On Time (Address 1Ch)
7 6 5 4 3 2 1 0
FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
6.21.1 Beep Frequency

Sets the frequency of the beep signal.
FREQ[3:0] Frequency (Fs = 12, 24, 48 or 96 kHz) Pitch
0000 260.87 Hz C4
0001 521.74 Hz C5
0010 585.37 Hz D5
0011 666.67 Hz E5
0100 705.88 Hz F5
0101 774.19 Hz G5
0110 888.89 Hz A5
0111 1000.00 Hz B5
1000 1043.48 Hz C6
1001 1200.00 Hz D6
1010 1333.33 Hz E6
1011 1411.76 Hz F6
1100 1600.00 Hz G6
1101 1714.29 Hz A6
1110 2000.00 Hz B6
1111 2181.82 Hz C7
Application: “Beep Generator” on page 29
Notes:
1. This setting must not change when BEEP is enabled.
2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each
speed mode.
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6.21.2 Beep On Time
Sets the on duration of the beep signal.
ONTIME[3:0] On Time (Fs = 12, 24, 48 or 96 kHz)
0000 ~86 ms
0001 ~430 ms
0010 ~780 ms
0011 ~1.20 s
0100 ~1.50 s
0101 ~1.80 s
0110 ~2.20 s
0111 ~2.50 s
1000 ~2.80 s
1001 ~3.20 s
1010 ~3.50 s
1011 ~3.80 s
1100 ~4.20 s
1101 ~4.50 s
1110 ~4.80 s
1111 ~5.20 s
Notes:
2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
6.22 Beep Volume and Off Time (Address 1Dh)

7 6 5 4 3 2 1 0
OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
6.22.1 Beep Off Time

Sets the off duration of the beep signal.
OFFTIME[2:0] Off Time (Fs = 48 or 96 kHz)
000 ~1.23 s
001 ~2.58 s
010 ~3.90 s
011 ~5.20 s
100 ~6.60 s
101 ~8.05 s
110 ~9.35 s
111 ~10.80 s
Notes:
2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed
mode.
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6.22.2 Beep Volume
Sets the volume of the beep signal.
BEEPVOL[4:0] Gain
00110 +6.0 dB
··· ···
00000 -6 dB
11111 -8 dB
11110 -10 dB
··· ···
00111 -56 dB
Step Size: 2 dB
Note: This setting must not change when BEEP is enabled.
6.23 Beep and Tone Configuration (Address 1Eh)

7 6 5 4 3 2 1 0
BEEP1 BEEP0 BEEPMIXDIS TREBCF1 TREBCF0 BASSCF1 BASSCF0 TCEN
6.23.1 Beep Configuration

Configures a beep mixed with the HP/Line and SPK output.
BEEP[1:0] Beep Occurrence
00 Off
01 Single
10 Multiple
11 Continuous
Notes:
1. When used in analog pass-through mode, the output alternates between the signal from the PGA and
the beep signal. The beep signal does not mix with the analog signal from the PGA.
2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON
for the maximum ONTIME duration.
6.23.2 Beep Mix Disable

Configures how the beep mixes with the serial data input.
BEEPMIXDIS Beep Output to HP/Line and Speaker
0 Mix Enabled; The beep signal mixes with the digital signal from the serial data input.
Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The
1
beep signal does not mix with the digital signal from the serial data input.
Note: This setting must not change when BEEP is enabled.
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6.23.3 Treble Corner Frequency
Sets the corner frequency (-3 dB point) for the treble shelving filter.
TREBCF[1:0] Treble Corner Frequency Setting
00 5 kHz
01 7 kHz
10 10 kHz
11 15 kHz
6.23.4 Bass Corner Frequency

Sets the corner frequency (-3 dB point) for the bass shelving filter.
BASSCF[1:0] Bass Corner Frequency Setting
00 50 Hz
01 100 Hz
10 200 Hz
11 250 Hz
6.23.5 Tone Control Enable

Configures the treble and bass activation.
TCEN Bass and Treble Control
0 Disabled
1 Enabled
6.24 Tone Control (Address 1Fh)

7 6 5 4 3 2 1 0
TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
6.24.1 Treble Gain

Sets the gain of the treble shelving filter.
TREB[3:0] Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
Step Size: 1.5 dB
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6.24.2 Bass Gain
Sets the gain of the bass shelving filter.
TREB[3:0] Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
Step Size: 1.5 dB
6.25 Master Volume Control: MSTA (Address 20h) and MSTB (Address 21h)
7 6 5 4 3 2 1 0
MSTxVOL7 MSTxVOL6 MSTxVOL5 MSTxVOL4 MSTxVOL3 MSTxVOL2 MSTxVOL1 MSTxVOL0
6.25.1 Master Volume Control

Sets the volume of the signal out the DSP.
MSTxVOL[7:0] Master Volume
0001 1000 +12.0 dB
··· ···
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -102 dB
··· ···
0001 1001 -102 dB
Step Size: 0.5 dB
6.26 Headphone Volume Control: HPA (Address 22h) and HPB (Address 23h)
7 6 5 4 3 2 1 0
HPxVOL7 HPxVOL6 HPxVOL5 HPxVOL4 HPxVOL3 HPxVOL2 HPxVOL1 HPxVOL0
6.26.1 Headphone Volume Control

Sets the volume of the signal out the DAC.
HPxVOL[7:0] Headphone Volume
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -96.0 dB
··· ···
0000 0001 Muted
Step Size: 0.5 dB
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6.27 Speaker Volume Control: SPKA (Address 24h) and SPKB (Address 25h)
7 6 5 4 3 2 1 0
SPKxVOL7 SPKxVOL6 SPKxVOL5 SPKxVOL4 SPKxVOL3 SPKxVOL2 SPKxVOL1 SPKxVOL0
6.27.1 Speaker Volume Control

Sets the volume of the signal out the PWM modulator.
SPKxVOL[7:0] Speaker Volume
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0100 0000 -96.0 dB
··· ···
0000 0001 Muted
Step Size: 0.5 dB
Note: The maximum step size error is ±0.15 dB.
6.28 ADC and PCM Channel Mixer (Address 26h)

7 6 5 4 3 2 1 0
PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 ADCASWP1 ADCASWP0 ADCBSWP1 ADCBSWP0
6.28.1 PCM Mix Channel Swap

Configures a mix/swap of the PCM Mix to the headphone/line or speaker outputs.
PCMxSWP[1:0] PCM Mix to HP/LINEOUTA PCM Mix to HP/LINEOUTB
00 Left Right
01
(Left + Right)/2 (Left + Right)/2
10
11 Right Left
6.28.2 ADC Mix Channel Swap

Configures a mix/swap of the ADC Mix to the headphone/line or speaker outputs.
ADCxSWP[1:0] ADC Mix to HP/LINEOUTA Channel ADC Mix to HP/LINEOUTB Channel
00 Left Right
01
(Left + Right)/2 (Left + Right)/2
10
11 Right Left
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6.29 Limiter Control 1, Min/Max Thresholds (Address 27h)
7 6 5 4 3 2 1 0
LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS
6.29.1 Limiter Maximum Threshold

Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack
rate (LIMARATE - “Limiter Release Rate” on page 66).
LMAX[2:0] Threshold Setting
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
Application: “Limiter” on page 30
Note: Bass, Treble, and digital gain settings that boost the signal beyond the maximum threshold may
trigger an attack.
6.29.2 Limiter Cushion Threshold

Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE -
“Limiter Release Rate” on page 66) until levels lie between the LMAX and CUSH thresholds.
CUSH[2:0] Threshold Setting
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
Note: This setting is usually set slightly below the LMAX threshold.
6.29.3 Limiter Soft Ramp Disable

Configures an override of the digital soft ramp setting.
LIMSRDIS Limiter Soft Ramp Disable
0 OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 53) setting
1 ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
Note: This bit is ignored when the DIGZC (“Digital Zero Cross” on page 53) is enabled.
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6.29.4 Limiter Zero Cross Disable
Configures an override of the digital zero-cross setting.
LIMZCDIS Limiter Zero Cross Disable
0 OFF; Limiter Attack Rate is dictated by the DIGZC (“Digital Zero Cross” on page 53) setting
1 ON; Limiter volume changes take effect in one step, regardless of the DIGZC setting.
6.30 Limiter Control 2, Release Rate (Address 28h)

7 6 5 4 3 2 1 0
LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0
6.30.1 Peak Detect and Limiter

Configures the peak-detect and limiter circuitry.
LIMIT Limiter Status
0 Disabled
1 Enabled
6.30.2 Peak Signal Limit All Channels

Sets how channels are attenuated when the limiter is enabled.
LIMIT_ALL Limiter action:
Apply the necessary attenuation on a specific channel only when the signal amplitude on that specific chan-
nel rises above LMAX.
0
Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below
CUSH.
Apply the necessary attenuation on BOTH channels when the signal amplitude on any ONE channel rises
1 above LMAX.
Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH.
6.30.3 Limiter Release Rate

Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] thresh-
old (“Limiter Cushion Threshold” on page 65) and returns the analog output level to the MSTxVOL[7:0]
(“Master Volume Control” on page 63) setting.
LIMRRATE[5:0] Release Time
00 0000 Fastest Release
··· ···
11 1111 Slowest Release
Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs,
and the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) setting.
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6.31 Limiter Attack Rate (Address 29h)
7 6 5 4 3 2 1 0
Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0
6.31.1 Limiter Attack Rate

Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page 65).
LIMARATE[5:0] Attack Time
00 0000 Fastest Attack
··· ···
11 1111 Slowest Attack
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 65 or “Limiter Zero Cross Disable” on
page 66) is enabled.
6.32 ALC Enable and Attack Rate (Address 2Ah)

7 6 5 4 3 2 1 0
ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0
6.32.1 ALCx Enable

Configures the automatic level controller.
ALC ALC Status
0 Disabled
1 Enabled
Notes:
1. When the ALC is enabled, the digital volume and PGA volume is automatically controlled and should
not be adjusted manually.
2. The ALC should only be configured while the power down bit is enabled.
3. The ALC is not available in passthrough mode.
6.32.2 ALC Attack Rate

Sets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0]
threshold (“ALC Maximum Threshold” on page 68).
LIMARATE[5:0] Attack Time
00 0000 Fastest Attack
··· ···
11 1111 Slowest Attack
Note: The ALC attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the ANLGSFTx (“Ch. x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on
page 49) setting unless the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero
Cross Disable” on page 56) is enabled.
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6.33 ALC Release Rate (Address 2Bh)
7 6 5 4 3 2 1 0
Reserved Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0
6.33.1 ALC Release Rate

Sets the rate at which the ALC releases the analog and/or digital attenuation from levels below the
MIN[2:0] threshold (“ALC Minimum Threshold” on page 69) and returns the signal level to the PGAx-
VOL[5:0] (“PGAx Volume” on page 56) and ADCxVOL[7:0] (“ADCx Volume” on page 57) setting.
ALCRRATE[5:0] Release Time
00 0000 Fastest Release
··· ···
11 1111 Slowest Release
Notes:
1. The ALC release rate is user-selectable but is also a function of the sampling frequency, Fs, and the
ANLGSFTx (“Ch. x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on
page 49) setting.
2. The Release Rate setting must always be slower than the Attack Rate.
6.34 ALC Threshold (Address 2Ch)

7 6 5 4 3 2 1 0
ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALCMIN0 Reserved Reserved
6.34.1 ALC Maximum Threshold

Sets the maximum level, below full scale, at which to limit and attenuate the input signal at the attack rate
(ALCARATE - “ALC Attack Rate” on page 67).
MAX[2:0] Threshold Setting
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
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6.34.2 ALC Minimum Threshold
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the re-
lease rate (ALCRRATE - “ALC Release Rate” on page 68) until levels lie between the ALCMAX and AL-
CMIN thresholds.
ALCMIN[2:0] Threshold Setting
000 0 dB
001 -3 dB
010 -6 dB
011 -9 dB
100 -12 dB
101 -18 dB
110 -24 dB
111 -30 dB
Notes:
1. This setting is usually set slightly below the ALCMAX threshold.
6.35 Noise Gate Control (Address 2Dh)

7 6 5 4 3 2 1 0
NGALL NG NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0
6.35.1 Noise Gate All Channels

Sets which channels are attenuated when clipping on any single channel occurs.
NGALL Noise Gate triggered by:
Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for
0
both channels.
Both channels A and B; Both channels must fall below the threshold setting for the noise gate attenuation to
1
take effect.
Application: “Noise Gate” on page 27
6.35.2 Noise Gate Enable

Configures the noise gate.
NG Noise Gate Status
0 Disabled
1 Enabled
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6.35.3 Noise Gate Threshold and Boost
THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenu-
ated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.
THRESH[2:0] Minimum Setting (NG_BOOST = 0) Minimum Setting (NG_BOOST = 1)
000 -64 dB -34 dB
001 -67 dB -37 dB
010 -70 dB -40 dB
011 -73 dB -43 dB
100 -76 dB -46 dB
101 -82 dB -52 dB
110 Reserved -58 dB
111 Reserved -64 dB
6.35.4 Noise Gate Delay Timing

Sets the delay time before the noise gate attacks.
NGDELAY[1:0] Delay Setting
00 50 ms
01 100 ms
10 150 ms
11 200 ms
Note: The Noise Gate attack rate is a function of the sampling frequency, Fs, and the ANLGSFTx (“Ch.
x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on page 49) setting unless
the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero Cross Disable” on
page 56) is enabled.
6.36 Status (Address 2Eh) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7 6 5 4 3 2 1 0
Reserved SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL ADCAOVFL ADCBOVFL
6.36.1 Serial Port Clock Error (Read Only)

Indicates the status of the MCLK to LRCK ratio.
SPCLKERR Serial Port Clock Status:
0 MCLK/LRCK ratio is valid.
1 MCLK/LRCK ratio is not valid.
Note: On initial power up and application of clocks, this bit will report 1 as the serial port re-synchroniz-
es.
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6.36.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
DSPxOVFL DSP Overflow Status:
0 No digital clipping has occurred in the data path after the DSP.
1 Digital clipping has occurred in the data path after the DSP.
Application: “Analog Outputs” on page 28
6.36.3 PCMx Overflow (Read Only)

Indicates the over-range status in the PCM mix data path.
PCMxOVFL PCM Overflow Status:
No digital clipping has occurred in the data path of the PCM mix (“PCM Mixer Channel x Volume” on page 58)
0
of the DSP.
1 Digital clipping has occurred in the data path of the PCM mix of the DSP.
Application: “Analog Outputs” on page 28
6.36.4 ADCx Overflow (Read Only)

Indicates the over-range status in the ADC signal path.
ADCxOVFL ADC Overflow Status:
0 No clipping has occurred anywhere in the ADC signal path.
1 Clipping has occurred in the ADC signal path.
6.37 Battery Compensation (Address 2Fh)

7 6 5 4 3 2 1 0
BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0
6.37.1 Battery Compensation

Configures automatic adjustment of the speaker volume when VP deviates from VPREF[3:0].
BATTCMP Automatic Battery Compensation
0 Disabled
1 Enabled
Application: “Maintaining a Desired Output Level” on page 33
6.37.2 VP Monitor
Configures the internal ADC that monitors the VP voltage level.
VPMONITOR VP ADC Status
0 Disabled
1 Enabled
Notes:
1. The internal ADC that monitors the VP supply is enabled automatically when BATTCMP is enabled,
regardless of the VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be
enabled by enabling VPMONITOR; this provides a convenient battery monitor without enabling
battery compensation.
2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting.
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6.37.3 VP Reference
Sets the desired VP reference used for battery compensation.
VPREF[3:0] Desired VP used to calculate the required attenuation on the speaker output:
(for VA = 1.8 V)
0000 1.5 V
0001 2.0 V
0010 2.5 V
0011 3.0 V
0100 3.5 V
0101 4.0 V
0110 4.5 V
0111 5.0 V
(for VA = 2.5 V)
1000 1.5 V
1001 2.0 V
1010 2.5 V
1011 3.0 V
1100 3.5 V
1101 4.0 V
1110 4.5 V
1111 5.0 V
Application: “VP Battery Compensation” on page 33
6.38 VP Battery Level (Address 30h) (Read Only)

7 6 5 4 3 2 1 0
VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0
6.38.1 VP Voltage Level (Read Only)

Indicates the unsigned VP voltage level.
VPLVL[7:0] VP Voltage
...
0101 1110 3.0 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
0111 0010 3.7 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.
...
Formula: VP Voltage = (Binary representation of VPLVL[7:0]) * VA / 63.3
6.39 Speaker Status (Address 31h) (Read Only)

7 6 5 4 3 2 1 0
Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved
6.39.1 Speaker Current Load Status (Read Only)

Indicates whether or not any of the speaker outputs is shorted to ground.
SPKxSHRT Speaker Output Load
0 No overload detected
1 Overload detected
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6.39.2 SPKR/HP Pin Status (Read Only)
Indicates the status of the SPKR/HP pin.
SPKR/HP Pin State
0 Pulled Low
1 Pulled High
6.40 Charge Pump Frequency (Address 34h)

7 6 5 4 3 2 1 0
CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved
6.40.1 Charge Pump Frequency

Sets the charge pump frequency on FLYN and FLYP.
CHGFREQ[3:0] N
0000 0
...
0101 5
...
1111 15
Formula: Frequency = (64xFs)/(N+2)
Note: The headphone output THD+N performance may be affected.
DS680F2 73
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7. ANALOG PERFORMANCE PLOTS
7.1 Headphone THD+N versus Output Power Plots

Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement band-
width is 10 Hz to 20 kHz; Fs = 48 kHz.
-10
G = 0.6047
-15
VHP = VA = 1.8 V
-20 G = 0.7099
-25 G = 0.8399
-30
G = 1.0000
-35
-40
G = 1.1430
-45 Legend
-50
d
B NOTE: Graph shows the out-
r -55
A
put power per channel (i.e.
-60
Output Power = 23 mW into
-65
single 16  and 46 mW into
-70 stereo 16  with THD+N = -
-75 75 dB).
-80
-85
-90
-95
-100
0 10m 20m 30m 40m 50m 60m 70m 80m
W
Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16  load)
-10
G = 0.6047
-15
VHP = VA = 2.5 V
-20
G = 0.7099
-25 G = 0.8399
-30
G = 1.0000
-35
-40
G = 1.1430
-45 Legend
d
B
-50
NOTE: Graph shows the out-
r -55
A
-60 Output Power = 44 mW into
-65 single 16  and 88 mW into
-75
75 dB).
-80
-85
-90
-95
-100
0 10m 20m 30m 40m 50m 60m 70m 80m
W
74 DS680F2
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CS42L52
G = 0.6047
VHP = VA = 1.8 V
-20 G = 0.7099
-30
G = 0.8399
-35
G = 1.0000
-40
G = 1.1430
-45
-50
Legend
d
-55 NOTE: Graph shows the out-
B
r -60 put power per channel (i.e.
A
-65
-70
stereo 32  with THD+N = -
-75 75 dB).
-80
-85
-90
-95
-100
0 6m 12m 18m 24m 30m 36m 42m 48m 54m 60m
W
-20
G = 0.6047
VHP = VA = 2.5 V
-25
G = 0.7099
-30
G = 0.8399
-35
G = 1.0000
-40
-45
G = 1.1430
-50
Legend
-55
d
B
r -60 NOTE: Graph shows the out-
A
-65
-70
-80 75 dB).
-85
-90
-95
-100
0 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m 60m
W
DS680F2 75
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8. EXAMPLE SYSTEM CLOCK FREQUENCIES *The”MCLKDIV2” bit must be enabled.
8.1 Auto Detect Enabled

Sample Rate MCLK (MHz)
LRCK (kHz) 1024x 1536x 2048x* 3072x*
8 8.1920 12.2880 16.3840 24.5760
11.025 11.2896 16.9344 22.5792 33.8688
12 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 512x 768x 1024x* 1536x*
16 8.1920 12.2880 16.3840 24.5760
22.05 11.2896 16.9344 22.5792 33.8688
24 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 256x 384x 512x* 768x*
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 128x 192x 256x* 384x*
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
8.2 Auto Detect Disabled

LRCK (kHz) 512x 768x 1024x 1536x 2048x 3072x
8 - 6.1440 8.1920 12.2880 16.3840 24.5760
11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688
12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 256x 384x 512x 768x 1024x 1536x
16 - 6.1440 8.1920 12.2880 16.3840 24.5760
22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688
24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 256x 384x 512x 768x
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640

LRCK (kHz) 128x 192x 256x 384x
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
76 DS680F2
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CS42L52
9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply and Grounding

As with any high-resolution converter, the CS42L52 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 1 on page 11 shows the recommend-
ed power arrangements, with VA and VHP connected to clean supplies VD, which powers the digital
circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply
via a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L52 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS42L52 to minimize inductance effects.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be po-
sitioned to minimize the electrical path from FILT+ and AGND. The CDB42L52 evaluation board demon-
strates the optimum layout and power supply arrangements.
9.2 QFN Thermal Pad

The CS42L52 is available in a compact QFN package. The underside of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS42L52 evaluation board demonstrates the optimum thermal pad and via configuration.
DS680F2 77
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CS42L52
10.ADC AND DAC DIGITAL FILTERS
Figure 26. ADC Passband Ripple Figure 27. ADC Stopband Rejection
Figure 28. ADC Transition Band Figure 29. ADC Transition Band (Detail)
Figure 30. DAC Passband Ripple Figure 31. DAC Stopband
Figure 32. DAC Transition Band Figure 33. DAC Transition Band (Detail)
78 DS680F2
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CS42L52
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert-
er's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS680F2 79
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CS42L52
12.PACKAGE DIMENSIONS
40L QFN (6 X 6 mm BODY) PACKAGE DRAWING

D
2.00 REF
b e
PIN #1 CORNER
PIN #1
IDENTIFIER
2.00 REF
0.500.10
LASER
MARKING
E2
E
A1 L
D2
A
INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.0394 -- -- 1.00 1
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.2362 BSC 6.00 BSC 1
D2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1
E 0.2362 BSC 6.00 BSC 1
E2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board JA - 44 - °C/Watt
4 Layer Board - 19 -
80 DS680F2
3/1/13
CS42L52
13.ORDERING INFORMATION
Product Description Package Pb-Free Grade Temp Range Container Order #

Low-Power, Stereo Rail CS42L52-CNZ
CS42L52 CODEC with Headphone 40L-QFN Yes Commercial -40 to +85° C
Tape and Reel CS42L52-CNZR
and Speaker Amps
CS42L52 Evaluation
CDB42L52 - No - - - CDB42L52
Board
CS42L52 Reference
CRD42L52 - No - - - CRD42L52
Design
14.REFERENCES
1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.
http://www.semiconductors.philips.com.
15.REVISION HISTORY
Revision Changes
F1 Initial draft
Removed the Automotive specification.
Added AD0 characteristics to “I/O Pin Characteristics” on page 10.
Added AD0 pin to Figure 1. Typical Connection Diagram on page 11.
Updated Note 6 on page 15.
Updated the VIH specification for VL = 1.8 V in “Digital Interface Specifications and Characteristics” on page 22.
Updated “PWM Outputs” on page 32 to exclude support of a 384x MCLK to LRCK ratio.
Added register commands for entering and exiting DSP 16-bit, 8 kHz Fs, SCLK = MCLK, master mode in section
“DSP Mode” on page 35.
Updated Section 4.9 “Recommended Power-up Sequence” on page 37.
Updated Section 4.10 “Recommended Power-Down Sequence” on page 37.
Added a description of the AD0 pin to “I²C Control” on page 38.
F2 Added AD0 detail to Figure 20. Control Port Timing, I²C Write on page 38 and Figure 21. Control Port Timing, I²C
Read on page 39.
Updated the first paragraph in “Register Quick Reference” on page 40 to allow for data sheet-specified control-
writes to reserved registers.
Removed I²C address heading row from “Register Quick Reference” on page 40.
Updated notes in “Auto-Detect” on page 44.
Updated table in “Speed Mode” on page 45.
Added note 1 in “Freeze Registers” on page 52.
Updated notes in “Digital Soft Ramp” on page 53.
Added note 4 to “Digital Zero Cross” on page 53.
Added notes 1 and 2 for ALC configuration in “ALC Enable and Attack Rate (Address 2Ah)” on page 67.
Corrected the E2 scale in the package drawing in “Package Dimensions” on page 80.
DS680F2 81
3/1/13
CS42L52
Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR-
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM-
ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT-
TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a trademark of Philips Semiconductor.
82 DS680F2

CS42L52 F2m

Uploaded by

CS42L52 F2m

Uploaded by

DRAFTv1

+1.65 V to +2.63 V +1.65 V to +2.63 V +1.60 V to +5.25 V

HPF Right HP/Line

MIC Bias Level Shifter Charge Pump +1.65 V to +2.63 V

Selectable +1.65 V to +2.63 V

Copyright  Cirrus Logic, Inc. 2013 MAR ’13

Pin Name # Pin Description

Power Pin Name I/O Internal Driver Receiver

* *Use low ESR ceramic capacitors. SPKR_OUTA+

Figure 1. Typical Connection Diagram

RECOMMENDED OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

Parameters (Note 5) Min Typ Max Unit

6. One (least-significant bit) LSB of triangular PDF dither is added to data.

ANALOG PASSTHROUGH CHARACTERISTICS

9. The PWM driver should be used in captive speaker systems only.

10. Optimal PWM performance is achieved when MCLK > 12 MHz.

HEADPHONE OUTPUT POWER CHARACTERISTICS

Parameters VA = 2.5V VA = 1.8V Unit

Figure 2. Headphone Output Test Load

COMBINED DAC INTERPOLATION AND ONCHIP ANALOG FILTER RESPONSE

Parameters Symbol Min Max Unit

Figure 4. Control Port Timing - I²C

DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS

23. VL current will slightly increase in master mode.

4.1.2 Line and MIC Inputs

4.1.3 Line and Headphone Outputs

4.1.4 Speaker Driver Outputs

4.1.5 Fixed Function DSP Engine

4.1.6 Beep Generator

4.1.7 Power Management

ADCAMUTE HPFRZA = PGAASEL[5:1]

Gain Adjust ADC

ANALOG PASS THRU TO

FROM DSP ENGINE

Figure 5. Analog Input Signal Flow

Referenced Control Register Location

Note: Output to PGA = (MIC + - MIC -)*gain + MIC -

Figure 6. Single-Ended MIC Configuration Figure 7. Differential MIC Configuration

4.2.2 Automatic Level Control (ALC)

Referenced Control Register Location

4.2.3 Noise Gate

Fixed Function DSP LIMARATE[7:0]

Digital Mix to ADC

Figure 10. DSP Engine Signal Flow

Referenced Control Register Location

Referenced Control Register Location

Referenced Control Register Location

4.3.1 Beep Generator

BEEP[1:0] = MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)

BEEP[1:0] = SINGLE-BEEP: Beep turns on at a

Figure 13. Beep Configuration Options

Referenced Control Register Location

Figure 14. Peak Detect and Limiter

4.4.1 Overriding the ADC Power Down

PDN_ADC PASSTHRU PDN_OVRD Speaker Channel ADC Status

Referenced Control Register Location

4.4.2 Overriding the PGA Power Down

PDN_PGA PASSTHRU HP Channel PGA Status

4.5 PWM Outputs

4.5.1 Mono Speaker Output Configuration

4.5.2.1 Maintaining a Desired Output Level

Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)

Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)

4.6 Serial Port Clocking

MCLK Sample Rate, SPEED[1:0] 32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2

4.7 Digital Interface Formats

SDIN MSB LS B M SB LS B MSB

Figure 16. I²S Format

SDIN MSB LS B M SB LS B MSB

Figure 17. Left-Justified Format

SDIN MSB LSB MSB LS B

Figure 18. Right-Justified Format (DAC only)

4.7.1 DSP Mode

SDIN L SB MSB L eft C h a n n el LS B M SB R ig ht C h a n n el LSB M SB

HP/LINE OUTA HP/LINE OUTB