8086/8088 MICRO PROCESSOR (GENERAL MICROPROCESSOR SYSTEM ARCHITECTURE ‘The Intel 8086 microprocessor was released in 1978, one year before the 8088 CPU. Both Processors have the same architecture and the only difference the 8086 CPU has from the 8088 CPU is the external data bus width which was reduced from 16 bits to 8 bits. The 8088 CPU uses two consecutive bus cycles to read or write 16 bit data instead of one cycle as itis with the 8086, thus making 8088 CPU to run slower than its predecessor. On the plus side, the hardware changes made to the 8088 C! made it compatible with the 8080/8085 support micro chips. This was an important factor in choosing the 8088 CPU for the IBM PC line of computers because at the time 8 bit support chips were cheaper than 16 bit support chips. Moreover, there was a better selection of 8 bit support chips. ‘The 8088 microprocessor has 16 bit registers, 16 bit internal data bus and a 20 bit address bus, which allows the processor to address up to IMB of memory (IMB = 2 = 1 048 576 bytes). The 8088 CPU uses the same segmented memory addressing as the 8086 CPU, ie, the processor can address 64KB of memory directly and to address more than 64 kBytes of memory, the CPU has to break the update into a few parts - Update up to 64KB of memory, change the Segment register, update another block of memory, update the Segment register again and so forth and so on, Like the 8086, the 8088 CPU also supports the Intel 8087 Numeric Co-Processor. It recognises all Floating Point (FP) Instructions and, when necessary, calculates the memory address for FP instruction Operands and does a dummy memory read. The CPU captures the calculated address and possibly the data and proceeds to execute the FP instruction. The CPU at the same time starts to execute the next instruction. Thus, both integer and FP instructions can be executed concurrently. The original Intel 8088 microprocessor was manufactured using HMOS (Hybrid Metal Oxide Semiconductor) technology. There were also CHMOS (Complementary HMOS) versions of the chip - The 80C88 and 80C88A. These microprocessors had a much lower power consumption and featured the Standby Mode. 1~O} xs JL ~ Fig, 4.1: Diagram showing a typical micoprocessor system architecture Fig. 4.1 shows the Microprocessor Unit (the MPU) - in this case the 8086/8088 - which implements the functions of the Central Processing Unit (CPU) on a single chip. The CPU includes an Arithmetic & Logic Unit (ALU), plus its inernal registers, and a Control Unit (CU), which decodes and internally sequences instructions.The MPU has three (3) buses: an Address Bus, a Data Bus and a Control Bus. A Bus is a 1 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)collection of interconecting lines that facilitate the movement of electronic signals that originate at @ common source and perform a common function, ‘The Address Bus is responsible for providing a pathway for the communication between the CPU and the ROM, RAM, or PIO (Parallel Input/Output). It facilitates the movement of address codes. ‘The Data Bus passes the actual information between the CPU and enables the system block. (see fig. 4,1). It facilitates the movement of data and instructions. ‘The Control Bus performs the dual tasks of electrically defining the type of communication as well as beginning (initiating) and ending (terminating) the transfer. It facilitates the movement of Contol Signals. In most applications, the CPU controls each bus. It is the function of the CPU to correctly time each bus so that reliable can occur. ‘The width of the bus determines the number of signal lines contained in the group comprising the bus. For the 8086/8088 the Address Bus can be up to 20 bits wide. The width of the Data Bus is 16 bits and the width of the Control Bus varies. The width of each bus differs from CPU to CPU, and from system to system. INSIDE A MICROPROCESSOR EXTERNAL DATA ‘BUS DATA BUS (8 BITS) SP PC Keo annsanann anoupraRaoom ADDRESS BUS (16 BITS) Fig. 4.2: The general Internal Architecture of a standard microprocessor ‘The Control box represents the Control Unit (CU) that synchronises the hardware and timing, The [Arithmetic & Logic Unit (ALU) performs all arithmetic and logic operations. Special registers called ‘Accumulators are usually connected the output of the ALU. They contain the results of arithmetic operations. In addition to the arithmetic and logic operations, the ALU also provides Shift and Rotate facilities. A “Shift” moves the contents of the accumulator to the left or to the right by one or more positions. 2 8086/8088“The Status or Condition Register appears to the left of the ALU. The job of this register is t0 store the “internal conditions of the microprocessor in codes. The Condition Codes are sometimes referred to as Condition Flags.An example of this is a bit that indicates when the result of an operation: performed by the ALU leaves all the accumulator bits equal to zero (0). ‘The contents of the code register can be tested by specialized instructions. The CPU alters its execution path based on the logical values of the codes, Moving on to the left in Fig, 4.2, one finds the address registers. These are used for the storage of addresses, They are connected to the system address bus. Whenever the CPU executes a program, the address registers are combincd logically to form a complete address. Some of the power of a microprocessor comes from its ability to combine the address registers in special ways to form the system address present on the address bus. ‘THE PROGRAM COUNTER (PC) Must be present in all microprocessors as it is fundamental to program execution. It is the register that contains the address of the next instruction to be fectched for decoding and subsequent execution. A program normally executes in a sequential fashion. To access the next instruction, it is necessary to fetch it from the system memory and read the instruction into the microprocessor. The contents of the PC are deposited onto the address bus and inputted to the memory address line. The memory then reads the contents of the specified address and sends the corresponding instruction to the CPU. ‘THE STACK POINTER (SP) It implements the system stack, The Stack Pointer contains the memory address of the top of the stack. ‘The stack is often used for handling the interrupts and subroutines. And for saving temporary data. ‘THE INDEX REGISTER (IR) Indexing is a memory addressing facility used to access blocks of data in memory, using only a single instruction. This facility is available in some microprocessors by not all. It is however available with the 8086/8088. An Index Register typically contains a “Displacement”, which is automatically added to a Base value when forming an address. In short, Indexing is use to access a word within a block of data. ‘THE STACK ‘A Stack, formally called a LIFO (Last-In, First-Out) structure , is a set of memory locations allocated to the stack data structure. The essential characteristic of the stack is that the first element introduced in the stack is always at the bottom, and the most recently deposited clement is always on top. In normal use, the stack in only accessible via two operations: PUSH and POP. The PUSH operation deposits elements on the top of the stack while the POP operation transfers the top elements of the ‘stack into the internal register specified by the instruction. ‘THE GENERAL INSTRUCTION CYCLE ‘The Instruction Cycle is a series or sequence of steps/actions that an instruction undergoes in the program execution process. ‘An instruction cycle has three main stages and these are: 1. The Fetch Stage 2. The Decoding Stage 3. The Execution Stage 3 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)‘The Fetch Stage: In this stage, the contents of the Program Counter are placed on the system address bus and inputted to the memory decoder at the correct time. The Control bus then generates a memory read signal. When the memory receives the read signal, the data stored in memory at the specified location or address is placed on the data bus. The microprocessor then reads the information on the data bus into an internal register called the Memory Buffer Register. The information read into the CPU is the Instruction. This action completes the fetch stage. After this, the Program Counter is incremented (this is done when the instruction is copied into the MBR). After incrementing the PC, the instruction is moved to the Current Instruction Register (CIR or simply IR). The Decoding Stage: Once the instruction is in the IR, the CU proceeds to decodes the instruction. Decoding involves finding out what action the instruction needs to be done. This implies examining the Op-code field of the machine instruction so as to determine/establish the action/s to be performed and generating the correct sequence of internal and external registers. Execution: Once the instruction is decoded and the correct sequence of internal and external registers generated, the CU proceeds to execute the instruction. This involves performing a series of events dictated by the instruction. Some instructions require simple tasks and thus take a little time to execute whilst others require several events to occur and thus take longer. The speed of execution of an instruction is usually expressed in the toatal number of clock cycles required for completion. INTERNAL ORGANISATION OF REGISTERS Most of the registers for the 8086/8088 contain data/instruction offsets within 64KB segements. There are four different 64kB segments for instructions, stack, data and extra data. To specify where in the MB of processor memory these four registers are located, the 8086/8088 processor uses four Segment registers. 1, Code segment (CS): is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions, 2. Stack segment (SS): is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction, 3. Data segment (DS): is a 16-bit register containing address of 64KB segment with program data, By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, Dl) is located in the data segment. DS register can be changed directly using POP and LDS instructions. 4, Extra segment (ES): is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: 1, Accumulator register: consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. 2, Base register: consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing, 4 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)4 \ consists of two 8-bit registers CL and CH, which can be combined together and tused as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions. Data register: consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. ‘The following registers are both general and index registers: 1, Stack Pointer (SP): is a 16-bit register pointing to program stack. 2. Base Pointer (BP): is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI): is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions, 4, Destination Index (D1}: is « 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: 5. Instruction Pointer (IP): is a 16-1 next instruction to be fetched. t register that serves the function of the PC by pointing to the ae ax ar] Accumutator pata [BE Bx BL | BASE enor Now x et | counr Da Dx, DL] Data SP STACK POINTER POINTER ‘AND BP BASE POINTER INDEX rt st SOURCE INDEX DI DESTINATION INDEX, Internal registers of the 8086/8088 enema CODE SEGMENT ‘The four segment registe: 8086/8088 DS DATA SEGMENT 5 STACK SEGMENT ES EXTRA SEGMENT of the 8086/8088. They are logically combined with the general registers to form a 20 bit system addres Fig. 4.3 Mumba M. Michael BS.CMP.S (UNZA)1. Flag represents the condition of the result of an arithmetic or logic operation that has just occurred. A Flag is a 16-bit register containing nine 1-bit flags. They are classified in two categories: Control Flags Single-step/Trap Flag (TF) - if set then single-step interrupt will occur after the next instruction. Direction Flag (DF) - if sct then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag (IF) - sctting this bit enables maskable interrupts. Status Flags Overflow Flag (OF) - sct if the result is too large positive number, or is too small negative number to fit into destination operand (when overflow occurs). ‘Sign Flag (SF) - it is set if the most significant bit of the result is set. Zero Flag (ZF) - it is set if the result is zero, Auxiliary carry Flag (AF) - it is set if there was a carry from or borrow to bits 0-3 in the AL register. Parity Flag (PF) ~ it is set if parity (the number of "1" bits) in the low-order byte of the result is even, ‘This flag is used to check for transmission errors, Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation. 15 The Flags Register INSTRUCTION SET Instruction set of Intel 8086 processor consists of the following instructions: 1 Data moving instructions. Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. Logic - AND, OR, exclusive OR, shift/rotate and test. String manipulation - load, store, move, compare and scan for byte/word. Control transfer - conditional, unconditional, call subroutine and return from subroutine. Input/Output instructions. Other - setting/clearing flag bits, stack operations, software interrupts, ete. 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)on eee re eee a sMORY ORGANISATION AND ADDRESSING MODES (G MODES Addressing modes are the ways how architectures specify the address of an object they want to access. ‘An addressing mode can specify a constant, a register or a location in memory. These are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. ‘A machine instruction is made up of two parts; the Operand field and the Opeode field. Operand Field: this is the portion of the machine instruction that specifies the location in memory of a variable /instruction /data. ‘Opeode Field: this is the portion of the machine instruction the action /operation to be performed as dictated by the instruction. [—Zero Component ————Immediate -Register Direct -Absolute | One Component ‘Register Indirect Det Adrensing modes Aes atet [swe component —[ red ndeet re mre enti senor net pst ndened 68020 L_ Multi-Component ‘Word displacement indexed (VAX-11) Frame memory relative (NS32000) Fig. 4.5: Classification of addressing mode: 1. IMMEDIATE ADDRESSING MODE This is the addressing mode in which the the data is provided explicitly within the instruction stream. It isa special form of addressing in which no addres components are are used, As a result, it is an example of Zero-Component Addressing. The operand v: alue is specified directly within the operand field of the instruction stream (in other words, the instruction comes with the data value to be worked on.) DIRECT ADDRESSING MODE This is the addressing mode in which the operand specifies the memory address where the data (operand value) is located. It is an example of One Component addressing and it is also referred to as Absolute Addressing as it specifies the addresses as they are offered to the memory system (the actual address in memory of the operand value is called the Absolute address or Effective address). 7 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)= ee eee | one of the most frequently used operand addressing modes is Register-Direct Mode, in which the fegister number that uniquely identifies the register containing the operand value is specified, This nade is frequently usec! duc to its efficiency and speed. This addressing works well with the SI, DI, BX and BP registers. 3. INDIRECT ADDRESSING MODE Itis an addressing mode in which the operand, instead of containg the effective address, actually contains the address of the location having the effective address. If the effective address in question is a register number, then the addressing mode is classified as Register-Indirect addressing mode, This is particularly useful and necessary when the addresses of the data structures are not known ‘until runtime because the addresses can be computed with instructions and stored in a register after which the operand can be accessed via this register. 4, INDEXED ADDRESSING MODE ‘An addressing mode that use a (fixed) Base address which is specified in the instruction stream comparable to the absolute address. To form the operand address, a Variable Offset (Displacement) contained in a register called the Index, is added to the Base address. This mode is used when the Base address of a data structure, such as a vector, is known at compile time but the exact element position can only be determined at run time. Indexed addressing is an example of Two Component addressing. 5. BASE ADDRESSING MODE ‘An addressing mode in which the instruction contains a fixed Displacement and the (Variable) base addressis contained a register. The main difference between indexed and base addressing is that the base address in indexed addressing must always be a full length address whilst the Dsplacement in Base addressing may either be short or long, If the Offset and the Base addresse have the same length, then Base and Indexed addressing cannot be distinguished. Base addressing is used when the base address of the data block is not known until runtime, while the relative position of an item is already known at compile time. It is an example of Two Component addressing, 6. BASED-INDEXED ADDRESSING MODE It isan addressing mode in which both the Base address and the Offset (Displacement) are variable, and they are computed at run time. This allows for accessing arbitrary elements in a data structure with a begin address that is not known at compile time, Indexed => Base (fixed) + Offset/index (variable) = Effective Address. Base Ofiset/ index (fixed) + Base (variable) = Effective Address. Base-Index : => Base (variable) + Offset/index (variable) = Effective Address SYSTEM MEMORY ORGANISATION OF THE 8086 ‘The 8086 has 20 addres lincs in its address bus. This means that it has 2" = 1,048,576 (1MB) unique storage locations that can be addressed. Since the data bus for the 8086 is 16 bits wide, the system memory for the 8086 is 16 bits (or 2 bytes) wide, These two bytes are labeled Upper byte and Lower byte. 8 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)16 bit Data bus 20 bit Address bus Fig 6 Block diagram showing how the 16 bits of the 8086 memory are divided Into upper and lower bytes ‘The 8086 can access any of the possible 1,048,576 bytes of memory. Since each word of memory uses two bytes, this gives a system memory that is 2” addresses of 16 bits each. (Note: it is important to remember that the 8086 can acces ‘The instructions for the 8086 are made up of 1 to 6 bytes of data. This means that the 8086 instructions may start at either an even address (Lower byte) or odd address (Upper byte). Two signals determine which byte is being accessed: AO & BHE (Bus High Enable). When AO is a logical 0, the 8086 is accessing the lower byte of the valid memory address. When BHE a logical 0, the 8086 is accessing the upper byte of the valid memory address. BHE is Not simply AO in all cases, ‘The 8086 is capable of accessing 16 bits (2 bytes) of data in memory in a single memory cycle. When this occurs, both the BIII5 and AO are a logical 0 at the same time. Accessing 16 bits at an even address. Let's assume that the 8086 is reading a 16 bit word from address 0OOFO, an even address. This means that the 8086 requires both (he upper and lower bytes of data at that address. The CPU then outputs an address on the address bus with the BHE and AO set to a logical 0. Both bytes of data communicate with the CPU at the same time. Now let’s assume the 8080 is reading a byte from address OOOFO, since this address is even, the byte of data will be read from the Lower byte of the address word. In this case, A0 is a logical 0 and BHE is a logical 1 Accessing 8 bits at an odd address. Let’s assume that the 8086 is reading an 8 bit word from address OOF 1, which is an odd » which is address. This data will be read from the upper byte of the 16 bit word at the addressOOOFO, In this i . instan logical 1 and BHE is a logical 0. stance, AO Accessing 16 bits at an odd address. bytes of memory as well as words). 9 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)15 o ore —2— Word on an Bven address W1 = Aligned W2 = Non-Aligned Fig. 4.8: Words (16 bits) stored in the 8086 memory residing at either even or odd address ALIGNED AND NON-ALIGNED WORDS ‘There are different ways in which the 8086 accesses data in memory. When the CPU acceses a word, (ie. 16 bits) located on even actress, it is an Aligned word, The word is aligned due to the fact that both bytes of the word are on the same word address and can be read or written in single memory cycle. When a CPU accesses a word starting at an odd address, it is accessing a Non-aligned word. This is due to the fact that both bytes of the word do not reside at the same word address and thus two memory cycles are required to read the entire word. ‘The 8086 is designed to handle both Aligned and Non-Aligned words. The importance of alignment and non-alignment is determined by the execution speed of certain operations. For example, if a program accesses or manipulates many word quantities, then storing the data starting at an even address can help in the speed of system execution. SYSTEM MEMORY ORGANISATION OF THE 8088 ‘The 8088 has 20 address lines in its address bus. But unlike the 8086, it has an 8 bit data bus. The | 8088 is essentially an 8 bit system that uses a 16 bit microprocessor. All of the 16 bit software capabilities are available on the 8088. This is demonstrated by the fact that both the 8086 and 8088 execute the same software instructions. 10 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)/ 8 bit Data bus (0000 System . Memory : : vere 20 bit Address bus Fig.: 4.9 Block diagram showing 8088 system memory ADDRESS GENERATION WITH THE 8086/8088 'Al the internal registers on the 8086/8088 are 16 bits wide. However the physical address bus of the CPU fe 20 bite wide. This means that more than one of the internal registers of the CPU must be used to generate a 20 bit physical address. “The two registers used for the instruction address are the Instruction Pointer (IP) and the (Code Segment (CS) registers. These two registers are combned in a special way to generate a complete 20 bit ‘address, The equation that describes how the two registers are combined is as follows; 20 bit Address = (1610 x CS) + IP For example, given that the CS = 1000Hex and the IP = 0414Hex, then: 20 bit Address = (1610 x 100016) + 041415 20 bit Address = (1016 x 100016) + 041416 20 bit Address = 1000016 + 041416 20 bit Address = 1041416, Hence 20 bit Address = 10414H ‘This will be the address in memory from which the instruction will be fetched. The IP register is referred to as the Offset and the CS register x 16 points to the strings address or segment in memory from which the Offset is computed. It points to the starting address of the memory segment that contains the instruction code, hence the name Code Segment Register. un 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)CS x 16 20 Bit Physical Address Fig. 4.10: Generation of a 20 bit address with 8086/8088 INTERRUPTS FOR THE 8086/8088 [An interupt js a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing, the current thread. The processor responds by suspending its current activities, saving its state, and executing a small program called an interrupt handler (or interrupt service routine, ISR) to deal with the event. This interruption is temporary, and after the interrupt handicr finishes, the processor resumes execution of the previous thread. ‘The meaning of ‘interrupts’ is to break the sequence of operation, While the cpu is executing a program, an interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR , the control is transferred back again to the main program.interrupt processing is an alternative to polling. The act of interrupting the CU is known as an Interrupt Request (IRQ) ‘There are two types of interrupts Hardware Interrupt is an clectronic alerting signal sent to the processor from an external device, either fa part of the computer itself such as a disk controller or an external peripheral. For example, pressing a key on the keyboard or moving the mouse triggers hardware interrupts that cause the processor to read the keystroke or mouse position. Unlike the software type (below), hardware interrupts are asynchronous and can occur in the middle of instruction execution, requiring additional care in programming. The act of initiating a hardware interrupt is referred to as an interrupt request (IRQ). Software Interrupt is caused cither by an exceptional condition in the processor itself, or a special instruction in the instruction sct which causes an interrupt when it is executed. The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. For example, if the processor's arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a divide-by-zero exception, perhaps causing the computer to abandon the calculation or display lan error message. Software interrupt instructions function similarly to subroutine calls and are used for a variety of purposes, such as to request services from low level system software such as device drivers, For example, compuicrs often use software interrupt instructions to communicate with the disk controller to request data be read or written to the disk. 12 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)merrupt haa its own interrupt handler. The number of hardware interrupts is limited by the Ben or interrupt request (IRQ) lines tothe processor, but there may be hundreds of different fortware interrupts. Interrupts are a commonly’ uscd technique for computer multitasking, especially in real-time computing, Such a system is said to be interrupt-driven. Interrupts can be categorized into these different types: 1, Maskable interrupt (IRQ) mask register's (IMR) bit-tn 2, Non-maskable interrupt (NMI) can never be ignored, NMIs are u watchdog timers, 3, Inter-processor interrupt (IPI): a special case of interrupt that is generated by one processor to interrupt another processor in a multiprocessor system. hardware interrupt that may be ignored by setting a bit in an interrupt m a hardware interrupt that lacks an associated bit-mask, so that it for the highest priority tasks such as timers, especially 4. Software interrupt: «an interrupt generated within a processor by executing an instruction. Software interrupts arc olten used to implement system calls because they result in a subroutine call with a CPU ring level change. 5. Spurious interrupt: a hardware interrupt that is unwanted. They are typically generated by eystem conditions such as electrical interference on an interrupt line or through incorrectly designed hardware. ‘An interrupt that leaves the machine in a well-defined state is called A Precise Interrupt. Such an interrupt has four properties © The Program Counter (PC) is saved in a known place. * Allinstructions before the one pointed to by the PC have fully executed. «No instruction beyond the one pointed to by the PC has been executed (that is no prohibition on instruction beyond that in PC, it is just that any changes they make to registers or memory must be undone before the interrupt happens}. © The execution state of the instruction pointed to by the PC is known. ‘An interrupt that does not mect these requirements is called an Imprecise Interrupt. ‘The phenomenon where the overall system performance is severely hindered by excessive amounts of processing time spent handling interrupts is called an interrupt storm. (PU ACTIVITY DURING THE NMI REQUEST The term Non-Maskable Interrupt implies that this interrupt must always be recognised by the processor as soon as electricully possible and the source of the interrupt attended to immediately as it Cannot be ignored. During an NMI operation, the first event to occur i that all the flags are pushed onto th system stack area and this action sources the values of all the flags. After this, the CPU then clears the IF (Interrupt Flag) and this disab/les any other interrupts from occuring on the INTR Tine, When thie lag is cleared, al interrupt requests from all other INTR inpute are electrically ignored, ‘The next action taken by the CPU is to push the CS and the IP registers onto the system stack. 13 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)- ‘A subroutine is also described as a block or section of instructions named by the programmer. It is executed when the main program executes a special CALL Instruction. A subroutine is terminated by executing a special instruction called the RETURN Instruction. Subroutines are a powerful programming tool, and the syntax of many programming languages includes support for writing and using them. Judicious use of subroutines (for example, through the structured programming approach) will often substantially reduce the cost of developing and maintaining a large program, while increasing its quality and reliability. Subroutines, often collected into libraries, are an important mechanism for sharing and trading software. The discipline of object- oriented programming is basccl on objects and methods {which are subroutines attached to these objects or object classes). The essential value of a subroutine is that it can be “Called” from any number of points in the main Program and the instructions in a subroutine can be used repeatedly without having to be rewritten. In the compilation technique called threaded code, the executable program is basically a sequence of ‘subroutine calls. Maurice Wilkes, David Wheeler, and Stanley Gill are credited with the invention of this concept, which they referred to as Closed Subroutine. Tastraction W Interrupt 32 occurs during ‘execution of instruction N in the main program Program control is passed to the first instruction of he — Interrupt service routine ‘control from the end of the service routine to the instruction N+ 1 of the main program Interrupt service routine for interrupt Fig 4.11: Interrupt program context switching mechanism (subroutine) 15 8086/8083 Mumba M. Michael BS.CMP.S (UNZA)Memory Table pugctge Address Entry on [ sas Vector 25510 va I I User Available 1 ! 82 cs 32 ector 3210 ool fA) Arse id CS 31 Ne Vector S1:0 [a eee Z t I : I ved : 1 vector 5 14 < 12 > Vector 4- Overflow 10 2 5 OE Vector 3 - Breakpoint oc oA oe ‘Vector 2 - NMI o8 IP2 F 7 + 06 cS1 = ‘Vector 1 - Single Ste] ee [25 ara aes : o2 CS Value - Vector 0 (CS 0) rector O - Dit 00 IP Value - Vector 0 (IP 0) eee 2 Bytes of Fig. 4.12: Interrupt Vector Table of the 8086 microprocessor 16 8086/8088 Mumba M. Michael BS.CMP.S (UNZA)