IS1102 Computer Systems
Sequential Logic Circuits
Digital Logic Circuits
There are two types of digital logic circuits
1. Combinational Logic circuits
2. Sequential Logic circuits
Combinational Circuit - Recap
● 2n possible input patterns
● Circuits can be represented using
○ Truth table
○ Boolean function
○ Logic gates
● Examples:
○ half adders, full adders, multiplexers, demultiplexers, encoders and decoder
Sequential Logic circuit
● A combination of combinational circuit and memory
● Present output depends on the present input and past output
● Examples : Flip flops , Counters, Registers
Combinational vs Sequential
Combinational Circuits Sequential Circuits
The output of a combinational circuit Consider not only its present inputs,
depends only on its current inputs. but also the previous outputs that are
stored in storage elements.
Purely built upon logic gates Stores previous outputs.
No feedback paths or memory
elements
Classification of Sequential Logic circuits
Synchronous Sequential Circuits Asynchronous Sequential Circuits
(Clock Driven) (Event Driven)
State changes only within discrete State changes immediately after
time intervals. inputs are changed.
Easy to design Difficult to design
Use clock signals Do not use clock signals
Slower Faster as clock is absent
What is a clock signal?
● A signal which oscillates between logic level 0 and logic level 1, repeatedly.
● It controls the outputs of the sequential circuit
● It determines when and how the memory elements change their outputs
Storage elements in sequential circuits
● Flip Flops
● Latches
Four main types of flip flops and latches
1. SR
2. D
3. JK
4. T
Flip flops vs. Latches
Flip Flops Latches
Building block of sequential circuits, Building block of sequential circuits,
built using latches along with an built using logic gates
additional clock signal.
slow compared to the latches fast compared to the Flip-Flops
Has a clock signal Does not has a clock signal
An edge sensitive device A level sensitive device
Clock signal vs. Enable Signal
A clock (clk) is a signal which is used to make the flip flop work at its
positive or negative edge (in exceptional case both edge) in the
digital system.
An enable is a signal which makes the flip flop function as long as it
is high (1). It can be made low (0) to make the flip flop stops its
function.
S-R Latch
S-R Latch with Control Signal
D Latch
D flip flop
CLK D Q(t+1)
0 x Q(t)
1 0 Q(t)
1 1 1
D latch : timing (example)
D flip flop : timing (example)
Clocked S-R Flip Flop
● Stands for SET-RESET flip-flops
● Basic flip-flop among all the flip-flops.
● All the other flip flops are developed after SR-flip-flop.
● When both S and R are 1, the SR flip-flop is unstable
CLK S R Q(t+1)
0 x x Q(t)
1 0 0 Q(t)
1 0 1 0
1 1 0 1
1 1 1 Forbidden
J-K Flip flop
A refinement of SR flip-flop
J-K Flip flop (Timing example)
T Flip flop
A single input version of JK flip-flop (both
inputs connected together).
Flip flop - Summary
Thank You
