Course Plan

A. Course Handout
Institute/School/College Name Chitkara University Institute of Engineering & Technology
Department/Centre Name Department of Computer Science & Engineering
Programme Name Bachelor of Engineering (B.E.)-Computer Science & Engineering
Course Name Computer System Architecture
Course Code CSL4208 Semester/Batch 3rd/2020
Lecture/Tutorial (Per Week) 3-2-0 Course Credit 04
Course Coordinator Name Dr. Rajeev Kumar

1. Objective of the Course

The course provides a wide scope of learning & understanding of the subject and after completion of
the course the student will have the ability to the develop

The main objective of the courses is:

• To make student familiar with basic architecture of computer system
• To make student learn about internal working of components of system
• Students would be able to understand the working and data flow in computer components

2. Course Learning Outcome:

CLO01: Ability to Understand Basic structure of computer
CLO02: Ability to perform Computer’s Arithmetic Operations
CLO03: Ability to understand control unit operations
CL004: Ability to Design memory organization that uses different word size operations
CL005: Ability to understand concept of cache memory technique.
CL006: Ability to conceptualize instruction level parallelism.

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Learning
Outcomes
CLO1 H H M
CLO2 H H M
CLO3 H M
CLO4 H H M
CLO5 H H M H M
CLO6

3. Recommended Books (Reference Books/Text Books):

B01: 'Computer System Architecture' by M. Morris Mano, Pearson Education, 2008
B02: John P Hayes, “Computer Architecture and Organization”, Prentice Hall
B03: Malvino Leech, Digital Electronics Fundamentals
B04: David A Patterson, Computer Architecture A Quantitative Approach, Pearson Education
B05: J.P. Hayes, Computer System Architecture, Pearson Education Asia
B06: William Stallings, Computer Organization and Architecture: Designing for Performance,
Prentice-Hall India

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4. Other readings & relevant websites:

S.No. Link of Journals, Magazines, websites and Research Papers

1. http://nptel.ac.in/courses/106104073/
2. http://nptel.ac.in/courses/106106092/
3. http://nptel.ac.in/courses/106103068/
4. http://nptel.iitm.ac.in/video.php?subjectId=106106093
5. http://www.anirbanm.in/mca203
5. Recommended Platforms

NPTEL (online Link- https://nptel.ac.in/courses/106/103/106103068/)

6. Course Plan:
a. Lecture Plan

Lecture No. Topic(s)

1-2 Introduction to Computer Organization & Architecture:

A Brief History of Computer Architecture and Organization,
Review of number systems
3 Basic Computer Organization: Instruction Codes, Computer
Registers, Computer Instructions
4-5 Timing and Control, Instruction Cycle
6-7 Memory Reference Instructions, Input-Output and Interrupt,
Complete Computer Description

8 Design of Basic Computer and Accumulator Logic

9-10 Micro programmed Control:

Control Memory, Address Sequencing
11-13 Micro program Examples and Design of Control unit

14 Central Processing Unit: Introduction, General Register

Organization
15-16 Stack Organization and Instruction Format

ST-1(Syllabus covered from 1- 16 lect.)

17-19 Addressing Modes, Data Transfer and Manipulation

20-21 Program Control: Status bits, Conditional Branch Instructions,
Subroutines call and return Program Interrupts & Types
22 RISC and CISC Characteristics
23 Introduction to Parallel processing/pipelining

24-25 Arithmetic Pipelining, Instruction Pipelining

26-28 Binary arithmetic - add, subtract algorithm and implementations

Binary arithmetic- multiply - algorithms and implementations
29 Input-Output Organization:
Peripheral Devices, I/O Interface
ST-2(Syllabus covered from 17-29 lect.)

30-31 Asynchronous Data Transfer

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32 Modes of Transfer

33-34 Direct Memory Access(DMA), Input-Output Processor(IOP),

Serial Communication
35-37 Memory Organization:
Memory Hierarchy, Main Memory, Auxiliary Memory,
Associative Memory
38-39 Cache Memory and Virtual Memory

ST-3(Syllabus covered from 1-39 lect.)

b. Tutorial Plan
*Numerical Problems of the following topics are to be covered in the tutorials.

Tutorial No. Topic(s)

1 Basic Computer Organization: Computer Registers, Instruction

Codes, Computer Instructions, Timing and Control, Instruction
Cycle
2 Memory Reference Instructions, Input-Output and Interrupt,
Complete Computer Description
3 Control Memory, Address Sequencing
4 Micro program Example: computer configuration, micro-
instruction format, symbolic microinstructions, fetch and
routine, Design of Control unit
5 Central Processing Unit: Introduction, General Register
Organization
6 Stack Organization. Instruction Format ( Three address, Two
Address, One address, Zero address),
7 Addressing Modes, Data Transfer and Manipulation
8 Program Control:
Status bits, Conditional Branch Instructions, Program Interrupts
& Types
9 Pipelining, Arithmetic pipelining
10 binary arithmetic - add, subtract algorithm and
implementations
11 binary arithmetic- multiply - algorithms and implementations
12 Input-Output Organization
13 Memory Organization
7. Action plan for different types of learners

Slow Learners Average Learners Fast Learners

Remedial Classes on Saturdays Workshop Competitions

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8. Evaluation Scheme & Components:

Evaluation Type of Component No. of Weightage of Mode of

Component Assessments Component Assessment
Subjective Test/Sessional
Component 1 03* 40% Offline
Tests (STs)

Component 2 End Term Examinations 01 60% Offline

Total 100%
*Out of 03 STs, the ERP system automatically picks the best 02 STs marks for evaluation of the STs as final marks.

9. Details of Evaluation Components:

Evaluation Description Syllabus Timeline of Examination Weightage

Component Covered (%) (%)

As defined in Academic
ST 01 Upto 40%
Calendar
Component As defined in Academic
ST 02 41% - 80% 40%
01 Calendar
As defined in Academic
ST 03 100%
Calendar

At the end of the

Component 60%
End Term Examination* 100%
02 semester

Total 100%
*As per Academic Guidelines minimum 75% attendance is required to become eligible for appearing in the End Semester
Examination.

10. Syllabus of the Course:

Subject: Computer System Architecture Subject Code: CSL4208

No. of Weightage
S.N. Topic (s)
Lectures %
1 Introduction to Computer Organization & Architecture: 2 10
A Brief History of Computer Architecture and Organization, Review
of number systems
2 Basic Computer Organization: 6 12
Computer Registers, Instruction Codes, Computer Instructions,
Timing and Control, Instruction Cycle, Memory Reference
Instructions, Input-Output and Interrupt, Complete Computer
Description
3 Microprogrammed Control: 7 18
Control Memory, Address Sequencing, Micro program Example,
Design of Control unit, Central Processing Unit introduction, General
Register Organization, Stack Organization. Instruction Format (
Three address, Two Address, One address, Zero address),
4 Addressing Modes, Data Transfer and Manipulation 3 10
5 Program Control: 3 10

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Status bits, Conditional Branch Instructions, Program Interrupts &

Types, RISC/CISC Characteristics
6 Pipelining and Instruction cycle: Parallel processing, Pipelining, 4 3
Arithmetic pipelining
7 Basic Computer Organization taking 8085 as an example, binary 3 10
arithmetic – add, subtract, multiply – algorithms and
implementations
8 Input-Output Organization: 6 20
Peripheral Devices, I/O Interface Asynchronous Data Transfer, Modes
of Transfer
Direct Memory Access(DMA),DMA Transfer, DMA Controller Input-
Output Processor(IOP), CPU-IOP Communication

9 Memory Organization: 5 7
Memory Hierarchy Main Memory(RAM & ROM Chips), Auxiliary
Memory(Magnetic Disc & Tapes) Associative Memory Cache
Memory(Associative Mapping, Direct Mapping, Set-Associative
Mapping), Virtual Memory

This Document is approved by:

Designation Name Signature

Course Coordinator Dr. Rajeev Kumar
Associate Dean
Dean Dr. Rishu Chabra
Date (DD/MM/YYYY) 26th Jan, 2022

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B. Course Execution Plan

Lecture No. Topics Date of delivery Remarks (if any)

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Signature with Name Counter Signed by

Faculty In-charge Associate Dean/Dean

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