An undefined length burst which concludes with a BUSY transfer.
N-B-S-B-S-B-I
An undefined length burst which concludes with a BUSY transfer and is followed immediately by another
burst.
N-B-S-B-S-B-N-S
25. How should AHB to APB bridges handle accesses that are not 32-bits?
The bridge should simply pass the entire 32-bit data bus through the bridge. Please note that when
transfers less than 32-bits are performed to an APB slave it is important to ensure that the peripheral is
located on the appropriate bits of the APB data bus.
_______________________________________________________________________________
AMBA AHB - Arbitration
1.When should a master assert and deassert the HLOCK signal for a locked transfer?
The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked
transfer. This is required so that the arbiter can sample the HLOCK signal as high at the start of the
address phase.
The master should deassert the HLOCK signal when the address phase of the last transfer in the locked
sequence has started.
2. Can an arbiter be designed to always allow bursts to complete?
A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early terminated. This is
outwith the control of the Arbiter and so must be supported.
Undefined length INCR bursts cannot have their end point predicted, so there is no efficient way that an
Arbiter design can allow the burst to complete before granting another master. INCR bursts must be
arbitrated on a cycle by cycle basis.
Defined length INCRx and WRAPx bursts can have their beats counted, and so allowed to complete by
the Arbiter. However because of the AHB arbitration synchronous timing, there is no way to avoid
possibly terminating a burst immediately after the first transfer of the burst has been indicated.
The Arbiter only knows that a defined length burst is in progress by sampling the HBURST bus. However
the first point at which HBURST can be sampled is after the first clock cycle of the first burst beat, by
which time the Arbiter may already have decided to grant another master and will have changed the
HGRANT outputs accordingly. Only a combinatorial path from HBURST to HGRANT would allow the burst
to be detected in time to avoid early termination in this scenario, but combinatorial paths in the AHB bus
are not allowed. ask ARM
3. Why is HADDR sometimes shown as an input to the arbiter?
The address bus, HADDR, is not required as an input to the arbiter but in some system designs it may be
useful to use the address bus to determine a good point to change over between bus masters. For
example, the arbiter could be designed to change bus ownership when a burst of transfers reaches a
quad word boundary.
4. When can the HGRANT signal change?
The HGRANT signal can change in any cycle and the following cases are possible:
* It is possible that the HGRANT signal may be asserted and then removed before the current transfer
completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is
high.
* A master can be granted the bus without requesting it.
* The above point also means that it is possible to be granted the bus in the same cycle that it is
requested. This can occur if the master is coincidentally granted the bus in the same cycle that it
requests it.
5. What is the relationship between the HLOCK signal and the HMASTLOCK signal?
At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master
that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will
be asserted by the arbiter for the duration of the address phase of the transfer.
6. When should a master deassert its HBUSREQ signal?
For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started
the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the
burst is zero wait state then the master may be granted the bus for an additional transfer at the end of
an undefined length burst.
