ESP32

Technical Reference Manual Version 5.2

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About This Manual
The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed
and complete information on how to use the ESP32 memory and peripherals.

For pin definition, electrical characteristics, and package information, please see ESP32 Datasheet.

Document Updates
Please always refer to the latest version at https://www.espressif.com/en/support/download/documents.

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For any changes to this document over time, please refer to the last page.

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Contents

Contents

1 System and Memory 24

1.1 Introduction 24
1.2 Features 24
1.3 Functional Description 26
1.3.1 Address Mapping 26
1.3.2 Embedded Memory 26
1.3.2.1 Internal ROM 0 28
1.3.2.2 Internal ROM 1 28
1.3.2.3 Internal SRAM 0 28
1.3.2.4 Internal SRAM 1 29
1.3.2.5 Internal SRAM 2 29
1.3.2.6 DMA 30
1.3.2.7 RTC FAST Memory 30
1.3.2.8 RTC SLOW Memory 30
1.3.3 External Memory 30
1.3.4 Cache 31
1.3.5 Peripherals 32
1.3.5.1 Asymmetric PID Controller Peripheral 33
1.3.5.2 Non-Contiguous Peripheral Memory Ranges 34
1.3.5.3 Memory Speed 34

2 Interrupt Matrix (INTERRUPT) 35

2.1 Overview 35
2.2 Features 35
2.3 Functional Description 35
2.3.1 Peripheral Interrupt Source 35
2.3.2 CPU Interrupt 38
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 38
2.3.4 CPU NMI Interrupt Mask 39
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 39
2.4 Registers 39

3 Reset and Clock 40

3.1 System Reset 40
3.1.1 Introduction 40
3.1.2 Reset Source 40
3.2 System Clock 41
3.2.1 Introduction 41
3.2.2 Clock Source 42
3.2.3 CPU Clock 42
3.2.4 Peripheral Clock 43
3.2.4.1 APB_CLK 43

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3.2.4.2 REF_TICK 43
3.2.4.3 LEDC_SCLK Source 44
3.2.4.4 APLL_SCLK Source 44
3.2.4.5 PLL_F160M_CLK Source 44
3.2.4.6 Clock Source Considerations 44
3.2.5 Wi-Fi BT Clock 44
3.2.6 RTC Clock 45
3.2.7 Audio PLL 45
3.3 Register Summary 45
3.4 Registers 46

4 IO_MUX and GPIO Matrix (GPIO, IO_MUX) 49

4.1 Overview 49
4.2 Peripheral Input via GPIO Matrix 50
4.2.1 Summary 50
4.2.2 Functional Description 50
4.2.3 Simple GPIO Input 51
4.3 Peripheral Output via GPIO Matrix 51
4.3.1 Summary 51
4.3.2 Functional Description 52
4.3.3 Simple GPIO Output 53
4.4 Direct I/O via IO_MUX 53
4.4.1 Summary 53
4.4.2 Functional Description 53
4.5 RTC IO_MUX for Low Power and Analog I/O 53
4.5.1 Summary 53
4.5.2 Analog Function Description 54
4.6 Light-sleep Mode Pin Functions 54
4.7 Pad Hold Feature 54
4.8 I/O Pad Power Supplies 55
4.8.1 VDD_SDIO Power Domain 56
4.9 Peripheral Signal List 56
4.10 IO_MUX Pad List 61
4.11 RTC_MUX Pin List 62
4.12 Register Summary 63
4.12.1 GPIO Matrix Register Summary 63
4.12.2 IO MUX Register Summary 64
4.12.3 RTC IO MUX Register Summary 65
4.13 Registers 66
4.13.1 GPIO Matrix Registers 66
4.13.2 IO MUX Registers 76
4.13.3 RTC IO MUX Registers 78

5 DPort Registers 94
5.1 Introduction 94
5.2 Features 94

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5.3 Functional Description 94

5.3.1 System and Memory Register 94
5.3.2 Reset and Clock Registers 94
5.3.3 Interrupt Matrix Register 94
5.3.4 DMA Registers 94
5.3.5 MPU/MMU Registers 94
5.3.6 APP_CPU Controller Registers 95
5.3.7 Peripheral Clock Gating and Reset 95
5.4 Register Summary 96
5.5 Registers 103

6 DMA Controller (DMA) 122

6.1 Overview 122
6.2 Features 122
6.3 Functional Description 122
6.3.1 DMA Engine Architecture 122
6.3.2 Linked List 123
6.4 UART DMA (UDMA) 123
6.5 SPI DMA Interface 125
6.6 I2S DMA Interface 126

7 SPI Controller (SPI) 127

7.1 Overview 127
7.2 SPI Features 128
7.3 GP-SPI 128
7.3.1 GP-SPI Four-line Full-duplex Communication 129
7.3.2 GP-SPI Four-line Half-duplex Communication 129
7.3.3 GP-SPI Three-line Half-duplex Communication 130
7.3.4 GP-SPI Data Buffer 130
7.4 GP-SPI Clock Control 131
7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 131
7.4.2 GP-SPI Timing 132
7.5 Parallel QSPI 133
7.5.1 Communication Format of Parallel QSPI 133
7.6 GP-SPI Interrupt Hardware 134
7.6.1 SPI Interrupts 134
7.6.2 DMA Interrupts 134
7.7 Register Summary 135
7.8 Registers 138

8 SDIO Slave Controller 161

8.1 Overview 161
8.2 Features 161
8.3 Functional Description 161
8.3.1 SDIO Slave Block Diagram 161
8.3.2 Sending and Receiving Data on SDIO Bus 162

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8.3.3 Register Access 162

8.3.4 DMA 162
8.3.5 Packet-Sending/-Receiving Procedure 163
8.3.5.1 Sending Packets to SDIO Host 164
8.3.5.2 Receiving Packets from SDIO Host 165
8.3.6 SDIO Bus Timing 166
8.3.7 Interrupt 167
8.3.7.1 Host Interrupt 167
8.3.7.2 Slave Interrupt 167
8.4 Register Summary 168
8.5 SLC Registers 170
8.6 SLC Host Registers 178
8.7 HINF Registers 192

9 SD/MMC Host Controller 194

9.1 Overview 194
9.2 Features 194
9.3 SD/MMC External Interface Signals 194
9.4 Functional Description 195
9.4.1 SD/MMC Host Controller Architecture 195
9.4.1.1 BIU 196
9.4.1.2 CIU 196
9.4.2 Command Path 196
9.4.3 Data Path 197
9.4.3.1 Data Transmit Operation 197
9.4.3.2 Data Receive Operation 198
9.5 Software Restrictions for Proper CIU Operation 198
9.6 RAM for Receiving and Sending Data 200
9.6.1 Transmit RAM Module 200
9.6.2 Receive RAM Module 200
9.7 Descriptor Chain 200
9.8 The Structure of a Linked List 200
9.9 Initialization 203
9.9.1 DMAC Initialization 203
9.9.2 DMAC Transmission Initialization 203
9.9.3 DMAC Reception Initialization 203
9.10 SD/MMC Timing 204
9.11 Clock Phase Selection 205
9.12 Interrupt 206
9.13 Register Summary 206
9.14 Registers 207

10 Ethernet Media Access Controller (MAC) 226

10.1 Overview 226
10.2 EMAC_CORE 228
10.2.1 Transmit Operation 228

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10.2.1.1 Transmit Flow Control 229

10.2.1.2 Retransmission During a Collision 229
10.2.2 Receive Operation 229
10.2.2.1 Reception Protocol 230
10.2.2.2 Receive Frame Controller 230
10.2.2.3 Receive Flow Control 230
10.2.2.4 Reception of Multiple Frames 231
10.2.2.5 Error Handling 231
10.2.2.6 Receive Status Word 231
10.3 MAC Interrupt Controller 231
10.4 MAC Address Filtering 232
10.4.1 Unicast Destination Address Filtering 232
10.4.2 Multicast Destination Address Filtering 232
10.4.3 Broadcast Address Filtering 232
10.4.4 Unicast Source Address Filtering 232
10.4.5 Inverse Filtering Operation 232
10.4.6 Good Transmitted Frames and Received Frames 234
10.5 EMAC_MTL (MAC Transaction Layer) 234
10.6 PHY Interface 234
10.6.1 MII (Media Independent Interface) 235
10.6.1.1 Interface Signals Between MII and PHY 235
10.6.1.2 MII Clock 236
10.6.2 RMII (Reduced Media-Independent Interface) 237
10.6.2.1 RMII Interface Signal Description 237
10.6.2.2 RMII Clock 237
10.6.3 Station Management Agent (SMA) Interface 238
10.6.4 RMII Timing 238
10.7 Ethernet DMA Features 239
10.8 Linked List Descriptors 239
10.8.1 Transmit Descriptors 239
10.8.2 Receive Descriptors 244
10.9 Register Summary 249
10.10 Registers 251

11 I2C Controller (I2C) 289

11.1 Overview 289
11.2 Features 289
11.3 Functional Description 289
11.3.1 Introduction 289
11.3.2 Architecture 290
11.3.3 I2C Bus Timing 291
11.3.4 I2C cmd Structure 292
11.3.5 I2C Master Writes to Slave 293
11.3.6 Master Reads from Slave 297
11.3.7 Interrupts 299
11.4 Register Summary 300

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11.5 Registers 302

12 I2S Controller (I2S) 313

12.1 Overview 313
12.2 Features 314
12.3 The Clock of I2S Module 315
12.4 I2S Mode 316
12.4.1 Supported Audio Standards 316
12.4.1.1 Philips Standard 316
12.4.1.2 MSB Alignment Standard 317
12.4.1.3 PCM Standard 317
12.4.2 Module Reset 317
12.4.3 FIFO Operation 317
12.4.4 Sending Data 318
12.4.5 Receiving Data 319
12.4.6 I2S Master/Slave Mode 321
12.4.7 I2S PDM 321
12.5 Camera-LCD Controller 323
12.5.1 LCD Master Transmitting Mode 324
12.5.2 Camera Slave Receiving Mode 324
12.5.3 ADC/DAC mode 325
12.6 I2S Interrupts 326
12.6.1 FIFO Interrupts 326
12.6.2 DMA Interrupts 327
12.7 Register Summary 327
12.8 Registers 329

13 UART Controller (UART) 347

13.1 Overview 347
13.2 UART Features 347
13.3 Functional Description 347
13.3.1 Introduction 347
13.3.2 UART Architecture 348
13.3.3 UART RAM 349
13.3.4 Baud Rate Detection 350
13.3.5 UART Data Frame 350
13.3.6 AT_CMD Character Structure 351
13.3.7 Flow Control 351
13.3.7.1 Hardware Flow Control 352
13.3.7.2 Software Flow Control 352
13.3.8 UART DMA 353
13.3.9 UART Interrupts 353
13.3.10 UHCI Interrupts 354
13.4 Register Summary 354
13.4.1 UART Register Summary 354
13.4.2 UHCI Register Summary 356

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13.5 Registers 358

13.5.1 UART Registers 358
13.5.2 UHCI Registers 358

14 LED PWM Controller (LEDC) 390

14.1 Introduction 390
14.2 Functional Description 390
14.2.1 Architecture 390
14.2.2 Timers 391
14.2.3 Channels 392
14.2.4 Interrupts 393
14.3 Register Summary 394
14.4 Registers 398

15 Remote Control Peripheral (RMT) 408

15.1 Introduction 408
15.2 Functional Description 408
15.2.1 RMT Architecture 408
15.2.2 RMT RAM 409
15.2.3 Clock 409
15.2.4 Transmitter 409
15.2.5 Receiver 410
15.2.6 Interrupts 410
15.3 Register Summary 410
15.4 Registers 411

16 Motor Control PWM (PWM) 417

16.1 Introduction 417
16.2 Features 417
16.3 Submodules 419
16.3.1 Overview 419
16.3.1.1 Prescaler Submodule 419
16.3.1.2 Timer Submodule 419
16.3.1.3 Operator Submodule 420
16.3.1.4 Fault Detection Submodule 422
16.3.1.5 Capture Submodule 422
16.3.2 PWM Timer Submodule 422
16.3.2.1 Configurations of the PWM Timer Submodule 422
16.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 423
16.3.2.3 PWM Timer Shadow Register 428
16.3.2.4 PWM Timer Synchronization and Phase Locking 428
16.3.3 PWM Operator Submodule 428
16.3.3.1 PWM Generator Submodule 430
16.3.3.2 Dead Time Generator Submodule 440
16.3.3.3 PWM Carrier Submodule 445
16.3.3.4 Fault Handler Submodule 448

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16.3.4 Capture Submodule 449

16.3.4.1 Introduction 449
16.3.4.2 Capture Timer 450
16.3.4.3 Capture Channel 450
16.4 Register Summary 451
16.5 Registers 453

17 Pulse Count Controller (PCNT) 501

17.1 Overview 501
17.2 Functional Description 501
17.2.1 Architecture 501
17.2.2 Counter Channel Inputs 502
17.2.3 Watchpoints 502
17.2.4 Examples 503
17.2.5 Interrupts 503
17.3 Register Summary 504
17.4 Registers 505

18 Timer Group (TIMG) 511

18.1 Introduction 511
18.2 Functional Description 511
18.2.1 16-bit Prescaler 511
18.2.2 64-bit Time-base Counter 511
18.2.3 Alarm Generation 512
18.2.4 MWDT 512
18.2.5 Interrupts 512
18.3 Register Summary 512
18.4 Registers 514

19 Watchdog Timers (WDT) 521

19.1 Introduction 521
19.2 Features 521
19.3 Functional Description 521
19.3.1 Clock 521
19.3.1.1 Operating Procedure 521
19.3.1.2 Write Protection 522
19.3.1.3 Flash Boot Protection 522
19.3.1.4 Registers 522

20 eFuse Controller 523

20.1 Introduction 523
20.2 Features 523
20.3 Functional Description 523
20.3.1 Structure 523
20.3.1.1 System Parameter efuse_wr_disable 525
20.3.1.2 System Parameter efuse_rd_disable 525

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20.3.1.3 System Parameter coding_scheme 526

20.3.1.4 BLK3_part_reserve 526
20.3.2 Programming of System Parameters 527
20.3.3 Software Reading of System Parameters 529
20.3.4 The Use of System Parameters by Hardware Modules 531
20.3.5 Interrupts 531
20.4 Register Summary 531
20.5 Registers 534

21 Two-wire Automotive Interface (TWAI) 545

21.1 Overview 545
21.2 Features 545
21.3 Functional Protocol 545
21.3.1 TWAI Properties 545
21.3.2 TWAI Messages 546
21.3.2.1 Data Frames and Remote Frames 547
21.3.2.2 Error and Overload Frames 549
21.3.2.3 Interframe Space 551
21.3.3 TWAI Errors 551
21.3.3.1 Error Types 551
21.3.3.2 Error States 552
21.3.3.3 Error Counters 552
21.3.4 TWAI Bit Timing 553
21.3.4.1 Nominal Bit 553
21.3.4.2 Hard Synchronization and Resynchronization 554
21.4 Architectural Overview 554
21.4.1 Registers Block 554
21.4.2 Bit Stream Processor 556
21.4.3 Error Management Logic 556
21.4.4 Bit Timing Logic 556
21.4.5 Acceptance Filter 556
21.4.6 Receive FIFO 557
21.5 Functional Description 557
21.5.1 Modes 557
21.5.1.1 Reset Mode 557
21.5.1.2 Operation Mode 557
21.5.2 Bit Timing 558
21.5.3 Interrupt Management 558
21.5.3.1 Receive Interrupt (RXI) 559
21.5.3.2 Transmit Interrupt (TXI) 559
21.5.3.3 Error Warning Interrupt (EWI) 559
21.5.3.4 Data Overrun Interrupt (DOI) 560
21.5.3.5 Error Passive Interrupt (TXI) 560
21.5.3.6 Arbitration Lost Interrupt (ALI) 560
21.5.3.7 Bus Error Interrupt (BEI) 560
21.5.4 Transmit and Receive Buffers 560

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21.5.4.1 Overview of Buffers 560

21.5.4.2 Frame Information 561
21.5.4.3 Frame Identifier 562
21.5.4.4 Frame Data 562
21.5.5 Receive FIFO and Data Overruns 563
21.5.6 Acceptance Filter 563
21.5.6.1 Single Filter Mode 564
21.5.6.2 Dual FIlter Mode 564
21.5.7 Error Management 565
21.5.7.1 Error Warning Limit 566
21.5.7.2 Error Passive 566
21.5.7.3 Bus-Off and Bus-Off Recovery 566
21.5.8 Error Code Capture 567
21.5.9 Arbitration Lost Capture 568
21.6 Register Summary 568
21.7 Registers 569

22 AES Accelerator (AES) 583

22.1 Introduction 583
22.2 Features 583
22.3 Functional Description 583
22.3.1 AES Algorithm Operations 583
22.3.2 Key, Plaintext and Ciphertext 583
22.3.3 Endianness 583
22.3.4 Encryption and Decryption Operations 586
22.3.5 Speed 586
22.4 Register Summary 586
22.5 Registers 587

23 SHA Accelerator (SHA) 589

23.1 Introduction 589
23.2 Features 589
23.3 Functional Description 589
23.3.1 Padding and Parsing the Message 589
23.3.2 Message Digest 589
23.3.3 Hash Operation 589
23.3.4 Speed 590
23.4 Register Summary 590
23.5 Registers 592

24 RSA Accelerator (RSA) 598

24.1 Introduction 598
24.2 Features 598
24.3 Functional Description 598
24.3.1 Initialization 598
24.3.2 Large Number Modular Exponentiation 598

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24.3.3 Large Number Modular Multiplication 600

24.3.4 Large Number Multiplication 600
24.4 Register Summary 601
24.5 Registers 602

25 Random Number Generator (RNG) 604

25.1 Introduction 604
25.2 Feature 604
25.3 Functional Description 604
25.4 Programming Procedure 605
25.5 Register Summary 605
25.6 Register 605

26 External Memory Encryption and Decryption (FLASH) 606

26.1 Overview 606
26.2 Features 606
26.3 Functional Description 606
26.3.1 Key Generator 607
26.3.2 Flash Encryption Block 607
26.3.3 Flash Decryption Block 608
26.4 Register Summary 608
26.5 Register 609

27 Memory Management and Protection Units (MMU, MPU) 611

27.1 Introduction 611
27.2 Features 611
27.3 Functional Description 611
27.3.1 PID Controller 611
27.3.2 MPU/MMU 611
27.3.2.1 Embedded Memory 612
27.3.2.2 External Memory 618
27.3.2.3 Peripheral 624

28 Process ID Controller (PID) 626

28.1 Overview 626
28.2 Features 626
28.3 Functional Description 626
28.3.1 Interrupt Identification 626
28.3.2 Information Recording 627
28.3.3 Proactive Process Switching 628
28.4 Register Summary 631
28.5 Registers 632

29 On-Chip Sensors and Analog Signal Processing 637

29.1 Introduction 637
29.2 Capacitive Touch Sensor 637

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29.2.1 Introduction 637

29.2.2 Features 637
29.2.3 Available GPIOs 638
29.2.4 Functional Description 638
29.2.5 Touch FSM 639
29.3 SAR ADC 640
29.3.1 Introduction 640
29.3.2 Features 641
29.3.3 Outline of Function 641
29.3.4 RTC SAR ADC Controllers 643
29.3.5 DIG SAR ADC Controllers 644
29.4 DAC 646
29.4.1 Introduction 646
29.4.2 Features 646
29.4.3 Structure 647
29.4.4 Cosine Waveform Generator 647
29.4.5 DMA support 648
29.5 Register Summary 649
29.5.1 Sensors 649
29.5.2 Advanced Peripheral Bus 649
29.5.3 RTC I/O 650
29.6 Registers 651
29.6.1 Sensors 651
29.6.2 Advanced Peripheral Bus 660
29.6.3 RTC I/O 664

30 ULP Coprocessor (ULP) 665

30.1 Introduction 665
30.2 Features 665
30.3 Functional Description 666
30.4 Instruction Set 666
30.4.1 ALU - Perform Arithmetic/Logic Operations 667
30.4.1.1 Operations Among Registers 667
30.4.1.2 Operations with Immediate Value 668
30.4.1.3 Operations with Stage Count Register 668
30.4.2 ST – Store Data in Memory 669
30.4.3 LD – Load Data from Memory 669
30.4.4 JUMP – Jump to an Absolute Address 670
30.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 670
30.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 671
30.4.7 HALT – End the Program 671
30.4.8 WAKE – Wake up the Chip 672
30.4.9 Sleep – Set the ULP Timer’s Wake-up Period 672
30.4.10 WAIT – Wait for a Number of Cycles 672
30.4.11 ADC – Take Measurement with ADC 672
30.4.12 I2C_RD/I2C_WR – Read/Write I²C 673

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30.4.13 REG_RD – Read from Peripheral Register 674

30.4.14 REG_WR – Write to Peripheral Register 674
30.5 ULP Program Execution 675
30.6 RTC_I2C Controller 676
30.6.1 Configuring RTC_I2C 677
30.6.2 Using RTC_I2C 677
30.6.2.1 I2C_RD - Read a Single Byte 677
30.6.2.2 I2C_WR - Write a Single Byte 678
30.6.2.3 Detecting Error Conditions 678
30.6.2.4 Connecting I²C Signals 679
30.7 Register Summary 679
30.7.1 SENS_ULP Address Space 679
30.7.2 RTC_I2C Address Space 679
30.8 Registers 681
30.8.1 SENS_ULP Address Space 681
30.8.2 RTC_I2C Address Space 683

31 Low-Power Management (RTC_CNTL) 690

31.1 Introduction 690
31.2 Features 690
31.3 Functional Description 690
31.3.1 Overview 691
31.3.2 Digital Core Voltage Regulator 691
31.3.3 Low-Power Voltage Regulator 691
31.3.4 Flash Voltage Regulator 692
31.3.5 Brownout Detector 693
31.3.6 RTC Module 693
31.3.7 Low-Power Clocks 695
31.3.8 Power-Gating Implementation 696
31.3.9 Predefined Power Modes 697
31.3.10 Wakeup Source 699
31.3.11 Reject Sleep 700
31.3.12 RTC Timer 701
31.3.13 RTC Boot 701
31.4 Register Summary 702
31.5 Registers 704

Glossary 732
Abbreviations for Peripherals 732
Abbreviations for Registers 732

Revision History 734

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List of Tables

List of Tables
1-1 Address Mapping 26
1-2 Embedded Memory Address Mapping 28
1-3 Module with DMA 30
1-4 External Memory Address Mapping 30
1-5 Cache memory mode 31
1-6 Peripheral Address Mapping 32
2-1 PRO_CPU, APP_CPU Interrupt Configuration 36
2-2 CPU Interrupts 38
3-1 PRO_CPU and APP_CPU Reset Reason Values 40
3-2 CPU_CLK Source 42
3-3 CPU_CLK Derivation 42
3-4 Peripheral Clock Usage 43
3-5 APB_CLK 43
3-6 REF_TICK 44
3-7 LEDC_SCLK Derivation 44
4-1 IO_MUX Light-sleep Pin Function Registers 54
4-2 GPIO Matrix Peripheral Signals 56
4-3 IO_MUX Pad Summary 61
4-4 RTC_MUX Pin Summary 62
4-8 Mapping of Bits to Pins 83
7-1 Mapping Between SPI Bus Signals and Pin Function Signals 127
7-2 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode 129
7-3 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master 131
7-4 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave 131
9-1 SD/MMC Signal Description 195
9-2 DES0 201
9-3 DES1 202
9-4 DES2 202
9-5 DES3 202
9-6 SD/MMC Timing Requirements 204
10-1 Destination Address Filtering 233
10-2 Source Address Filtering 233
10-3 Timing Parameters - Receiving Data 238
10-4 Timing Parameters – Transmitting Data 239
10-5 Transmit Descriptor 0 (TDES0) 240
10-6 Transmit Descriptor 1 (TDES1) 244
10-7 Transmit Descriptor 2 (TDES2) 244
10-8 Transmit Descriptor 3 (TDES3) 244
10-9 Receive Descriptor 0 (RDES0) 245
10-10 Receive Descriptor 1 (RDES1) 247
10-11 Receive Descriptor 2 (RDES2) 248
10-12 Receive Descriptor 3 (RDES3) 248
10-13 Receive Descriptor 4 (RDES4) 248

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List of Tables

11-1 SCL Frequency Configuration 291

12-1 I2S Signal Bus Description 314
12-2 Register Configuration 318
12-3 Send Channel Mode 319
12-4 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration 320
12-5 The Register Configuration to Which the Four Modes Correspond 321
12-6 Upsampling Rate Configuration 322
12-7 Down-sampling Configuration 323
14-1 Commonly-used Frequencies and Resolutions 392
16-1 Configuration Parameters of the Operator Submodule 421
16-2 Timing Events Used in PWM Generator 430
16-3 Timing Events Priority When PWM Timer Increments 431
16-4 Timing Events Priority when PWM Timer Decrements 431
16-5 Dead Time Generator Switches Control Registers 441
16-6 Typical Dead Time Generator Operating Modes 442
20-1 System Parameters 523
20-2 BLOCK1/2/3 Encoding 526
20-3 Program Registers 527
20-4 Timing Configuration 529
20-5 Software Read Registers 530
21-1 Data Frames and Remote Frames in SFF and EFF 548
21-2 Error Frame 549
21-3 Overload Frame 550
21-4 Interframe Space 551
21-5 Segments of a Nominal Bit Time 553
21-6 Bit Information of TWAI_CLOCK_DIVIDER_REG; TWAI Address 0x18 558
21-7 Bit Information of TWAI_BUS_TIMING_1_REG; TWAI Address 0x1c 558
21-8 Buffer Layout for Standard Frame Format and Extended Frame Format 560
21-9 TX/RX Frame Information (SFF/EFF); TWAI Address 0x40 561
21-10 TX/RX Identifier 1 (SFF); TWAI Address 0x44 562
21-11 TX/RX Identifier 2 (SFF); TWAI Address 0x48 562
21-12 TX/RX Identifier 1 (EFF); TWAI Address 0x44 562
21-13 TX/RX Identifier 2 (EFF); TWAI Address 0x48 562
21-14 TX/RX Identifier 3 (EFF); TWAI Address 0x4c 562
21-15 TX/RX Identifier 4 (EFF); TWAI Address 0x50 562
21-16 Bit Information of TWAI_ERR_CODE_CAP_REG; TWAI Address 0x30 567
21-17 Bit Information of Bits SEG.4 - SEG.0 567
21-18 Bit Information of TWAI_ARB LOST CAP_REG; TWAI Address 0x2c 568
22-1 Operation Mode 583
22-2 AES Text Endianness 584
22-3 AES-128 Key Endianness 585
22-4 AES-192 Key Endianness 585
22-5 AES-256 Key Endianness 585
27-1 MPU and MMU Structure for Internal Memory 612
27-2 MPU for RTC FAST Memory 613
27-3 MPU for RTC SLOW Memory 613

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List of Tables

27-4 Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 614
27-5 Page Boundaries for SRAM0 MMU 615
27-6 Page Boundaries for SRAM2 MMU 615
27-7 DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG 616
27-8 MPU for DMA 617
27-9 Virtual Address for External Memory 619
27-10 MMU Entry Numbers for PRO_CPU 619
27-11 MMU Entry Numbers for APP_CPU 619
27-12 MMU Entry Numbers for PRO_CPU (Special Mode) 620
27-13 MMU Entry Numbers for APP_CPU (Special Mode) 620
27-14 Virtual Address Mode for External SRAM 621
27-15 Virtual Address for External SRAM ( Normal Mode ) 622
27-16 Virtual Address for External SRAM ( Low-High Mode ) 622
27-17 Virtual Address for External SRAM (Even-Odd Mode) 622
27-18 MMU Entry Numbers for External RAM 623
27-19 MPU for Peripheral 624
27-20 DPORT_AHBLITE_MPU_TABLE_X_REG 625
28-1 Interrupt Vector Entry Address 627
28-2 Configuration of PIDCTRL_LEVEL_REG 627
28-3 Configuration of PIDCTRL_FROM_n_REG 628
29-1 ESP32 Capacitive Sensing Touch Pads 638
29-2 Inputs of SAR ADC 643
29-3 ESP32 SAR ADC Controllers 643
29-4 Fields of the Pattern Table Register 645
29-5 Fields of Type I DMA Data Format 646
29-6 Fields of Type II DMA Data Format 646
30-1 ALU Operations Among Registers 667
30-2 ALU Operations with Immediate Value 668
30-3 ALU Operations with Stage Count Register 669
30-4 Input Signals Measured Using the ADC Instruction 673
31-1 RTC Power Domains 696
31-2 Wake-up Source 700

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List of Figures

List of Figures
1-1 System Structure 25
1-2 System Address Mapping 25
1-3 Cache Block Diagram 31
2-1 Interrupt Matrix Structure 35
3-1 System Reset 40
3-2 System Clock 41
4-1 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 49
4-2 Peripheral Input via IO_MUX, GPIO Matrix 50
4-3 Output via GPIO Matrix 52
4-4 ESP32 I/O Pad Power Sources (QFN 6*6, Top View) 55
4-5 ESP32 I/O Pad Power Sources (QFN 5*5, Top View) 56
6-1 DMA Engine Architecture 122
6-2 Linked List Structure 123
6-3 Data Transfer in UDMA Mode 124
6-4 SPI DMA 125
7-1 SPI Architecture 127
7-2 SPI Master and Slave Full-duplex/Half-duplex Communication 128
7-3 SPI Data Buffer 130
7-4 GP-SPI ������ 133
7-5 Parallel QSPI 133
7-6 Communication Format of Parallel QSPI 134
8-1 SDIO Slave Block Diagram 161
8-2 SDIO Bus Packet Transmission 162
8-3 CMD53 Content 162
8-4 SDIO Slave DMA Linked List Structure 163
8-5 SDIO Slave Linked List 163
8-6 Packet Sending Procedure (Initiated by Slave) 164
8-7 Packet Receiving Procedure (Initiated by Host) 165
8-8 Loading Receiving Buffer 166
8-9 Sampling Timing Diagram 166
8-10 Output Timing Diagram 167
9-1 SD/MMC Controller Topology 194
9-2 SD/MMC Controller External Interface Signals 195
9-3 SDIO Host Block Diagram 196
9-4 Command Path State Machine 197
9-5 Data Transmit State Machine 198
9-6 Data Receive State Machine 198
9-7 Descriptor Chain 200
9-8 The Structure of a Linked List 201
9-9 SD/MMC Timing in HS Mode 204
9-10 Clock Phase Selection 205
10-1 Ethernet MAC Functionality Overview 226
10-2 Ethernet Block Diagram 228

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List of Figures

10-3 MII Interface 235

10-4 MII Clock 236
10-5 RMII Interface 237
10-6 RMII Clock 238
10-7 RMII Timing - Receiving Data 238
10-8 RMII Timing – Transmitting Data 239
10-9 Transmit Descriptor 239
10-10 Receive Descriptor 245
11-1 I2C Master Architecture 290
11-2 I2C Slave Architecture 290
11-3 I2C Sequence Chart 291
11-4 Structure of The I2C Command Register 292
11-5 I2C Master Writes to Slave with 7-bit Address 293
11-6 I2C Master Writes to Slave with 10-bit Address 294
11-7 I2C Master Writes to addrM in RAM of Slave with 7-bit Address 295
11-8 Master Writes to Slave with 7-bit Address in Three Segments 296
11-9 Master Reads from Slave with 7-bit Address 297
11-10 Master Reads from Slave with 10-bit Address 298
11-11 Master Reads N Bytes of Data from addrM in Slave with 7-bit Address 298
11-12 Master Reads from Slave with 7-bit Address in Three Segments 299
12-1 I2S System Block Diagram 313
12-2 I2S Clock 315
12-3 Philips Standard 316
12-4 MSB Alignment Standard 317
12-5 PCM Standard 317
12-6 Tx FIFO Data Mode 318
12-7 The First Stage of Receiving Data 320
12-8 Modes of Writing Received Data into FIFO 320
12-9 PDM Transmitting Module 322
12-10 PDM Sends Signal 323
12-11 PDM Receives Signal 323
12-12 PDM Receive Module 323
12-13 LCD Master Transmitting Mode 324
12-14 LCD Master Transmitting Data Frame, Form 1 324
12-15 LCD Master Transmitting Data Frame, Form 2 324
12-16 Camera Slave Receiving Mode 325
12-17 ADC Interface of I2S0 325
12-18 DAC Interface of I2S 326
12-19 Data Input by I2S DAC Interface 326
13-1 UART Basic Structure 348
13-2 UART Shared RAM 349
13-3 UART Data Frame Structure 350
13-4 AT_CMD Character Format 351
13-5 Hardware Flow Control 352
14-1 LED_PWM Architecture 390
14-2 LED_PWM High-speed Channel Diagram 390

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List of Figures

14-3 LED_PWM Divider 391

14-4 LED PWM Output Signal Diagram 392
14-5 Output Signal Diagram of Fading Duty Cycle 393
15-1 RMT Architecture 408
15-2 Data Structure 409
16-1 MCPWM Module Overview 417
16-2 Prescaler Submodule 419
16-3 Timer Submodule 419
16-4 Operator Submodule 420
16-5 Fault Detection Submodule 422
16-6 Capture Submodule 422
16-7 Count-Up Mode Waveform 423
16-8 Count-Down Mode Waveforms 424
16-9 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 424
16-10 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 424
16-11 UTEP and UTEZ Generation in Count-Up Mode 425
16-12 DTEP and DTEZ Generation in Count-Down Mode 426
16-13 DTEP and UTEZ Generation in Count-Up-Down Mode 426
16-14 Submodules Inside the PWM Operator 429
16-15 Symmetrical Waveform in Count-Up-Down Mode 433
16-16 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High 434
16-17 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 435
16-18 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Active High 436
16-19 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Complementary 437
16-20 Example of an NCI Software-Force Event on PWMxA 438
16-21 Example of a CNTU Software-Force Event on PWMxB 439
16-22 Options for Setting up the Dead Time Generator Submodule 441
16-23 Active High Complementary (AHC) Dead Time Waveforms 442
16-24 Active Low Complementary (ALC) Dead Time Waveforms 443
16-25 Active High (AH) Dead Time Waveforms 443
16-26 Active Low (AL) Dead Time Waveforms 444
16-27 Example of Waveforms Showing PWM Carrier Action 446
16-28 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule447
16-29 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 448
17-1 PULSE_CNT Architecture 501
17-2 PULSE_CNT Upcounting Diagram 503
17-3 PULSE_CNT Downcounting Diagram 503
21-1 The bit fields of Data Frames and Remote Frames 547
21-2 Various Fields of an Error Frame 549
21-3 The Bit Fields of an Overload Frame 550
21-4 The Fields within an Interframe Space 551
21-5 Layout of a Bit 555
21-6 TWAI Overview Diagram 555

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List of Figures

21-7 Acceptance Filter 563

21-8 Single Filter Mode 564
21-9 Dual Filter Mode 565
21-10 Error State Transition 566
21-11 Positions of Arbitration Lost Bits 570
25-1 Noise Source 604
26-1 Flash Encryption/Decryption Module Architecture 606
27-1 MMU Access Example 614
28-1 Interrupt Nesting 629
29-1 Touch Sensor 637
29-2 Touch Sensor Structure 638
29-3 Touch Sensor Operating Flow 639
29-4 Touch FSM Structure 640
29-5 SAR ADC Depiction 641
29-6 SAR ADC Outline of Function 642
29-7 RTC SAR ADC Outline of Function 644
29-8 Diagram of DIG SAR ADC Controllers 645
29-9 Diagram of DAC Function 647
29-10 Cosine Waveform (CW) Generator 648
30-1 ULP Coprocessor Diagram 665
30-2 The ULP Coprocessor Instruction Format 666
30-3 Instruction Type — ALU for Operations Among Registers 667
30-4 Instruction Type — ALU for Operations with Immediate Value 668
30-5 Instruction Type — ALU for Operations with Stage Count Register 668
30-6 Instruction Type — ST 669
30-7 Instruction Type — LD 669
30-8 Instruction Type — JUMP 670
30-9 Instruction Type — JUMPR 670
30-10 Instruction Type — JUMP 671
30-11 Instruction Type — HALT 671
30-12 Instruction Type — WAKE 672
30-13 Instruction Type — SLEEP 672
30-14 Instruction Type — WAIT 672
30-15 Instruction Type — ADC 672
30-16 Instruction Type — I²C 673
30-17 Instruction Type — REG_RD 674
30-18 Instruction Type — REG_WR 674
30-19 Control of ULP Program Execution 675
30-20 Sample of a ULP Operation Sequence 676
30-21 I²C Read Operation 678
30-22 I²C Write Operation 678
31-1 ESP32 Power Control 690
31-2 Digital Core Voltage Regulator 691
31-3 Low-Power Voltage Regulator 692
31-4 Flash Voltage Regulator 693
31-5 Brownout Detector 693

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List of Figures

31-6 RTC Structure 694

31-7 RTC Low-Power Clocks 695
31-8 Digital Low-Power Clocks 696
31-9 RTC States 696
31-10 Power Modes 698
31-11 ESP32 Boot Flow 702

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1 System and Memory

1 System and Memory

1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.

With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they
use the same addresses to access the same memory. Multiple peripherals in the system can access embedded
memory via DMA.

The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most
purposes the two CPUs are interchangeable.

1.2 Features
• Address Space

– Symmetric address mapping

– 4 GB (32-bit) address space for both data bus and instruction bus

– 1296 KB embedded memory address space

– 19704 KB external memory address space

– 512 KB peripheral address space

– Some embedded and external memory regions can be accessed by either data bus or instruction
bus

– 328 KB DMA address space

• Embedded Memory

– 448 KB Internal ROM

– 520 KB Internal SRAM

– 8 KB RTC FAST Memory

– 8 KB RTC SLOW Memory

• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.

– Supports up to 16 MB off-Chip SPI Flash.

– Supports up to 8 MB off-Chip SPI SRAM.

• Peripherals

– 41 peripherals

• DMA

– 13 modules are capable of DMA operation

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The block diagram in Figure 1-1 illustrates the system structure, and the block diagram in Figure 1-2 illustrates the
address map structure.

Figure 1-1. System Structure

Figure 1-2. System Address Mapping

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1.3 Functional Description

1.3.1 Address Mapping
Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are
symmetric between the two CPUs.

Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.

The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and the most significant bytes of the
32-bit word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or
non-aligned byte, half-word and word read-and-write operations. The CPU can read and write data through the
instruction bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.

Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1-1
illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.

Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.

Table 1-1. Address Mapping

Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Mem-
ory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Mem-
ory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
Data / Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Mem-
ory
0x5000_2000 0xFFFF_FFFF Reserved

1.3.2 Embedded Memory

The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST
memory (8 KB) and RTC SLOW memory (8 KB).

The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The 520
KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and Internal
SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.

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Table 1-2 lists all embedded memories and their address ranges on the data and instruction buses.

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Table 1-2. Embedded Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data Instruc-
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
tion

1.3.2.1 Internal ROM 0

The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range 0x4000_0000
~ 0x4005_FFFF, which is on the instruction bus.

The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order
to access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF
any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done
on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or DPORT_APP_BOOT_REMAP_CTRL_REG
will remap SRAM for the PRO_CPU and APP_CPU, respectively.

1.3.2.2 Internal ROM 1

The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.

1.3.2.3 Internal SRAM 0

The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses

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0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.

1.3.2.4 Internal SRAM 1

The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses 0x3FFE_0000
~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the instruction
bus.

The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the
data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word

The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is
not reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.

Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more informa-
tion.

1.3.2.5 Internal SRAM 2

The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.

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1.3.2.6 DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1
and an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.

In the ESP32, 13 peripherals are equipped with DMA. Table 1-3 lists these peripherals.

Table 1-3. Module with DMA

UART0 UART1 UART2

SPI1 SPI2 SPI3
I2S0 I2S1
SDIO Slave SDMMC
EMAC
BT WIFI

1.3.2.7 RTC FAST Memory

RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF
on the instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.

The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.

1.3.2.8 RTC SLOW Memory

RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.

1.3.3 External Memory

The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 1-4 provides a list of external
memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When
a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an
external physical memory address (in the external memory’s address space), according to the MMU settings.
Due to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.

Table 1-4. External Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write
Boundary Address
Bus Type Size Target Comment
Low Address High Address

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Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read

1.3.4 Cache
As shown in Figure 1-3, each of the two CPUs in ESP32 has 32 KB of cache featuring a block size of 32 bytes for
accessing external storage. PRO CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG
to enable the Cache, while APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG
to enable the same function.

Figure 1-3. Cache Block Diagram

ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or APP
CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select POOL0 or
POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the Cache function,
POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory, while they can also
be used by the instruction bus. This is depicted in table 1-5 below.

Table 1-5. Cache memory mode

CACHE_MUX_MODE POOL0 POOL1

0 PRO CPU APP CPU
1 PRO CPU/APP CPU -
2 - PRO CPU/APP CPU
3 APP CPU PRO CPU

As described in table 1-5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable
the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used
as the cache memory, and cannot be used by the instruction bus as well.

ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.

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Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be ”PRO” or ”APP”,
indicating that the cache flush operation has been completed.

For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and
External Memory.

1.3.5 Peripherals
The ESP32 has 41 peripherals. Table 1-6 specifically describes the peripherals and their respective address
ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single
exception; this being the PID Controller.

Table 1-6. Peripheral Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts

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1 System and Memory

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB eFuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB MCPWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
Data 0x3FF6_B000 0x3FF6_BFFF 4KB TWAI
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB MCPWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB Reserved
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB Reserved
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved

Notice:

• Peripherals accessed by the CPU via 0x3FF40000 ~ 0x3FF7FFFF address space (DPORT address) can
also be accessed via 0x60000000 ~ 0x6003FFFF (AHB address). (0x3FF40000 + n) address and
(0x60000000 + n) address access the same content, where n = 0 ~ 0x3FFFF.

• The CPU can access peripherals via DPORT address more efficiently than via AHB address. However,
DPORT address is characterized by speculative reads, which means it cannot guarantee that each read
is valid. In addition, DPORT address will upset the order of r/w operations on the bus to improve perfor-
mance, which may cause programs that have strict requirements on the r/w order to crash. On the other
hand, using AHB address to read FIFO registers will cause unpredictable errors. To address above issues
please strictly follow the instructions documented in ESP32 ECO and Workarounds for Bugs, specifically
sections 3.3, 3.10, 3.16, and 3.17.

1.3.5.1 Asymmetric PID Controller Peripheral

There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart. Each
CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.

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1 System and Memory

1.3.5.2 Non-Contiguous Peripheral Memory Ranges

The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.

1.3.5.3 Memory Speed

The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single cycle.
The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the FAST_CLOCK, so
access to these memories may be slower. DMA uses the APB_CLK to access memory.

Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.

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2 Interrupt Matrix (INTERRUPT)

2.1 Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different
needs.
2.2 Features
• Accepts 71 peripheral interrupt sources as input.

• Generates 26 peripheral interrupt sources per CPU as output (52 total).

• CPU NMI Interrupt Mask.

• Queries current interrupt status of peripheral interrupt sources.

The structure of the Interrupt Matrix is shown in Figure 2-1.

Figure 2-1. Interrupt Matrix Structure

2.3 Functional Description

2.3.1 Peripheral Interrupt Source
ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 2-1. 67 of 71
ESP32 peripheral interrupt sources can be allocated to either CPU.

The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and GPIO_INTERRUPT
_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each have 69 peripheral
interrupt sources.

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 Table 2-1. PRO_CPU, APP_CPU Interrupt Configuration
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2 Interrupt Matrix (INTERRUPT)

PRO_CPU APP_CPU
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
DPORT_PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 DPORT_APP_MAC_INTR_MAP_REG
DPORT_PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 DPORT_APP_MAC_NMI_MAP_REG
DPORT_PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 DPORT_APP_BB_INT_MAP_REG
DPORT_PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 DPORT_APP_BT_MAC_INT_MAP_REG
DPORT_PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 DPORT_APP_BT_BB_INT_MAP_REG
DPORT_PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 DPORT_APP_BT_BB_NMI_MAP_REG
DPORT_PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 DPORT_APP_RWBT_IRQ_MAP_REG
DPORT_PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 DPORT_APP_RWBLE_IRQ_MAP_REG
DPORT_PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 DPORT_APP_RWBT_NMI_MAP_REG
DPORT_PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 DPORT_APP_RWBLE_NMI_MAP_REG
DPORT_PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 DPORT_APP_SLC0_INTR_MAP_REG
DPORT_PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 DPORT_APP_SLC1_INTR_MAP_REG
DPORT_PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 DPORT_APP_UHCI0_INTR_MAP_REG
DPORT_PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 DPORT_APP_UHCI1_INTR_MAP_REG
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 DPORT_APP_TG_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 DPORT_APP_TG_T1_LEVEL_INT_MAP_REG
DPORT_PRO_INTR_STATUS_REG_0_REG DPORT_APP_INTR_STATUS_REG_0_REG
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DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG

DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_MAP_REG 22 22 GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP 22 22 DPORT_APP_GPIO_INTERRUPT_MAP_REG
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG 23 23 GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI 23 23 DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG
36

DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG

DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG
DPORT_PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 DPORT_APP_SPI_INTR_0_MAP_REG
DPORT_PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 DPORT_APP_SPI_INTR_1_MAP_REG
DPORT_PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 DPORT_APP_SPI_INTR_2_MAP_REG
DPORT_PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 DPORT_APP_SPI_INTR_3_MAP_REG
DPORT_PRO_I2S0_INT_MAP_REG 0 32 I2S0_INT 32 0 DPORT_APP_I2S0_INT_MAP_REG
DPORT_PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 DPORT_APP_I2S1_INT_MAP_REG
DPORT_PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 DPORT_APP_UART_INTR_MAP_REG
DPORT_PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 DPORT_APP_UART1_INTR_MAP_REG
DPORT_PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 DPORT_APP_UART2_INTR_MAP_REG
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG
DPORT_PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 DPORT_APP_EMAC_INT_MAP_REG
DPORT_PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 DPORT_APP_PWM0_INTR_MAP_REG
DPORT_PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 DPORT_APP_PWM1_INTR_MAP_REG
ESP32 TRM (Version 5.2)

Reserved 9 41 Reserved 41 9 Reserved

Reserved 10 DPORT_PRO_INTR_STATUS_REG_1_REG 42 Reserved 42 DPORT_APP_INTR_STATUS_REG_1_REG 10 Reserved
DPORT_PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 DPORT_APP_LEDC_INT_MAP_REG
DPORT_PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 DPORT_APP_EFUSE_INT_MAP_REG
DPORT_PRO_TWAI_INT_MAP_REG 13 45 TWAI_INT 45 13 DPORT_APP_TWAI_INT_MAP_REG
DPORT_PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 DPORT_APP_RTC_CORE_INTR_MAP_REG
DPORT_PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 DPORT_APP_RMT_INTR_MAP_REG
DPORT_PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 DPORT_APP_PCNT_INTR_MAP_REG
DPORT_PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 DPORT_APP_I2C_EXT0_INTR_MAP_REG
DPORT_PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 DPORT_APP_I2C_EXT1_INTR_MAP_REG
DPORT_PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 DPORT_APP_RSA_INTR_MAP_REG
DPORT_PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 DPORT_APP_SPI1_DMA_INT_MAP_REG
 Espressif Systems

2 Interrupt Matrix (INTERRUPT)

PRO_CPU APP_CPU
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
DPORT_PRO_SPI2_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 DPORT_APP_SPI2_DMA_INT_MAP_REG
DPORT_PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 DPORT_APP_SPI3_DMA_INT_MAP_REG
DPORT_PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 DPORT_APP_WDG_INT_MAP_REG
DPORT_PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 DPORT_APP_TIMER_INT1_MAP_REG
DPORT_PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 DPORT_APP_TIMER_INT2_MAP_REG
DPORT_PRO_TG_T0_EDGE_INT_MAP_REG 26 DPORT_PRO_INTR_STATUS_REG_1_REG 58 TG_T0_EDGE_INT 58 DPORT_APP_INTR_STATUS_REG_1_REG 26 DPORT_APP_TG_T0_EDGE_INT_MAP_REG
DPORT_PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 DPORT_APP_TG_T1_EDGE_INT_MAP_REG
DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 DPORT_APP_TG_WDT_EDGE_INT_MAP_REG
DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 DPORT_APP_TG_LACT_EDGE_INT_MAP_REG
DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 DPORT_APP_TG1_T0_EDGE_INT_MAP_REG
DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 DPORT_APP_TG1_T1_EDGE_INT_MAP_REG
DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG 0 64 TG1_WDT_EDGE_INT 64 0 DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG
DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG
DPORT_PRO_MMU_IA_INT_MAP_REG 2 DPORT_PRO_INTR_STATUS_REG_2_REG 66 MMU_IA_INT 66 DPORT_APP_INTR_STATUS_REG_2_REG 2 DPORT_APP_MMU_IA_INT_MAP_REG
DPORT_PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 DPORT_APP_MPU_IA_INT_MAP_REG
DPORT_PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 DPORT_APP_CACHE_IA_INT_MAP_REG
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2 Interrupt Matrix (INTERRUPT)

2.3.2 CPU Interrupt

Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All interrupts
in a CPU are listed in Table 2-2.

Table 2-2. CPU Interrupts

No. Category Type Priority Level

0 Peripheral Level-Triggered 1
1 Peripheral Level-Triggered 1
2 Peripheral Level-Triggered 1
3 Peripheral Level-Triggered 1
4 Peripheral Level-Triggered 1
5 Peripheral Level-Triggered 1
6 Internal Timer.0 1
7 Internal Software 1
8 Peripheral Level-Triggered 1
9 Peripheral Level-Triggered 1
10 Peripheral Edge-Triggered 1
11 Internal Profiling 3
12 Peripheral Level-Triggered 1
13 Peripheral Level-Triggered 1
14 Peripheral NMI NMI
15 Internal Timer.1 3
16 Internal Timer.2 5
17 Peripheral Level-Triggered 1
18 Peripheral Level-Triggered 1
19 Peripheral Level-Triggered 2
20 Peripheral Level-Triggered 2
21 Peripheral Level-Triggered 2
22 Peripheral Edge-Triggered 3
23 Peripheral Level-Triggered 3
24 Peripheral Level-Triggered 4
25 Peripheral Level-Triggered 4
26 Peripheral Level-Triggered 5
27 Peripheral Level-Triggered 3
28 Peripheral Edge-Triggered 4
29 Internal Software 3
30 Peripheral Edge-Triggered 4
31 Peripheral Level-Triggered 5

2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU

In this section:

• Source_X stands for any particular peripheral interrupt source.

• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration reg-

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ister of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. In Table 2-1 the registers listed under “PRO_CPU (APP_CPU) - Pe-
ripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in “Peripheral
Interrupt Source - Name”.

• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5,
8 ~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.

• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15, 16,
29.

Using this terminology, the possible operations of the Interrupt Matrix controller can be described as fol-
lows:

• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG (or APP_X_MAP_REG) to Num_P. Num_P can be any CPU peripheral interrupt num-
ber. CPU interrupts can be shared between multiple peripherals (see below).

• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG (or APP_X _MAP_REG) for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I is connected to either CPU.

• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral inter-
rupts will trigger CPU Interrupt_P.

2.3.4 CPU NMI Interrupt Mask

The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s )
NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the
peripheral PID Controller, respectively.

2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source

The current interrupt status of a peripheral interrupt source can be read via the bit value in PRO_INTR_STATUS_REG_n
(APP_INTR_STATUS_REG_n), as shown in the mapping in Table 2-1.

2.4 Registers
The interrupt matrix registers are part of the DPORT registers and are described in Section 5.4 in Chapter 5 DPort
Registers.

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3 Reset and Clock

3.1 System Reset

3.1.1 Introduction
The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear
the RAM. Figure 3-1 shows the subsystems included in each reset level.

Figure 3-1. System Reset

• CPU reset: Only resets the registers of one or both of the CPU cores.

• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC
is not reset.

• System reset: Resets all the registers on the chip, including those of the RTC.

3.1.2 Reset Source

While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to
reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU
reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in
RTC_CNTL_RESET_CAUSE_APPCPU. Table 3-1 shows the possible reset reason values that can be read from
these registers.

Table 3-1. PRO_CPU and APP_CPU Reset Reason Values

PRO APP Source Reset Type Note

0x01 0x01 Chip Power On Reset System Reset -
0x10 0x10 RWDT System Reset System Reset See WDT Chapter.
0x0F 0x0F Brown Out Reset System Reset See Power Management Chapter.
0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register.
0x05 0x05 Deep Sleep Reset Core Reset See Power Management Chapter.
0x06 0x06 SDIO Reset Core Reset Reserved

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PRO APP APP Source Reset Type Note

0x07 0x07 MWDT0 Global Reset Core Reset See WDT Chapter.
0x08 0x08 MWDT1 Global Reset Core Reset See WDT Chapter.
0x09 0x09 RWDT Core Reset Core Reset See WDT Chapter.
0x0B - MWDT0 CPU Reset CPU Reset See WDT Chapter.
0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
- 0x0B MWDT1 CPU Reset CPU Reset See WDT Chapter.
- 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
0x0D 0x0D RWDT CPU Reset CPU Reset See WDT Chapter.
Indicates that the PRO CPU has independently
- 0xE PRO CPU Reset CPU Reset reset the APP CPU by configuring the
DPORT_APPCPU_RESETTING register.

3.2 System Clock

3.2.1 Introduction
The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can
be configured to meet different requirements. Figure 3-2 shows the system clock structure.

Figure 3-2. System Clock

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3.2.2 Clock Source

The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:

• High Speed Clocks

– PLL_CLK is an internal PLL clock with a frequency of 320 MHz or 480 MHz.

– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.

• Low Power Clocks

– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.

– RC_FAST_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.

– RC_FAST_DIV_CLK is divided from RC_FAST_CLK. Its frequency is (RC_FAST_CLK / 256). With the
default RC_FAST_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.

– RC_SLOW_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.

• Audio Clock

– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.

3.2.3 CPU Clock

As Figure 3-2 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 240
MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce
power consumption.

The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RC_FAST_CLK, and XTL_CLK can be set as the CPU_CLK source; see Table 3-2 and 3-3.

Table 3-2. CPU_CLK Source

RTC_CNTL_SOC_CLK_SEL Value Clock Source

0 XTL_CLK
1 PLL_CLK
2 RC_FAST_CLK
3 APLL_CLK

Table 3-3. CPU_CLK Derivation

Clock Source *SEL_0 *SEL_1 CPU Clock Frequency

XTL_CLK 0 - CPU_CLK = XTL_CLK / (SYSCON_PRE_DIV_CNT+1)
CPU_CLK = PLL_CLK / 4
PLL_CLK (320 MHz) 1 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
PLL_CLK (320 MHz) 1 1
CPU_CLK frequency is 160 MHz
CPU_CLK = PLL_CLK / 2
PLL_CLK (480 MHz) 1 2
CPU_CLK frequency is 240 MHz
RC_FAST_CLK 2 - CPU_CLK = RC_FAST_CLK / (SYSCON_PRE_DIV_CNT+1)
APLL_CLK 3 0 CPU_CLK = APLL_CLK / 4

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APLL_CLK 3 1 CPU_CLK = APLL_CLK / 2

*SEL_0: The value of register RTC_CNTL_SOC_CLK_SEL

*SEL_1: The value of register CPU_CPUPERIOD_SEL

3.2.4 Peripheral Clock

Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK, and PLL_F160M_CLK.
Table 3-4 shows which clocks can be used by which peripherals.

Table 3-4. Peripheral Clock Usage

Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_F160M_CLK

EMAC Y N N Y N
TIMG Y N N N N
I2S Y N N Y Y
UART Y Y N N N
RMT Y Y N N N
LED PWM Y Y Y N N
PWM Y N N N Y
I2C Y N N N N
SPI Y N N N N
PCNT Y N N N N
eFuse Controller Y N N N N
SDIO Slave Y N N N N
SDMMC Y N N N N

3.2.4.1 APB_CLK
The APB_CLK frequency is determined by CPU_CLK source, as detailed in Table 3-5.

Table 3-5. APB_CLK

CPU_CLK Source APB_CLK Frequency

PLL_CLK 80 MHz
APLL_CLK CPU_CLK / 2
XTL_CLK CPU_CLK
RC_FAST_CLK CPU_CLK

3.2.4.2 REF_TICK
REF_TICK is derived from APB_CLK. The APB_CLK frequency is determined by CPU_CLK source. The REF_TICK
frequency should be fixed. When CPU_CLK source changes, users need to make sure the REF_TICK frequency
remains unchanged by setting a correct divider value.

Clock divider registers are shown in Table 3-6.

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Table 3-6. REF_TICK

CPU_CLK Source APB_CLK Frequency REF_TICK Frequency

PLL_CLK 80 MHz APB_CLK / (SYSCON_PLL_TICK_NUM+1)
APLL_CLK CPU_CLK / 2 APB_CLK / (SYSCON_APLL_TICK_NUM+1)
XTL_CLK CPU_CLK APB_CLK / (SYSCON_XTAL_TICK_NUM+1)
FOSC_CLK CPU_CLK APB_CLK / (SYSCON_CK8M_TICK_NUM+1)

For example, when CPU_CLK source is PLL_CLK and users need to keep the REF_TICK frequency at 1 MHz,
then they should set SYSCON_PLL_TICK_NUM to 79 (0x4F) so that the REF_TICK frequency = 80 MHz / (79+1)
= 1 MHz.

3.2.4.3 LEDC_SCLK Source

The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 3-7.

Table 3-7. LEDC_SCLK Derivation

LEDC_APB_CLK_SEL Value LEDC_SCLK Source

0 RC_FAST_CLK
1 APB_CLK

3.2.4.4 APLL_SCLK Source

The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.

3.2.4.5 PLL_F160M_CLK Source

PLL_F160M_CLK is divided from PLL_CLK by automatically adjusting the clock division and its frequency is
always 160 MHz.

3.2.4.6 Clock Source Considerations

Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change. Pe-
ripherals accessing REF_TICK can continue operating normally when switching clock sources, without changing
clock source. Please see Table 3-4 for details.

The LED PWM module can use RC_FAST_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see Power Management Chapter), normal peripherals will
be halted (APB_CLK is turned off), but the LED PWM can work normally via RC_FAST_CLK.

3.2.5 Wi-Fi BT Clock

Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low-power consumption mode first.

For LOW_POWER_CLK, one of RC_SLOW_CLK, RTC_SLOW_CLK, RC_FAST_CLK or XTL_CLK can be selected as

the low-power consumption mode clock source for Wi-Fi and BT.

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3.2.6 RTC Clock

The clock sources of RTC_SLOW_CLK and RTC_FAST_CLK are low-frequency clocks. The RTC module can
operate when most other clocks are stopped.

RTC_SLOW_CLK is used to clock the Power Management module. It can be sourced from RC_SLOW_CLK,
XTL32K_CLK or RC_FAST_DIV_CLK.

RTC_FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RC_FAST_CLK.

3.2.7 Audio PLL

The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter,
and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may
carry jitter and, therefore, they do not support a high-precision clock frequency setting.

Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an
audio PLL. The Audio PLL formula is as follows:

fxtal (sdm2 + sdm1

28
+ sdm0
216
+ 4)
fout =
2(odiv + 2)

The parameters of this formula are defined below:

• fxtal : the frequency of the crystal oscillator, usually 40 MHz;

• sdm0: the value is 0 ~ 255;

• sdm1: the value is 0 ~ 255;

• sdm2: the value is 0 ~ 63;

• odiv: the value is 0 ~ 31;

The operating frequency range of the numerator is 350 MHz ~ 500 MHz:

sdm1 sdm0
350M Hz < fxtal (sdm2 + + + 4) < 500M Hz
28 216

Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ECO and Workarounds for Bugs in ESP32 for further details.

Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA
_FORCE_PD, respectively. Disabling it takes priority over enabling it. When RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system, i.e., when the system enters sleep
mode, PLL will be disabled automatically; when the system wakes up, PLL will be enabled automatically.

3.3 Register Summary

The addresses in this section are relative to the SYSCON base address provided in Table 1-6 Peripheral Address
Mapping in Chapter 1 System and Memory.

Name Description Address Access

Configuration register
SYSCON_SYSCLK_CONF_REG Configures system clock frequency 0x0000 R/W
SYSCON_XTAL_TICK_CONF_REG Configures the divider value of REF_TICK 0x0004 R/W

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Name Description Address Access

SYSCON_PLL_TICK_CONF_REG Configures the divider value of REF_TICK 0x0008 R/W
SYSCON_CK8M_TICK_CONF_REG Configures the divider value of REF_TICK 0x000C R/W
SYSCON_APLL_TICK_CONF_REG Configures the divider value of REF_TICK 0x003C R/W
Chip revision register
SYSCON_DATE_REG Chip revision register 0x007C R/W

3.4 Registers
The addresses in this section are relative to the SYSCON base address provided in Table 1-6 Peripheral Address
Mapping in Chapter 1 System and Memory.

Register 3.1. SYSCON_SYSCLK_CONF_REG (0x0000)

T
CN
IV_
_D
RE
_P
)
ed

ON
rv

SC
se
(re

SY
31 10 9 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset

SYSCON_PRE_DIV_CNT Configures the divider value of CPU_CLK when the source of CPU_CLK
is XTL_CLK or RC_FAST_CLK. The value range is 0x0 ~ 0x3FF. CPU_CLK = XTL_CLK ( or
RC_FAST_CLK) / (the value of this field +1). (R/W)

Register 3.2. SYSCON_XTAL_TICK_CONF_REG (0x0004)

M
NU
K_
IC
_T
L
TA
_X
)
ed

ON
rv

SC
se
(re

SY

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 Reset

SYSCON_XTAL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is XTL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

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Register 3.3. SYSCON_PLL_TICK_CONF_REG (0x0008)

M
NU
K_
IC
_T
LL
_P
d)
ve

ON
r

SC
se
(re

SY
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 Reset

SYSCON_PLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is PLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

Register 3.4. SYSCON_CK8M_TICK_CONF_REG (0x000C)

UM
_N
ICK
_T
K8M
_C
)
ed

ON
rv

SC
se
(re

SY
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 Reset

SYSCON_CK8M_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is FOSC_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

Register 3.5. SYSCON_APLL_TICK_CONF_REG (0x003C)

UM
_N
ICK
_T
L
PL
_A
)
ed

ON
rv

SC
se
(re

SY

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 Reset

SYSCON_APLL_TICK_NUM Configures the divider value of REF_TICK when the source of APB_CLK
is APLL_CLK. The value range is 0x0 ~ 0xFF. REF_TICK = APB_CLK /(the value of this field + 1).
(R/W)

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Register 3.6. SYSCON_DATE_REG (0x007C)

E
AT
_D
ON
SC
SY
31 0

0x16042000 Reset

SYSCON_DATE Chip revision register. For more information see ESP32 Series SoC Errata. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

4.1 Overview
The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible
for routing signals from the peripherals to GPIO pads. Together these systems provide highly configurable
I/O.

Note that the I/O GPIO pads are 0-19, 21-23, 25-27, 32-39, while the output GPIOs are 0-19, 21-23, 25-27,
32-33. GPIO pads 34-39 are input-only.

GPIO 20 serves as a valid input and output only on ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to
ESP32-PICO Series Datasheet for more information.

This chapter describes the signal selection and connection between the digital pads (FUN_SEL, IE, OE, WPU,
WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE,
etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO_MUX.

Figure 4-1. IO_MUX, RTC IO_MUX and GPIO Matrix Overview

1. The IO_MUX contains one register per GPIO pad. Each pad can be configured to perform a ”GPIO” function
(when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed
digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency
digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral.)

See Section 4.10 for a list of IO_MUX functions for each I/O pad.

2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads.

• For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pad as the input
source.

• For output from the chip: The output signal of each of the 34 GPIO pads can be from one of the 176

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peripheral output signals.

See Section 4.9 for a list of GPIO Matrix peripheral signals.

3. RTC IO_MUX is used to connect GPIO pads to their low-power and analog functions. Only a subset of
GPIO pads have these optional ”RTC” functions.

See Section 4.11 for a list of RTC IO_MUX functions.

4.2 Peripheral Input via GPIO Matrix

4.2.1 Summary
To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral
signal’s input index (0-18, 23-36, 39-58, 61-90, 95-124, 140-155, 164-181, 190-195, 198-206) from one of the 34
GPIOs (0-19, 21-23, 25-27, 32-39).

The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the
chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix, which
in turn routes it to the selected peripheral input.

4.2.2 Functional Description

Figure 4-2 shows the logic for input selection via GPIO Matrix.

Figure 4-2. Peripheral Input via IO_MUX, GPIO Matrix

To read GPIO pad X into peripheral signal Y, follow the steps below:

1. Configure the GPIO_FUNCy_IN_SEL_CFG register corresponding to peripheral signal Y in the GPIO Matrix:

• Set GPIO_SIGy_IN_SEL to enable peripheral signal input via GPIO matrix.

• Set the GPIO_FUNCy_IN_SEL field in this register, corresponding to the GPIO pad X to read from.

2. Configure the GPIO_FUNCx_OUT_SEL_CFG register and clear the GPIO_ENABLE_DATA[x] field correspond-
ing to GPIO pad X in the GPIO Matrix:

• Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s
output state to be determined always by the GPIO_ENABLE_DATA[x] field.

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• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or GPIO_ENABLE1_REG

(GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.

3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:

• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
2—numeric value 2—for all pins).

• Enable the input by setting the FUN_IE bit.

• Set or clear the FUN_WPU and FUN_WPD bits, as desired, to enable/disable internal pull-up/pull-
down resistors.

Notes:

• One input pad can be connected to multiple input_signals.

• The input signal can be inverted with GPIO_FUNCy_IN_INV_SEL.

• It is possible to have a peripheral read a constantly low or constantly high input value without connecting
this input to a pad. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO
number:

– When GPIO_FUNCy_IN_SEL is 0x30, input_signal_x is always 0.

– When GPIO_FUNCy_IN_SEL is 0x38, input_signal_x is always 1.

For example, to connect RMT peripheral channel 0 input signal (RMT_SIG_IN0_IDX, signal index 83) to GPIO 15,
please follow the steps below. Note that GPIO 15 is also named the MTDO pin:

1. Set the GPIO_FUNC83_IN_SEL_CFG register field GPIO_FUNC83_IN_SEL value to 15.

2. As this is an input-only signal, set GPIO_FUNC15_OEN_SEL bit in GPIO_FUNC15_OUT_SEL_CFG_REG.

3. Clear bit 15 of GPIO_ENABLE_REG (field GPIO_ENABLE_DATA[15]).

4. Set the IO_MUX_GPIO15 register MCU_SEL field to 2 (GPIO function) and also set the FUN_IE bit (input
mode).

4.2.3 Simple GPIO Input

The GPIO_IN_REG/GPIO_IN1_REG register holds the input values of each GPIO pad.

The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular
peripheral signal. However, it is necessary to enable the input in the IO_MUX by setting the FUN_IE bit in the
IO_MUX_x_REG register corresponding to pad X, as mentioned in Section 4.2.2.
4.3 Peripheral Output via GPIO Matrix
4.3.1 Summary
To output a signal from a peripheral via the GPIO Matrix, the GPIO Matrix is configured to route the peripheral
output signal (0-18, 23-37, 61-121, 140-125, 224-228) to one of the 28 GPIOs (0-19, 21-23, 25-27, 32-33).

The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is
configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to
the pad.

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Note:
The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from
another GPIO.

4.3.2 Functional Description

One of the 176 output signals can be selected to go through the GPIO matrix into the IO_MUX and then to a
pad. Figure 4-3 illustrates the configuration.

In GPIO matrix In IO MUX

GPIO_FUNCx_OUT_SEL

signal0_out 0 MCU_SEL
signal1_out 1
signal2_out 2
signal3_out 3

0 (FUNC)
1 (FUNC)
GPIO X out I/O Pad x
2 (GPIO)
GPIOx_out
signal228_out 228

FUN_OE = 1
GPIO_OUT_DATA bit x 256 (0x100)
256sdfsdfasdfgas

Figure 4-3. Output via GPIO Matrix

To output peripheral signal Y to particular GPIO pad X, follow these steps:

1. Configure the GPIO_FUNCx_OUT_SEL_CFG register and GPIO_ENABLE_DATA[x] field corresponding to

GPIO X in the GPIO Matrix:

• Set the GPIO_FUNCx_OUT_SEL field in GPIO_FUNCx_OUT_SEL_CFG to the numeric index (Y) of de-
sired peripheral output signal Y.

• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in the
GPIO_FUN
Cx_OUT_SEL_CFG register and the GPIO_ENABLE_DATA[x] field in the GPIO_ENABLE_REG register
corresponding to GPIO pad X. To have the output enable signal decided by internal logic, clear the
GPIO_FUNCx_OEN_SEL bit instead.

• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or GPIO_ENABLE1

_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.

2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register corresponding to
GPIO pad X. For push/pull mode (default), clear this bit.

3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:

• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
2—numeric value 2—for all pins).

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• Set the FUN_DRV field to the desired value for output strength (0-3). The higher the drive strength,
the more current can be sourced/sunk from the pin.

• If using open drain mode, set/clear the FUN_WPU and FUN_WPD bits to enable/disable the internal
pull-up/down resistors.

Notes:

• The output signal from a single peripheral can be sent to multiple pads simultaneously.

• Only the 28 GPIOs can be used as outputs.

• The output signal can be inverted by setting the GPIO_FUNCx_OUT_INV_SEL bit.

4.3.3 Simple GPIO Output

The GPIO Matrix can also be used for simple GPIO output – setting a bit in the GPIO_OUT_DATA register will write
to the corresponding GPIO pad.

To configure a pad as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a
special peripheral index value (0x100).

4.4 Direct I/O via IO_MUX

4.4.1 Summary
Some high speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better
high-frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the
peripheral.

Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can
only select from a limited number of functions. However, better high-frequency digital performance will be
maintained.

4.4.2 Functional Description

Two registers must be configured in order to bypass the GPIO Matrix for peripheral I/O:

1. IO_MUX for the GPIO pad must be set to the required pad function. (Please refer to section 4.10 for a list
of pad functions.)

2. For inputs, the SIG_IN_SEL register must be cleared to route the input directly to the peripheral.

4.5 RTC IO_MUX for Low Power and Analog I/O

4.5.1 Summary
18 GPIO pads have low power capabilities (RTC domain) and analog functions which are handled by the RTC
subsystem of ESP32. The IO_MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is
used to redirect the I/O to the RTC subsystem.

When configured as RTC GPIOs, the output pads can still retain the output level value when the chip is in
Deep-sleep mode, and the input pads can wake up the chip from Deep-sleep.

Section 4.11 has a list of RTC_MUX pins and their functions.

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4.5.2 Analog Function Description

The RTC function and analog function of RTC_GPIOs can only be selected one at a time. For the RTC_GPIO8 to
RTC_GPIO17 pins, their analog outputs can be directed to the IO_MUX, controlled by the RTC_IO_TOUCH_PADn/m_TO_GPIO
bit. If the bit is set to 1, the analog output is enabled, allowing the signal to be routed to IO_MUX through analog
function. On the other hand, if the bit is set to 0, the input signal from the pad is output to IO_MUX through
digital function.

4.6 Light-sleep Mode Pin Functions

Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX
register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in
Light-sleep mode:

Table 4-1. IO_MUX Light-sleep Pin Function Registers

Normal Execution Light-sleep Mode

IO_MUX Function
OR SLP_SEL = 0 AND SLP_SEL = 1
Output Drive Strength FUN_DRV MCU_DRV
Pull-up Resistor FUN_WPU MCU_WPU
Pull-down Resistor FUN_WPD MCU_WPD
Output Enable (From GPIO Matrix _OEN field) MCU_OE

If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.

4.7 Pad Hold Feature

Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad
is set to hold, the state is latched at that moment and will not change no matter how the internal signals change
or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the
pads to retain the pad state through a core reset triggered by watchdog time-out or Deep-sleep events.

The Hold state of each pin is controlled by the result of OR operation of the pin’s Hold enable signal and the
global Hold enable signal.

• Digital Pins (GPIO18 ~ GPIO19, GPIO21 ~ GPIO23, GPIO25 ~ GPIO27, GPIO32 ~ GPIO39)

– RTCIO_DIG_PAD_HOLD_REG[n], controls the Hold enable signal of each digital pin. See Table 4-8 for
the bit mapping for the pins.

– RTC_CNTL_DG_PAD_FORCE_HOLD, controls the global Hold signal of all digital pins.

To use this feature, follow the steps below:

– To maintain the pin’s input/output status in Deep-sleep, set RTCIO_DIG_PAD_HOLD_REG[n] (n = 0 ~

31) before power off. See Table 4-8 for the bit mapping for the pins. To disable the Hold function of
each pin after the chip is woken up, clear the bits above.

– Alternatively, set RTC_CNTL_DG_PAD_FORCE_HOLD to hold the values of all digital pins, or set
RTC_CNTL_DG_PAD_FORCE_UNHOLD to disable the hold function of all digital pins.

• RTC Pins (GPIO0 ~ GPIO17)

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– RTC_CNTL_HOLD_FORCE_REG[n](n = 0 ~ 17), controls the Hold enable signal of each RTC pins
(GPIO0 ~ GPIO17).

– RTC_CNTL_DG_PAD_FORCE_HOLD, controls the global Hold signal of all RTC pins.

To use this feature, follow the steps below:

– To maintain the pin’s input/output status in Deep-sleep, set RTC_CNTL_HOLD_FORCE_REG[n]. n

ranges from 0 to 17, corresponding to GPIO0 ~ GPIO17, respectively. To disable the Hold function of
each pin after the chip is woken up, clear the bits above.

– Alternatively, set RTC_CNTL_DG_PAD_FORCE_HOLD to hold the values of all RTC pins, or set
RTC_CNTL_DG_PAD_FORCE_UNHOLD to disable the hold function of all RTC pins.

4.8 I/O Pad Power Supplies

Figure 4-4 and 4-5 show the IO pad power supplies.

VDD3P3_CPU
GPIO21

GPIO22

GPIO19
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39

38

37

VDDA 1 36 GPIO23

LNA_IN 2 35 GPIO18

VDD3P3 3 34 GPIO5

VDD3P3 4 33 SD_DATA_1

SENSOR_VP 5 32 SD_DATA_0

SENSOR_CAPP 6 ESP32 31 SD_CLK

SENSOR_CAPN 7 49 GND 30 SD_CMD

SENSOR_VN 8 29 SD_DATA_3

CHIP_PU 9 28 SD_DATA_2

VDET_1 10 27 GPIO17

VDET_2 11 26 VDD_SDIO

32K_XP 12 25 GPIO16
13

14

15

16

17

18

19

20

21

22

23

24

Analog pads
32K_XN

GPIO25

GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4

Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 4-4. ESP32 I/O Pad Power Sources (QFN 6*6, Top View)

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GPIO21

GPIO22
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39
VDDA 1 38 GPIO19

LNA_IN 2 37 VDD3P3_CPU

VDD3P3 3 36 GPIO23

VDD3P3 4 35 GPIO18

SENSOR_VP 5 34 GPIO5

SENSOR_CAPP 6 33 SD_DATA_1

SENSOR_CAPN 7 32 SD_DATA_0
ESP32
49 GND
SENSOR_VN 8 31 SD_CLK

CHIP_PU 9 30 SD_CMD

VDET_1 10 29 SD_DATA_3

VDET_2 11 28 SD_DATA_2

32K_XP 12 27 GPIO17

32K_XN 13 26 VDD_SDIO

GPIO25 14 25 GPIO16
15

16

17

18

19

20

21

22

23

24
Analog pads
GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4 Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 4-5. ESP32 I/O Pad Power Sources (QFN 5*5, Top View)

• Pads marked blue are RTC pads that have their individual analog function and can also act as normal digital
IO pads. For details, please see Section 4.11.

• Pads marked yellow and green have digital functions only.

• Pads marked green can be powered externally or internally via VDD_SDIO (see below).

4.8.1 VDD_SDIO Power Domain

VDD_SDIO can source or sink current, allowing this power domain to be powered externally or internally. To
power VDD_SDIO externally, apply the same power supply of VDD3P3_RTC to the VDD_SDIO pad.

Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be
configured to be either 1.8V or the same as VDD3P3_RTC, depending on the state of the MTDI pad at reset –
a high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the
efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the
VDD_SDIO by configuring register bits.

4.9 Peripheral Signal List

Table 4-2 contains a list of Peripheral Input/Output signals used by the GPIO Matrix:

Table 4-2. GPIO Matrix Peripheral Signals

Signal Input Signal Output Signal Direct I/O in IO_MUX

0 SPICLK_in SPICLK_out YES
1 SPIQ_in SPIQ_out YES

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2 SPID_in SPID_out YES
3 SPIHD_in SPIHD_out YES
4 SPIWP_in SPIWP_out YES
5 SPICS0_in SPICS0_out YES
6 SPICS1_in SPICS1_out -
7 SPICS2_in SPICS2_out -
8 HSPICLK_in HSPICLK_out YES
9 HSPIQ_in HSPIQ_out YES
10 HSPID_in HSPID_out YES
11 HSPICS0_in HSPICS0_out YES
12 HSPIHD_in HSPIHD_out YES
13 HSPIWP_in HSPIWP_out YES
14 U0RXD_in U0TXD_out YES
15 U0CTS_in U0RTS_out YES
16 U0DSR_in U0DTR_out -
17 U1RXD_in U1TXD_out YES
18 U1CTS_in U1RTS_out YES
23 I2S0O_BCK_in I2S0O_BCK_out -
24 I2S1O_BCK_in I2S1O_BCK_out -
25 I2S0O_WS_in I2S0O_WS_out -
26 I2S1O_WS_in I2S1O_WS_out -
27 I2S0I_BCK_in I2S0I_BCK_out -
28 I2S0I_WS_in I2S0I_WS_out -
29 I2CEXT0_SCL_in I2CEXT0_SCL_out -
30 I2CEXT0_SDA_in I2CEXT0_SDA_out -
31 pwm0_sync0_in sdio_tohost_int_out -
32 pwm0_sync1_in pwm0_out0a -
33 pwm0_sync2_in pwm0_out0b -
34 pwm0_f0_in pwm0_out1a -
35 pwm0_f1_in pwm0_out1b -
36 pwm0_f2_in pwm0_out2a -
37 - pwm0_out2b -
39 pcnt_sig_ch0_in0 - -
40 pcnt_sig_ch1_in0 - -
41 pcnt_ctrl_ch0_in0 - -
42 pcnt_ctrl_ch1_in0 - -
43 pcnt_sig_ch0_in1 - -
44 pcnt_sig_ch1_in1 - -
45 pcnt_ctrl_ch0_in1 - -
46 pcnt_ctrl_ch1_in1 - -
47 pcnt_sig_ch0_in2 - -
48 pcnt_sig_ch1_in2 - -
49 pcnt_ctrl_ch0_in2 - -

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50 pcnt_ctrl_ch1_in2 - -
51 pcnt_sig_ch0_in3 - -
52 pcnt_sig_ch1_in3 - -
53 pcnt_ctrl_ch0_in3 - -
54 pcnt_ctrl_ch1_in3 - -
55 pcnt_sig_ch0_in4 - -
56 pcnt_sig_ch1_in4 - -
57 pcnt_ctrl_ch0_in4 - -
58 pcnt_ctrl_ch1_in4 - -
61 HSPICS1_in HSPICS1_out -
62 HSPICS2_in HSPICS2_out -
63 VSPICLK_in VSPICLK_out_mux YES
64 VSPIQ_in VSPIQ_out YES
65 VSPID_in VSPID_out YES
66 VSPIHD_in VSPIHD_out YES
67 VSPIWP_in VSPIWP_out YES
68 VSPICS0_in VSPICS0_out YES
69 VSPICS1_in VSPICS1_out -
70 VSPICS2_in VSPICS2_out -
71 pcnt_sig_ch0_in5 ledc_hs_sig_out0 -
72 pcnt_sig_ch1_in5 ledc_hs_sig_out1 -
73 pcnt_ctrl_ch0_in5 ledc_hs_sig_out2 -
74 pcnt_ctrl_ch1_in5 ledc_hs_sig_out3 -
75 pcnt_sig_ch0_in6 ledc_hs_sig_out4 -
76 pcnt_sig_ch1_in6 ledc_hs_sig_out5 -
77 pcnt_ctrl_ch0_in6 ledc_hs_sig_out6 -
78 pcnt_ctrl_ch1_in6 ledc_hs_sig_out7 -
79 pcnt_sig_ch0_in7 ledc_ls_sig_out0 -
80 pcnt_sig_ch1_in7 ledc_ls_sig_out1 -
81 pcnt_ctrl_ch0_in7 ledc_ls_sig_out2 -
82 pcnt_ctrl_ch1_in7 ledc_ls_sig_out3 -
83 rmt_sig_in0 ledc_ls_sig_out4 -
84 rmt_sig_in1 ledc_ls_sig_out5 -
85 rmt_sig_in2 ledc_ls_sig_out6 -
86 rmt_sig_in3 ledc_ls_sig_out7 -
87 rmt_sig_in4 rmt_sig_out0 -
88 rmt_sig_in5 rmt_sig_out1 -
89 rmt_sig_in6 rmt_sig_out2 -
90 rmt_sig_in7 rmt_sig_out3 -
91 - rmt_sig_out4 -
92 - rmt_sig_out5 -
93 - rmt_sig_out6 -
94 twai_rx rmt_sig_out7 -

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95 I2CEXT1_SCL_in I2CEXT1_SCL_out -
96 I2CEXT1_SDA_in I2CEXT1_SDA_out -
97 host_card_detect_n_1 host_ccmd_od_pullup_en_n-
98 host_card_detect_n_2 host_rst_n_1 -
99 host_card_write_prt_1 host_rst_n_2 -
100 host_card_write_prt_2 gpio_sd0_out -
101 host_card_int_n_1 gpio_sd1_out -
102 host_card_int_n_2 gpio_sd2_out -
103 pwm1_sync0_in gpio_sd3_out -
104 pwm1_sync1_in gpio_sd4_out -
105 pwm1_sync2_in gpio_sd5_out -
106 pwm1_f0_in gpio_sd6_out -
107 pwm1_f1_in gpio_sd7_out -
108 pwm1_f2_in pwm1_out0a -
109 pwm0_cap0_in pwm1_out0b -
110 pwm0_cap1_in pwm1_out1a -
111 pwm0_cap2_in pwm1_out1b -
112 pwm1_cap0_in pwm1_out2a -
113 pwm1_cap1_in pwm1_out2b -
114 pwm1_cap2_in - -
115 - - -
116 - - -
117 - - -
118 - - -
119 - - -
120 - - -
121 - - -
122 - - -
123 - twai_tx -
124 - twai_bus_off_on -
125 - twai_clkout -
140 I2S0I_DATA_in0 I2S0O_DATA_out0 -
141 I2S0I_DATA_in1 I2S0O_DATA_out1 -
142 I2S0I_DATA_in2 I2S0O_DATA_out2 -
143 I2S0I_DATA_in3 I2S0O_DATA_out3 -
144 I2S0I_DATA_in4 I2S0O_DATA_out4 -
145 I2S0I_DATA_in5 I2S0O_DATA_out5 -
146 I2S0I_DATA_in6 I2S0O_DATA_out6 -
147 I2S0I_DATA_in7 I2S0O_DATA_out7 -
148 I2S0I_DATA_in8 I2S0O_DATA_out8 -
149 I2S0I_DATA_in9 I2S0O_DATA_out9 -
150 I2S0I_DATA_in10 I2S0O_DATA_out10 -
151 I2S0I_DATA_in11 I2S0O_DATA_out11 -

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152 I2S0I_DATA_in12 I2S0O_DATA_out12 -
153 I2S0I_DATA_in13 I2S0O_DATA_out13 -
154 I2S0I_DATA_in14 I2S0O_DATA_out14 -
155 I2S0I_DATA_in15 I2S0O_DATA_out15 -
156 - I2S0O_DATA_out16 -
157 - I2S0O_DATA_out17 -
158 - I2S0O_DATA_out18 -
159 - I2S0O_DATA_out19 -
160 - I2S0O_DATA_out20 -
161 - I2S0O_DATA_out21 -
162 - I2S0O_DATA_out22 -
163 - I2S0O_DATA_out23 -
164 I2S1I_BCK_in I2S1I_BCK_out -
165 I2S1I_WS_in I2S1I_WS_out -
166 I2S1I_DATA_in0 I2S1O_DATA_out0 -
167 I2S1I_DATA_in1 I2S1O_DATA_out1 -
168 I2S1I_DATA_in2 I2S1O_DATA_out2 -
169 I2S1I_DATA_in3 I2S1O_DATA_out3 -
170 I2S1I_DATA_in4 I2S1O_DATA_out4 -
171 I2S1I_DATA_in5 I2S1O_DATA_out5 -
172 I2S1I_DATA_in6 I2S1O_DATA_out6 -
173 I2S1I_DATA_in7 I2S1O_DATA_out7 -
174 I2S1I_DATA_in8 I2S1O_DATA_out8 -
175 I2S1I_DATA_in9 I2S1O_DATA_out9 -
176 I2S1I_DATA_in10 I2S1O_DATA_out10 -
177 I2S1I_DATA_in11 I2S1O_DATA_out11 -
178 I2S1I_DATA_in12 I2S1O_DATA_out12 -
179 I2S1I_DATA_in13 I2S1O_DATA_out13 -
180 I2S1I_DATA_in14 I2S1O_DATA_out14 -
181 I2S1I_DATA_in15 I2S1O_DATA_out15 -
182 - I2S1O_DATA_out16 -
183 - I2S1O_DATA_out17 -
184 - I2S1O_DATA_out18 -
185 - I2S1O_DATA_out19 -
186 - I2S1O_DATA_out20 -
187 - I2S1O_DATA_out21 -
188 - I2S1O_DATA_out22 -
189 - I2S1O_DATA_out23 -
190 I2S0I_H_SYNC - -
191 I2S0I_V_SYNC - -
192 I2S0I_H_ENABLE - -
193 I2S1I_H_SYNC - -
194 I2S1I_V_SYNC - -

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195 I2S1I_H_ENABLE - -
196 - - -
197 - - -
198 U2RXD_in U2TXD_out YES
199 U2CTS_in U2RTS_out YES
200 emac_mdc_i emac_mdc_o -
201 emac_mdi_i emac_mdo_o -
202 emac_crs_i emac_crs_o -
203 emac_col_i emac_col_o -
204 pcmfsync_in bt_audio0_irq -
205 pcmclk_in bt_audio1_irq -
206 pcmdin bt_audio2_irq -
207 - ble_audio0_irq -
208 - ble_audio1_irq -
209 - ble_audio2_irq -
210 - pcmfsync_out -
211 - pcmclk_out -
212 - pcmdout -
213 - ble_audio_sync0_p -
214 - ble_audio_sync1_p -
215 - ble_audio_sync2_p -
224 - sig_in_func224 -
225 - sig_in_func225 -
226 - sig_in_func226 -
227 - sig_in_func227 -
228 - sig_in_func228 -

Direct I/O in IO_MUX ”YES” means that this signal is also available directly via IO_MUX. To apply the GPIO Matrix
to these signals, their corresponding SIG_IN_SEL register must be cleared.

4.10 IO_MUX Pad List

Table 4-3 shows the IO_MUX functions for each I/O pad:

Table 4-3. IO_MUX Pad Summary

GPIO Pad Name Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 Reset Notes
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R
1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 -
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R
3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 -
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 -
6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 -
7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 -
8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 -
9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 -
10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 -

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GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 -
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 2 R
14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 3 R
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R
16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 -
17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 -
18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 -
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 -
21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 -
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 -
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 -
25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R
26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R
27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 0 R
32 32K_XP GPIO32 - GPIO32 - - - 0 R
33 32K_XN GPIO33 - GPIO33 - - - 0 R
34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I
35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I
36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I
37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I
38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I
39 SENSOR_VN GPIO39 - GPIO39 - - - 0 R, I

Reset Configurations

”Reset” column shows each pad’s default configurations after reset:

• 0 - IE=0 (input disabled).

• 1 - IE=1 (input enabled).

• 2 - IE=1, WPD=1 (input enabled, pull-down resistor).

• 3 - IE=1, WPU=1 (input enabled, pull-up resistor).

Notes

• R - Pad has RTC/analog functions via RTC_MUX.

• I - Pad can only be configured as input GPIO. These input-only pads do not feature an output driver or
internal pull-up/pull-down circuitry.

Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details.

4.11 RTC_MUX Pin List

Table 4-4 shows the RTC pins and how they correspond to GPIO pads:

Table 4-4. RTC_MUX Pin Summary

Analog Function RTC Function

RTC GPIO Num GPIO Num Pad Name Function 0 Function 1
0 1 2
(FUN_SEL = 0) (FUN_SEL = 3)
0 36 SENSOR_VP ADC_H ADC1_CH0 - RTC_GPIO0 -
1 37 SENSOR_CAPP ADC_H ADC1_CH1 - RTC_GPIO1 -
2 38 SENSOR_CAPN ADC_H ADC1_CH2 - RTC_GPIO2 -

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Analog Function RTC Function

RTC GPIO Num GPIO Num Pad Name Function 0 Function 1
0 1 2
(FUN_SEL = 0) (FUN_SEL = 3)
3 39 SENSOR_VN ADC_H ADC1_CH3 - RTC_GPIO3 -
4 34 VDET_1 - ADC1_CH6 - RTC_GPIO4 -
5 35 VDET_2 - ADC1_CH7 - RTC_GPIO5 -
6 25 GPIO25 DAC_1 ADC2_CH8 - RTC_GPIO6 -
7 26 GPIO26 DAC_2 ADC2_CH9 - RTC_GPIO7 -
8 33 32K_XN XTAL_32K_N ADC1_CH5 TOUCH8 RTC_GPIO8 -
9 32 32K_XP XTAL_32K_P ADC1_CH4 TOUCH9 RTC_GPIO9 -
10 4 GPIO4 - ADC2_CH0 TOUCH0 RTC_GPIO10 I2C_SCL∗
11 0 GPIO0 - ADC2_CH1 TOUCH1 RTC_GPIO11 I2C_SDA∗
12 2 GPIO2 - ADC2_CH2 TOUCH2 RTC_GPIO12 I2C_SCL∗
13 15 MTDO - ADC2_CH3 TOUCH3 RTC_GPIO13 I2C_SDA∗
14 13 MTCK - ADC2_CH4 TOUCH4 RTC_GPIO14 -
15 12 MTDI - ADC2_CH5 TOUCH5 RTC_GPIO15 -
16 14 MTMS - ADC2_CH6 TOUCH6 RTC_GPIO16 -
17 27 GPIO27 - ADC2_CH7 TOUCH7 RTC_GPIO17 -

Note:
For more information on the configuration of sar_i2c_xx, see Section RTC I2C Controller in Chapter 30 ULP Coprocessor
(ULP).

4.12 Register Summary

4.12.1 GPIO Matrix Register Summary
Name Description Address Access
GPIO_OUT_REG GPIO 0-31 output register 0x3FF44004 R/W
GPIO_OUT_W1TS_REG GPIO 0-31 output register_W1TS 0x3FF44008 WO
GPIO_OUT_W1TC_REG GPIO 0-31 output register_W1TC 0x3FF4400C WO
GPIO_OUT1_REG GPIO 32-39 output register 0x3FF44010 R/W
GPIO_OUT1_W1TS_REG GPIO 32-39 output bit set register 0x3FF44014 WO
GPIO_OUT1_W1TC_REG GPIO 32-39 output bit clear register 0x3FF44018 WO
GPIO_ENABLE_REG GPIO 0-31 output enable register 0x3FF44020 R/W
GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable register_W1TS 0x3FF44024 WO
GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable register_W1TC 0x3FF44028 WO
GPIO_ENABLE1_REG GPIO 32-39 output enable register 0x3FF4402C R/W
GPIO_ENABLE1_W1TS_REG GPIO 32-39 output enable bit set register 0x3FF44030 WO
GPIO_ENABLE1_W1TC_REG GPIO 32-39 output enable bit clear register 0x3FF44034 WO
GPIO_STRAP_REG Bootstrap pin value register 0x3FF44038 RO
GPIO_IN_REG GPIO 0-31 input register 0x3FF4403C RO
GPIO_IN1_REG GPIO 32-39 input register 0x3FF44040 RO
GPIO_STATUS_REG GPIO 0-31 interrupt status register 0x3FF44044 R/W
GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS 0x3FF44048 WO
GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC 0x3FF4404C WO

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Name Description Address Access

GPIO_STATUS1_REG GPIO 32-39 interrupt status register1 0x3FF44050 R/W
GPIO_STATUS1_W1TS_REG GPIO 32-39 interrupt status bit set register 0x3FF44054 WO
GPIO_STATUS1_W1TC_REG GPIO 32-39 interrupt status bit clear register 0x3FF44058 WO
GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU interrupt status 0x3FF44060 RO
GPIO 0-31 APP_CPU non-maskable interrupt sta-
GPIO_ACPU_NMI_INT_REG 0x3FF44064 RO
tus
GPIO_PCPU_INT_REG GPIO 0-31 PRO_CPU interrupt status 0x3FF44068 RO
GPIO 0-31 PRO_CPU non-maskable interrupt sta-
GPIO_PCPU_NMI_INT_REG 0x3FF4406C RO
tus
GPIO_ACPU_INT1_REG GPIO 32-39 APP_CPU interrupt status 0x3FF44074 RO
GPIO 32-39 APP_CPU non-maskable interrupt
GPIO_ACPU_NMI_INT1_REG 0x3FF44078 RO
status
GPIO_PCPU_INT1_REG GPIO 32-39 PRO_CPU interrupt status 0x3FF4407C RO
GPIO 32-39 PRO_CPU non-maskable interrupt
GPIO_PCPU_NMI_INT1_REG 0x3FF44080 RO
status
GPIO_PIN0_REG Configuration for GPIO pin 0 0x3FF44088 R/W
GPIO_PIN1_REG Configuration for GPIO pin 1 0x3FF4408C R/W
GPIO_PIN2_REG Configuration for GPIO pin 2 0x3FF44090 R/W
... ...
GPIO_PIN38_REG Configuration for GPIO pin 38 0x3FF44120 R/W
GPIO_PIN39_REG Configuration for GPIO pin 39 0x3FF44124 R/W
GPIO_FUNC0_IN_SEL_CFG_REG Peripheral function 0 input selection register 0x3FF44130 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Peripheral function 1 input selection register 0x3FF44134 R/W
... ...
GPIO_FUNC254_IN_SEL_CFG_REG Peripheral function 254 input selection register 0x3FF44528 R/W
GPIO_FUNC255_IN_SEL_CFG_REG Peripheral function 255 input selection register 0x3FF4452C R/W
GPIO_FUNC0_OUT_SEL_CFG_REG Peripheral output selection for GPIO 0 0x3FF44530 R/W
GPIO_FUNC1_OUT_SEL_CFG_REG Peripheral output selection for GPIO 1 0x3FF44534 R/W
... ...
GPIO_FUNC38_OUT_SEL_CFG_REG Peripheral output selection for GPIO 38 0x3FF445C8 R/W
GPIO_FUNC39_OUT_SEL_CFG_REG Peripheral output selection for GPIO 39 0x3FF445CC R/W

4.12.2 IO MUX Register Summary

Name Description Address Access
IO_MUX_PIN_CTRL Clock output configuration register 0x3FF49000 R/W
IO_MUX_GPIO36_REG Configuration register for pad GPIO36 0x3FF49004 R/W
IO_MUX_GPIO37_REG Configuration register for pad GPIO37 0x3FF49008 R/W
IO_MUX_GPIO38_REG Configuration register for pad GPIO38 0x3FF4900C R/W
IO_MUX_GPIO39_REG Configuration register for pad GPIO39 0x3FF49010 R/W
IO_MUX_GPIO34_REG Configuration register for pad GPIO34 0x3FF49014 R/W
IO_MUX_GPIO35_REG Configuration register for pad GPIO35 0x3FF49018 R/W
IO_MUX_GPIO32_REG Configuration register for pad GPIO32 0x3FF4901C R/W
IO_MUX_GPIO33_REG Configuration register for pad GPIO33 0x3FF49020 R/W

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Name Description Address Access

IO_MUX_GPIO25_REG Configuration register for pad GPIO25 0x3FF49024 R/W
IO_MUX_GPIO26_REG Configuration register for pad GPIO26 0x3FF49028 R/W
IO_MUX_GPIO27_REG Configuration register for pad GPIO27 0x3FF4902C R/W
IO_MUX_MTMS_REG Configuration register for pad MTMS 0x3FF49030 R/W
IO_MUX_MTDI_REG Configuration register for pad MTDI 0x3FF49034 R/W
IO_MUX_MTCK_REG Configuration register for pad MTCK 0x3FF49038 R/W
IO_MUX_MTDO_REG Configuration register for pad MTDO 0x3FF4903C R/W
IO_MUX_GPIO2_REG Configuration register for pad GPIO2 0x3FF49040 R/W
IO_MUX_GPIO0_REG Configuration register for pad GPIO0 0x3FF49044 R/W
IO_MUX_GPIO4_REG Configuration register for pad GPIO4 0x3FF49048 R/W
IO_MUX_GPIO16_REG Configuration register for pad GPIO16 0x3FF4904C R/W
IO_MUX_GPIO17_REG Configuration register for pad GPIO17 0x3FF49050 R/W
IO_MUX_SD_DATA2_REG Configuration register for pad SD_DATA2 0x3FF49054 R/W
IO_MUX_SD_DATA3_REG Configuration register for pad SD_DATA3 0x3FF49058 R/W
IO_MUX_SD_CMD_REG Configuration register for pad SD_CMD 0x3FF4905C R/W
IO_MUX_SD_CLK_REG Configuration register for pad SD_CLK 0x3FF49060 R/W
IO_MUX_SD_DATA0_REG Configuration register for pad SD_DATA0 0x3FF49064 R/W
IO_MUX_SD_DATA1_REG Configuration register for pad SD_DATA1 0x3FF49068 R/W
IO_MUX_GPIO5_REG Configuration register for pad GPIO5 0x3FF4906C R/W
IO_MUX_GPIO18_REG Configuration register for pad GPIO18 0x3FF49070 R/W
IO_MUX_GPIO19_REG Configuration register for pad GPIO19 0x3FF49074 R/W
1
IO_MUX_GPIO20_REG Configuration register for pad GPIO20 0x3FF49078 R/W
IO_MUX_GPIO21_REG Configuration register for pad GPIO21 0x3FF4907C R/W
IO_MUX_GPIO22_REG Configuration register for pad GPIO22 0x3FF49080 R/W
IO_MUX_U0RXD_REG Configuration register for pad U0RXD 0x3FF49084 R/W
IO_MUX_U0TXD_REG Configuration register for pad U0TXD 0x3FF49088 R/W
IO_MUX_GPIO23_REG Configuration register for pad GPIO23 0x3FF4908C R/W
IO_MUX_GPIO24_REG Configuration register for pad GPIO24 0x3FF49090 R/W

1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet
for more information.

4.12.3 RTC IO MUX Register Summary

Name Description Address Access
GPIO configuration / data registers
RTCIO_RTC_GPIO_OUT_REG RTC GPIO output register 0x3FF48400 R/W
RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO output bit set register 0x3FF48404 WO
RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO output bit clear register 0x3FF48408 WO
RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO output enable register 0x3FF4840C R/W
RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO output enable bit set register 0x3FF48410 WO
RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO output enable bit clear register 0x3FF48414 WO
RTCIO_RTC_GPIO_STATUS_REG RTC GPIO interrupt status register 0x3FF48418 WO
RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO interrupt status bit set register 0x3FF4841C WO

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Name Description Address Access

RTCIO_RTC_GPIO_STATUS_W1TC_REG RTC GPIO interrupt status bit clear register 0x3FF48420 WO
RTCIO_RTC_GPIO_IN_REG RTC GPIO input register 0x3FF48424 RO
RTCIO_RTC_GPIO_PIN0_REG RTC configuration for pin 0 0x3FF48428 R/W
RTCIO_RTC_GPIO_PIN1_REG RTC configuration for pin 1 0x3FF4842C R/W
RTCIO_RTC_GPIO_PIN2_REG RTC configuration for pin 2 0x3FF48430 R/W
RTCIO_RTC_GPIO_PIN3_REG RTC configuration for pin 3 0x3FF48434 R/W
RTCIO_RTC_GPIO_PIN4_REG RTC configuration for pin 4 0x3FF48438 R/W
RTCIO_RTC_GPIO_PIN5_REG RTC configuration for pin 5 0x3FF4843C R/W
RTCIO_RTC_GPIO_PIN6_REG RTC configuration for pin 6 0x3FF48440 R/W
RTCIO_RTC_GPIO_PIN7_REG RTC configuration for pin 7 0x3FF48444 R/W
RTCIO_RTC_GPIO_PIN8_REG RTC configuration for pin 8 0x3FF48448 R/W
RTCIO_RTC_GPIO_PIN9_REG RTC configuration for pin 9 0x3FF4844C R/W
RTCIO_RTC_GPIO_PIN10_REG RTC configuration for pin 10 0x3FF48450 R/W
RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11 0x3FF48454 R/W
RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12 0x3FF48458 R/W
RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13 0x3FF4845C R/W
RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14 0x3FF48460 R/W
RTCIO_RTC_GPIO_PIN15_REG RTC configuration for pin 15 0x3FF48464 R/W
RTCIO_RTC_GPIO_PIN16_REG RTC configuration for pin 16 0x3FF48468 R/W
RTCIO_RTC_GPIO_PIN17_REG RTC configuration for pin 17 0x3FF4846C R/W
RTCIO_DIG_PAD_HOLD_REG RTC GPIO hold register 0x3FF48474 R/W
GPIO RTC function configuration registers
RTCIO_SENSOR_PADS_REG Sensor pads configuration register 0x3FF4847C R/W
RTCIO_ADC_PAD_REG ADC configuration register 0x3FF48480 R/W
RTCIO_PAD_DAC1_REG DAC1 configuration register 0x3FF48484 R/W
RTCIO_PAD_DAC2_REG DAC2 configuration register 0x3FF48488 R/W
RTCIO_XTAL_32K_PAD_REG 32KHz crystal pads configuration register 0x3FF4848C R/W
RTCIO_TOUCH_CFG_REG Touch sensor configuration register 0x3FF48490 R/W
RTCIO_TOUCH_PAD0_REG Touch pad configuration register 0x3FF48494 R/W
... ...
RTCIO_TOUCH_PAD9_REG Touch pad configuration register 0x3FF484B8 R/W
RTCIO_EXT_WAKEUP0_REG External wake up configuration register 0x3FF484BC R/W
RTCIO_XTL_EXT_CTR_REG Crystal power down enable GPIO source 0x3FF484C0 R/W
RTCIO_SAR_I2C_IO_REG RTC I2C pad selection 0x3FF484C4 R/W

4.13 Registers
4.13.1 GPIO Matrix Registers
The addresses in parenthesis besides register names are the register addresses relative to the GPIO base ad-
dress provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute register
addresses are listed in Section 4.12.1 GPIO Matrix Register Summary.

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Register 4.1. GPIO_OUT_REG (0x0004)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_REG GPIO0-31 output value. (R/W)

Register 4.2. GPIO_OUT_W1TS_REG (0x0008)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here,
the corresponding bit in GPIO_OUT_REG will be set. (WO)

Register 4.3. GPIO_OUT_W1TC_REG (0x000c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)

Register 4.4. GPIO_OUT1_REG (0x0010)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value. (R/W)

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Register 4.5. GPIO_OUT1_W1TS_REG (0x0014)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)

Register 4.6. GPIO_OUT1_W1TC_REG (0x0018)

TA
DA
T_
)
ed

U
_O
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)

Register 4.7. GPIO_ENABLE_REG (0x0020)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_REG GPIO0-31 output enable. (R/W)

Register 4.8. GPIO_ENABLE_W1TS_REG (0x0024)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be set. (WO)

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Register 4.9. GPIO_ENABLE_W1TC_REG (0x0028)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)

Register 4.10. GPIO_ENABLE1_REG (0x002c)

TA
DA
E_
BL
)

NA
ed

_E
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W)

Register 4.11. GPIO_ENABLE1_W1TS_REG (0x0030)

TA
DA
E_
BL
)

NA
ed

_E
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)

Register 4.12. GPIO_ENABLE1_W1TC_REG (0x0034)

TA
DA
E_
BL
)

NA
ed

_E
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)

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Register 4.13. GPIO_STRAP_REG (0x0038)

NG
PI
AP
)

TR
ed

_S
rv
se

IO
(re

GP
31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Reset

GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI,

GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively.

Register 4.14. GPIO_IN_REG (0x003c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0 for
low level. (RO)

Register 4.15. GPIO_IN1_REG (0x0040)

EXT
_N
TA
DA
)
ed

N_
rv

_I
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO)

Register 4.16. GPIO_STATUS_REG (0x0044)

NT
I
S_
TU
TA
_S
IO
GP

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT GPIO0-31 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16
bits in GPIO_PINn_REG should be set to 1. (R/W)

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Register 4.17. GPIO_STATUS_W1TS_REG (0x0048)

S
1T
_W
NTI
S_
TU
TA
_S
IO
GP
31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT_W1TS GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be set. (WO)

Register 4.18. GPIO_STATUS_W1TC_REG (0x004c)

C
1T
_W
NT
_I
US
AT
ST
IO_
GP

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_INT_W1TC GPIO0-31 interrupt status clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INT will be cleared. (WO)

Register 4.19. GPIO_STATUS1_REG (0x0050)

NT
_I
S1
TU
)

TA
ed

_S
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT GPIO32-39 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_PINn_INT_ENA, corresponding to the 13-16
bits in GPIO_PINn_REG should be set to 1. (R/W)

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Register 4.20. GPIO_STATUS1_W1TS_REG (0x0054)

S
1T
_W
NT
_I
S1
TU
d)

TA
ve

_S
r
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT_W1TS GPIO32-39 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS1_INT will be set. (WO)

Register 4.21. GPIO_STATUS1_W1TC_REG (0x0058)

C
1T
_W
NT
_I
S1
TU
)

TA
ed

_S
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS1_INT_W1TC GPIO32-39 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS1_INT will be cleared. (WO)

Register 4.22. GPIO_ACPU_INT_REG (0x0060)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)

Register 4.23. GPIO_ACPU_NMI_INT_REG (0x0064)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO)

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Register 4.24. GPIO_PCPU_INT_REG (0x0068)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO)

Register 4.25. GPIO_PCPU_NMI_INT_REG (0x006c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO)

Register 4.26. GPIO_ACPU_INT1_REG (0x0074)

NT
I
U_
CP
)

PP
ed

_A
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO)

Register 4.27. GPIO_ACPU_NMI_INT1_REG (0x0078)

T
IN
I_
M
N
U_
CP
)

PP
ed

_A
rv
se

IO
(re

GP

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO)

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Register 4.28. GPIO_PCPU_INT1_REG (0x007c)

T
IN
U_
CP
RO
)
ed

_P
rv
se

IO
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO)

Register 4.29. GPIO_PCPU_NMI_INT1_REG (0x0080)

T
IN
I_
N M
U_
CP
RO
)
ed

P
rv

O_
se

I
(re

GP
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO)

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Register 4.30. GPIO_PINn_REG (n: 0-39) (0x88+0x4*n)

LE
AB

R
EN

VE
P_

PE

RI
A
EN

EU

_D
TY
T_

T_
AK

AD
IN

IN
W

_P
n_

n_

n_

(re INn
d)

GP ed)

)
ed

ed
IN

IN

IN
ve

_P

_P

_P
rv

rv

rv
O_
r
se

se

se

se
IO

IO

IO
I
(re

(re

(re
GP

GP

GP
31 18 17 13 12 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x 0 0 x x x x 0 0 0 0 x 0 0 Reset

GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W)

bit0: APP CPU interrupt enable;
bit1: APP CPU non-maskable interrupt enable;
bit2: PRO CPU interrupt enable;
bit3: PRO CPU non-maskable interrupt enable.

GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)

GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)

Register 4.31. GPIO_FUNCy_IN_SEL_CFG_REG (y: 0-255) (0x130+0x4*y)

L
SE
V_

L
SE
IN
_I L
Cy SE
N_

N_
UN IN_

_I
Cy
_F _
IO IGy

UN
)
ed

GP _S

_F
rv
se

IO

IO
GP

GP
(re

31 8 7 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_SIGy_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal directly
to peripheral configured in the IO_MUX. (R/W)

GPIO_FUNCy_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)

GPIO_FUNCy_IN_SEL Selection control for peripheral input y. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)

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Register 4.32. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-19, 21-23, 25-27, 32-33) (0x530+0x4*n)

UT EL EL

EL
_O _S _S

_S

EL
Cn EN INV

NV

_S
_I
UN n_O _

UT
_F C EN
IO UN _O

_O
GP _F Cn

Cn
d)

IO UN

UN
ve

GP _F

_F
r
se

IO

IO
(re

GP

GP
31 12 11 10 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x Reset

GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)

GPIO_FUNCn_OEN_SEL 1: Force the output enable signal to be sourced from bit n of

GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W)

GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)

GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. A value of s (0<=s<256)

connects peripheral output s to GPIO output n. A value of 256 selects bit n of
GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the output
value and output enable. (R/W)

4.13.2 IO MUX Registers

The addresses in parenthesis besides register names are the register addresses relative to the IO MUX base
addresses provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute
register addresses are listed in Section 4.12.2 IO MUX Register Summary.

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Register 4.33. IO_MUX_PIN_CTRL (0x00)

K2
K3

K1
CL

CL

CL
L_

L_

L_
)
ed

R
CT

CT

CT
rv
se

N_

N_

N_
(re

PI

PI

PI
31 12 11 8 7 4 3 0

0x0 0x0 0x0 0x0 Reset

If you want to output clock for I2S0 (I2S0_CLK) to:

CLK_OUT1, then set PIN_CTRL[3:0] = 0x0;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0.
If you want to output clock for I2S1 (I2S1_CLK) to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0xF;
CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0.

If you want to output clock for APLL to

CLK_OUT1, then set PIN_CTRL[3:0] = 0x6;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x6 and PIN_CTRL[7:4] = 0x6;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x6 and PIN_CTRL[11:8] = 0x6. (R/W)

Note:

• Only the above mentioned combinations of clock source (i.e. I2S0/1_CLK, APLL clock) and clock output pins
(i.e. CLK_OUT1 ~ 3) are possible.

• The CLK_OUT1 ~ 3 can be found in the IO_MUX Pad Summary.

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Register 4.34. IO_MUX_x_REG (x: GPIO0-GPIO39) (0x10+4*x)

U
P_ PD
)

CU V
N_ PU

CU D
EL

FU RV
ed

CU P
R

E
CU L
P

M _IE
M _W
SL _W
_D

_O
M SE
_S

FU IE
FU _W
W
rv

D
N_

N_
se

CU

CU
N
(re

FU
M

M
31 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 0 0 0 0x0 0 0 0 0 0 Reset

MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1,
etc. (R/W)

FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength.
For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table
”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. (R/W)

FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W)

FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO
pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-
down circuitry, therefore, their FUN_WPU is always 0. (R/W)

FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal
pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. (R/W)

MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds
with a higher strength. (R/W)

MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W)

MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)

MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: in-
ternal pull-down disabled. (R/W)

SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W)

MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W)

4.13.3 RTC IO MUX Registers

The addresses in parenthesis besides register names are the register addresses relative to (the RTC base ad-
dress + 0x0400). The RTC base address is provided in Table 1-6 Peripheral Address Mapping in Chapter 1
System and Memory. The absolute register addresses are listed in Section 4.12.3 RTC IO MUX Register Sum-
mary.

Espressif Systems 78 ESP32 TRM (Version 5.2)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.35. RTCIO_RTC_GPIO_OUT_REG (0x0000)

A
AT
_D
UT
_O
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc. (R/W)

Register 4.36. RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004)

S
1T
A _W
AT
_D
UT
_O
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the value
written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO)

Register 4.37. RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008)

C
1T
A _W
AT
_D
UT
_O
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.38. RTCIO_RTC_GPIO_ENABLE_REG (0x000C)

B LE
NA
_E
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1 means
this GPIO pad is output. (R/W)

Register 4.39. RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)

S
1T
W
E_
BL
E NA
O_I
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)

Register 4.40. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)

C
1T
W
E_
BL
NA
_E
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.41. RTCIO_RTC_GPIO_STATUS_REG (0x0018)

NTI
S_
TU
TA
_S
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1],

etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT-
CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W)

Register 4.42. RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)

S
1T
_W
NT
I
U S_
AT
ST
O_
I
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO)

Register 4.43. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)

C
1T
_W
NTI
S_
TU
TA
_S
IO
GP
C_

)
RT

ed
O_

rv
se
CI

(re
RT

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared. (WO)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.44. RTCIO_RTC_GPIO_IN_REG (0x0024)

XT
NE
N_
_I
IO
GP
C_

d)
RT

ve
O_

r
se
CI

(re
RT
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each bit
represents a pad input value, 1 for high level, and 0 for low level. (RO)

Register 4.45. RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (0x28+4*n)

LE
AB

ER
EN

IV
P_

DR
P
EU

TY

D_
T_
AK

PA
IN
W
n_

n_

n_
IN

IN

IN
_P

_P

_P
IO

IO

ed PIO
GP

GP

se C_G
C_

C_
)

)
RT

RT

(re RT
ed

ed
O_

O_

O_
rv

rv

rv
se

se
CI

CI

CI
(re

(re
RT

RT

RT
31 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 0 x 0 0 Reset

RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the ESP32
from Light-sleep. (R/W)

RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.46. RTCIO_DIG_PAD_HOLD_REG (0x0074)

31 0

0 Reset

RTCIO_DIG_PAD_HOLD_REG Selects the digital pads which should be put on hold. While 0 allows
normal operation, 1 puts the pad on hold. (R/W)

Table 4-8. Mapping of Bits to Pins

Name Description
Bit[0] Set to 1 to enable the Hold function of pad U0RXD
Bit[1] Set to 1 to enable the Hold function of pad U0TXD
Bit[2] Set to 1 to enable the Hold function of pad
SD_CLK
Bit[3] Set to 1 to enable the Hold function of pad
SD_DATA0
Bit[4] Set to 1 to enable the Hold function of pad
SD_DATA1
Bit[5] Set to 1 to enable the Hold function of pad
SD_DATA2
Bit[6] Set to 1 to enable the Hold function of pad
SD_DATA3
Bit[7] Set to 1 to enable the Hold function of pad
SD_CMD
Bit[8] Set to 1 to enable the Hold function of pad GPIO5
Bit[9] Set to 1 to enable the Hold function of pad GPIO16
Bit[10] Set to 1 to enable the Hold function of pad GPIO17
Bit[11] Set to 1 to enable the Hold function of pad GPIO18
Bit[12] Set to 1 to enable the Hold function of pad GPIO19
Bit[13] Set to 1 to enable the Hold function of pad
GPIO201
Bit[14] Set to 1 to enable the Hold function of pad GPIO21
Bit[15] Set to 1 to enable the Hold function of pad
GPIO22
Bit[16] Set to 1 to enable the Hold function of pad
GPIO23

1. GPIO20 is only available for ESP32-PICO-V3 and ESP32-PICO-V3-02. Please refer to ESP32-PICO Series Datasheet
for more information.

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.47. RTCIO_SENSOR_PADS_REG (0x007C)

R_ SE4 U SEL
UX EL
EL

S E LP L

_S SE SL EL
NS SEN E3_ UX EL

E LP EL

_S E3_ P_ L

4_ P_ L
O_ SOR SEN E2_ _SE

O_ SOR SEN E3_ _SE

_S E1_ P_I L
SE

O_ NS _S E3_ _IE

L E

SE SL SE
O_ NS _S E4_ _IE

IE
M _S
_S

S SL E

S
IE

SE 2_F _IE

UN E
_ S M S

FU I E
SO ENS 2_S _S

_S
EN FU E
M _
C SE OR EN 3_ LD

EN 1_ _S
CI SE OR EN 4_ LD
RT SE OR EN 1_M LD

NS _S SE UN_

N_
I
O_ SOR SEN E2_ UX_
C SE OR EN 2_ D

N_

N_

EN 4_ P_
X

UN

SE E3 LP
RT IO_ NS _S SE OL

P
RT IO_ NS _S SE HO
RT IO_ NS _S SE HO
O_ NS _S SE HO

FU

FU
FU

_S SE SL

S
S
F

F
C SE OR EN 1_H

O_ NS _S E2_

_
_

OR EN _
O_ NS _S E1_

OR EN 1_

4
RT IO_ NS _S SE

NS _S SE
N _ S

N _ S
S

NS

N _ S
S
S

NS
C SE OR EN

EN

RT SE OR EN

RT SE OR EN

RT SE OR EN

SE OR EN
E
RT IO_ NS _S

R_

_
C SE OR

CI E R

OR

CI SE OR

CI SE OR

OR

CI SE OR
O

O
RT IO_ NS

RT O_ NS

NS

RT O_ NS

RT IO_ NS

RT _ S
EN

EN

)
C SE

RT SE

CI SE

RT SE

CI SE

C SE

CI SE

ed
S

S
RT IO_

RT _

O_

RT O_

RT _

RT O_

rv
O

se
CI

CI

CI

CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal oper-
ation. (R/W)

RTCIO_SENSOR_SENSEn_MUX_SEL 1: route sensen to the RTC block; 0: route sensen to the

digital IO_MUX. (R/W)

RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pad. 0: select Func-
tion 0. (R/W)

RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad in
sleep mode. (R/W)

RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.48. RTCIO_ADC_PAD_REG (0x0080)

EL

AD AD 2_S SEL
UX EL

RT AD AD _SL EL

C2 LP EL
C LP EL

E
_S

_F E

_F _IE
C_ 2_M X_S

AD _S _S

_I
C_ 1_F _IE
AD _M LD

_
AD _S _S

_I
RT AD AD _H D

N_

UN

UN
C_ C2 LP
UN
O_ C_ C OL

C_ C1 P
C_ C1 O
C U

FU
CI AD AD H
RT IO_ C_ C1_

_
2

C2
C1

1
O_ C_ C

O_ C_ C
C AD AD

AD

CI AD AD

AD

CI AD AD
RT O_ C_

RT _ _

RT O_ C_
C

)
CI AD

RT AD

CI AD

RT AD

CI AD

ed
RT IO_

O_

RT O_

O_

RT O_

rv
O

se
CI

CI

CI

CI
C

(re
RT

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_ADC_ADCn_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route pad to the RTC block.

RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 3: select
Function 1. (R/W)

RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad
to sleep. (R/W)

RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W)

RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1 enabled; 0 disabled. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.49. RTCIO_PAD_DAC1_REG (0x0084)

E
RC
FO
D_
FU EL
AC UX_ C

CI PA PD 1_S SEL

O_ D_ AC L EL
M DA

XP
AC FU E
DA IE
S

D_ AC SL E
PD 1_ P_O
CI PA PD 1_S _S
PD 1_ LD

N_

1_ N_
PA PD 1_ P_I

C_
D_ C1_ D_
C
V

E
1_ E

RT _ _ C LP
D_ AC HO

RU
DR

AC RD

DA

A XP
1_

PA D _

1_

O_ _PD C1_

1_
1
AC

O_ D_ AC

AC

RT O_ D_ AC
D A

A
PD

CI PA PD

PD

RT PA PD

PD

CI PA PD
P
D_

RT _ _

D_

O_ D_

RT O_ D_
D

)
RT PA

CI PA

PA

CI PA

RT PA

CI PA

ed
O_

RT IO_

O_

RT O_

RT O_

rv
O

se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC1_DRV Select the drive strength of the pad. (R/W)

RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pad; set to 0 for normal opera-
tion. (R/W)

RTCIO_PAD_PDAC1_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC1_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC1_DAC PAD DAC1 output value. (R/W)

RTCIO_PAD_PDAC1_XPD_DAC Power on DAC1. Usually, PDAC1 needs to be tristated if we power on

the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC1_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC1_FUN_SEL the functional selection signal of the pad. (R/W)

RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)

RTCIO_PAD_PDAC1_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_SLP_OE Output enable of the pad. 1: enabled ; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled it; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if we

power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.50. RTCIO_PAD_DAC2_REG (0x0088)

E
RC
FO
D_
UN L
DA MU DAC

RT IO_ D_ AC SLP L

PA PD 2_ P_ L
_F SE

XP
AC FU OE
O_ D_ AC SL E

DA IE
_S

D_ AC SL IE
CI PA PD 2_ _S
C2 X_
PD 2_ LD

2_ N_
C_
D_ C2_ PD_

PD 2_ P_
C
O_ D_ AC RV

E
2_ E
D_ AC HO

RU
AC RD

DA
D

A X
2_

PA D _

2_

O_ _PD C2_

C PA PD 2_
2
AC

AC

RT _ _ C
D A

A
PD

CI PA PD

PD

RT PA PD

CI A D
P

P
D_

RT _ _

D_

O_ D_

RT O_ D_
D

)
RT PA

CI PA

PA

CI PA

RT PA

CI PA

ed
P
O_

RT IO_

O_

RT O_

RT _

rv
O

se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC2_DRV Select the drive strength of the pad. (R/W)

RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_PAD_PDAC2_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC2_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC2_DAC PAD DAC2 output value. (R/W)

RTCIO_PAD_PDAC2_XPD_DAC Power on DAC2. PDAC2 needs to be tristated if we power on the

DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC2_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pad. 0: select Function 0. (R/W)

RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)

RTCIO_PAD_PDAC2_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_SLP_OE Output enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if we

power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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4 IO_MUX and GPIO Matrix (GPIO, IO_MUX)

Register 4.51. RTCIO_XTAL_32K_PAD_REG (0x008C)

K
K
2N X_S L

32
CI XT X3 _S SEL
CI XT X3 FUN L

O_ AL 2 LP L

32
2K

2P U 2K

L_ 2N LP EL
U SE

L_ 2P LP_ L
E

E
X3 FUN E
E

DR UN E
RT XTA X3 _S SE

_X E

L_
X3 _S _IE

_S
_ _O

X3 _S IE
_3

L_
RT XTA _X3 _S _S

_I
X3 M 3
_M X_

_F _O
_I
X3 _R D

_
X3 _R D

TA
L_ 2N OL
CI XT X3 DRV

X3 RUE
2N DE

N P

2N LP

UN
L_ 2P OL
RV

UE

TA
2P DE

CI XT XP TAL

L_ 2N L

2P LP
O_ AL 2 L
A

_X
RT XTA _X3 _H

RT XTA _X3 XT
_D

RT XTA X3 _H

_R

CI XT X3 _S
_F
_

_
X

AS
C_

ES
_
2N

RT _ L_ N
2P

2P

RT O_ L_ 2P

P
O_ AL D
O_ AL 2

O_ AL 2

ed DBI
DA
X3

CI XT X3

X3

CI XT X3
L_

RT _ L_

L_

RT O_ AL_

L_

RT O_ L_

L_

RT O_ L_

L_

RT IO_ AL_

L_

L_
RT XTA

RT XTA

RT XTA

RT XTA

A
A

RT XTA

(re XTA

)
CI XT

CI XT

CI XT

CI XT

C T

XT
X
O_

RT IO_

O_

RT _

O_

RT _

O_

RT _

O_

RT O_

O_

O_

rv
O

se
CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI
C
RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

2 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

RTCIO_XTAL_X32N_DRV Select the drive strength of the pad. (R/W)

RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32N_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32N_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_X32P_DRV Select the drive strength of the pad. (R/W)

RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pad, 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32P_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32P_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_DAC_XTAL_32K 32K XTAL bias current DAC value. (R/W)

RTCIO_XTAL_XPD_XTAL_32K Power up 32 KHz crystal oscillator. (R/W)

RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pad to the digital IO_MUX; 1: route to RTC block.
(R/W)

RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pad to the digital IO_MUX; 1: route to RTC block.
(R/W)

RTCIO_XTAL_X32N_FUN_SEL Select the RTC function. 0: select function 0. (R/W)

RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)

RTCIO_XTAL_X32N_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32N_SLP_OE Output enable of the pad. 1: enabled; 0; disabled. (R/W)

RTCIO_XTAL_X32N_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32P_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.

(R/W)

RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)

RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

Continued on the next page...

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Register 4.51. RTCIO_XTAL_32K_PAD_REG (0x008C)

Continued from the previous page...

RTCIO_XTAL_X32P_SLP_OE Output enable of the pad in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_XTAL_X32P_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W)

RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W)

Register 4.52. RTCIO_TOUCH_CFG_REG (0x0090)

RE S
_D BIA

GE
FH

UR
AN
EF
UC PD_

DC
DR

DR
X
O_ CH_

H_
H

CH

CH

UC
RT TOU

)
TO

TO

TO

TO

ed
O_

O_

O_

O_

rv
se
CI

CI

CI

CI

CI

(re
RT

RT

RT

RT

31 30 29 28 27 26 25 24 23 22 0

0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W)

RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W)

RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W)

RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W)

RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is
available. (R/W)

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Register 4.53. RTCIO_TOUCH_PADn_REG (n: 0-7) (0x94+4*n)

FU EL

RT IO_T UC PA _SL EL

TO H D LP EL

IO
Dn D T

Dn UN E
O_ E
S
RT TOU PA _XP OP

_S

UC _PA n_S _IE

GP
PA _F _O
P _T T

O_ UC PA _S S

_T _I
Dn X_
D

RT TOU H_ Dn TAR

CI O _ n P_
N
PA HOL

AC

O_ CH_ ADn IE_

V

E
n_ E

H_ Dn LP
U
RU
R

AD RD

_M
_D

_D

O_ UC PA _S
_

) _P n_

_
Dn

Dn

Dn

CI O _ n

C O H_ Dn
ed H D

D
RT TOU PA

rv C A

PA

RT O_T UC PA

RT IO_T UC PA
P

P
O_ CH_

RT IO_T H_

se OU H_

H_

CI O H_

RT IO_T H_

C O _
H

H
C

(re O_T UC

UC

RT _T C

RT O_T UC
RT TOU

d)
CI O

TO

CI O

CI O

ve
RT O_T
O_

O_

r
se
CI

CI

CI

CI

CI
C

(re
RT

RT

RT
31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 0

0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_PADn_HOLD Write 1 to hold the current value of the output. (R/W)

RTCIO_TOUCH_PADn_DRV Selects the drive strength of the pad. A higher value corresponds with a
higher strength. For detailed drive strength, please see ESP32 Datasheet > Appendix A.1 Notes
on ESP32 Pin Lists > Note 8. (R/W)

RTCIO_TOUCH_PADn_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_TOUCH_PADn_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pad. Default is b’100.
(R/W)

RTCIO_TOUCH_PADn_START Write 1 to start touch sensor. (R/W)

RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option.

0: Tied to 0 V
1: Tied to VDD_RTC voltage
(R/W)

RTCIO_TOUCH_PADn_XPD Write 1 to power on the touch sensor. (R/W)

RTCIO_TOUCH_PADn_MUX_SEL Selects RTC IO_MUX or IO_MUX to control the IE/OE/RUE/RDE

statues of RTC pad.
1: Selects RTC IO_MUX
0: Selects IO_MUX
(R/W)

RTCIO_TOUCH_PADn_FUN_SEL Selects the function of the RTC.

0: RTC Function 0
1: Reserved
2: Reserved
3: RTC Function 1
(R/W)

RTCIO_TOUCH_PADn_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)

Continued on the next page...

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Register 4.53. RTCIO_TOUCH_PADn_REG (n: 0-7) (x94+4*n)

Continued from the previous page...

RTCIO_TOUCH_PADn_SLP_IE Input enable of the pad in sleep mode (SLP_SEL = 1).

1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_SLP_OE Output enable of the pad in sleep mode (SLP_SEL = 1).

1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_FUN_IE Input enable of the pad in normal working mode (SLP_SEL = 0).
1: Enabled
0: Disabled
(R/W)

RTCIO_TOUCH_PADn_TO_GPIO Controls the routing of touch pad input signals to IO_MUX.

1: The input signal from the touch pad is routed to IO_MUX through analog function.
0: The input signal from the touch pad is routed to IO_MUX through digital function.
(R/W)

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Register 4.54. RTCIO_TOUCH_PADm_REG (m = 8, 9) (0x00B4, 0x00B8)

IO
Dm XP PT

GP
UC _PA m_ ART
PA _ _O
AC

_T D
O_
H_ Dm TIE
TO H D ST
_D

O_ UC PA _
Dm

CI O H_ Dm
PA

RT _T C A P
H_

CI O _ H
UC

RT O_T UC
U
)

d)
TO

CI O
ed

ve
RT _T
O_
rv

r
se

se
CI

CI
(re

(re
RT

RT
31 26 25 23 22 21 20 19 16 0

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_PADm_DAC Touch sensor slope control. 3-bit for each touch pad. Default b’100.
(R/W)

RTCIO_TOUCH_PADm_START Write 1 to start touch sensor. (R/W)

RTCIO_TOUCH_PADm_TIE_OPT Default touch sensor tie option.

0: Tied to 0 V
1: Tied to VDD_RTC voltage
(R/W)

RTCIO_TOUCH_PADm_XPD Write 1 to power on the touch sensor. (R/W)

RTCIO_TOUCH_PADm_TO_GPIO Controls the routing of touch pad input signals to IO_MUX.

1: The input signal from the touch pad is routed to IO_MUX through analog function.
0: The input signal from the touch pad is routed to IO_MUX through digital function.
(R/W)

Register 4.55. RTCIO_EXT_WAKEUP0_REG (0x00BC)

E L
_S
P0
EU
AK
_W
XT

)
ed
E
O_

rv
se
CI

(re
RT

31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the
sleep mode. This register prompts the pad source to wake up the chip when the latter is in
deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W)

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Register 4.56. RTCIO_XTL_EXT_CTR_REG (0x00C0)

S EL
R_
CT
T_
_EX
TL

d)
X

ve
O_

r
se
CI

(re
RT

31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into
sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR
RTC_CNTL_XTL_EXT_CTR_LV is the crystal power down enable signal. (R/W)

Register 4.57. RTCIO_SAR_I2C_IO_REG (0x00C4)

L

L
SE

SE
A_

L_
SC
SD
C_

C_
I2

I2
R_

R_

)
SA

SA

ed
O_

O_

rv
se
CI

CI

(re
RT

RT

31 30 29 28 27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SAR_I2C_SDA_SEL Selects the other pad as the RTC I2C SDA signal. 0: pad
TOUCH_PAD[1]; 1: pad TOUCH_PAD[3]. Default value is 0. (R/W)

RTCIO_SAR_I2C_SCL_SEL Selects the other pad as the RTC I2C SCL signal. 0: pad
TOUCH_PAD[0]; 1: pad TOUCH_PAD[2]. Default value is 0. (R/W)

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5 DPort Registers

5.1 Introduction
The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve
optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock
management (clock gating), power management, and the configuration of peripherals and core-system mod-
ules. The system arranges each module with configuration registers contained in the DPort Register.

5.2 Features
DPort registers correspond to different peripheral blocks and core modules:

• System and memory

• Reset and clock

• Interrupt matrix

• DMA

• MPU/MMU

• APP_CPU controller

• Peripheral clock gating and reset

5.3 Functional Description

5.3.1 System and Memory Register
System and memory registers are used for system and memory configuration, such as cache configuration
and memory remapping. They are listed in Section 5.4, categorized as ”System and memory registers”. For a
detailed description of these registers, please refer to Chapter System and Memory.

5.3.2 Reset and Clock Registers

Reset and clock registers are listed in Section 5.4, categorized as ”Reset and clock registers”. For a detailed
description of these registers, please refer to Chapter Reset and Clock.

5.3.3 Interrupt Matrix Register

The interrupt matrix registers are used for configuring and mapping interrupts through the interrupt matrix. They
are listed in Section 5.4, categorized as ”Interrupt matrix registers”. For a detailed description of these registers,
please refer to Chapter Interrupt Matrix (INTERRUPT).

5.3.4 DMA Registers

DMA registers are used for the SPI DMA configuration. They are listed in Section 5.4, categorized as ”DMA
registers”. For a detailed description of these registers, please refer to Chapter DMA Controller (DMA).

5.3.5 MPU/MMU Registers

MPU/MMU registers are used for MPU/MMU configuration and operation control. They are listed in Section
5.4, categorized as ”MPU/MMU registers”. For a detailed description of these registers, please refer to Chapter
Memory Management and Protection Units (MMU, MPU).

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5.3.6 APP_CPU Controller Registers

APP_CPU controller registers are used for some basic configuration of the APP_CPU, such as performing a
stalling execution, and for configuring the ROM boot jump address. The registers are listed in Section 5.4,
categorized as ”APP_CPU controller registers”. A detailed description of these registers is provided in section
5.5. Note that reset bits are not self-clearing.

5.3.7 Peripheral Clock Gating and Reset

The following registers are used for controlling the clock gating and reset of different peripherals. A detailed
description of these registers is provided in section 5.5.

• DPORT_PERI_CLK_EN_REG

• DPORT_PERI_RST_EN_REG

• DPORT_PERIP_CLK_EN_REG

• DPORT_PERIP_RST_EN_REG

• DPORT_WIFI_CLK_EN_REG

• DPORT_WIFI_RST_EN_REG

Notice:

• Clock gating and reset registers are active high.

• Reset registers cannot be cleared by hardware. Therefore, SW reset clear is required after setting the reset
registers.

• ESP32 features low power consumption. This is why some peripheral clocks are gated (disabled) by
default. Before using any of these peripherals, it is mandatory to enable the clock for the given periph-
eral by setting the corresponding CLK_EN bit to 1, and release the peripheral from reset state to make it
operational by setting the RST_EN bit to 0.

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5.4 Register Summary

Name Description Address Access
System and memory registers
DPORT_PRO_BOOT_REMAP_CTRL_REG remap mode for PRO_CPU 0x3FF00000 R/W
DPORT_APP_BOOT_REMAP_CTRL_REG remap mode for APP_CPU 0x3FF00004 R/W
the mode of the two caches
DPORT_CACHE_MUX_MODE_REG 0x3FF0007C R/W
sharing the memory
Reset and clock registers
DPORT_CPU_PER_CONF_REG Selects CPU clock 0x3FF0003C R/W
Interrupt matrix registers
DPORT_CPU_INTR_FROM_CPU_0_REG interrupt 0 in both CPUs 0x3FF000DC R/W
DPORT_CPU_INTR_FROM_CPU_1_REG interrupt 1 in both CPUs 0x3FF000E0 R/W
DPORT_CPU_INTR_FROM_CPU_2_REG interrupt 2 in both CPUs 0x3FF000E4 R/W
DPORT_CPU_INTR_FROM_CPU_3_REG interrupt 3 in both CPUs 0x3FF000E8 R/W
DPORT_PRO_INTR_STATUS_REG_0_REG PRO_CPU interrupt status 0 0x3FF000EC RO
DPORT_PRO_INTR_STATUS_REG_1_REG PRO_CPU interrupt status 1 0x3FF000F0 RO
DPORT_PRO_INTR_STATUS_REG_2_REG PRO_CPU interrupt status 2 0x3FF000F4 RO
DPORT_APP_INTR_STATUS_REG_0_REG APP_CPU interrupt status 0 0x3FF000F8 RO
DPORT_APP_INTR_STATUS_REG_1_REG APP_CPU interrupt status 1 0x3FF000FC RO
DPORT_APP_INTR_STATUS_REG_2_REG APP_CPU interrupt status 2 0x3FF00100 RO
DPORT_PRO_MAC_INTR_MAP_REG interrupt map 0x3FF00104 R/W
DPORT_PRO_MAC_NMI_MAP_REG interrupt map 0x3FF00108 R/W
DPORT_PRO_BB_INT_MAP_REG interrupt map 0x3FF0010C R/W
DPORT_PRO_BT_MAC_INT_MAP_REG interrupt map 0x3FF00110 R/W
DPORT_PRO_BT_BB_INT_MAP_REG interrupt map 0x3FF00114 R/W
DPORT_PRO_BT_BB_NMI_MAP_REG interrupt map 0x3FF00118 R/W
DPORT_PRO_RWBT_IRQ_MAP_REG interrupt map 0x3FF0011C R/W
DPORT_PRO_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00120 R/W
DPORT_PRO_RWBT_NMI_MAP_REG interrupt map 0x3FF00124 R/W
DPORT_PRO_RWBLE_NMI_MAP_REG interrupt map 0x3FF00128 R/W
DPORT_PRO_SLC0_INTR_MAP_REG interrupt map 0x3FF0012C R/W
DPORT_PRO_SLC1_INTR_MAP_REG interrupt map 0x3FF00130 R/W
DPORT_PRO_UHCI0_INTR_MAP_REG interrupt map 0x3FF00134 R/W
DPORT_PRO_UHCI1_INTR_MAP_REG interrupt map 0x3FF00138 R/W
DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0013C R/W
DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00140 R/W
DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00144 R/W
DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00148 R/W
DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0014C R/W
DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00150 R/W
DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00154 R/W
DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00158 R/W
DPORT_PRO_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF0015C R/W
DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00160 R/W

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Name Description Address Access

DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00164 R/W
DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF00168 R/W
DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG Interrupt map 0x3FF0016C R/W
DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00170 R/W
DPORT_PRO_SPI_INTR_0_MAP_REG interrupt map 0x3FF00174 R/W
DPORT_PRO_SPI_INTR_1_MAP_REG interrupt map 0x3FF00178 R/W
DPORT_PRO_SPI_INTR_2_MAP_REG interrupt map 0x3FF0017C R/W
DPORT_PRO_SPI_INTR_3_MAP_REG interrupt map 0x3FF00180 R/W
DPORT_PRO_I2S0_INT_MAP_REG interrupt map 0x3FF00184 R/W
DPORT_PRO_I2S1_INT_MAP_REG interrupt map 0x3FF00188 R/W
DPORT_PRO_UART_INTR_MAP_REG interrupt map 0x3FF0018C R/W
DPORT_PRO_UART1_INTR_MAP_REG interrupt map 0x3FF00190 R/W
DPORT_PRO_UART2_INTR_MAP_REG interrupt map 0x3FF00194 R/W
DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF00198 R/W
DPORT_PRO_EMAC_INT_MAP_REG interrupt map 0x3FF0019C R/W
DPORT_PRO_PWM0_INTR_MAP_REG interrupt map 0x3FF001A0 R/W
DPORT_PRO_PWM1_INTR_MAP_REG interrupt map 0x3FF001A4 R/W
DPORT_PRO_LEDC_INT_MAP_REG interrupt map 0x3FF001B0 R/W
DPORT_PRO_EFUSE_INT_MAP_REG interrupt map 0x3FF001B4 R/W
DPORT_PRO_TWAI_INT_MAP_REG interrupt map 0x3FF001B8 R/W
DPORT_PRO_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF001BC R/W
DPORT_PRO_RMT_INTR_MAP_REG interrupt map 0x3FF001C0 R/W
DPORT_PRO_PCNT_INTR_MAP_REG interrupt map 0x3FF001C4 R/W
DPORT_PRO_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF001C8 R/W
DPORT_PRO_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF001CC R/W
DPORT_PRO_RSA_INTR_MAP_REG interrupt map 0x3FF001D0 R/W
DPORT_PRO_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF001D4 R/W
DPORT_PRO_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF001D8 R/W
DPORT_PRO_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF001DC R/W
DPORT_PRO_WDG_INT_MAP_REG interrupt map 0x3FF001E0 R/W
DPORT_PRO_TIMER_INT1_MAP_REG interrupt map 0x3FF001E4 R/W
DPORT_PRO_TIMER_INT2_MAP_REG interrupt map 0x3FF001E8 R/W
DPORT_PRO_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001EC R/W
DPORT_PRO_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF001F0 R/W
DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF001F4 R/W
DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF001F8 R/W
DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001FC R/W
DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00200 R/W
DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00204 R/W
DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF00208 R/W
DPORT_PRO_MMU_IA_INT_MAP_REG interrupt map 0x3FF0020C R/W
DPORT_PRO_MPU_IA_INT_MAP_REG interrupt map 0x3FF00210 R/W
DPORT_PRO_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00214 R/W

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Name Description Address Access

DPORT_APP_MAC_INTR_MAP_REG interrupt map 0x3FF00218 R/W
DPORT_APP_MAC_NMI_MAP_REG interrupt map 0x3FF0021C R/W
DPORT_APP_BB_INT_MAP_REG interrupt map 0x3FF00220 R/W
DPORT_APP_BT_MAC_INT_MAP_REG interrupt map 0x3FF00224 R/W
DPORT_APP_BT_BB_INT_MAP_REG interrupt map 0x3FF00228 R/W
DPORT_APP_BT_BB_NMI_MAP_REG interrupt map 0x3FF0022C R/W
DPORT_APP_RWBT_IRQ_MAP_REG interrupt map 0x3FF00230 R/W
DPORT_APP_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00234 R/W
DPORT_APP_RWBT_NMI_MAP_REG interrupt map 0x3FF00238 R/W
DPORT_APP_RWBLE_NMI_MAP_REG interrupt map 0x3FF0023C R/W
DPORT_APP_SLC0_INTR_MAP_REG interrupt map 0x3FF00240 R/W
DPORT_APP_SLC1_INTR_MAP_REG interrupt map 0x3FF00244 R/W
DPORT_APP_UHCI0_INTR_MAP_REG interrupt map 0x3FF00248 R/W
DPORT_APP_UHCI1_INTR_MAP_REG interrupt map 0x3FF0024C R/W
DPORT_APP_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00250 R/W
DPORT_APP_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00254 R/W
DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00258 R/W
DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0025C R/W
DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00260 R/W
DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00264 R/W
DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00268 R/W
DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0026C R/W
DPORT_APP_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF00270 R/W
DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00274 R/W
DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00278 R/W
DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF0027C R/W
DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG interrupt map 0x3FF00280 R/W
DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00284 R/W
DPORT_APP_SPI_INTR_0_MAP_REG interrupt map 0x3FF00288 R/W
DPORT_APP_SPI_INTR_1_MAP_REG interrupt map 0x3FF0028C R/W
DPORT_APP_SPI_INTR_2_MAP_REG interrupt map 0x3FF00290 R/W
DPORT_APP_SPI_INTR_3_MAP_REG interrupt map 0x3FF00294 R/W
DPORT_APP_I2S0_INT_MAP_REG interrupt map 0x3FF00298 R/W
DPORT_APP_I2S1_INT_MAP_REG interrupt map 0x3FF0029C R/W
DPORT_APP_UART_INTR_MAP_REG interrupt map 0x3FF002A0 R/W
DPORT_APP_UART1_INTR_MAP_REG interrupt map 0x3FF002A4 R/W
DPORT_APP_UART2_INTR_MAP_REG interrupt map 0x3FF002A8 R/W
DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF002AC R/W
DPORT_APP_EMAC_INT_MAP_REG interrupt map 0x3FF002B0 R/W
DPORT_APP_PWM0_INTR_MAP_REG interrupt map 0x3FF002B4 R/W
DPORT_APP_PWM1_INTR_MAP_REG interrupt map 0x3FF002B8 R/W
DPORT_APP_LEDC_INT_MAP_REG interrupt map 0x3FF002C4 R/W
DPORT_APP_EFUSE_INT_MAP_REG interrupt map 0x3FF002C8 R/W

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5 DPort Registers

Name Description Address Access

DPORT_APP_TWAI_INT_MAP_REG interrupt map 0x3FF002CC R/W
DPORT_APP_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF002D0 R/W
DPORT_APP_RMT_INTR_MAP_REG interrupt map 0x3FF002D4 R/W
DPORT_APP_PCNT_INTR_MAP_REG interrupt map 0x3FF002D8 R/W
DPORT_APP_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF002DC R/W
DPORT_APP_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF002E0 R/W
DPORT_APP_RSA_INTR_MAP_REG interrupt map 0x3FF002E4 R/W
DPORT_APP_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF002E8 R/W
DPORT_APP_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF002EC R/W
DPORT_APP_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF002F0 R/W
DPORT_APP_WDG_INT_MAP_REG interrupt map 0x3FF002F4 R/W
DPORT_APP_TIMER_INT1_MAP_REG interrupt map 0x3FF002F8 R/W
DPORT_APP_TIMER_INT2_MAP_REG interrupt map 0x3FF002FC R/W
DPORT_APP_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00300 R/W
DPORT_APP_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00304 R/W
DPORT_APP_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00308 R/W
DPORT_APP_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0030C R/W
DPORT_APP_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00310 R/W
DPORT_APP_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00314 R/W
DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00318 R/W
DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0031C R/W
DPORT_APP_MMU_IA_INT_MAP_REG interrupt map 0x3FF00320 R/W
DPORT_APP_MPU_IA_INT_MAP_REG interrupt map 0x3FF00324 R/W
DPORT_APP_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00328 R/W
DMA registers
selects DMA channel for
DPORT_SPI_DMA_CHAN_SEL_REG 0x3FF005A8 R/W
SPI1, SPI2, and SPI3
MPU/MMU registers
determines the virtual
DPORT_PRO_CACHE_CTRL_REG address mode of the 0x3FF00040 R/W
external SRAM
PRO cache MMU
DPORT_PRO_CACHE_CTRL1_REG 0x3FF00044 R/W
configuration
determines the virtual
DPORT_APP_CACHE_CTRL_REG address mode of the 0x3FF00058 R/W
external SRAM
APP cache MMU
DPORT_APP_CACHE_CTRL1_REG 0x3FF0005C R/W
configuration
page size in the MMU for the
DPORT_IMMU_PAGE_MODE_REG 0x3FF00080 R/W
internal SRAM 0
page size in the MMU for the
DPORT_DMMU_PAGE_MODE_REG 0x3FF00084 R/W
internal SRAM 2
DPORT_AHB_MPU_TABLE_0_REG MPU for configuring DMA 0x3FF000B4 R/W
DPORT_AHB_MPU_TABLE_1_REG MPU for configuring DMA 0x3FF000B8 R/W

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5 DPort Registers

Name Description Address Access

DPORT_AHBLITE_MPU_TABLE_UART_REG MPU for peripherals 0x3FF0032C R/W
DPORT_AHBLITE_MPU_TABLE_SPI1_REG MPU for peripherals 0x3FF00330 R/W
DPORT_AHBLITE_MPU_TABLE_SPI0_REG MPU for peripherals 0x3FF00334 R/W
DPORT_AHBLITE_MPU_TABLE_GPIO_REG MPU for peripherals 0x3FF00338 R/W
DPORT_AHBLITE_MPU_TABLE_RTC_REG MPU for peripherals 0x3FF00348 R/W
DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG MPU for peripherals 0x3FF0034C R/W
DPORT_AHBLITE_MPU_TABLE_HINF_REG MPU for peripherals 0x3FF00354 R/W
DPORT_AHBLITE_MPU_TABLE_UHCI1_REG MPU for peripherals 0x3FF00358 R/W
DPORT_AHBLITE_MPU_TABLE_I2S0_REG MPU for peripherals 0x3FF00364 R/W
DPORT_AHBLITE_MPU_TABLE_UART1_REG MPU for peripherals 0x3FF00368 R/W
DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG MPU for peripherals 0x3FF00374 R/W
DPORT_AHBLITE_MPU_TABLE_UHCI0_REG MPU for peripherals 0x3FF00378 R/W
DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG MPU for peripherals 0x3FF0037C R/W
DPORT_AHBLITE_MPU_TABLE_RMT_REG MPU for peripherals 0x3FF00380 R/W
DPORT_AHBLITE_MPU_TABLE_PCNT_REG MPU for peripherals 0x3FF00384 R/W
DPORT_AHBLITE_MPU_TABLE_SLC_REG MPU for peripherals 0x3FF00388 R/W
DPORT_AHBLITE_MPU_TABLE_LEDC_REG MPU for peripherals 0x3FF0038C R/W
DPORT_AHBLITE_MPU_TABLE_EFUSE_REG MPU for peripherals 0x3FF00390 R/W
DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG MPU for peripherals 0x3FF00394 R/W
DPORT_AHBLITE_MPU_TABLE_PWM0_REG MPU for peripherals 0x3FF0039C R/W
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG MPU for peripherals 0x3FF003A0 R/W
DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG MPU for peripherals 0x3FF003A4 R/W
DPORT_AHBLITE_MPU_TABLE_SPI2_REG MPU for peripherals 0x3FF003A8 R/W
DPORT_AHBLITE_MPU_TABLE_SPI3_REG MPU for peripherals 0x3FF003AC R/W
DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG MPU for peripherals 0x3FF003B0 R/W
DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG MPU for peripherals 0x3FF003B4 R/W
DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG MPU for peripherals 0x3FF003B8 R/W
DPORT_AHBLITE_MPU_TABLE_EMAC_REG MPU for peripherals 0x3FF003BC R/W
DPORT_AHBLITE_MPU_TABLE_PWM1_REG MPU for peripherals 0x3FF003C4 R/W
DPORT_AHBLITE_MPU_TABLE_I2S1_REG MPU for peripherals 0x3FF003C8 R/W
DPORT_AHBLITE_MPU_TABLE_UART2_REG MPU for peripherals 0x3FF003CC R/W
DPORT_AHBLITE_MPU_TABLE_PWR_REG MPU for peripherals 0x3FF003E4 R/W
MMU register 1 for internal
DPORT_IMMU_TABLE0_REG 0x3FF00504 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE1_REG 0x3FF00508 R/W
SRAM 0
MMU register 1 for Internal
DPORT_IMMU_TABLE2_REG 0x3FF0050C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE3_REG 0x3FF00510 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE4_REG 0x3FF00514 R/W
SRAM 0

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5 DPort Registers

Name Description Address Access

MMU register 1 for internal
DPORT_IMMU_TABLE5_REG 0x3FF00518 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE6_REG 0x3FF0051C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE7_REG 0x3FF00520 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE8_REG 0x3FF00524 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE9_REG 0x3FF00528 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE10_REG 0x3FF0052C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE11_REG 0x3FF00530 R/W
SRAM 0
MMU register 1 for Internal
DPORT_IMMU_TABLE12_REG 0x3FF00534 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE13_REG 0x3FF00538 R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE14_REG 0x3FF0053C R/W
SRAM 0
MMU register 1 for internal
DPORT_IMMU_TABLE15_REG 0x3FF00540 R/W
SRAM 0
MMU register 1 for Internal
DPORT_DMMU_TABLE0_REG 0x3FF00544 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE1_REG 0x3FF00548 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE2_REG 0x3FF0054C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE3_REG 0x3FF00550 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE4_REG 0x3FF00554 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE5_REG 0x3FF00558 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE6_REG 0x3FF0055C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE7_REG 0x3FF00560 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE8_REG 0x3FF00564 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE9_REG 0x3FF00568 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE10_REG 0x3FF0056C R/W
SRAM 2

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5 DPort Registers

Name Description Address Access

MMU register 1 for internal
DPORT_DMMU_TABLE11_REG 0x3FF00570 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE12_REG 0x3FF00574 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE13_REG 0x3FF00578 R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE14_REG 0x3FF0057C R/W
SRAM 2
MMU register 1 for internal
DPORT_DMMU_TABLE15_REG 0x3FF00580 R/W
SRAM 2
APP_CPU controller registers
DPORT_APPCPU_CTRL_REG_A_REG reset for APP_CPU 0x3FF0002C R/W
DPORT_APPCPU_CTRL_REG_B_REG clock gate for APP_CPU 0x3FF00030 R/W
DPORT_APPCPU_CTRL_REG_C_REG stall for APP_CPU 0x3FF00034 R/W
DPORT_APPCPU_CTRL_REG_D_REG boot address for APP_CPU 0x3FF00038 R/W
Peripheral clock gating and reset registers
DPORT_PERI_CLK_EN_REG clock gate for peripherals 0x3FF0001C R/W
DPORT_PERI_RST_EN_REG reset for peripherals 0x3FF00020 R/W
DPORT_PERIP_CLK_EN_REG clock gate for peripherals 0x3FF000C0 R/W
DPORT_PERIP_RST_EN_REG reset for peripherals 0x3FF000C4 R/W
DPORT_WIFI_CLK_EN_REG clock gate for Wi-Fi 0x3FF000CC R/W
DPORT_WIFI_RST_EN_REG reset for Wi-Fi 0x3FF000D0 R/W

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5 DPort Registers

5.5 Registers
The addresses in parenthesis besides register names are the register addresses relative to the DPORT base
address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute
register addresses are listed in Section 5.4 Register Summary.

Register 5.1. DPORT_PRO_BOOT_REMAP_CTRL_REG (0x000)

AP
EM
_R
OT
BO
O_
R
d)

_P
ve

RT
r
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PRO_BOOT_REMAP Remap mode for PRO_CPU. (R/W)

Register 5.2. DPORT_APP_BOOT_REMAP_CTRL_REG (0x004)

AP
EM
R
T_
OO
_B
PP
)
ed

_A
rv

RT
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APP_BOOT_REMAP Remap mode for APP_CPU. (R/W)

Register 5.3. DPORT_PERI_CLK_EN_REG (0x01C)

N_ A
RI N_ A

S
_E SH
PE E S

AE
T_ RI_ _R
OR PE _EN
DP RT_ ERI
)
ed

O P
DP RT_
rv
se

O
(re

DP

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PERI_EN_RSA Set the bit to enable the clock of RSA module. Clear the bit to disable the
clock of RSA module. (R/W)

DPORT_PERI_EN_SHA Set the bit to enable the clock of SHA module. Clear the bit to disable the
clock of SHA module. (R/W)

DPORT_PERI_EN_AES Set the bit to enable the clock of AES module. Clear the bit to disable the
clock of AES module. (R/W)

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5 DPort Registers

Register 5.4. DPORT_PERI_RST_EN_REG (0x020)

ST HA
RI ST_ A

ES
PE R RS

_A
_R S
T_ RI_ T_
OR PE _RS
DP RT_ ERI
d)

O P
ve

DP RT_
r
se

O
(re

DP
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_PERI_RST_RSA Set the bit to reset RSA module. Clear the bit to release RSA module. (R/W)

DPORT_PERI_RST_SHA Set the bit to reset SHA module. Clear the bit to release SHA module. (R/W)

DPORT_PERI_RST_AES Set the bit to reset AES module. Clear the bit to release AES module. (R/W)

Register 5.5. DPORT_APPCPU_CTRL_REG_A_REG (0x02C)

NG
I
E TT
ES
R
U_
CP
PP
)
ed

A
T_
rv

OR
se
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

DPORT_APPCPU_RESETTING Set to 1 to reset APP_CPU. Clear the bit to release APP_CPU. (R/W)

Register 5.6. DPORT_APPCPU_CTRL_REG_B_REG (0x030)

N
E _E
AT
KG
CL
U_
CP
PP
d)

_A
ve

RT
r
se

O
(re

DP

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APPCPU_CLKGATE_EN Set to 1 to enable the clock of APP_CPU. Clear the bit to disable
the clock of APP_CPU. (R/W)

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5 DPort Registers

Register 5.7. DPORT_APPCPU_CTRL_REG_C_REG (0x034)

ALL
ST
RUN
U_
CP
PP
d)

_A
ve

RT
r
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_APPCPU_RUNSTALL Set to 1 to put APP_CPU into stalled state. Clear the bit to release
APP_CPU from stalled state. (R/W)

Register 5.8. DPORT_APPCPU_CTRL_REG_D_REG (0x038)

31 0

0x000000000 Reset

DPORT_APPCPU_CTRL_REG_D_REG When APP_CPU is booted up with ROM code, it will jump to

the address stored in this register. (R/W)

Register 5.9. DPORT_CPU_PER_CONF_REG (0x03C)

L
SE
D_
IO
ER
P UP
_C
PU
)
ed

C
T_
rv

OR
se
(re

DP

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CPU_CPUPERIOD_SEL Select CPU clock. Refer to Table 3-3 for details. (R/W)

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5 DPort Registers

Register 5.10. DPORT_PRO_CACHE_CTRL_REG (0x040)

EN H_ NE
LE A
NA

E_ US DO
AB EN
_E

CH FL H_
M

CA E_ US
LE LIT
RA

O_ CH FL
NG SP
L

_I
_H

PR CA E_
SI _
M

O_ AM

T_ O_ CH
RA

PR DR

OR PR CA
_D

T_ O_

DP T_ O_
RO

OR PR

OR PR
)

)
ed

ed

ed

ed
P
T_

DP RT_

DP T_
rv

rv

rv

rv
OR

OR
se

se

se

se
O
(re

(re

(re

(re
DP

DP

DP
31 17 16 15 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

DPORT_PRO_DRAM_HL Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W)

DPORT_PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external

flash. (R/W)

DPORT_PRO_CACHE_FLUSH_DONE PRO_CPU cache-flush done. (RO)

DPORT_PRO_CACHE_FLUSH_ENA Flushes the PRO_CPU cache. (R/W)

DPORT_PRO_CACHE_ENABLE Enables the PRO_CPU cache. (R/W)

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5 DPort Registers

Register 5.11. DPORT_PRO_CACHE_CTRL1_REG (0x044)

O_ CH M K_ OM M
PR CA E_ S R A
CA E_ AS DR 0
T_ O_ CH MA _D DR

E_ AS IRO 1
M K_ M0
R

0
CH M K_ AM

IR 1
CL

K_ AM
AM
OR PR CA E_ ASK PS
A_

AS IR
DP RT_ RO_ ACH _M K_O
PD _I
U_ U

O P C E AS
M MM

DP RT_ RO_ ACH _M

CM E_

O P C E
O_ CH

DP RT_ RO_ ACH

PR CA

O P C
T_ O_

DP T_ O_
OR PR

OR PR
d)

)
ed
ve

DP RT_

DP RT_
rv
r
se

se
O

O
(re

(re
DP

DP
31 14 13 12 11 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Reset

DPORT_PRO_CACHE_MMU_IA_CLR Clears PRO cache MMU error flag. (R/W)

DPORT_PRO_CMMU_PD Disables PRO cache MMU. (R/W)

DPORT_PRO_CACHE_MASK_OPSDRAM Disables access from APP_CPU DRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_DROM0 Disables access from PRO_CPU DROM0 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_DRAM1 Disables access from PRO_CPU DRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IROM0 Disables access from PRO_CPU IROM0 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IRAM1 Disables access from PRO_CPU IRAM1 to PRO cache.

1: Disable
0: Enable
(R/W)

DPORT_PRO_CACHE_MASK_IRAM0 Disables access from PRO_CPU IRAM0 to PRO cache.

1: Disable
0: Enable
(R/W)

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5 DPort Registers

Register 5.12. DPORT_APP_CACHE_CTRL_REG (0x058)

EN H_ NE
LE A
NA

E_ US DO
AB EN
_E

CH FL H_
M

CA E_ US
LE LIT
RA

P_ CH FL
NG SP
L

_I
_H

AP CA E_
SI _
AM

P_ AM

T_ P_ CH
rv _DR

AP DR

OR AP CA
T_ _

DP T_ P_
P

P
(re _AP

OR AP

OR AP
)

OR )

)
ed

ed

ed
e

DP T_

DP T_
rv

rv

rv
T
OR

OR
se

se

se

se
(re

(re

(re
DP

DP

DP
31 15 14 13 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

DPORT_APP_DRAM_HL Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W)

DPORT_APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external

flash. (R/W)

DPORT_APP_CACHE_FLUSH_DONE APP_CPU cache-flush done. (RO)

DPORT_APP_CACHE_FLUSH_ENA Flushes the APP_CPU cache. (R/W)

DPORT_APP_CACHE_ENABLE Enables the APP_CPU cache. (R/W)

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5 DPort Registers

Register 5.13. DPORT_APP_CACHE_CTRL1_REG (0x05C)

AP CA E_ SK RO AM
CA E_ S R 0
T_ P_ CH MA _D DR

E_ AS IRO 1
M K_ M0
R

0
P_ CH MA _D M
CH M K_ AM

IR 1
CL

K_ AM
AM
OR AP CA E_ SK PS
A_

AS IR
DP RT_ PP_ CH MA K_O
PD _I
U_ U

O A CA E_ S
M MM

DP RT_ PP_ CH MA
CM E_

O A CA E_
P_ CH

DP RT_ PP_ CH
AP CA

O A CA
T_ P_

DP RT_ PP_
OR AP
d)

)
ed

O A
ve

DP RT_

DP RT_
rv
r
se

se
O

O
(re

(re
DP

DP
31 14 13 12 11 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Reset

DPORT_APP_CACHE_MMU_IA_CLR Clears APP cache MMU error flag. (R/W)

DPORT_APP_CMMU_PD Disables APP cache MMU. (R/W)

DPORT_APP_CACHE_MASK_OPSDRAM Disables access from PRO_CPU DRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_DROM0 Disables access from APP_CPU DROM0 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_DRAM1 Disables access from APP_CPU DRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IROM0 Disables access from APP_CPU IROM0 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IRAM1 Disables access from APP_CPU IRAM1 to APP cache.

1: Disable
0: Enable
(R/W)

DPORT_APP_CACHE_MASK_IRAM0 Disables access from APP_CPU IRAM0 to APP cache.

1: Disable
0: Enable
(R/W)

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5 DPort Registers

Register 5.14. DPORT_CACHE_MUX_MODE_REG (0x07C)

E
OD
_M
UX
M
E_
CH
CA
)
ed

T_
rv

OR
se
(re

DP
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)

Register 5.15. DPORT_IMMU_PAGE_MODE_REG (0x080)

E
OD
_M
GE
ed _PA
U
M
)

(re _IM

)
ed
rv

rv
T
OR
se

se
(re

DP
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)

Register 5.16. DPORT_DMMU_PAGE_MODE_REG (0x084)

E
OD
_M
GE
PA
U_
M
(re _DM
)

)
ed

ed
rv

rv
T
OR
se

se
(re

DP

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)

Register 5.17. DPORT_AHB_MPU_TABLE_0_REG (0x0B4)

31 0

0xFFFFFFFF Reset

DPORT_AHB_MPU_TABLE_0_REG MPU for DMA. (R/W)

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Register 5.18. DPORT_AHB_MPU_TABLE_1_REG (0x0B8)

1
T_
RAN
_G
SS
E
CC
_A
HB
)
ed

A
T_
rv

OR
se
(re

DP
31 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1FF Reset

DPORT_AHB_ACCESS_GRANT_1 MPU for DMA. (R/W)

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Register 5.19. DPORT_PERIP_CLK_EN_REG (0x0C0)

DP T_ NT LK N EN
DP RT_ HCI RO EN K_E
DP RT_ S1_ A_ EN EN

OR PC _C _E LK_

se I2 1_ E EN
O TW 1_ EN EN

O TI C K_ EN
O I2 DM K_ _

O U RG K_ L
DP RT_ ME CL 1_C
DP RT_ I_ CL CLK

(re RT_ RT LK_ LK_

DP RT_ WM K_ K_

DP RT_ ME LK_ EN
DP RT_ I3_ CL K_

DP RT_ DC CLK _C

DP RT_ I2 T0_ EN

K_ N
DP RT_ C_ LK_ EN

EN
DP RT_ HCI LK_ N
DP RT_ MT_ LK N

) CL EN
DP RT_ WM T1_ N

EN
DP rve S0 CLK N
DP RT_ US RO N

O d _CL _E
OR I2 0_ EN
O TI E_ UP

O LE 1_ UP
O P CL CL

O U C _E
O R _C _E
O SP 0_ CL

O SP EX K_
O SP 2_ _

O UA _C C
O P EX E
O I2 _C _

O EF RG E

K_
ed 1_ _
DP RT_ RT EM

DP RT_ AI CLK

DP T_ C_ CL

rv I0 LK
O UA _M

se SP _C
DP T_ RT

(re RT_ RT
OR UA

O UA
d)

se d)

DP RT_ )

DP RT_ )
O d
ve

(re rve
DP rve
r
se

se
(re

(re

31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

11111 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 Reset

Set the following bit to enable the clock of the corresponding module. Clear the bit to disable the
clock of the corresponding module.

DPORT_UART_MEM_CLK_EN Shared memory of UART0 ~ 2. To use any UART peripherals, enable

the clock for UART memory. (R/W)

DPORT_UART2_CLK_EN UART2 module. (R/W)

DPORT_SPI_DMA_CLK_EN SPI_DMA module. (R/W)

DPORT_I2S1_CLK_EN I2S1 module. (R/W)

DPORT_PWM1_CLK_EN PWM1 module. (R/W)

DPORT_TWAI_CLK_EN TWAI module. (R/W)

DPORT_I2C_EXT1_CLK_EN I2C1 module. (R/W)

DPORT_PWM0_CLK_EN PWM0 module. (R/W)

DPORT_SPI3_CLK_EN SPI3 module. (R/W)

DPORT_TIMERGROUP1_CLK_EN TIMG1 module. (R/W)

DPORT_EFUSE_CLK_EN eFuse module. (R/W)

DPORT_TIMERGROUP_CLK_EN TIMG0 module. (R/W)

DPORT_UHCI1_CLK_EN UDMA1 module. (R/W)

DPORT_LEDC_CLK_EN LEDC module. (R/W)

DPORT_PCNT_CLK_EN PCNT module. (R/W)

DPORT_RMT_CLK_EN RMT module. (R/W)

DPORT_UHCI0_CLK_EN UDMA0 module. (R/W)

DPORT_I2C_EXT0_CLK_EN I2C0 module. (R/W)

DPORT_SPI2_CLK_EN SPI2 module. (R/W)

Continued on the next page...

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Register 5.19. DPORT_PERIP_CLK_EN_REG (0x0C0)

Continued from the previous page...

DPORT_UART1_CLK_EN UART1 module. (R/W)

DPORT_I2S0_CLK_EN I2S0 module. (R/W)

DPORT_UART_CLK_EN UART0 module. (R/W)

DPORT_SPI01_CLK_EN SPI0 and SPI1 module. (R/W)

Register 5.20. DPORT_PERIP_RST_EN_REG (0x0C4)

ST

ST
DP RT_ ME RS 1_R
DP RT_ I_ RS RST

DP RT_ DC RST _R

(re RT_ RT ST ST
DP RT_ WM T T

DP RT_ I3_ RS T
O P RS RS

O TI E_ UP

P
O SP 0_ RS
O SP 2_ _

O UA _R R
U
O U RG T
O I2 DM T

O TI R T

O SP EX T
DP RT_ RT EM

DP rve S0 RST
DP T_ AI ST

DP RT_ I2 T0_
DP RT_ S1_ A_

T
DP RT_ MT_ ST
DP T_ NT ST
DP RT_ WM T1_

DP RT_ US RO

DP RT_ HCI RO

DP RT_ C_ RS

rv I0 ST
DP RT_ C_ ST

T
DP RT_ ME ST

DP T_ CI T

) RS
O d _RS
OR TW 1_R

OR UH RS
O UA _M

R
OR PC _R

se SP _R
O I2 0_
O EF RG
O I2 _R

se I2 1_
O P EX

O LE _

ed 1_
_
1
DP T_ RT

(re RT_ RT
OR UA

O UA
)

se d)

DP RT_ )

DP RT_ )
ed

O d

R
(re rve
DP rve
rv
se

se

O
(re

(re

31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

Set each bit to reset the corresponding module. Clear the bit to release the corresponding module. For the list
of modules, please refer to register 5.19.

Register 5.21. DPORT_WIFI_CLK_EN_REG (0x0CC)

EN

N
_E
T_

E
OS
IO EN

AV
_H

SL
SD C_

IO
K_ A
CL EM

SD
I_ _

K_
IF K
W CL

CL
T_ FI_

I_
IF
)

)
OR WI

W
ed

ed

ed
DP RT_

T_
rv

rv

rv
OR
se

se

se
O
(re

(re

(re
DP

DP

31 15 14 13 12 5 4 3 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset

DPORT_WIFI_CLK_EMAC_EN Set the bit to enable the clock of Ethernet MAC module. Clear the bit
to disable the clock of Ethernet MAC module. (R/W)

DPORT_WIFI_CLK_SDIO_HOST_EN Set the bit to enable the clock of SD/MMC module. Clear the
bit to disable the clock of SD/MMC module. (R/W)

DPORT_WIFI_CLK_SDIOSLAVE_EN Set the bit to enable the clock of SDIO module. Clear the bit to
disable the clock of SDIO module. (R/W)

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Register 5.22. DPORT_WIFI_RST_EN_REG (0x0D0)

T
ST RS
_R T_
T_ IO ST
IO OS
OR SD _R
SD _H
DP T_ AC
OR EM
d)

)
ed
ve

DP RT_

rv
r
se

se
O
(re

(re
DP
31 8 7 6 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_EMAC_RST Set the bit to reset Ethernet MAC module. Clear the bit to release Ethernet MAC
module. (R/W)

DPORT_SDIO_HOST_RST Set the bit to reset SD/MMC module. Clear the bit to release SD/MMC
module. (R/W)

DPORT_SDIO_RST Set the bit to reset SDIO module. Clear the bit to release SDIO module. (R/W)

Register 5.23. DPORT_CPU_INTR_FROM_CPU_n_REG (n: 0-3) (0xDC+4*n)

n
PU_
_C
M
RO
_F
TR
IN
U_
P
)
ed

_C
rv

RT
se

O
(re

DP
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_CPU_INTR_FROM_CPU_n Interrupt in both CPUs. (R/W)

Register 5.24. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 0-2) (0xEC+4*n)

31 0

0x000000000 Reset

DPORT_PRO_INTR_STATUS_REG_n_REG PRO_CPU interrupt status. (RO)

Register 5.25. DPORT_APP_INTR_STATUS_REG_n_REG (n: 0-2) (0xF8+4*n)

31 0

0x000000000 Reset

DPORT_APP_INTR_STATUS_REG_n_REG APP_CPU interrupt status. (RO)

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Register 5.26. DPORT_PRO_MAC_INTR_MAP_REG (0x104)

Register 5.27. DPORT_PRO_MAC_NMI_MAP_REG (0x108)

Register 5.28. DPORT_PRO_BB_INT_MAP_REG (0x10C)

Register 5.29. DPORT_PRO_BT_MAC_INT_MAP_REG (0x110)

Register 5.30. DPORT_PRO_BT_BB_INT_MAP_REG (0x114)

Register 5.31. DPORT_PRO_BT_BB_NMI_MAP_REG (0x118)

Register 5.32. DPORT_PRO_RWBT_IRQ_MAP_REG (0x11C)

Register 5.33. DPORT_PRO_RWBLE_IRQ_MAP_REG (0x120)

Register 5.34. DPORT_PRO_RWBT_NMI_MAP_REG (0x124)

Register 5.35. DPORT_PRO_RWBLE_NMI_MAP_REG (0x128)

Register 5.36. DPORT_PRO_SLC0_INTR_MAP_REG (0x12C)

Register 5.37. DPORT_PRO_SLC1_INTR_MAP_REG (0x130)

Register 5.38. DPORT_PRO_UHCI0_INTR_MAP_REG (0x134)

Register 5.39. DPORT_PRO_UHCI1_INTR_MAP_REG (0x138)

Register 5.40. DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (0x13C)

Register 5.41. DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (0x140)

Register 5.42. DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (0x144)

Register 5.43. DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (0x148)

Register 5.44. DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (0x14C)

Register 5.45. DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (0x150)

Register 5.46. DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (0x154)

Register 5.47. DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (0x158)

Register 5.48. DPORT_PRO_GPIO_INTERRUPT_MAP_REG (0x15C)

Register 5.49. DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (0x160)

Register 5.50. DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (0x164)

Register 5.51. DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (0x168)

Register 5.52. DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (0x16C)

Register 5.53. DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x170)

Register 5.54. DPORT_PRO_SPI_INTR_0_MAP_REG (0x174)

Register 5.55. DPORT_PRO_SPI_INTR_1_MAP_REG (0x178)

Register 5.56. DPORT_PRO_SPI_INTR_2_MAP_REG (0x17C)

Register 5.57. DPORT_PRO_SPI_INTR_3_MAP_REG (0x180)

Register 5.58. DPORT_PRO_I2S0_INT_MAP_REG (0x184)

Register 5.59. DPORT_PRO_I2S1_INT_MAP_REG (0x188)

Register 5.60. DPORT_PRO_UART_INTR_MAP_REG (0x18C)

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Register 5.61. DPORT_PRO_UART1_INTR_MAP_REG (0x190)

Register 5.62. DPORT_PRO_UART2_INTR_MAP_REG (0x194)

Register 5.63. DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (0x198)

Register 5.64. DPORT_PRO_EMAC_INT_MAP_REG (0x19C)

Register 5.65. DPORT_PRO_PWM0_INTR_MAP_REG (0x1A0)

Register 5.66. DPORT_PRO_PWM1_INTR_MAP_REG (0x1A4)

Register 5.67. DPORT_PRO_LEDC_INT_MAP_REG (0x1B0)

Register 5.68. DPORT_PRO_EFUSE_INT_MAP_REG (0x1B4)

Register 5.69. DPORT_PRO_TWAI_INT_MAP_REG (0x1B8)

Register 5.70. DPORT_PRO_RTC_CORE_INTR_MAP_REG (0x1BC)

Register 5.71. DPORT_PRO_RMT_INTR_MAP_REG (0x1C0)

Register 5.72. DPORT_PRO_PCNT_INTR_MAP_REG (0x1C4)

Register 5.73. DPORT_PRO_I2C_EXT0_INTR_MAP_REG (0x1C8)

Register 5.74. DPORT_PRO_I2C_EXT1_INTR_MAP_REG (0x1CC)

Register 5.75. DPORT_PRO_RSA_INTR_MAP_REG (0x1D0)

Register 5.76. DPORT_PRO_SPI1_DMA_INT_MAP_REG (0x1D4)

Register 5.77. DPORT_PRO_SPI2_DMA_INT_MAP_REG (0x1D8)

Register 5.78. DPORT_PRO_SPI3_DMA_INT_MAP_REG (0x1DC)

Register 5.79. DPORT_PRO_WDG_INT_MAP_REG (0x1E0)

Register 5.80. DPORT_PRO_TIMER_INT1_MAP_REG (0x1E4)

Register 5.81. DPORT_PRO_TIMER_INT2_MAP_REG (0x1E8)

Register 5.82. DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (0x1EC)

Register 5.83. DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (0x1F0)

Register 5.84. DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (0x1F4)

Register 5.85. DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (0x1F8)

Register 5.86. DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (0x1FC)

Register 5.87. DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (0x200)

Register 5.88. DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (0x204)

Register 5.89. DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (0x208)

Register 5.90. DPORT_PRO_MMU_IA_INT_MAP_REG (0x20C)

Register 5.91. DPORT_PRO_MPU_IA_INT_MAP_REG (0x210)

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Register 5.92. DPORT_PRO_CACHE_IA_INT_MAP_REG (0x214)

AP
M
*_
O_
PR
d)
ve

T_
r

OR
se
(re

DP
31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 Reset

DPORT_PRO_*_MAP Interrupt map. (R/W)

Register 5.93. DPORT_APP_MAC_INTR_MAP_REG (0x218)

Register 5.94. DPORT_APP_MAC_NMI_MAP_REG (0x21C)

Register 5.95. DPORT_APP_BB_INT_MAP_REG (0x220)

Register 5.96. DPORT_APP_BT_MAC_INT_MAP_REG (0x224)

Register 5.97. DPORT_APP_BT_BB_INT_MAP_REG (0x228)

Register 5.98. DPORT_APP_BT_BB_NMI_MAP_REG (0x22C)

Register 5.99. DPORT_APP_RWBT_IRQ_MAP_REG (0x230)

Register 5.100. DPORT_APP_RWBLE_IRQ_MAP_REG (0x234)

Register 5.101. DPORT_APP_RWBT_NMI_MAP_REG (0x238)

Register 5.102. DPORT_APP_RWBLE_NMI_MAP_REG (0x23C)

Register 5.103. DPORT_APP_SLC0_INTR_MAP_REG (0x240)

Register 5.104. DPORT_APP_SLC1_INTR_MAP_REG (0x244)

Register 5.105. DPORT_APP_UHCI0_INTR_MAP_REG (0x248)

Register 5.106. DPORT_APP_UHCI1_INTR_MAP_REG (0x24C)

Register 5.107. DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (0x250)

Register 5.108. DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (0x254)

Register 5.109. DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (0x258)

Register 5.110. DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (0x25C)

Register 5.111. DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (0x260)

Register 5.112. DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (0x264)

Register 5.113. DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (0x268)

Register 5.114. DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (0x26C)

Register 5.115. DPORT_APP_GPIO_INTERRUPT_MAP_REG (0x270)

Register 5.116. DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (0x274)

Register 5.117. DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (0x278)

Register 5.118. DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (0x27C)

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Register 5.119. DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (0x280)

Register 5.120. DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (0x284)

Register 5.121. DPORT_APP_SPI_INTR_0_MAP_REG (0x288)

Register 5.122. DPORT_APP_SPI_INTR_1_MAP_REG (0x28C)

Register 5.123. DPORT_APP_SPI_INTR_2_MAP_REG (0x290)

Register 5.124. DPORT_APP_SPI_INTR_3_MAP_REG (0x294)

Register 5.125. DPORT_APP_I2S0_INT_MAP_REG (0x298)

Register 5.126. DPORT_APP_I2S1_INT_MAP_REG (0x29C)

Register 5.127. DPORT_APP_UART_INTR_MAP_REG (0x2A0)

Register 5.128. DPORT_APP_UART1_INTR_MAP_REG (0x2A4)

Register 5.129. DPORT_APP_UART2_INTR_MAP_REG (0x2A8)

Register 5.130. DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (0x2AC)

Register 5.131. DPORT_APP_EMAC_INT_MAP_REG (0x2B0)

Register 5.132. DPORT_APP_PWM0_INTR_MAP_REG (0x2B4)

Register 5.133. DPORT_APP_PWM1_INTR_MAP_REG (0x2B8)

Register 5.134. DPORT_APP_LEDC_INT_MAP_REG (0x2C4)

Register 5.135. DPORT_APP_EFUSE_INT_MAP_REG (0x2C8)

Register 5.136. DPORT_APP_TWAI_INT_MAP_REG (0x2CC)

Register 5.137. DPORT_APP_RTC_CORE_INTR_MAP_REG (0x2D0)

Register 5.138. DPORT_APP_RMT_INTR_MAP_REG (0x2D4)

Register 5.139. DPORT_APP_PCNT_INTR_MAP_REG (0x2D8)

Register 5.140. DPORT_APP_I2C_EXT0_INTR_MAP_REG (0x2DC)

Register 5.141. DPORT_APP_I2C_EXT1_INTR_MAP_REG (0x2E0)

Register 5.142. DPORT_APP_RSA_INTR_MAP_REG (0x2E4)

Register 5.143. DPORT_APP_SPI1_DMA_INT_MAP_REG (0x2E8)

Register 5.144. DPORT_APP_SPI2_DMA_INT_MAP_REG (0x2EC)

Register 5.145. DPORT_APP_SPI3_DMA_INT_MAP_REG (0x2F0)

Register 5.146. DPORT_APP_WDG_INT_MAP_REG (0x2F4)

Register 5.147. DPORT_APP_TIMER_INT1_MAP_REG (0x2F8)

Register 5.148. DPORT_APP_TIMER_INT2_MAP_REG (0x2FC)

Register 5.149. DPORT_APP_TG_T0_EDGE_INT_MAP_REG (0x300)

Register 5.150. DPORT_APP_TG_T1_EDGE_INT_MAP_REG (0x304)

Register 5.151. DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (0x308)

Register 5.152. DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (0x30C)

Register 5.153. DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (0x310)

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Register 5.154. DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (0x314)

Register 5.155. DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (0x318)

Register 5.156. DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (0x31C)

Register 5.157. DPORT_APP_MMU_IA_INT_MAP_REG (0x320)

Register 5.158. DPORT_APP_MPU_IA_INT_MAP_REG (0x324)

Register 5.159. DPORT_APP_CACHE_IA_INT_MAP_REG (0x328)

AP
_M
_*
PP
d)

A
ve

T_
r

OR
se
(re

DP
31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 Reset

DPORT_APP_*_MAP Interrupt map. (R/W)

Register 5.160. DPORT_AHBLITE_MPU_TABLE_UART_REG (0x32C)

Register 5.161. DPORT_AHBLITE_MPU_TABLE_SPI1_REG (0x330)

Register 5.162. DPORT_AHBLITE_MPU_TABLE_SPI0_REG (0x334)

Register 5.163. DPORT_AHBLITE_MPU_TABLE_GPIO_REG (0x338)

Register 5.164. DPORT_AHBLITE_MPU_TABLE_RTC_REG (0x348)

Register 5.165. DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (0x34C)

Register 5.166. DPORT_AHBLITE_MPU_TABLE_HINF_REG (0x354)

Register 5.167. DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (0x358)

Register 5.168. DPORT_AHBLITE_MPU_TABLE_I2S0_REG (0x364)

Register 5.169. DPORT_AHBLITE_MPU_TABLE_UART1_REG (0x368)

Register 5.170. DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (0x374)

Register 5.171. DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (0x378)

Register 5.172. DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (0x37C)

Register 5.173. DPORT_AHBLITE_MPU_TABLE_RMT_REG (0x380)

Register 5.174. DPORT_AHBLITE_MPU_TABLE_PCNT_REG (0x384)

Register 5.175. DPORT_AHBLITE_MPU_TABLE_SLC_REG (0x388)

Register 5.176. DPORT_AHBLITE_MPU_TABLE_LEDC_REG (0x38C)

Register 5.177. DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (0x390)

Register 5.178. DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (0x394)

Register 5.179. DPORT_AHBLITE_MPU_TABLE_PWM0_REG (0x39C)

Register 5.180. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (0x3A0)

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Register 5.181. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (0x3A4)

Register 5.182. DPORT_AHBLITE_MPU_TABLE_SPI2_REG (0x3A8)

Register 5.183. DPORT_AHBLITE_MPU_TABLE_SPI3_REG (0x3AC)

Register 5.184. DPORT_AHBLITE_MPU_TABLE_SYSCON_REG (0x3B0)

Register 5.185. DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (0x3B4)

Register 5.186. DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (0x3B8)

Register 5.187. DPORT_AHBLITE_MPU_TABLE_EMAC_REG (0x3BC)

Register 5.188. DPORT_AHBLITE_MPU_TABLE_PWM1_REG (0x3C4)

Register 5.189. DPORT_AHBLITE_MPU_TABLE_I2S1_REG (0x3C8)

Register 5.190. DPORT_AHBLITE_MPU_TABLE_UART2_REG (0x3CC)

Register 5.191. DPORT_AHBLITE_MPU_TABLE_PWR_REG (0x3E4)

IG
NF
CO
T_
AN
GR
S_
ES
C
AC
*_
E_
T
LI
HB
)
ed

A
T_
rv

OR
se
(re

DP
31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_AHBLITE_*_ACCESS_GRANT_CONFIG MPU for peripherals. (R/W)

Register 5.192. DPORT_IMMU_TABLEn_REG (n: 0-15) (0x504+4*n) n

BLE
TA
U_
M
M
d)

I
ve

T_
r

OR
se
(re

DP

31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000 Reset

DPORT_IMMU_TABLEn MMU for internal SRAM. When n is 0 ~ 9, the reset value is 0. When n is 10
~ 15, the reset value is 10, 11, 12, 13, 14, 15, respectively. (R/W)

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Register 5.193. DPORT_DMMU_TABLEn_REG (n: 0-15) (0x544+4*n)

En
BL
TA
U_
M
M
d)

D
ve

T_
r

OR
se
(re

DP
31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000 Reset

DPORT_DMMU_TABLEn MMU for internal SRAM. When n is 0 ~ 15, the reset value is 0 ~ 15, respec-
tively. (R/W)

Register 5.194. DPORT_SPI_DMA_CHAN_SEL_REG (0x5A8)

EL
L

EL
E

_S
_S

_S
AN
AN

AN
CH
CH

CH
A_
A_

A_
M
M

DM
_D
_D

I1_
I2
I3
P

P
_S

_S

_S
PI

PI

PI
)
ed

S
T_

T_

T_
rv

OR

OR

OR
se
(re

DP

DP

DP
31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DPORT_SPI_SPI3_DMA_CHAN_SEL Selects DMA channel for SPI3. (R/W)

DPORT_SPI_SPI2_DMA_CHAN_SEL Selects DMA channel for SPI2. (R/W)

DPORT_SPI_SPI1_DMA_CHAN_SEL Selects DMA channel for SPI1. (R/W)

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6 DMA Controller (DMA)

6.1 Overview
Direct Memory Access (DMA) is used for high-speed data transfer between peripherals and memory, as well as
from memory to memory. Data can be quickly moved with DMA without any CPU intervention, thus allowing for
more efficient use of the cores when processing data.

In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1,
SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.

6.2 Features
The DMA controllers in the ESP32 feature:

• AHB bus architecture

• Support for full-duplex and half-duplex data transfers

• Programmable data transfer length in bytes

• Support for 4-beat burst transfer

• 328 KB DMA address space

• All high-speed communication modules powered by DMA

6.3 Functional Description

All modules that require high-speed data transfer in bulk contain a DMA controller. DMA addressing uses the
same data bus as the CPU to read/write to the internal RAM.

Each DMA controller features different functions. However, the architecture of the DMA engine (DMA_ENGINE)
is the same in all DMA controllers.

6.3.1 DMA Engine Architecture

Figure 6-1. DMA Engine Architecture

The DMA Engine accesses SRAM over the AHB BUS. In Figure 6-1, the RAM represents the internal SRAM banks
available on ESP32. Further details on the SRAM addressing range can be found in Chapter System and Memory.

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Software can use a DMA Engine by assigning a linked list to define the DMA operational parameters.

The DMA Engine transmits the data from the RAM to a peripheral, according to the contents of the out_link
descriptor. Also, the DMA Engine stores the data received from a peripheral into a specified RAM location,
according to the contents of the in_link descriptor.

6.3.2 Linked List

Figure 6-2. Linked List Structure

The DMA descriptor’s linked lists (out_link and in_link) have the same structure. As shown in Figure 6-2, a
linked-list descriptor consists of three words. The meaning of each field is as follows:

• owner (DW0) [31]: The allowed operator of the buffer corresponding to the current linked list.
1’b0: the allowed operator is the CPU;
1’b1: the allowed operator is the DMA controller.

• eof (DW0) [30]: End-Of-File character.

1’b0: the linked-list item does not mark the end of the linked list;
1’b1: the linked-list item is at the end of the linked list.

• reserved (DW0) [29:24]: Reserved bits.

Software should not write 1’s in this space.

• length (DW0) [23:12]: The number of valid bytes in the buffer corresponding to the current linked list. The
field value indicates the number of bytes to be transferred to/from the buffer denoted by word DW1.

• size (DW0) [11:0]: The size of the buffer corresponding to the current linked list.
NOTE: The size must be word-aligned.

• buffer address pointer (DW1): Buffer address pointer. This is the address of the data buffer.
NOTE: The buffer address must be word-aligned.

• next descriptor address (DW2): The address pointer of the next linked-list item. The value is 0, if the
current linked-list item is the last on the list (eof=1).

When receiving data, if the data transfer length is smaller than the specified buffer size, DMA will not use
the remaining space. This enables the DMA engine to be used for transferring an arbitrary number of data
bytes.

6.4 UART DMA (UDMA)

The ESP32 has three UART interfaces that share two UDMA (UART DMA) controllers. The UHCI_UARTx_CE (x
is 0, 1, or 2) is used for selecting the UART controller to use the UDMA.

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Figure 6-3. Data Transfer in UDMA Mode

Figure 6-3 shows the data transfer in UDMA mode. Before the DMA Engine receives data, software must initialize
the receive-linked-list. UHCI_INLINK_ADDR is used to point to the first in_link descriptor. The register must be
programmed with the lower 20 bits of the address of the initial linked-list item. After UHCI_INLINK_START is
set, the Universal Host Controller Interface (UHCI) will transmit the data received by UART to the Decoder. After
being parsed, the data will be stored in the RAM as specified by the receive-linked-list descriptor.

Before DMA transmits data, software must initialize the transmit-linked-list and the data to be transferred. UHCI_
OUTLINK_ADDR is used to point to the first out_link descriptor. The register must be programmed with the lower
20 bits of the address of the initial transmit-linked-list item. After UHCI_OUTLINK_START is set, the DMA Engine
will read data from the RAM location specified by the linked-list descriptor and then transfer the data through
the Encoder. The DMA Engine will then shift the data out serially through the UART transmitter.

The UART DMA follows a format of (separator + data + separator). The Encoder is used for adding separa-
tors before and after data, as well as using special-character sequences to replace data that are the same
as separators. The Decoder is used for removing separators before and after data, as well as replacing the
special-character sequences with separators. There can be multiple consecutive separators marking the be-
ginning or end of data. These separators can be configured through UHCI_SEPER_CH, with the default val-
ues being 0xC0. Data that are the same as separators can be replaced with UHCI_ESC_SEQ0_CHAR0 (0xDB
by default) and UHCI_ESC_SEQ0_CHAR1 (0xDD by default). After the transmission process is complete, a
UHCI_OUT_TOTAL_EOF_INT interrupt will be generated. After the reception procedure is complete, a UHCI_IN_
SUC_EOF_INT interrupt will be generated.

Note:
Please note that the buffer address pointer field in in_link descriptors should be word-aligned, and the size field in the
last in_link descriptor should be at least 4 bytes larger than the length of received data.

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6.5 SPI DMA Interface

Figure 6-4. SPI DMA

ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from
Figure 6-4, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be used
by any one SPI controller at any given time.

The ESP32 SPI DMA Engine also uses a linked list to receive/transmit data. Burst transmission is supported. The
data size for a single transfer must be four bytes aligned. Consecutive data transfer is also supported.

SPI1_DMA_CHAN_SEL[1:0], SPI2_DMA_CHAN_SEL[1:0] and SPI3_DMA_CHAN_SEL[1:0] in DPORT_SPI_DMA_

CHAN_SEL_REG must be configured to enable the SPI DMA interface for a specific SPI controller. Each SPI
controller corresponds to one domain which has two bits with values 0, 1 and 2. Value 3 is reserved and must
not be configured for operation.

Considering SPI1 as an example,

if SPI SPI1_DMA_CHAN_SEL[1:0] = 0, then SPI1 does not use any DMA channel;
if SPI1_DMA_CHAN_SEL[1:0] = 1, then SPI1 enables DMA channel1;
if SPI1_DMA_CHAN_SEL[1:0] = 2, then SPI1 enables DMA channel2.

The SPI_OUTLINK_START bit in SPI_DMA_OUT_LINK_REG and the SPI_INLINK_START bit in SPI_DMA_IN_LINK_REG

are used for enabling the DMA Engine. The two bits are self-cleared by hardware. When SPI_OUTLINK_START
is set to 1, the DMA Engine starts processing the outbound linked list descriptor and prepares to transmit data.
When SPI_INLINK_START is set to 1, then the DMA Engine starts processing the inbound linked-list descriptor
and gets prepared to receive data.

Software should configure the SPI DMA as follows:

1. Reset the DMA state machine and FIFO parameters;

2. Configure the DMA-related registers for operation;

3. Configure the SPI-controller-related registers accordingly;

4. Set SPI_USR to enable DMA operation.

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6.6 I2S DMA Interface

The ESP32 integrates two I2S modules, I2S0 and I2S1, each of which is powered by a DMA channel. The
REG_I2S_DSCR_EN bit in I2S_FIFO_CONF_REG is used for enabling the DMA operation. ESP32 I2S DMA
uses the standard linked-list descriptor to configure DMA operations for data transfer. Burst transfer is sup-
ported. However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.
REG_I2S_RX_EOF_NUM[31:0] bit in I2S_RXEOF_NUM_REG is used for configuring the data size of a single trans-
fer operation, in multiples of one word.

I2S_OUTLINK_START bit in I2S_OUT_LINK_REG and I2S_INLINK_START bit in I2S_IN_LINK_REG are used for en-
abling the DMA Engine and are self-cleared by hardware. When I2S_OUTLINK_START is set to 1, the DMA Engine
starts processing the outbound linked-list descriptor and gets prepared to send data. When I2S_INLINK_START
is set to 1, the DMA Engine starts processing the inbound linked-list descriptor and gets prepared to receive
data.

Software should configure the I2S DMA as follows:

1. Configure I2S-controller-related registers;

2. Reset the DMA state machine and FIFO parameters;

3. Configure DMA-related registers for operation;

4. In I2S master mode, set I2S_TX_START bit or I2S_RX_START bit to initiate an I2S operation;
In I2S slave mode, set I2S_TX_START bit or I2S_RX_START bit and wait for data transfer to be initiated by
the host device.

For more information on I2S DMA interrupts, please see Section DMA Interrupts, in Chapter I2S.

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7 SPI Controller (SPI)

7.1 Overview

Figure 7-1. SPI Architecture

As Figure 7-1 shows, ESP32 integrates four SPI controllers which can be used to communicate with external
devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller
SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When
used as a master, each SPI controller can drive multiple CS signals (CS0~CS2) to activate multiple slaves.
Controllers SPI1~SPI3 share two DMA channels.

The SPI signal buses consist of D, Q, CS0-CS2, CLK, WP, and HD signals, as Table 7-1 shows. Controllers SPI0
and SPI1 share one signal bus through an arbiter; the signals of the shared bus start with “SPI”. Controllers SPI2
and SPI3 use signal buses starting with “HSPI” and “VSPI” respectively. The I/O lines included in the above-
mentioned signal buses can be mapped to pins via either the IO_MUX module or the GPIO matrix. (Please refer
to Chapter IO_MUX for details.)

The SPI controller supports four-line full-duplex/half-duplex communication (MOSI, MISO, CS, and CLK lines)
and three-line half-duplex-only communication (DATA, CS, and CLK lines) in GP-SPI mode. In QSPI mode, an
SPI controller accesses the flash or SRAM by using signal buses D, Q, CS0~CS2, CLK, WP, and HD as a four-bit
parallel SPI bus. The mapping between SPI bus signals and pin function signals under different communication
modes is shown in Table 7-1.

Table 7-1. Mapping Between SPI Bus Signals and Pin Function Signals

Four-line GP-SPI Three-line GP-SPI QSPI Pin function signals

Full-duplex/half- Half-duplex signal Signal bus SPI signal HSPI signal VSPI signal
duplex signal bus bus bus bus bus
MOSI DATA D SPID HSPID VSPID
MISO - Q SPIQ HSPIQ VSPIQ
CS CS CS SPICS0 HSPICS0 VSPICS0
CLK CLK CLK SPICLK HSPICLK VSPICLK
- - WP SPIWP HSPIWP VSPIWP
- - HD SPIHD HSPIHD VSPIHD

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7.2 SPI Features

General Purpose SPI (GP-SPI)

• Programmable data transfer length, in multiples of 1 byte

• Four-line full-duplex/half-duplex communication and three-line half-duplex communication support

• Master mode and slave mode

• Programmable CPOL and CPHA

• Programmable clock

Parallel QSPI

• Communication format support for specific slave devices such as flash

• Programmable communication format

• Six variations of flash-read operations available

• Automatic shift between flash and SRAM access

• Automatic wait states for flash access

SPI DMA Support

• Support for sending and receiving data using linked lists

SPI Interrupt Hardware

• SPI interrupts

• SPI DMA interrupts

7.3 GP-SPI
The SPI master mode supports four-line full-duplex/half-duplex communication and three-line half-duplex com-
munication. Figure 7-2 outlines the connections needed for four-line full-duplex/half-duplex communications.

Figure 7-2. SPI Master and Slave Full-duplex/Half-duplex Communication

The SPI1~SPI3 controllers can communicate with other slaves as a standard SPI master. SPI2 and SPI3 can be
configured as either a master or a slave. Every SPI master can be connected to three slaves at most by default.
When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data length is in
multiples of one byte.

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Table 7-2. Command Definitions Supported by GP-SPI Slave in Half-duplex Mode

Command Description
0x1 Received by slave; writes data sent by the master into the slave status register via MOSI.
0x2 Received by slave; writes data sent by the master into the slave data buffer via MOSI.
0x3 Sent by slave; sends data in the slave buffer to master via MISO.
0x4 Sent by slave; sends data in the slave status register to master via MISO.
Writes master data on MOSI into data buffer and then sends the date in the slave data buffer
0x6
to MISO.

7.3.1 GP-SPI Four-line Full-duplex Communication

When configured to four-line full-duplex mode, the ESP32 SPI can act as either a master or a slave. The length
of received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG
registers for master mode as well as SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for
slave mode. The SPI_DOUTDIN bit and SPI_USR_MOSI bit in register SPI_USER_REG should be configured to
enable this communication mode. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize
a data transfer.

7.3.2 GP-SPI Four-line Half-duplex Communication

When configured to four-line half-duplex mode, the ESP32 SPI can act as either a master or a slave. In this
mode, the SPI communication supports flexible communication format as: command + address + dummy phase
+ received and/or sent data. The format is specified as follows:

1. command: length of 0~16 bits; Master Out Slave In (MOSI).

2. address: length of 0~32/64 bits; Master Out Slave In (MOSI).

3. dummy phase: length of 0~256 SPI clocks.

4. received and/or sent data: length of 0~512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave
Out (MISO).

The address length is up to 32 bits in GP-SPI master mode and 64 bits in QSPI master mode. The command
phase, address phase, dummy phase and received/sent data phase are controlled by bits SPI_USR_COMMAND,
SPI_USR_ADDR, SPI_USR_DUMMY, and SPI_USR_MISO/SPI_USR_MOSI respectively in register SPI_USER_REG.
A certain phase is enabled only when its corresponding control bit is set to 1. Details can be found in register
description. When SPI works as a master, the register can be configured by software as required to determine
whether or not to enable a certain phase.

When SPI works as a slave, the communication format must contain command, address, received and/or sent
data, among which the command has several options listed in Table 7-2. During data transmission or reception,
the CS signal should keep logic level low. If the CS signal is pulled up during transmission, the internal state of
the slave will be reset.

The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from
register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK bit in
register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and writing
slave status register, thus realizing complex communication with ease.

The length of received and sent data is controlled by SPI_MISO_DLEN_REG and SPI_MOSI_DLEN_REG in master
mode, as well as SPI_SLV_RDBUF_DLEN_REG and SPI_SLV_WRBUF_DLEN_REG in slave mode. A reception or

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transmission of data is controlled by bit SPI_USR_MOSI or SPI_USR_MISO in SPI_USER_REG. The SPI_USR bit
in register SPI_CMD_REG needs to be configured to initialize a data transfer.

7.3.3 GP-SPI Three-line Half-duplex Communication

The three-line half-duplex communication differs from four-line half-duplex communication in that the reception
and transmission shares one signal bus and that the communication format must contain command, address,
received and/or sent data. Software can enable three-line half-duplex communication by configuring SPI_SIO
bit in SPI_USER_REG register.

Note:

• In half-duplex communication, the order of command, address, received and/or sent data in the communication
format should be followed strictly.

• In half-duplex communication, communication formats ”command + address + received data + sent data” and
”received data + sent data” are not applicable to DMA.

• When ESP32 SPI acts as a slave, the master CS should be active at least one SPI clock period before a read/write
process is initiated, and should be inactive at least one SPI clock period after the read/write process is com-
pleted.

7.3.4 GP-SPI Data Buffer

Figure 7-3. SPI Data Buffer

ESP32 SPI has 16 × 32 bits of data buffer to buffer data-send and data-receive operations. As is shown in Figure
7-3, received data is written from the low byte of SPI_W0_REG by default and the writing ends with SPI_W15_REG.
If the data length is over 64 bytes, the extra part will be written from SPI_W0_REG.

Data buffer blocks SPI_W0_REG ~ SPI_W7_REG and SPI_W8_REG ~ SPI_W15_REG data correspond to the
lower part and the higher part respectively. They can be used separately, and are controlled by the SPI_USR_MOSI
_HIGHPART bit and the SPI_USR_MISO_HIGHPART bit in register SPI_USER_REG. For example, if SPI is config-
ured as a master, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for
sending data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for re-
ceiving data. If SPI acts as a slave, when SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are
used as buffer for receiving data; when SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used
as buffer for sending data.

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Table 7-3. Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master

Registers mode0 mode1 mode2 mode3

SPI_CK_IDLE_EDGE 0 0 1 1
SPI_CK_OUT_EDGE 0 1 1 0
SPI_MISO_DELAY_MODE 2(0) 1(0) 1(0) 2(0)
SPI_MISO_DELAY_NUM 0 0 0 0
SPI_MOSI_DELAY_MODE 0 0 0 0
SPI_MOSI_DELAY_NUM 0 0 0 0

7.4 GP-SPI Clock Control

The maximum output clock frequency of ESP32 GP-SPI master is fapb /2, and the maximum input clock fre-
quency of the ESP32 GP-SPI slave is fapb /8. The master can derive other clock frequencies via frequency
division.

fapb
fspi =
(SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1)

SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to 7.7 Register De-
scription for details). SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1
2 –1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L. When the SPI_CLK_EQU_SYSCLK
bit in register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output clock frequency is
fapb . For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. In slave mode, SPI_CLKCNT_N,
SPI_CLKCNT_L, SPI_CLKCNT_H and SPI_CLKDIV_PRE should all be 0.

7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA)

The clock polarity and clock phase of ESP32 SPI are controlled by SPI_CK_IDLE_EDGE bit in register SPI_PIN_REG,
SPI_CK_OUT_EDGE bit and SPI_CK_I_EDGE bit in register SPI_USER_REG, as well as SPI_MISO_DELAY_MODE[1:0]
bit, SPI_MISO_DELAY_NUM[2:0] bit, SPI_MOSI_DELAY_MODE[1:0] bit, SPI_MOSI_DELAY_MUM[2:0] bit in reg-
ister SPI_CTRL2_REG. Table 7-3 and Table 7-4 show the clock polarity and phase as well as the corresponding
register values for ESP32 SPI master and slave, respectively. Note that for mode0 and mode2 in Table 7-4, the
registers are configured differently in non-DMA mode and DMA mode, and that the SPI slave data is output in
advance in DMA mode.

Table 7-4. Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave

Registers mode0 mode1 mode2 mode3

Non-DMA DMA Non-DMA DMA
SPI_CK_IDLE_EDGE 1 0 1 0 1 0
SPI_CK_I_EDGE 0 1 1 1 0 0
SPI_MISO_DELAY_MODE 0 0 2 0 0 1
SPI_MISO_DELAY_NUM 0 2 0 0 2 0
SPI_MOSI_DELAY_MODE 2 0 0 1 0 0
SPI_MOSI_DELAY_NUM 2 3 0 2 3 0

1. mode0 means CPOL=0, CPHA=0. When SPI is idle, the clock output is logic low; data changes on the
falling edge of the SPI clock and is sampled on the rising edge;

2. mode1 means CPOL=0, CPHA=1. When SPI is idle, the clock output is logic low; data changes on the
rising edge of the SPI clock and is sampled on the falling edge;
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3. mode2 means when CPOL=1, CPHA=0. When SPI is idle, the clock output is logic high; data changes on
the rising edge of the SPI clock and is sampled on the falling edge;

4. mode3 means when CPOL=1, CPHA=1. When SPI is idle, the clock output is logic high; data changes on
the falling edge of the SPI clock and is sampled on the rising edge.

7.4.2 GP-SPI Timing

The data signals of ESP32 GP-SPI can be mapped to physical pins either via IO_MUX or via IO_MUX and GPIO
matrix. Input signals will be delayed by two clkapb clock cycles when they pass through the matrix. Output
signals will not be delayed.

When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if GP-
SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 when configuring
the clock polarity. If GP-SPI output clock frequency is not higher than clkapb /4, register SPI_MISO_DELAY_MODE
can be set to the corresponding value in Table 7-3 when configuring the clock polarity.

When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix:

1. If GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 and the
dummy phase should be enabled (SPI_USR_DUMMY = 1) for one clkspi clock cycle (SPI_USR_DUMMY_CYC
LELEN = 0) when configuring the clock polarity;

2. If GP-SPI output clock frequency is clkapb /4, register SPI_MISO_DELAY_MODE should be set to 0 when
configuring the clock polarity;

3. If GP-SPI output clock frequency is not higher than clkapb /8, register SPI_MISO_DELAY_MODE can be set
to the corresponding value in Table 7-3 when configuring the clock polarity.

When GP-SPI is used in slave mode, the clock signal and the data signals should be routed to the SPI controller
via the same path, i.e., neither the clock signal nor the data signals passes through GPIO matrix, or both of
them pass through GPIO matrix. This is important in ensuring that the signals are not delayed by different time
periods before they reach the SPI hardware.

Assume that tspi , tpre and tv in Figure 7-4 denote SPI clock period, how far ahead data output is, and data output
delay time, respectively. Assume the SPI slave’s main clock period is tapb . For non-DMA mode0, SPI slave data
output is delayed by tv :

• tv < 3.5 ∗ tapb , if CLK does not pass through GPIO matrix;

• tv < 5.5 ∗ tapb , if CLK passes through GPIO matrix.

In DMA mode1 and mode3, SPI slave data output is delayed by the same period of time as in non-DMA mode.
However, for mode0 and mode2, SPI slave data is output earlier by tpre :

• tpre < (tspi /2 − 5.5 ∗ tapb ), if CLK does not pass through GPIO matrix;

• tpre < (tspi /2 − 7.5 ∗ tapb ), if CLK passes through GPIO matrix.

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Figure 7-4. GP-SPI ������

To conclude, if signals do not pass through GPIO matrix, the SPI slave clock frequency is up to fapb /8; if signals
pass through GPIO matrix, the SPI slave clock frequency is up to fapb /12. Note that (tspi /2–tpre ) represents data
output hold time for SPI slave in mode0 and mode2.

7.5 Parallel QSPI

ESP32 SPI controllers support SPI bus memory devices (such as flash and SRAM). The hardware connection
between the SPI pins and the memories is shown by Figure 7-5.

Figure 7-5. Parallel QSPI

SPI1, SPI2 and SPI3 controllers can also be configured as QSPI master to connect to external memory. The
maximum output clock frequency of the SPI memory interface is fapb , with the same clock configuration as that
of the GP-SPI master.

7.5.1 Communication Format of Parallel QSPI

To support communication with special slave devices, ESP32 QSPI implements a specifically designed com-
munication protocol. The communication format of ESP32 QSPI master is the same as that of GP-SPI four-line
half-duplex communication, except that in address phase and data phase, software can configure registers to
enable two-line or four-line transmission. Figure 7-6 shows a QSPI communication mode with four-line trans-
mission in address phase and data phase.

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Figure 7-6. Communication Format of Parallel QSPI

ESP32 QSPI supports flash-read operation in one-line, two-line, and four-line modes. When working as a QSPI
master, the command phase, address phase, dummy phase and data phase can be configured as needed, as
flexible as in GP-SPI mode.

Note that GPI-SPI full-duplex mode does not support dummy phase.

7.6 GP-SPI Interrupt Hardware

ESP32 SPI generates two types of interrupts. One is the SPI interrupt and the other is the SPI DMA inter-
rupt.

ESP32 SPI reckons the completion of send- and/or receive-operations as the completion of one operation from
the controller and generates one interrupt. When ESP32 SPI is configured to slave mode, the slave will generate
read/write status registers and read/write buffer data interrupts according to different operations.

7.6.1 SPI Interrupts

The SPI_*_INTEN bits in the SPI_SLAVE_REG register can be set to enable SPI interrupts. When an SPI interrupt
happens, the interrupt flag in the corresponding SPI_*_DONE register will get set. This flag is writable, and an
interrupt can be cleared by setting the bit to zero.

• SPI_TRANS_DONE_INT: Triggered when an SPI operation is done.

• SPI_SLV_WR_STA_INT: Triggered when an SPI slave status write is done.

• SPI_SLV_RD_STA_INT: Triggered when an SPI slave status read is done.

• SPI_SLV_WR_BUF_INT: Triggered when an SPI slave buffer write is done.

• SPI_SLV_RD_BUD_INT: Triggered when an SPI slave buffer read is done.

7.6.2 DMA Interrupts

• SPI_OUT_TOTAL_EOF_INT: Triggered when all linked lists are sent.

• SPI_OUT_EOF_INT: Triggered when one linked list is sent.

• SPI_OUT_DONE_INT: Triggered when the last linked list item has zero length.

• SPI_IN_SUC_EOF_INT: Triggered when all linked lists are received.

• SPI_IN_ERR_EOF_INT: Triggered when there is an error receiving linked lists.

• SPI_IN_DONE_INT: Triggered when the last received linked list had a length of 0.

• SPI_INLINK_DSCR_ERROR_INT: Triggered when the received linked list is invalid.

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• SPI_OUTLINK_DSCR_ERROR_INT: Triggered when the linked list to be sent is invalid.

• SPI_INLINK_DSCR_EMPTY_INT: Triggered when no valid linked list is available.

7.7 Register Summary

Name Description SPI0 SPI1 SPI2 SPI3 Acc
Control and configuration registers
Bit order and
SPI_CTRL_REG QIO/DIO/QOUT/DOUT 3FF43008 3FF42008 3FF64008 3FF65008 R/W
mode settings
SPI_CTRL2_REG Timing configuration 3FF43014 3FF42014 3FF64014 3FF65014 R/W
SPI_CLOCK_REG Clock configuration 3FF43018 3FF42018 3FF64018 3FF65018 R/W
Polarity and CS con-
SPI_PIN_REG 3FF43034 3FF42034 3FF64034 3FF65034 R/W
figuration
Slave mode configuration registers
Slave mode config-
SPI_SLAVE_REG uration and interrupt 3FF43038 3FF42038 3FF64038 3FF65038 R/W
status
SPI_SLAVE1_REG Slave data bit 3FF4303C 3FF4203C 3FF6403C 3FF6503C R/W
lengths
Dummy cycle length
SPI_SLAVE2_REG 3FF43040 3FF42040 3FF64040 3FF65040 R/W
configuration
Slave status/Part
SPI_SLV_WR_STATUS_REG 3FF43030 3FF42030 3FF64030 3FF65030 R/W
of lower master
address
Write-buffer opera-
SPI_SLV_WRBUF_DLEN_REG 3FF43048 3FF42048 3FF64048 3FF65048 R/W
tion length
Read-buffer opera-
SPI_SLV_RDBUF_DLEN_REG 3FF4304C 3FF4204C 3FF6404C 3FF6504C R/W
tion length
Read data operation
SPI_SLV_RD_BIT_REG 3FF43064 3FF42064 3FF64064 3FF65064 R/W
length
User-defined command mode registers
Start user-defined
SPI_CMD_REG 3FF43000 3FF42000 3FF64000 3FF65000 R/W
command
SPI_ADDR_REG Address data 3FF43004 3FF42004 3FF64004 3FF65004 R/W
User defined com-
SPI_USER_REG 3FF4301C 3FF4201C 3FF6401C 3FF6501C R/W
mand configuration
Address and dummy
SPI_USER1_REG 3FF43020 3FF42020 3FF64020 3FF65020 R/W
cycle configuration
Command length
SPI_USER2_REG and value configura- 3FF43024 3FF42024 3FF64024 3FF65024 R/W
tion
SPI_MOSI_DLEN_REG MOSI length 3FF43028 3FF42028 3FF64028 3FF65028 R/W
SPI_W0_REG SPI data register 0 3FF43080 3FF42080 3FF64080 3FF65080 R/W
SPI_W1_REG SPI data register 1 3FF43084 3FF42084 3FF64084 3FF65084 R/W

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Name Description SPI0 SPI1 SPI2 SPI3 Acc

SPI_W2_REG SPI data register 2 3FF43088 3FF42088 3FF64088 3FF65088 R/W
SPI_W3_REG SPI data register 3 3FF4308C 3FF4208C 3FF6408C 3FF6508C R/W
SPI_W4_REG SPI data register 4 3FF43090 3FF42090 3FF64090 3FF65090 R/W
SPI_W5_REG SPI data register 5 3FF43094 3FF42094 3FF64094 3FF65094 R/W
SPI_W6_REG SPI data register 6 3FF43098 3FF42098 3FF64098 3FF65098 R/W
SPI_W7_REG SPI data register 7 3FF4309C 3FF4209C 3FF6409C 3FF6509C R/W
SPI_W8_REG SPI data register 8 3FF430A0 3FF420A0 3FF640A0 3FF650A0 R/W
SPI_W9_REG SPI data register 9 3FF430A4 3FF420A4 3FF640A4 3FF650A4 R/W
SPI_W10_REG SPI data register 10 3FF430A8 3FF420A8 3FF640A8 3FF650A8 R/W
SPI_W11_REG SPI data register 11 3FF430AC 3FF420AC 3FF640AC 3FF650AC R/W
SPI_W12_REG SPI data register 12 3FF430B0 3FF420B0 3FF640B0 3FF650B0 R/W
SPI_W13_REG SPI data register 13 3FF430B4 3FF420B4 3FF640B4 3FF650B4 R/W
SPI_W14_REG SPI data register 14 3FF430B8 3FF420B8 3FF640B8 3FF650B8 R/W
SPI_W15_REG SPI data register 15 3FF430BC 3FF420BC 3FF640BC 3FF650BC R/W
DMA configuration registers
DMA configuration
SPI_DMA_CONF_REG 3FF43100 3FF42100 3FF64100 3FF65100 R/W
register
DMA outlink address
SPI_DMA_OUT_LINK_REG 3FF43104 3FF42104 3FF64104 3FF65104 R/W
and configuration
DMA inlink address
SPI_DMA_IN_LINK_REG 3FF43108 3FF42108 3FF64108 3FF65108 R/W
and configuration
SPI_DMA_STATUS_REG DMA status 3FF4310C 3FF4210C 3FF6410C 3FF6510C RO
Descriptor address
SPI_IN_ERR_EOF_DES_ADDR_REG where an error 3FF43120 3FF42120 3FF64120 3FF65120 RO
occurs
Descriptor address
SPI_IN_SUC_EOF_DES_ADDR_REG 3FF43124 3FF42124 3FF64124 3FF65124 RO
where EOF occurs
Current descriptor
SPI_INLINK_DSCR_REG 3FF43128 3FF42128 3FF64128 3FF65128 RO
pointer
Next descriptor data
SPI_INLINK_DSCR_BF0_REG 3FF4312C 3FF4212C 3FF6412C 3FF6512C RO
pointer
Current descriptor
SPI_INLINK_DSCR_BF1_REG 3FF43130 3FF42130 3FF64130 3FF65130 RO
data pointer
Relative buffer ad-
SPI_OUT_EOF_BFR_DES_ADDR_REG dress where EOF oc- 3FF43134 3FF42134 3FF64134 3FF65134 RO
curs
Descriptor address
SPI_OUT_EOF_DES_ADDR_REG 3FF43138 3FF42138 3FF64138 3FF65138 RO
where EOF occurs
Current descriptor
SPI_OUTLINK_DSCR_REG 3FF4313C 3FF4213C 3FF6413C 3FF6513C RO
pointer
Next descriptor data
SPI_OUTLINK_DSCR_BF0_REG 3FF43140 3FF42140 3FF64140 3FF65140 RO
pointer
Current descriptor
SPI_OUTLINK_DSCR_BF1_REG 3FF43144 3FF42144 3FF64144 3FF65144 RO
data pointer

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Name Description SPI0 SPI1 SPI2 SPI3 Acc

DMA memory read
SPI_DMA_RSTATUS_REG 3FF43148 3FF42148 3FF64148 3FF65148 RO
status
DMA memory write
SPI_DMA_TSTATUS_REG 3FF4314C 3FF4214C 3FF6414C 3FF6514C RO
status
DMA interrupt registers
SPI_DMA_INT_RAW_REG Raw interrupt status 3FF43114 3FF42114 3FF64114 3FF65114 RO
Masked interrupt sta-
SPI_DMA_INT_ST_REG 3FF43118 3FF42118 3FF64118 3FF65118 RO
tus
SPI_DMA_INT_ENA_REG Interrupt enable bits 3FF43110 3FF42110 3FF64110 3FF65110 R/W
SPI_DMA_INT_CLR_REG Interrupt clear bits 3FF4311C 3FF4211C 3FF6411C 3FF6511C R/W

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7.8 Registers
The addresses in parenthesis besides register names are the register addresses relative to the SPI0/SPI1/SPI2/SPI3
base addresses provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The ab-
solute register addresses are listed in Section 7.7 Register Summary.

Register 7.1. SPI_CMD_REG (0x0)

)
ed

ed
R
US
rv

rv
se

se
I_
(re

(re
SP
31 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_USR An SPI operation will be triggered when this bit is set. The bit will be cleared once the
operation is done. (R/W)

Register 7.2. SPI_ADDR_REG (0x4)

31 0

0x000000000 Reset

SPI_ADDR_REG It stores the transmitting address when master is in half-duplex mode or QSPI mode.
If the address length is bigger than 32 bits, this register stores the higher 32 bits of address value,
SPI_SLV_WR_STATUS_REG stores the rest lower part of address value. If the address length is
smaller than 33 bits, this register stores all the address value. The register is in valid only when
SPI_USR_ADDR bit is set to 1. (R/W)

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Register 7.3. SPI_CTRL_REG (0x8)

I_ EA OR R
se EA IO R

E
SP FR IT_ DE
(re FR D_Q DE

OD
AD

_M L
RD A
I_ d DIO
I_ _B OR

ST DU
QU
SP RD IT_

SP rve D_

D_

FA D_
)

SP WP )

d)
I_ _B

EA

I_ EA
ed

ed

ve
SP WR

FR

SP FR
rv

rv

r
se

se

se
I_

I_

I_
(re

(re

(re
SP

SP
31 27 26 25 24 23 22 21 20 19 15 14 13 12 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_WR_BIT_ORDER This bit determines the bit order for command, address and data in transmitted
signal. 1: sends LSB first; 0: sends MSB first. (R/W)

SPI_RD_BIT_ORDER This bit determines the bit order for received data in received signal. 1: re-
ceives LSB first; 0: receives MSB first. (R/W)

SPI_FREAD_QIO This bit is used to enable four-line address writes and data reads in QSPI mode.
(R/W)

SPI_FREAD_DIO This bit is used to enable two-line address writes and data reads in QSPI mode.
(R/W)

SPI_WP This bit determines the write-protection signal output when SPI is idle in QSPI mode. 1:
output high; 0: output low. (R/W)

SPI_FREAD_QUAD This bit is used to enable four-line data reads in QSPI mode. (R/W)

SPI_FREAD_DUAL This bit is used to enable two-line data reads in QSPI mode. (R/W)

SPI_FASTRD_MODE Reserved.

Register 7.4. SPI_CTRL1_REG (0xC)

LAY
DE
L D_
HO

)
ed
S_

rv
_C

se
I

(re
SP

31 28 27 0

0x05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_CS_HOLD_DELAY Reserved.

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Register 7.5. SPI_RD_STATUS_REG (0x10)

XT
_E
US

US
AT

AT
ST

ST
I_

I_
SP

SP
31 24 23 16 15 0

0x000 0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_STATUS_EXT Reserved.

SPI_STATUS Reserved.

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Register 7.6. SPI_CTRL2_REG (0x14)

E
OD
M

OD
UM
E

NU
OD
UM

_M
_N
Y_

Y_
_M

AY

AY
_N

E
LA

LA

M
EL

EL
AY

AY

M
DE

DE

TI
I
D

D
EL

EL

_T

P_
I_

I_

O_

O_

LD
_D

_D

TU
OS

OS

ed

d
IS

IS

HO
CS

CS

SE
ve
M

_M

rv

r
I_

I_

I_

I_

I_

I_

I_
se

se
I
SP

SP

SP

SP

SP

SP

SP

SP
re

re
31 28 27 26 25 23 22 21 20 18 17 16 15 12 11 8 7 4 3 0

0x00 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x01 0x01 Reset

SPI_CS_DELAY_NUM Reserved.

SPI_CS_DELAY_MODE Reserved.

SPI_MOSI_DELAY_NUM It is used to configure the number of system clock cycles by which the
MOSI signals are delayed. (R/W)

SPI_MOSI_DELAY_MODE This register field determines the way the MOSI signals are delayed by
SPI clock. (R/W)
After being delayed by SPI_MOSI_DELAY_NUM system clocks, the MOSI signals will then be
delayed by the configuration of SPI_MOSI_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MOSI signals are delayed one cycle.

SPI_MISO_DELAY_NUM It is used to configure the number of system clock cycles by which the
MISO signals are delayed. (R/W)

SPI_MISO_DELAY_MODE This register field determines the way MISO signals are delayed by SPI
clock. (R/W)
After being delayed by SPI_MISO_DELAY_NUM system clock, the MISO signals will then be de-
layed by the configuration of SPI_MISO_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MISO signals are delayed by one cycle.

SPI_HOLD_TIME The number of SPI clock cycles by which CS pin signals are delayed. It is only
valid when SPI_CS_HOLD is set to 1. (R/W)

SPI_SETUP_TIME It is to configure the time between the CS signal active edge and the first SPI
clock edge. It is only valid in half-duplex mode or QSPI mode and when SPI_CS_SETUP is set
to 1. (R/W)

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Register 7.7. SPI_CLOCK_REG (0x18)

LK
SC
SY

E
PR
U_

_N

_H

_L
IV_

NT

NT

NT
EQ

KD

KC

KC

KC
K_
CL

CL

CL

CL

CL
I_

I_

I_

I_

I_
SP

SP

SP

SP

SP
31 30 18 17 12 11 6 5 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0x03 0x01 0x03 Reset

SPI_CLK_EQU_SYSCLK In master mode, when this bit is set to 1, SPI output clock is equal to system
clock; when set to 0, SPI output clock is divided from system clock. In slave mode, it should be
set to 0. (R/W)

SPI_CLKDIV_PRE In master mode, it is used to configure the pre-divider value for SPI output clock.
It is only valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_N In master mode, it is used to configure the divider for SPI output clock. It is only
valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_H In master mode, SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1

2 –1⌋. It is only valid when
SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_L In master mode, it is equal to SPI_CLKCNT_N. It is only valid when

SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

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Register 7.8. SPI_USER_REG (0x1C)

GH RT
RT
HI PA
PA
M I_H LE

d) OR R
R
O_ H
R_ OS Y_ID

E
I_ R_ DR ND

DE
IS IG

E_ D

I_ _S GE E
SP WR TE_ UAD

(re _B E_ L
YT OR

SP CS ED DG
SP US AD MA

SP US MIS MY

RD YT A
SP FW TE_ IO
SP FW TE_ IO
I_ R_ MM

I_ _B DU

_H UP
I_ R_ O
I_ R_ SI

I_ _I_ _E
I_ RI D
I_ RI Q

I_ RI Q
I_ R_ M
I_ R_ M

N
SP FW E_
SP US MO
SP US DU

SP US DU
SP US CO

SP CK UT

OL
CS ET

DI
US M

I_ RIT
)

UT
I_ _O
I_ R_

ed

ed
e
SP SIO
SP FW

DO
SP US

SP CK
rv

rv

rv
se

se

se
I_

I_
I_

I_

I_
(re

(re
SP

SP

SP

SP
31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset

SPI_USR_COMMAND This bit enables the command phase of an SPI operation in SPI half-duplex
mode and QSPI mode. (R/W)

SPI_USR_ADDR This bit enables the address phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_DUMMY This bit enables the dummy phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_MISO This bit enables the read-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_MOSI This bit enables the write-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_DUMMY_IDLE The SPI clock signal is disabled in the dummy phase when the bit is set in
SPI half-duplex mode and QSPI mode. (R/W)

SPI_USR_MOSI_HIGHPART If set, MOSI data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)

SPI_USR_MISO_HIGHPART If set, MISO data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)

SPI_SIO Set this bit to enable three-line half-duplex communication. (R/W)

SPI_FWRITE_QIO Reserved.

SPI_FWRITE_DIO Reserved.

SPI_FWRITE_QUAD Reserved.

SPI_FWRITE_DUAL Reserved.

SPI_WR_BYTE_ORDER This bit determines the byte order of the command, address and data in
transmitted signal. 1: big-endian; 0: little-endian. (R/W)

SPI_RD_BYTE_ORDER This bit determines the byte order of received data in transmitted signal. 1:
big-endian; 0: little_endian. (R/W)

SPI_CK_OUT_EDGE This bit, combined with SPI_MOSI_DELAY_MODE, sets the MOSI signal delay
mode. It is only valid in master mode. (R/W)

SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is
combined with SPI_MISO_DELAY_MODE. It is only valid in slave mode. (R/W)

Continued on the next page...

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Register 7.8. SPI_USER_REG (0x1C)

Continued from the previous page...

SPI_CS_SETUP Setting this bit enables a delay between CS active edge and the first clock edge,
in multiples of one SPI clock cycle. In full-duplex mode and QSPI mode, setting this bit results in
(SPI_SETUP_TIME + 1.5) SPI clock cycles delay. In full-duplex mode, there will be 1.5 SPI clock
cycles delay for mode0 and mode2, and 1 SPI clock cycle delay for mode1 and mode3. (R/W)

SPI_CS_HOLD Setting this bit enables a delay between the end of a transmission and CS being
inactive, as specified in SPI_HOLD_TIME. (R/W)

SPI_DOUTDIN Set the bit to enable full-duplex communication. (R/W)

Register 7.9. SPI_USER1_REG (0x20)

EN
EL
N

CL
LE

CY
IT

Y_
B
R_

M
UM
DD

D
A

)
R_

R_
ed
US

US
rv
se
I_

I_
(re
SP

SP
31 26 25 8 7 0

23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 Reset

SPI_USR_ADDR_BITLEN It indicates the bit length of the transmitted address minus one in half-
duplex mode and QSPI mode, in multiples of one bit. It is only valid when SPI_USR_ADDR is set
to 1. (RO)

SPI_USR_DUMMY_CYCLELEN It indicates the number of SPI clock cycles for the dummy phase
minus one in SPI half-duplex mode and QSPI mode. It is only valid when SPI_USR_DUMMY is
set to 1. (R/W)

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Register 7.10. SPI_USER2_REG (0x24)

E
LE

LU
IT

VA
B
D_

D_
AN

AN
M

M
M

M
CO

CO
)
R_

R_
ed
US

US
rv
se
I_

I_
(re
SP

SP
31 28 27 16 15 0

7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_USR_COMMAND_BITLEN It indicates the bit length of the command phase minus one in SPI
half-duplex mode and QSPI mode. It is only valid when SPI_USR_COMMAND is set to 1. (R/W)

SPI_USR_COMMAND_VALUE It indicates the value of the command to be transmitted in SPI half-

duplex mode and QSPI mode. It is only valid when SPI_USR_COMMAND is set to 1. (R/W)

Register 7.11. SPI_MOSI_DLEN_REG (0x28)

E N
TL
BI
_D
I
OS
M
)

R_
ed

US
rv
se

I_
(re

SP

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_USR_MOSI_DBITLEN It indicates the length of MOSI data minus one, in multiples of one bit. It
is only valid when SPI_USR_MOSI is set to 1 in master mode. (R/W)

Register 7.12. SPI_MISO_DLEN_REG (0x2C)

EN
TL
D BI
O_
IS
M
)

R_
ed

US
rv
se

I_
(re

SP

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_USR_MISO_DBITLEN It indicates the length of MISO data minus one, in multiples of one bit. It
is only valid when SPI_USR_MISO is set to 1 in master mode. (R/W)

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Register 7.13. SPI_SLV_WR_STATUS_REG (0x30)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_WR_STATUS_REG In the slave mode this register is the status register for the master to
write the slave. In the master mode, if the address length is bigger than 32 bits, SPI_ADDR_REG
stores the higher 32 bits of address value, and this register stores the rest lower part of address
value. (R/W)

Register 7.14. SPI_PIN_REG (0x34)

OL
ED IVE

E L
GE

_P
_S
E_ T
DL AC

CS
CK
_I P_

R_

R_

SP CS DIS

S
CS IS
CK EE

DI
IS
TE

TE

I_ 1_D
I_ d)

SP ed)
(re _D

I_ 2_

0_
I_ _K

ed

ed
AS

AS
SP rve
SP CS

SP CS
CK
rv

rv

rv
M

M
se

se

se

se
I_

I_

I_

I_
(re

(re

(re
SP

SP

SP
31 30 29 28 14 13 11 10 9 8 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Reset

SPI_CS_KEEP_ACTIVE This bit is only used in master mode where when it is set, the CS signal will
keep active. (R/W)

SPI_CK_IDLE_EDGE This bit is only used in master mode to configure the logicl level of SPI output
clock in idle state. (R/W)
1: the spi_clk line keeps high when idle;
0: the spi_clk line keeps low when idle.

SPI_MASTER_CK_SEL Reserved.

SPI_MASTER_CS_POL Reserved.

SPI_CK_DIS Reserved.

SPI_CS2_DIS This bit enables the SPI CS2 signal. 1: disables CS2; 0: enables CS2. (R/W)

SPI_CS1_DIS This bit enables the SPI CS1 signal. 1: disables CS1; 0: enables CS1. (R/W)

SPI_CS0_DIS This bit enables the SPI CS0 signal. 1: disables CS0; 0: enables CS0. (R/W)

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Register 7.15. SPI_SLAVE_REG (0x38)

D
D_ ST EN
FI EN

SP SLV S_D F_ TEN

AN

SP SLV R_ NE TEN
SP SLV R_ A_ TEN

_D NE
SP TRA D_ UF_ TEN

E
V_ _B D E
_B F_D E

ON
SL R A_ N
CM D F_

RD U ON
DE A_
NE

UF O
I_ _W ST DO
TE

I_ N BU I N
I_ _W O IN
I_ _W ST IN
V_ _R BU

I_ _R B I N
OM
TA

SP SLV R_ EN
SP SLV D_ A_

SP SLV D_ A_
SP SLV R_ DE
SP SLV E_M ET

SL R _
_

E
NT

_C
_S
I_ _W RD

I_ _R ST

I_ _R ST
I_ _W NT
I_ _W O

SP RA OD
I_ AV ES

ST

ST
_C

SP SLV S_I
SP SL _R

_M
LA

LA
NS

)
I_ NC

I_ N
ed

_I
V_

V_
RA

CS
rv
SP SY

SL

SL
I_T

I_T
se
I_

I_

I_

I_
(re
SP

SP

SP

SP

SP

SP
31 30 29 28 27 26 23 22 20 19 17 16 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SYNC_RESET When set, it resets the latched values of the SPI clock line, CS line and data line.
(R/W)

SPI_SLAVE_MODE This bit is used to set the mode of the SPI device. (R/W)
1: slave mode;
0: master mode.

SPI_SLV_WR_RD_BUF_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read data commands are enabled. (R/W)

SPI_SLV_WR_RD_STA_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read status commands are enabled. (R/W)

SPI_SLV_CMD_DEFINE Reserved.

SPI_TRANS_CNT The counter for operations in both the master mode and the slave mode. (RO)

SPI_SLV_LAST_STATE In slave mode, this contains the state of the SPI state machine. (RO)

SPI_SLV_LAST_COMMAND Reserved.

SPI_CS_I_MODE Reserved.

SPI_TRANS_INTEN The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt. (R/W)

SPI_SLV_WR_STA_INTEN The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt. (R/W)

SPI_SLV_RD_STA_INTEN The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt. (R/W)

SPI_SLV_WR_BUF_INTEN The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt. (R/W)

SPI_SLV_RD_BUF_INTEN The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt. (R/W)

SPI_TRANS_DONE The raw interrupt status bit for the SPI_TRANS_DONE_INT interrupt. It is set by
hardware and cleared by software. (R/W)

SPI_SLV_WR_STA_DONE The raw interrupt status bit for the SPI_SLV_WR_STA_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

SPI_SLV_RD_STA_DONE The raw interrupt status bit for the SPI_SLV_RD_STA_INT interrupt. It is set
by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

Continued on the next page...

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Register 7.15. SPI_SLAVE_REG (0x38)

Continued from the previous page ...

SPI_SLV_WR_BUF_DONE The raw interrupt status bit for the SPI_SLV_WR_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

SPI_SLV_RD_BUF_DONE The raw interrupt status bit for the SPI_SLV_RD_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

Register 7.16. SPI_SLAVE1_REG (0x3C)

M N
EN
BU DU MY N
K

F_ M _EN
M _E
EN
AC

RD F_ M _E
N
EA EN

Y_
LE

DU MY
V_ BU U Y
N

TL
DB

SL R _D M
_R T_
LE

IT

BI

I_ _W TA UM
US AS

B
IT

R_
R_
_B

AT _F

SP SLV DS _D
DD
DD
US

ST S

I_ _R TA
V_ TU

A
A
AT

SP SLV RS
R_
D_
SL TA
ST

I_ _W
R
I_ _S

)
ed
V_

V_

V_
SP LV

SP SLV
rv
SL

SL

SL
S

se
I_

I_

I_

I_

I_
(re
SP

SP

SP

SP

SP
31 27 26 25 24 16 15 10 9 4 3 2 1 0

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x00 0x00 0 0 0 0 Reset

SPI_SLV_STATUS_BITLEN It is only used in slave half-duplex mode to configure the length of the
master writing into the status register. (R/W)

SPI_SLV_STATUS_FAST_EN Reserved.

SPI_SLV_STATUS_READBACK Reserved.

SPI_SLV_RD_ADDR_BITLEN It indicates the address length in bits minus one for a slave-read op-
eration. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WR_ADDR_BITLEN It indicates the address length in bits minus one for a slave-write op-
eration. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WRSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for write-status
operations. It is only valid in slave half-duplex mode.(R/W)

SPI_SLV_RDSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for read-status op-
erations. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WRBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for write-buffer
operations. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer op-
erations. It is only valid in slave half-duplex mode. (R/W)

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Register 7.17. SPI_SLAVE2_REG (0x40)

EN

EN

EN
LE
EL

EL

EL
E
CL

CL

CL

CL
CY

CY

CY

CY
Y_

Y_

Y_

Y_
M

M
UM

UM

M
DU

DU
D

_D
F_

F_

A_
TA
U

ST
RB

RS
DB

RD
W

W
R
V_

V_

V_

V_
SL

SL

SL

SL
I_

I_

I_

I_
SP

SP

SP

SP
31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0x000 0x000 0x000 Reset

SPI_SLV_WRBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for the
dummy phase for write-data operations. It is only valid when SPI_SLV_WRBUF_DUMMY_EN is set
to 1 in slave half-duplex mode. (R/W)

SPI_SLV_RDBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for the
dummy phase for read-data operations. It is only valid when SPI_SLV_RDBUF_DUMMY_EN is set
to 1 in slave half-duplex mode. (R/W)

SPI_SLV_WRSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one

for the dummy phase for write-status register operations. It is only valid when
SPI_SLV_WRSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)

SPI_SLV_RDSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one

for the dummy phase for read-status register operations. It is only valid when
SPI_SLV_RDSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)

Register 7.18. SPI_SLAVE3_REG (0x44)

E

E
E

LU

LU
LU

LU

VA

VA
VA

VA

D_

D_
D_

D_

M
M

CM

_C

_C
_C

A_

UF

UF
TA

ST

RB
RS

DB
RD
W

R
V_

V_

V_

V_
SL

SL

SL

SL
I_

I_

I_

I_
SP

SP

SP

SP

31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_WRSTA_CMD_VALUE Reserved.

SPI_SLV_RDSTA_CMD_VALUE Reserved.

SPI_SLV_WRBUF_CMD_VALUE Reserved.

SPI_SLV_RDBUF_CMD_VALUE Reserved.

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Register 7.19. SPI_SLV_WRBUF_DLEN_REG (0x48)

N
LE
BIT
_D
UF
RB
W
d)

V_
ve

SL
r
se

I_
(re

SP
31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_SLV_WRBUF_DBITLEN It indicates the length of written data minus one, in multiples of one bit.
It is only valid in slave half-duplex mode. (R/W)

Register 7.20. SPI_SLV_RDBUF_DLEN_REG (0x4C)

N
LE
T
BI
_D
UF
DB
R
)
ed

V_
rv

SL
se

I_
(re

SP

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_SLV_RDBUF_DBITLEN It indicates the length of read data minus one, in multiples of one bit. It
is only valid in slave half-duplex mode. (R/W)

Register 7.21. SPI_SLV_RD_BIT_REG (0x64)

T
_ BI
TA
RDA
)
ed

V_
rv

SL
se

I_
(re

SP

31 24 23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_RDATA_BIT It indicates the bit length of data the master reads from the slave, minus one.
It is only valid in slave half-duplex mode. (R/W)

Register 7.22. SPI_Wn_REG (n: 0-15) (0x80+4*n)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_Wn_REG Data buffer. (R/W)

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Register 7.23. SPI_TX_CRC_REG (0xC0)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_TX_CRC_REG Reserved.

Register 7.24. SPI_EXT2_REG (0xF8)

d)
ve

ST
r
se

I_
(re

SP
31 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_ST The current state of the SPI state machine: (RO)

0: idle state
1: preparation state
2: send command state
3: send data state
4: read data state
5: write data state
6: wait state
7: done state

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Register 7.25. SPI_DMA_CONF_REG (0x100)

T_ CR_ ST _EN

E N
OD _E
F_ UR N
R T
EO B _E
M ST

(re _RS T RST

I_ TD BU RS
se A_ _S UE

P
I_ d _S P

SP OU CR_ _BU
TO
(re DM TX IN
SP rve RX TO

I N RS _
I_ T_ IFO
I_ A_ NT

I_ BM ST
I_ S A
SP IND AT
SP DM CO

SP AH _R
SP OU _F

T
OU S
D

I_ BM
I_ A_
)

SP OU )

)
I_ T_
ed

ed

ed
SP DM

SP AH
rv

rv

rv
se

se

se
I_

I_
(re

(re
SP

SP
31 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset

SPI_DMA_CONTINUE This bit enables SPI DMA continuous data TX/RX mode. (R/W)

SPI_DMA_TX_STOP When in continuous TX/RX mode, setting this bit stops sending data. (R/W)

SPI_DMA_RX_STOP When in continuous TX/RX mode, setting this bit stops receiving data. (R/W)

SPI_OUT_DATA_BURST_EN SPI DMA reads data from memory in burst mode. (R/W)

SPI_INDSCR_BURST_EN SPI DMA reads inlink descriptor in burst mode. (R/W)

SPI_OUTDSCR_BURST_EN SPI DMA reads outlink descriptor in burst mode. (R/W)

SPI_OUT_EOF_MODE DMA out-EOF-flag generation mode. (R/W)

1: out-EOF-flag is generated when DMA has popped all data from the FIFO;
0: out-EOF-flag is generated when DMA has pushed all data to the FIFO.

SPI_AHBM_RST reset SPI DMA AHB master. (R/W)

SPI_AHBM_FIFO_RST This bit is used to reset SPI DMA AHB master FIFO pointer. (R/W)

SPI_OUT_RST The bit is used to reset DMA out-FSM and out-data FIFO pointer. (R/W)

SPI_IN_RST The bit is used to reset DMA in-DSM and in-data FIFO pointer. (R/W)

Register 7.26. SPI_DMA_OUT_LINK_REG (0x104)

IN STA RT
TL K_ STA

ST T

DR
OP
K_ R

AD
OU IN E
I_ TL _R

K_
SP OU INK

IN
I_ d)

d)
I_ TL

TL
SP rve

ve
SP OU

OU
r
se

se

I_
(re

(re

SP

31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SPI_OUTLINK_RESTART Set the bit to add new outlink descriptors. (R/W)

SPI_OUTLINK_START Set the bit to start to use outlink descriptor. (R/W)

SPI_OUTLINK_STOP Set the bit to stop to use outlink descriptor. (R/W)

SPI_OUTLINK_ADDR The address of the first outlink descriptor. (R/W)

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Register 7.27. SPI_DMA_IN_LINK_REG (0x108)

ET
NK TA T

R
LI S AR

O_
_S RT

R
P
IN K_ T

DD
UT
I_ IN RES

TO

_A

_A
SP INL K_

NK

NK
I_ d)

)
I_ IN

ed

LI

LI
SP rve
SP INL

rv

IN

IN
se

se

I_

I_
(re

(re

SP

SP
31 30 29 28 27 21 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SPI_INLINK_RESTART Set the bit to add new inlink descriptors. (R/W)

SPI_INLINK_START Set the bit to start to use inlink descriptor. (R/W)

SPI_INLINK_STOP Set the bit to stop to use inlink descriptor. (R/W)

SPI_INLINK_AUTO_RET when the bit is set, inlink descriptor jumps to the next descriptor when a
packet is invalid. (R/W)

SPI_INLINK_ADDR The address of the first inlink descriptor. (R/W)

Register 7.28. SPI_DMA_STATUS_REG (0x10C)

N
RX N
_E
A_ _E
DM TX
I_ A_
)
ed

SP DM
rv
se

I_
(re

SP
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_DMA_TX_EN SPI DMA write-data status bit. (RO)

SPI_DMA_RX_EN SPI DMA read-data status bit. (RO)

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Register 7.29. SPI_DMA_INT_ENA_REG (0x110)

EN A
T_ N
PT R_ ENA

A
I N _E
Y_ INT
EM RO T_
A

R_ ER IN
SP IN_ C_ _IN NA EN

SC R_ R_
SP OU K_ INT T_E A
I_ TL DS _E NA
I_ SU NE E T_

I_ IN E_ IN N
I_ D EO IN A

_D SC RO
SP IN_ DO INT_ _IN

SP INL ON F_ T_E
SP IN_ R_ F_ EN

IN IN CR NA
NK D ER
I_ ER EO T_
I_ T_ F_ OF

LI K_ _
SP OU EO _E
I_ T_ AL
SP OU OT
I_ T_T
)
ed

SP OU
rv
se

I_
(re

SP
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_TOTAL_EOF_INT interrupt.

(R/W)

SPI_OUT_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_EOF_INT interrupt. (R/W)

SPI_OUT_DONE_INT_ENA The interrupt enable bit for the SPI_OUT_DONE_INT interrupt. (R/W)

SPI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the SPI_IN_SUC_EOF_INT interrupt. (R/W)

SPI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the SPI_IN_ERR_EOF_INT interrupt. (R/W)

SPI_IN_DONE_INT_ENA The interrupt enable bit for the SPI_IN_DONE_INT interrupt. (R/W)

SPI_INLINK_DSCR_ERROR_INT_ENA The interrupt enable bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (R/W)

SPI_OUTLINK_DSCR_ERROR_INT_ENA The interrupt enable bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W)

SPI_INLINK_DSCR_EMPTY_INT_ENA The interrupt enable bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (R/W)

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Register 7.30. SPI_DMA_INT_RAW_REG (0x114)

RA W
T_ A
PT R_ RAW

W
I N _R
Y_ INT
EM RO T_
W

R_ ER IN
SP IN_ C_ _IN AW RA

SC R_ R_
I_ IN E_ IN AW
I_ TL DS _R AW
I_ SU NE R T_

I_ D EO IN W

_D SC RO
SP INL ON F_ T_R
SP IN_ DO INT_ _IN

SP OU K_ INT T_R
SP IN_ R_ F_ RA

IN IN CR AW
NK D ER
I_ ER EO T_
I_ T_ F_ OF

LI K_ _
SP OU EO _E
I_ T_ AL
SP OU TOT
d)

I_ T_
ve

SP OU
r
se

I_
(re

SP
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_TOTAL_EOF_INT inter-
rupt. (RO)

SPI_OUT_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)

SPI_OUT_DONE_INT_RAW The raw interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO)

SPI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)

SPI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)

SPI_IN_DONE_INT_RAW The raw interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)

SPI_INLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_OUTLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_INLINK_DSCR_EMPTY_INT_RAW The raw interrupt status bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO)

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Register 7.31. SPI_DMA_INT_ST_REG (0x118)

T_ T
IN _S
PT R_ ST

ST
Y_ INT
EM RO T_
R_ ER IN
SP IN_ C_ _IN T ST

SC R_ R_
I_ SU NE S T_

I_ IN E_ IN T
I_ TL DS _S T

_D SC RO
SP INL ON F_ T_S
SP IN_ DO INT_ _IN

SP OU K_ INT T_S
SP IN_ R_ F_ ST

NK D ER
IN IN CR T
I_ ER EO T_
I_ T_ F_ OF

I_ D EO IN

LI K_ _
SP OU EO _E
I_ T_ AL
SP OU OT
I_ T_T
)
ed

SP OU
rv
se

I_
(re

SP
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_TOTAL_EOF_INT in-
terrupt. (RO)

SPI_OUT_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)

SPI_OUT_DONE_INT_ST The masked interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO)

SPI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)

SPI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)

SPI_IN_DONE_INT_ST The masked interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)

SPI_INLINK_DSCR_ERROR_INT_ST The masked interrupt status bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_OUTLINK_DSCR_ERROR_INT_ST The masked interrupt status bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_INLINK_DSCR_EMPTY_INT_ST The masked interrupt status bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO)

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Register 7.32. SPI_DMA_INT_CLR_REG (0x11C)

CL R
T_ L
PT R_ LR

R
IN _C
EM RO T_C
Y_ INT
R

R_ ER IN
SP IN_ C_ _IN LR CL

SC R_ R_
I_ IN E_ IN LR
I_ TL DS _C LR
I_ SU NE C T_

I_ D EO IN R

_ D S C RO
SP INL ON F_ T_C
SP IN_ DO INT_ _IN

SP OU K_ INT T_C
SP IN_ R_ F_ CL

IN IN CR LR
NK D ER
I_ ER EO T_
I_ T_ F_ OF

LI K_ _
SP OU EO _E
I_ T_ AL
SP OU OT
I_ T_T
d)
ve

SP OU
r
se

I_
(re

SP
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_CLR Set this bit to clear the SPI_OUT_TOTAL_EOF_INT interrupt. (R/W)

SPI_OUT_EOF_INT_CLR Set this bit to clear the SPI_OUT_EOF_INT interrupt. (R/W)

SPI_OUT_DONE_INT_CLR Set this bit to clear the SPI_OUT_DONE_INT interrupt. (R/W)

SPI_IN_SUC_EOF_INT_CLR Set this bit to clear the SPI_IN_SUC_EOF_INT interrupt. (R/W)

SPI_IN_ERR_EOF_INT_CLR Set this bit to clear the SPI_IN_ERR_EOF_INT interrupt. (R/W)

SPI_IN_DONE_INT_CLR Set this bit to clear the SPI_IN_DONE_INT interrupt. (R/W)

SPI_INLINK_DSCR_ERROR_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_ERROR_INT inter-

rupt. (R/W)

SPI_OUTLINK_DSCR_ERROR_INT_CLR Set this bit to clear the SPI_OUTLINK_DSCR_ERROR_INT

interrupt. (R/W)

SPI_INLINK_DSCR_EMPTY_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_EMPTY_INT inter-

rupt. (R/W)

Register 7.33. SPI_IN_ERR_EOF_DES_ADDR_REG (0x120)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_IN_ERR_EOF_DES_ADDR_REG The inlink descriptor address when SPI DMA encountered an

error in receiving data. (RO)

Register 7.34. SPI_IN_SUC_EOF_DES_ADDR_REG (0x124)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_IN_SUC_EOF_DES_ADDR_REG The last inlink descriptor address when SPI DMA encountered
EOF. (RO)

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Register 7.35. SPI_INLINK_DSCR_REG (0x128)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_REG The address of the current inlink descriptor. (RO)

Register 7.36. SPI_INLINK_DSCR_BF0_REG (0x12C)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_BF0_REG The address of the next inlink descriptor. (RO)

Register 7.37. SPI_INLINK_DSCR_BF1_REG (0x130)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_BF1_REG The address of the next inlink data buffer. (RO)

Register 7.38. SPI_OUT_EOF_BFR_DES_ADDR_REG (0x134)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_EOF_BFR_DES_ADDR_REG The buffer address corresponding to the outlink descriptor

that produces EOF. (RO)

Register 7.39. SPI_OUT_EOF_DES_ADDR_REG (0x138)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_EOF_DES_ADDR_REG The last outlink descriptor address when SPI DMA encountered
EOF. (RO)

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Register 7.40. SPI_OUTLINK_DSCR_REG (0x13C)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_REG The address of the current outlink descriptor. (RO)

Register 7.41. SPI_OUTLINK_DSCR_BF0_REG (0x140)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_BF0_REG The address of the next outlink descriptor. (RO)

Register 7.42. SPI_OUTLINK_DSCR_BF1_REG (0x144)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_BF1_REG The address of the next outlink data buffer. (RO)

Register 7.43. SPI_DMA_RSTATUS_REG (0x148)

SS
FU TY

RE
LL
O_ P

DD
IF EM

_A
)
_F _

ed
TX FIFO

ES
rv

_D
se
_

(re
TX

TX

31 30 29 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TX_FIFO_EMPTY The SPI DMA TX FIFO is empty. (RO)

TX_FIFO_FULL The SPI DMA TX FIFO is full. (RO)

TX_DES_ADDRESS The LSB of the SPI DMA outlink descriptor address. (RO)

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Register 7.44. SPI_DMA_TSTATUS_REG (0x14C)

SS
FU TY

RE
LL
O_ P

DD
IF EM

A
)
_F _

ed

S_
RX FIFO

rv

E
_D
se
_

(re
RX

RX
31 30 29 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RX_FIFO_EMPTY The SPI DMA RX FIFO is empty. (RO)

RX_FIFO_FULL The SPI DMA RX FIFO is full. (RO)

RX_DES_ADDRESS The LSB of the SPI DMA inlink descriptor address. (RO)

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8 SDIO Slave Controller

8.1 Overview
The ESP32 features hardware support for the industry-standard Secure Digital (SD) device interface that
conforms to the SD Input/Output (SDIO) Specification Version 2.0. This allows a host controller to access the
ESP32 via an SDIO bus protocol, enabling high-speed data transfer.

The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via Direct
Memory Access (DMA), thus reducing processing overhead while maintaining high performance.

8.2 Features
• Meets SDIO V2.0 specification

• Supports SDIO SPI, 1-bit, and 4-bit transfer modes

• Full host clock range of 0 ~ 50 MHz

• Configurable sample and drive clock edge

• Integrated, SDIO-accessible registers for information interaction

• Supports SDIO interrupt mechanism

• Automatic data padding

• Block size of up to 512 bytes

• Interrupt vector between Host and Slave for bidirectional interrupt

• Supports DMA for data transfer

8.3 Functional Description

8.3.1 SDIO Slave Block Diagram
The functional block diagram of the SDIO slave module is shown in Figure 8-1.

Figure 8-1. SDIO Slave Block Diagram

The Host System represents any SDIO specification V2.0-compatible host device. The Host System interacts
with the ESP32 (configured as the SDIO slave) via the standard SDIO bus implementation.

The SDIO Device Interface block enables effective communication with the external Host by directly providing
SDIO interface registers and enabling DMA operation for high-speed data transfer over the Advanced
High-performance Bus (AHB) without engaging the CPU.

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8.3.2 Sending and Receiving Data on SDIO Bus

Data is transmitted between Host and Slave through the SDIO bus I/O Function1. After the Host enables the I/O
Function1 in the Slave, according to the SDIO protocol, data transmission will begin.

ESP32 segregates data into packets sent to/from the Host. To achieve high bus utilization and data transfer
rates, we recommend the single block transmission mode. For detailed information on this mode, please refer
to the SDIO V2.0 protocol specification. When Host and Slave exchange data as blocks on the SDIO bus, the
Slave automatically pads data-when sending data out-and automatically strips padding data from the incoming
data block.

Whether the Slave pads or discards the data depends on the data address on the SDIO bus. When the data
address is equal to, or greater than, 0x1F800, the Slave will start padding or discarding data. Therefore, the
starting data address should be 0x1F800 - Packet_length, where Packet_length is measured in bytes. Data
flow on the SDIO bus is shown in Figure 8-2.

Figure 8-2. SDIO Bus Packet Transmission

The standard IO_RW_EXTENDED (CMD53) command is used to initiate a packet transfer of an arbitrary length.
The content of the CMD53 command used in data transmission is as illustrated in Figure 8-3 below. For
detailed information on CMD53, please refer to the SDIO protocol specifications.

Figure 8-3. CMD53 Content

8.3.3 Register Access

For effective interaction between Host and Slave, the Host can access certain registers in the Slave via the
SDIO bus I/O Function1. These registers are in continuous address fields from SLC0HOST_TOKEN_RDATA to
SSLC0HOST_INT_ST_REG. The Host device can access these registers by simply setting the register
addresses of CMD52 or CMD53 to the low 10 bits of the corresponding register address. The Host can access
several consecutive registers at one go with CMD53, thus achieving a higher effective transfer rate.

There are 52 bytes of field between SLCHOST_CONF_W0_REG and SLCHOST_CONF_W15_REG. Host and Slave
can access and change these fields, thus facilitating the information interaction between Host and
Slave.

8.3.4 DMA
The SDIO Slave module uses dedicated DMA to access data residing in the RAM. As shown in Figure 8-1, the
RAM is accessed over the AHB. DMA accesses RAM through a linked-list descriptor. Every linked list is

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composed of three words, as shown in Figure 8-4.

Figure 8-4. SDIO Slave DMA Linked List Structure

• Owner: The allowed operator of the buffer that corresponds to the current linked list. 0: CPU is the
allowed operator; 1: DMA is the allowed operator.

• Eof: End-of-file marker, indicating that this linked-list element is the last element of the data packet.

• Length: The number of valid bytes in the buffer, i.e., the number of bytes that should be accessed from
the buffer for reading/writing.

• Size: The maximum number of available buffers.

• Buffer Address Pointer: The address of the data buffer as seen by the CPU (according to the RAM
address space).

• Next Descriptor Address: The address of the next linked-list element in the CPU RAM address space. If
the current linked list is the last one, the Eof bit should be 1, and the last descriptor address should be 0.

The Slave’s linked-list chain is shown in Figure 8-5:

Figure 8-5. SDIO Slave Linked List

8.3.5 Packet-Sending/-Receiving Procedure

The SDIO Host and Slave devices need to follow specific data transfer procedures to successfully exchange
data over the SDIO interface.

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8.3.5.1 Sending Packets to SDIO Host

The transmission of packets from Slave to Host is initiated by the Slave. The Host will be notified with an
interrupt (for detailed information on interrupts, please refer to SDIO protocol). After the Host reads the
relevant information from the Slave, it will initiate an SDIO bus transaction accordingly. The whole procedure is
illustrated in Figure 8-6.

Figure 8-6. Packet Sending Procedure (Initiated by Slave)

When the Host is interrupted, it reads relevant information from the Slave by visiting registers SLC0HOST_INT
and SLCHOST_PKT_LEN.

• SLC0HOST_INT: Interrupt status register. If the value of SLC0_RX_NEW_PACKET_INT_ST is 1, this

indicates that the Slave has a packet to send.

• SLCHOST_PKT_LEN: Packet length accumulator register. The current value minus the value of last time
equals the packet length sent this time.

In order to start DMA, the CPU needs to write the low 20 bits of the address of the first linked-list element to

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the SLC0_RXLINK_ADDR bit of SLC0RX_LINK, then set the SLC0_RXLINK_START bit of SLC0RX_LINK. The
DMA will automatically complete the data transfer. Upon completion of the operation, DMA will interrupt the
CPU so that the buffer space can be freed or reused.

8.3.5.2 Receiving Packets from SDIO Host

Transmission of packets from Host to Slave is initiated by the Host. The Slave receives data via DMA and stores
it in RAM. After transmission is completed, the CPU will be interrupted to process the data. The whole
procedure is demonstrated in Figure 8-7.

Figure 8-7. Packet Receiving Procedure (Initiated by Host)

The Host obtains the number of available receiving buffers from the Slave by accessing register
SLC0HOST_TOKEN_RDATA. The Slave CPU should update this value after the receiving DMA linked list is
prepared.

HOSTREG_SLC0_TOKEN1 in SLC0HOST_TOKEN_RDATA stores the accumulated number of available

buffers.

The Host can figure out the available buffer space, using HOSTREG_SLC0_TOKEN1 minus the number of
buffers already used.

If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers
available.

To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list.
The process is shown in Figure 8-8.

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Figure 8-8. Loading Receiving Buffer

The CPU first needs to append new buffer segments at the end of the linked list that is being used by DMA
and is available for receiving data.

The CPU then needs to notify the DMA that the linked list has been modified. This can be done by setting bit
SLC0_TXLINK_RESTART of the SLC0TX_LINK register. Please note that when the CPU initiates DMA to receive
packets for the first time, SLC0_TXLINK_RESTART should be set to 1.

Lastly, the CPU refreshes any available buffer information by writing to the SLC0TOKEN1 register.

8.3.6 SDIO Bus Timing

The SDIO bus operates at a very high speed and the PCB trace length usually affects signal integrity by
introducing latency. To ensure that the timing characteristics conform to the desired bus timing, the SDIO
Slave module supports configuration of input sampling clock edge and output driving clock edge.

When the incoming data changes near the rising edge of the clock, the Slave will perform sampling on the
falling edge of the clock, or vice versa, as Figure 8-9 shows.

Figure 8-9. Sampling Timing Diagram

By default, the MTDO strapping value determines the Slave’s sampling edge. However, users can decide the
sampling edge by configuring the SLCHOST_CONF_REG register, with priority from high to low: (1) Set
SLCHOST_FRC_POS_SAMP to sample the corresponding signal at the rising edge; (2) Set
SLCHOST_FRC_NEG_SAMP to sample the corresponding signal at the falling edge.

SLCHOST_FRC_POS_SAMP and SLCHOST_FRC_NEG_SAMP fields are five bits wide. The bits correspond to
the CMD line and four DATA lines (0-3). Setting a bit causes the corresponding line to be sampled for input at
the rising clock edge or falling clock edge.

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The Slave can also select which edge to drive the output lines, in order to accommodate for any latency
caused by the physical signal path. The output timing is shown in Figure 8-10.

Figure 8-10. Output Timing Diagram

By default, the GPIO5 strapping value determines the Slave’s output driving edge. However, users can decide
the output driving edge by configuring the following registers, with priority from high to low: (1) Set
SLCHOST_FRC_SDIO11 in SLCHOST_CONF_REG to output the corresponding signal at the falling clock edge;
(2) Set SLCHOST_FRC_SDIO22 in SLCHOST_CONF_REG to output the corresponding signal at the rising clock
edge; (3) Set HINF_HIGHSPEED_ENABLE in HINF_CFG_DATA1_REG and SLCHOST_HSPEED_CON_EN in
SLCHOST_CONF_REG, then set the EHS (Enable High-Speed) bit in CCCR at the Host side to output the
corresponding signal at the rising clock edge.

SLCHOST_FRC_SDIO11 and SLCHOST_FRC_SDIO22 fields are five bits wide. The bits correspond to the CMD
line and four DATA lines (0-3). Setting a bit causes the corresponding line to output at the rising clock edge or
falling clock edge.

Notes on priority setting: The configuration of strapping pins has the lowest priority when controlling the
sampling edge or driving edge. The lower-priority configuration takes effect only when the higher-priority
configuration is not set. For example, the MTDO strapping value determines the sampling edge only when
SCLHOST_FRC_POS_SAMP and SCLHOST_FRC_NEG_SAMP are not set.

8.3.7 Interrupt
Host and Slave can interrupt each other via the interrupt vector. Both Host and Slave have eight interrupt
vectors. The interrupt is enabled by configuring the interrupt vector register (setting the enable bit to 1). The
interrupt vector registers can clear themselves automatically, which means one interrupt at a time and no other
configuration is required.

8.3.7.1 Host Interrupt

• SLC0HOST_SLC0_RX_NEW_PACKET_INT Slave has a packet to send.

• SLC0HOST_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt.

• SLC0HOST_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt.

• SLC0HOST_SLC0_TOHOST_BITn_INT (n: 0 ~ 7) Slave interrupts Host.

8.3.7.2 Slave Interrupt

• SLC0INT_SLC0_RX_DSCR_ERR_INT Slave sending descriptor error.

• SLC0INT_SLC0_TX_DSCR_ERR_INT Slave receiving descriptor error.

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• SLC0INT_SLC0_RX_EOF_INT Slave sending operation is finished.

• SLC0INT_SLC0_RX_DONE_INT A single buffer is sent by Slave.

• SLC0INT_SLC0_TX_SUC_EOF_INT Slave receiving operation is finished.

• SLC0INT_SLC0_TX_DONE_INT A single buffer is finished during receiving operation.

• SLC0INT_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt.

• SLC0INT_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt.

• SLC0INT_SLC0_TX_START_INT Slave receiving interrupt initialization.

• SLC0INT_SLC0_RX_START_INT Slave sending interrupt initialization.

• SLC0INT_SLC_FRHOST_BITn_INT (n: 0 ~ 7) Host interrupts Slave.

8.4 Register Summary

Name Description Address Access
SDIO DMA (SLC) configuration registers
SLCCONF0_REG SLCCONF0_SLC configuration 0x3FF58000 R/W
SLC0RX_LINK_REG Transmitting linked list configuration 0x3FF5803C R/W
SLC0TX_LINK_REG Receiving linked list configuration 0x3FF58040 R/W
SLCINTVEC_TOHOST_REG Interrupt sector for Slave to interrupt Host 0x3FF5804C WO
SLC0TOKEN1_REG Number of receiving buffer 0x3FF58054 WO
SLCCONF1_REG Control register 0x3FF58060 R/W
SLC_RX_DSCR_CONF_REG DMA transmission configuration 0x3FF58098 R/W
SLC0_LEN_CONF_REG Length control of the transmitting packets 0x3FF580E4 R/W
SLC0_LENGTH_REG Length of the transmitting packets 0x3FF580E8 R/W
Interrupt Registers
SLC0INT_RAW_REG Raw interrupt status 0x3FF58004 RO
SLC0INT_ST_REG Interrupt status 0x3FF58008 RO
SLC0INT_ENA_REG Interrupt enable 0x3FF5800C R/W
SLC0INT_CLR_REG Interrupt clear 0x3FF58010 WO

Name Description Address Access

SDIO SLC Host registers
The accumulated number of Slave’s receiving
SLC0HOST_TOKEN_RDATA 0x3FF55044 RO
buffers
SLCHOST_PKT_LEN_REG Length of the transmitting packets 0x3FF55060 RO
SLCHOST_CONF_W0_REG Host and Slave communication register0 0x3FF5506C R/W
SLCHOST_CONF_W1_REG Host and Slave communication register1 0x3FF55070 R/W
SLCHOST_CONF_W2_REG Host and Slave communication register2 0x3FF55074 R/W
SLCHOST_CONF_W3_REG Host and Slave communication register3 0x3FF55078 R/W
SLCHOST_CONF_W4_REG Host and Slave communication register4 0x3FF5507C R/W
SLCHOST_CONF_W6_REG Host and Slave communication register6 0x3FF55088 R/W
SLCHOST_CONF_W8_REG Host and Slave communication register8 0x3FF5509C R/W
SLCHOST_CONF_W9_REG Host and Slave communication register9 0x3FF550A0 R/W

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SLCHOST_CONF_W10_REG Host and Slave communication register10 0x3FF550A4 R/W

SLCHOST_CONF_W11_REG Host and Slave communication register11 0x3FF550A8 R/W
SLCHOST_CONF_W12_REG Host and Slave communication register12 0x3FF550AC R/W
SLCHOST_CONF_W13_REG Host and Slave communication register13 0x3FF550B0 R/W
SLCHOST_CONF_W14_REG Host and Slave communication register14 0x3FF550B4 R/W
SLCHOST_CONF_W15_REG Host and Slave communication register15 0x3FF550B8 R/W
SLCHOST_CONF_REG Edge configuration 0x3FF551F0 R/W
Interrupt Registers
SLC0HOST_INT_RAW_REG Raw interrupt 0x3FF55000 RO
SLC0HOST_INT_ST_REG Masked interrupt status 0x3FF55058 RO
SLC0HOST_INT_CLR_REG Interrupt clear 0x3FF550D4 WO
SLC0HOST_FUNC1_INT_ENA_REG Interrupt enable 0x3FF550DC R/W
SLCHOST_CONF_W7_REG Interrupt vector for Host to interrupt Slave 0x3FF5508C WO

Name Description Address Access

SDIO HINF registers
HINF_CFG_DATA1_REG SDIO specification configuration 0x3FF4B004 R/W

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8.5 SLC Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave
base address (0x3FF5_8000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and
Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

Register 8.1. SLCCONF0_REG (0x0)

P_ ST K
R

OO TE AC
CL

_L P_ RB

ST
O_

TE
TX OO W
UT

0_ _L O_
_A

LC RX UT

TX ST
ST
EN

_S 0_ _A

0_ _R
_R
K

(re NF0 SLC RX

LC RX
TO
0_

O 0_ 0_

_S 0_
LC

CC F LC

F0 LC
_S

SL CON 0_S

ON 0_S
F0
d)

CC )
C F

CC F
ed

d
ON

SL CON

SL ON
ve

e
rv

rv
r

CC
se

se

se
C
(re

(re
SL

SL

SL
31 15 14 13 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset

SLCCONF0_SLC0_TOKEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W)

SLCCONF0_SLC0_RX_AUTO_WRBACK Allows changing the owner bit of the transmitting buffer’s

linked list when transmitting data. (R/W)

SLCCONF0_SLC0_RX_LOOP_TEST Loop around when the slave buffer finishes sending packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_TX_LOOP_TEST Loop around when the slave buffer finishes receiving packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_RX_RST Set this bit to reset the transmitting FSM. (R/W)

SLCCONF0_SLC0_TX_RST Set this bit to reset the receiving FSM. (R/W)

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Register 8.2. SLC0INT_RAW_REG (0x4)

IN AW

RA W
RA

SL INT LC_ RHO _B _IN RAW

IT T_ W

W
W

HO _B _IN AW
C_ HO BI IN AW
SL INT LC_ RHO _B _IN RAW

IN AW
R_ T_R

T_ RA

_B IN RA

RA
IN LC RH _B _IN RA
T_

SL INT LC_ RHO _B _IN W

ON OF AW

SL INT LC_ RHO _B NT_ W

W

FR ST T2 T_R
SL R T_ 3_ T_R

0_ R
IN T_
ER IN

C0 _S F ST IT7 RA

C0 _S F ST IT5 T_

ST IT1_ T_

T_
C0 _S F ST IT4 T_
C0 _S F ST _IN W
SU _I W

C0 _S F ST _I RA

C0 _S F ST IT6 T_
C0 _S 0_ ST INT W
_D _E _R
R_ R_

E_ _IN

SL INT LC_ RX_ ART _RA

C0 _ NE RA

SL INT LC X_ F_ _RA

SL INT LC_ RHO ART T_

TX C NT
SC ER

SL _TX O T_

C0 _S 0_ UD NT
N

T_ _F OS IT
_D CR_

C0 X_ F_I

SL INT LC RX_ F_I

C0 d) 0_ DS

C0 _S 0_ EO

C0 _S 0_ OV
D
SL rve LC RX_

SL INT LC RX_

SL INT C X_
TX

T
se _S 0_

C0 _S 0_

C0 _S 0_
(re INT LC

SL INT LC

SL NT C
L

L
L
C0 _S

C0 _S

C0 _S
)

)
_
ed

ed

ed
SL INT

SL INT

SL INT
IN
rv

rv

rv

I
C0

C0
se

se

se
(re

(re

(re
SL

SL
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error
(RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error.
(RO)

SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit for Slave sending operation finished. (RO)

SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave.
(RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt bit to mark Slave receiving operation as

finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during
Slave receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow.
(RO)

SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initialization
interrupt. (RO)

SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization inter-
rupt. (RO)

SLC0INT_SLC_FRHOST_BIT7_INT_RAW The interrupt mark bit 7 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT6_INT_RAW The interrupt mark bit 6 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT5_INT_RAW The interrupt mark bit 5 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT4_INT_RAW The interrupt mark bit 4 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT3_INT_RAW The interrupt mark bit 3 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO)

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Register 8.3. SLC0INT_ST_REG (0x8)

IN ST
ST

T_ ST

C0 T_ _F O BI IN T

IT NT_ T

ST
R_ T_

T_ _ O B IN ST

HO _B _ ST
C_ HO _B _I ST
T_

C T_ _ O BI IN T

IN T
SL 0IN SLC FRH ST_ T5_ T_S

_B _I _S
SL 0IN SLC FRH ST_ T6_ T_S

0_ S
IN T_
ER IN

T_
IN SLC RH ST_ T4_ T_
SL 0IN SLC FRH ST_ T7_ ST
ON OF ST

FR ST IT2 NT_
SL FR ST IT3 T_
SL 0IN SLC FRH ST_ _IN ST
ST

ST IT1 INT
E_ _IN
R_ RR_

C T_ _ _S T_ ST
ST

C T_ _ O BI T_
_D _E T_

C T_ 0 _S _I ST

C T_ _ O BI IN
C T_ _ O RT T_
SL 0IN SLC _RX TAR NT_
LC TX ON T_
SL ed) _TX UC _IN

SL 0IN SLC _TX DF T_

SL 0IN SLC FRH TA IN

SC _E

(re T_S 0_ _D _IN

C T_ 0 _U IN
E
_D R

SL IN SLC RX VF_
SL 0IN ) _TX SC

IN LC RX OF
C d 0 _D

C0 T_ 0_ _E

C0 T_ 0_ _O
_S
SL rve SLC _RX

SL IN SLC RX

SL IN LC TX
C0 T_ 0_

C0 T_ 0_
se T_ 0

0
(re 0IN SLC

SL IN SLC

SL IN SLC
S

S
d)

d)

C T_

C0 T_

C0 _ T
ve

ve

SL 0IN

SL 0IN
rv
r

r
se

se

se
C

C
(re

(re

SL
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_ST The interrupt status bit for Slave sending descriptor error.
(RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ST The interrupt status bit for Slave receiving descriptor error.
(RO)

SLC0INT_SLC0_RX_EOF_INT_ST The interrupt status bit for finished Slave sending operation. (RO)

SLC0INT_SLC0_RX_DONE_INT_ST The interrupt status bit for finished Slave sending operation.
(RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_ST The interrupt status bit for marking Slave receiving operation
as finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_ST The interrupt status bit for marking a single buffer as finished
during the receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_ST The interrupt status bit for Slave receiving overflow interrupt. (RO)

SLC0INT_SLC0_RX_UDF_INT_ST The interrupt status bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_ST The interrupt status bit for Slave receiving interrupt initialization.
(RO)

SLC0INT_SLC0_RX_START_INT_ST The interrupt status bit for Slave sending interrupt initialization.
(RO)

SLC0INT_SLC_FRHOST_BIT7_INT_ST The interrupt status bit 7 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT6_INT_ST The interrupt status bit 6 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT5_INT_ST The interrupt status bit 5 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT4_INT_ST The interrupt status bit 4 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT3_INT_ST The interrupt status bit 3 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO)

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8 SDIO Slave Controller

Register 8.4. SLC0INT_ENA_REG (0xC)

IN NA
A
EN

T_ ENA

_B _IN ENA

A
A

T_ 2_I ENA
T_ A
R_ _E

_IN NA
SL INT_ C_F OST IT5_ T_EN

EN
SL INT_ C_F OST IT4_ T_EN
T_ _FR ST_ T3_ _EN
SL INT_ C_F OST IT6_ _EN
T_

SL INT_ C_F OST IT7_ ENA

ER INT

DO OF NA

SL INT_ C_F OST T_IN NA

A

IT0 T_E
_IN T_

T_
EN

SL INT_ C_F _ST _IN A

A

HO BIT NT
SL INT_ C0_ _STA INT_ A

T
_E _E

SL RH _B INT
R T_E
RT EN
NE _IN
_

IN
IN
F_ EN

IN
SL RH _B T_

IN
SC ERR

E
_T SUC INT
T_ 0_T DO NT_

SL INT_ C0_ _UD NT_

1
_

T
_D R_
R_

I
I
I

SL RH _B
SL RH _B
SL RH _B
B
SL RX F_I
F_
N
C

A
SL rved C0_ _DS

ST
SL INT_ C0_ _EO

SL INT_ C0_ _OV

C_ OS
O
_
_
X_

SL RH

H
SL RX

SL RX
SL RX

SL RX
TX

SL TX

SL TX

FR
(re INT_ C0_

SL INT_ C0_

0_
C0
C

C
SL

SL

SL

SL
S
d)

d)

)
SL INT_

SL INT_

SL INT_

_
d

T
rve

rve

rve
IN

IN
I
C0
C0

C0
C0
C0
C0

C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
se

se

se

se
(re

(re

(re
SL

SL

SL
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave sending linked list de-
scriptor error. (R/W)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave receiving linked list de-
scriptor error. (R/W)

SLC0INT_SLC0_RX_EOF_INT_ENA The interrupt enable bit for Slave sending operation completion.
(R/W)

SLC0INT_SLC0_RX_DONE_INT_ENA The interrupt enable bit for single buffer’s sent interrupt, in
Slave sending mode. (R/W)

SLC0INT_SLC0_TX_SUC_EOF_INT_ENA The interrupt enable bit for Slave receiving operation com-
pletion. (R/W)

SLC0INT_SLC0_TX_DONE_INT_ENA The interrupt enable bit for single buffer’s full event, in Slave
receiving mode. (R/W)

SLC0INT_SLC0_TX_OVF_INT_ENA The interrupt enable bit for Slave receiving buffer overflow.
(R/W)

SLC0INT_SLC0_RX_UDF_INT_ENA The interrupt enable bit for Slave sending buffer underflow.
(R/W)

SLC0INT_SLC0_TX_START_INT_ENA The interrupt enable bit for Slave receiving operation initializa-
tion. (R/W)

SLC0INT_SLC0_RX_START_INT_ENA The interrupt enable bit for Slave sending operation initializa-
tion. (R/W)

SLC0INT_SLC_FRHOST_BIT7_INT_ENA The interrupt enable bit 7 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT6_INT_ENA The interrupt enable bit 6 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT5_INT_ENA The interrupt enable bit 5 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT4_INT_ENA The interrupt enable bit 4 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT3_INT_ENA The interrupt enable bit 3 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT2_INT_ENA The interrupt enable bit 2 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT1_INT_ENA The interrupt enable bit 1 for Host to interrupt Slave. (R/W)
Espressif Systems 173 ESP32 TRM (Version 5.2)
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Submit The interrupt enable
Documentation bit 0 for Host to interrupt Slave. (R/W)
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8 SDIO Slave Controller

Register 8.5. SLC0INT_CLR_REG (0x10)

IN LR
R
CL

T_ CLR

_B _IN CLR

R
I N LR
R_ _C

T_ 2_I CLR
T_ R
R

_IN LR
L

CL
T_ _FR ST_ T3_ _CL
T_

SL INT_ C_F OST IT6_ _CL

ER INT

SL INT_ C_F OST IT5_ T_C

SL INT_ C_F OST IT4_ T_C
SL INT_ C_F OST IT7_ LR
DO OF LR

SL INT_ C_F OST T_IN LR

R

IT0 T_C
_IN T_

T_
CL

SL INT_ C_F _ST _IN R

R

HO BIT NT
SL RH _B T_C
_E _C

F_ CLR

T
R T_C

SL RH _B INT
NE _IN
_

RT CL
L

IN
IN

IN
SC ERR

C
_T SUC INT

SL INT_ C0_ _STA INT_

T_ 0_T DO NT_

SL INT_ C0_ _UD NT_

1
_

T
_D R_
R_

I
I
I

SL RH _B
SL RH _B
SL RH _B
B
SL RX F_I
F_
N
C

A
SL rved C0_ _DS

ST
SL INT_ C0_ _EO

SL INT_ C0_ _OV

C_ OS
O
_
_
X_

SL RH

H
SL RX

SL RX
SL RX

SL RX
TX

SL TX

SL TX

FR
(re INT_ C0_

SL INT_ C0_

0_
C0
C

C
SL

SL

SL

SL
S
d)

d)

)
SL INT_

SL INT_

SL INT_

_
d

T
rve

rve

rve
IN

IN
I
C0
C0

C0
C0
C0
C0

C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
C0
se

se

se

se
(re

(re

(re
SL

SL

SL
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor
error. (WO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor
error. (WO)

SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO)

SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer’s sent interrupt, in Slave
sending mode. (WO)

SLC0INT_SLC0_TX_SUC_EOF_INT_CLR Interrupt clear bit for Slave receiving operation completion.

(WO)

SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer’s full event, in Slave receiv-
ing mode. (WO)

SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO)

SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO)

SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation
initialization. (WO)

SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation
initialization. (WO)

SLC0INT_SLC_FRHOST_BIT7_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT7_INT in-

terrupt. (WO)

SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT6_INT

interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT5_INT

interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT4_INT

interrupt. (WO)

Continued on the next page...

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8 SDIO Slave Controller

Register 8.5. SLC0INT_CLR_REG (0x10)

Continued from the previous page...

SLC0INT_SLC_FRHOST_BIT3_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT3_INT inter-

rupt. (WO)

SLC0INT_SLC_FRHOST_BIT2_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT2_INT inter-

rupt. (WO)

SLC0INT_SLC_FRHOST_BIT1_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT1_INT inter-

rupt. (WO)

SLC0INT_SLC_FRHOST_BIT0_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT0_INT inter-

rupt. (WO)

Register 8.6. SLC0RX_LINK_REG (0x3C)

NK TA T
LI _S AR
_S RT

DR
P
RX K EST

TO

AD
0_ LIN R
LC RX K_

K_
_S 0_ LIN

IN
XL
RX LC RX

R
C0 _S 0_

0_
SL 0RX LC

LC
C _S

_S
SL RX )

)
C0 d

ed
SL rve

RX
rv

C0
se

se
(re

(re

SL

31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0RX_SLC0_RXLINK_RESTART Set this bit to restart and continue the linked list operation for
sending packets. (R/W)

SLC0RX_SLC0_RXLINK_START Set this bit to start the linked list operation for sending packets.
Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W)

SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W)

SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list.
(R/W)

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Register 8.7. SLC0TX_LINK_REG (0x40)

NK TA T
LI S AR
_S RT

R
P
TX K_ ST

DD
TO
0_ LIN RE

_A
LC TX K_

K
_S 0_ LIN

IN
XL
TX LC TX

_T
C0 _S 0_

C0
SL 0TX LC

SL
C _S
SL TX )

)
C0 d

ed

X_
SL rve

rv

T
C0
se

se
(re

(re

SL
31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0TX_SLC0_TXLINK_RESTART Set this bit to restart and continue the linked list operation for
receiving packets. (R/W)

SLC0TX_SLC0_TXLINK_START Set this bit to start the linked list operation for receiving packets.
Receiving will start from the address indicated by SLC0_TXLINK_ADDR. (R/W)

SLC0TX_SLC0_TXLINK_STOP Set this bit to stop the linked list operation for receiving packets.
(R/W)

SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked
list. (R/W)

Register 8.8. SLCINTVEC_TOHOST_REG (0x4C)

EC
TV
N
_I
ST
HO
TO
0_
LC
S
C_
)

VE
ed

ed

ed

NT
rv

rv

rv
se

se

se

CI
(re

(re

(re

SL

31 24 23 16 15 8 7 0

0x000 0 0 0 0 0 0 0 0 0x000 0x000 Reset

SLCINTVEC_SLC0_TOHOST_INTVEC The interrupt vector for Slave to interrupt Host. (WO)

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Register 8.9. SLC0TOKEN1_REG (0x54)

E
OR
_M

TA
DA
NC

W
_I

1_
1

N1
EN

EN
KE
OK

OK
TO
_T

_T
0_
C0

C0
ed SLC
SL

SL
1_

1_
se EN1
EN

EN
)

TO )

)
ed

C0 d
K

K
SL rve
TO

TO
rv

rv
C0

C0
se

se
(re

(re

(re
SL

SL
31 28 27 16 15 14 13 12 11 0

0x00 0x0000 0 0 0 0 0x0000 Reset

SLC0TOKEN1_SLC0_TOKEN1 The accumulated number of buffers for receiving packets. (RO)

SLC0TOKEN1_SLC0_TOKEN1_INC_MORE Set this bit to add the value of

SLC0TOKEN1_SLC0_TOKEN1_WDATA to that of SLC0TOKEN1_SLC0_TOKEN1. (WO)

SLC0TOKEN1_SLC0_TOKEN1_WDATA The number of available receiving buffers. (WO)

Register 8.10. SLCCONF1_REG (0x60)

LR
N_ CH N
TO N
LE TIT _E

_C
AU _E
0_ _S CH
LC TX TIT
_S 0_ S
F1 LC RX_
ON 1_S 0_
CC F LC
SL CON 1_S
)

C F
ed

ed

ed

SL CON
rv

rv

rv
se

se

se

C
(re

(re

(re

SL

31 23 22 16 15 7 6 5 4

0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Reset

SLCCONF1_SLC0_RX_STITCH_EN Please initialize to 0. Do not modify it. (R/W)

SLCCONF1_SLC0_TX_STITCH_EN Please initialize to 0. Do not modify it. (R/W)

SLCCONF1_SLC0_LEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W)

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Register 8.11. SLC_RX_DSCR_CONF_REG (0x98)

E
AC
PL
E
_R
NO
N_
KE
TO
0_
d)

LC
ve

S
r
se

C_
(re

SL
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC_SLC0_TOKEN_NO_REPLACE Please initialize to 1. Do not modify it. (R/W)

Register 8.12. SLC0_LEN_CONF_REG (0xE4)

O RE
ed C_M

TA
DA
N

_W
_I
EN

EN
)

)
ed

ed

_L

_L
rv

rv

rv
C0

C0
se

se

se
(re

(re

(re
SL

31 29 28 23 22 21 20 19
SL 0

0x0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA.
(WO)

SLC0_LEN_WDATA The packet length sent. (WO)

Register 8.13. SLC0_LENGTH_REG (0xE8)

N
)
ed

LE
rv

_
C0
se
(re

SL

31 20 19 0

0x0000 0x000000 Reset

SLC0_LEN Indicates the packet length sent by the Slave. (RO)

8.6 SLC Host Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave
base address (0x3FF5_5000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and
Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

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Register 8.14. SLC0HOST_TOKEN_RDATA (0x44)

N1
KE
TO
0_
LC
_S
)

d)
ed

EG

ve
rv

r
ST
se

se
HO
(re

(re
31 28 27 16 15 0

0x000 0x000 0x000 Reset

HOSTREG_SLC0_TOKEN1 The accumulated number of Slave’s receiving buffers. (RO)

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Register 8.15. SLC0HOST_INT_RAW_REG (0x50)

W
RA

SL HOS SLC OH T_BI _INT AW

IT0 T_R W

W
HO _SL _TO ST_B 4_IN RAW

HO _BIT INT W
LC OH T_B _INT AW
SL HOS SLC OH T_BI _INT AW

_IN AW
T_

1_ _RA

RA
A
_R
_IN

_R
R
T6 _R

T_
_
T_
W

SL HOS SLC OH T_BI INT

ET

_IN AW

_B IN
RA
CK

_
_
DF _R

0_ OS IT2
T5
T_

3
T7
PA

T
T
_U NT

SL HOS SLC OH T_BI

I
W_

RX F_I

T
ST
T_ 0_T OS
T_ 0_T OS
T_ 0_T OS
T_ 0_T OS

S
NE

0_ OV

O
ST C0 HO
X_

SL HOS SLC OH
LC X_

TO
R

_S _T

T_ 0_T

_S _T
0_

ST C0

0
LC

SL HOS SLC
HO SL
_S

T_

T_
ST

T
d)

d)

d)

d)
OS

SL HOS
rve

rve

rve

rve
HO

H
C0

C0
C0

C0
C0
C0
C0
C0
C0
C0
C0
se

se

se

se
(re

(re

(re

(re
SL

SL
SL

SL
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

SLC0HOST_SLC0_TX_OVF_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

SLC0HOST_SLC0_RX_UDF_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

Espressif Systems 180 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.16. SLC0HOST_INT_ST_REG (0x58)

T
_S
INT

C0 ST_S 0_TO ST_B _INT T

_IN ST

T
C0 ST_S 0_TO ST_B _INT T

C0 HOS IT2 T_ST

_IN T
IT6 _ST

0_ ST
_S

_S
S
_S

T_
_

_
ET_

C0 ST_S 0_TO ST_B _INT

INT
C0 ST_S 0_TO ST_B _INT

T
_ IN
T
F_ ST
CK

_S

IT5

IT3
IT 7

IT4

HO BIT1
_
INT
PA

BIT
X_ _INT

C0 ST_S 0_TO ST_B

B
W_

ST_
T_
ST_
F
UD
NE

C0 _OV

HO
HO
HO
HO
HO
HO
X_

C0 ST_S 0_TO

O
_TO
X
_R

_R
ST_ C0_T

ST_ 0_T
C0

LC
LC
LC
LC
LC
LC
LC
SL

L
SL

SL
C0 ST_S

C0 ST_S
ST_
d)

d)

d)

d)
rve

rve

rve

rve
HO

HO
HO

HO
HO
HO
HO
HO
HO
HO
HO
C0

C0

C0
se

se

se

se
(re

(re

(re

(re
SL

SL
SL

SL
SL
SL
SL
SL
SL
SL
SL
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

SLC0HOST_SLC0_TX_OVF_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

SLC0HOST_SLC0_RX_UDF_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

Espressif Systems 181 ESP32 TRM (Version 5.2)

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Register 8.17. SLCHOST_PKT_LEN_REG (0x60)

K
H EC
_C
EN

N
LE
L
0_

0_
LC

LC
_S

_S
EG

EG
TR

TR
OS

OS
H

_H
T_

ST
OS

O
CH

CH
SL

SL
31 20 19 0

0x000 0x000 Reset

SLCHOST_HOSTREG_SLC0_LEN_CHECK Its value is HOSTREG_SLC0_LEN[9:0] plus

HOSTREG_SLC0_LEN[19:10]. (RO)

SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The
value gets updated only when the Host reads it.

Register 8.18. SLCHOST_CONF_W0_REG (0x6C)

F0
F2
F3

F1
ON

ON

ON
CO
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

Espressif Systems 182 ESP32 TRM (Version 5.2)

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Register 8.19. SLCHOST_CONF_W1_REG (0x70)

F5

4
F7

NF

F
ON

ON

ON
CO
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

Register 8.20. SLCHOST_CONF_W2_REG (0x74)

0
11

F9

8
F1
NF

F
ON

ON

ON
O
_C

C
T_

T_

T_
ST

OS

OS

OS
O
CH

CH

CH

CH
SL

SL

SL

31 24 23 16 15 8 7
SL 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

Espressif Systems 183 ESP32 TRM (Version 5.2)

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Register 8.21. SLCHOST_CONF_W3_REG (0x78)

15

1 4
NF

NF
O

O
_C

_C

)
ed

ed
ST

ST

rv

rv
O

O
CH

CH

se

se
(re

(re
SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x0 0xc0 Reset

SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)

SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)

Register 8.22. SLCHOST_CONF_W4_REG (0x7C)

19

8
F1
F
ON

N
CO
C
T_

T_

)
ed

ed
OS

OS

rv

rv
CH

CH

se

se
(re

(re
SL

SL

31 24 23 16 15 8 7 0

0x000 0x000 0x1 0xff Reset

SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 184 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.23. SLCHOST_CONF_W6_REG (0x88)

26

24
7
F2

F2
NF

F
ON

ON

ON
O
C

_C

C
T_

T_

T_
ST
OS

OS

OS
O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.24. SLCHOST_CONF_W8_REG (0x9C)

3
35

32
4
F3

F3
F

F
ON

ON

ON

ON
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

31 24 23 16 15 8 7 SL 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 185 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.25. SLCHOST_CONF_W9_REG (0xA0)

36
9

7
F3

F3
NF

F
ON

ON

ON
CO
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.26. SLCHOST_CONF_W10_REG (0xA4)

40
2
43

1
F4

F4
NF

F
ON

ON

ON
O
_C

C
T_

T_

T_
ST

OS

OS

OS
O
CH

CH

CH

CH
SL

SL

SL

31 24 23 16 15 8 7 SL 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 186 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.27. SLCHOST_CONF_W11_REG (0xA8)

46

44
47

F4
NF

NF

F
ON

ON
O

O
_C

_C

C
T_

T_
ST

ST

OS

OS
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.28. SLCHOST_CONF_W12_REG (0xAC)

0

48
9
51

F5

F4
F

F
ON

ON

ON

ON
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

31 24 23 16 15 8 7 SL 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 187 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.29. SLCHOST_CONF_W13_REG (0xB0)

55

52
5 4

F5
NF

NF

F
ON

ON
O

O
_C

_C

C
T_

T_
ST

ST

OS

OS
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.30. SLCHOST_CONF_W14_REG (0xB4)

56
8
9

7
F5

F5

F5

F
ON

ON

ON

ON
C

C
T_

T_

T_

T_
OS

OS

OS

OS
CH

CH

CH

CH
SL

SL

SL

31 24 23 16 15 8 7 SL 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 188 ESP32 TRM (Version 5.2)

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Register 8.31. SLCHOST_CONF_W15_REG (0xB8)

60
3

62

61
F6

NF

NF

F
ON

ON
CO

O
C

_C

C
T_

T_

T_
ST
OS

OS

OS
O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Espressif Systems 189 ESP32 TRM (Version 5.2)

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8 SDIO Slave Controller

Register 8.32. SLC0HOST_INT_CLR_REG (0xD4)

LR
_C

C0 ST_S 0_TO ST_B _INT LR

_IN CLR

LR
C0 ST_S 0_TO ST_B _INT LR

R
_IN LR
C0 ST_S 0_TO ST_B _INT R

0_ CLR
INT

C0 HOS IT2 T_CL

IT6 _CL
_C

_C
C
_C

T_
_

T_
ET_

INT
C0 ST_S 0_TO ST_B _INT
LR

_ IN
F_ CLR
CK

_C

IT5

IT3
IT 7

IT4

HO BIT1
_
INT
PA

BIT
X_ _INT

C0 ST_S 0_TO ST_B

B
W_

ST_
T_
ST_
F
UD
NE

C0 _OV

HO
HO
HO
HO
HO
HO
X_

C0 ST_S 0_TO

O
_TO
X
_R

_R
ST_ C0_T

ST_ 0_T
C0

LC
LC
LC
LC
LC
LC
LC
SL

L
SL

SL
C0 ST_S

C0 ST_S
ST_
d)

d)

d)

d)
rve

rve

rve

rve
HO

HO
HO

HO
HO
HO
HO
HO
HO
HO
HO
C0

C0

C0
se

se

se

se
(re

(re

(re

(re
SL

SL
SL

SL
SL
SL
SL
SL
SL
SL
SL
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (WO)

SLC0HOST_SLC0_TX_OVF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TX_OVF_INT inter-

rupt. (WO)

SLC0HOST_SLC0_RX_UDF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_UDF_INT inter-

rupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO)

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Register 8.33. SLC0HOST_FUNC1_INT_ENA_REG (0xDC)

NA
_E

_IN NA

_IN ENA

NA
ST_ 1_SL _TOH T_BI INT_ A

0_ OST T2_I ENA

A
NA

0_ ENA
N
INT

EN
C0 ST_F SLC OHO BIT5 NT_E

_E
C0 ST_F SLC OHO BIT4 T_E
C0 ST_F SLC OHO BIT6 T_E

_
BI INT_

T_
T_

NT

INT
A
_IN NA

_IN
EN
KE

_I

_
_
E
AC

T_

T3
C0 ST_F SLC OHO BIT7

HO BIT1
_U INT_

B IT
_P

ST_
ST_
T_
ST_

T_
_
ST_
EW

0_ OVF_
DF

S
OS
_N

C0 ST_F SLC OHO

H
_
RX

RX

1_S _TO
TO
1_S 0_TX

N1_ 0_T
N1_ 0_T
N1_ 0_T
N1_ 0_T
N1_ 0_T
0_

0
C0
LC

C
LC

C0 ST_F SLC

LC
ST_ 1_SL
1_S

N1_
FN

N
FN

N
FN
C0 ST_F

C0 ST_F
ST_
d)

d)

d)

d)
rve

rve

rve

rve
HO

HO
HO

HO
HO
HO
HO
HO
HO
HO
HO
C0

C0

C0
se

se

se

se
(re

(re

(re

(re
SL

SL
SL

SL
SL
SL
SL
SL
SL
SL
SL
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TX_OVF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_RX_UDF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W)

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Register 8.34. SLCHOST_CONF_W7_REG (0x8C)

9
1

F2
F3
ON

ON
C

C
T_

T_
)

)
ed

ed
OS

OS
rv

rv
CH

CH
se

se
(re

(re
SL

SL
31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0x000 0 0 0 0 0 0 0 0 0x000 Reset

SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)

SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)

Register 8.35. SLCHOST_CONF_REG (0x1F0)

N

P
_E

M
N

20
CO

_S

_S

11
IO

IO
OS

EG
D_

D
_N
_P
EE

_S

_S
SP

RC

RC

RC

RC
H

_F

_F

F
T_

T_

T_
)

)
ed

ed

ST

ST
OS

OS

OS
rv

rv

O
CH

CH

CH

CH

CH
se

se
(re

(re
SL

SL

SL

SL

SL
31 28 27 26 20 19 15 14 10 9 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLCHOST_HSPEED_CON_EN Set this bit and HINF_HIGHSPEED_ENABLE, then set the EHS (Enable
High-Speed) bit in CCCR at the Host side to output the corresponding signal at the rising clock
edge. (R/W)

SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge.
(R/W)

SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge.
(R/W)

SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge.
(R/W)

SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge.
(R/W)

8.7 HINF Registers

The addresses in parenthesis besides register names are the register addresses relative to the SDIO Slave
base address (0x3FF4_B000) provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and
Memory. The absolute register addresses are listed in Section 8.4 Register Summary.

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Register 8.36. HINF_CFG_DATA1_REG (0x4)

Y1 LE
AD AB
RE N
IO _E
O_ ED
DI PE
_S HS
)
ed

NF IG
HI _H
rv
se

NF
(re

HI
31 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

HINF_HIGHSPEED_ENABLE Please initialize to 1. Do not modify it. (R/W)

HINF_SDIO_IOREADY1 Please initialize to 1. Do not modify it. (R/W)

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9 SD/MMC Host Controller

9.1 Overview
The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral
Bus (APB) and an external memory device. The memory card interface allows the ESP32 to be connected to
SDIO memory cards, MMC cards and devices with a CE-ATA interface. It supports two external cards (Card0
and Card1).

9.2 Features
This module has the following features:

• Two external cards

• Supports SD Memory Card standard: versions 3.0 and 3.01

• Supports MMC: versions 4.41, 4.5, and 4.51

• Supports CE-ATA: version 1.1

• Supports 1-bit, 4-bit, and 8-bit (Card0 only) modes

The SD/MMC controller topology is shown in Figure 9-1. The controller supports two peripherals which cannot
be functional at the same time.

Figure 9-1. SD/MMC Controller Topology

9.3 SD/MMC External Interface Signals

The primary external interface signals, which enable the SD/MMC controller to communicate with an external
device, are clock (clk), command (cmd) and data signals. Additional signals include the card interrupt, card
detect, and write-protect signals. The direction of each signal is shown in Figure 9-2. The direction and de-
scription of each pin are listed in Table 9-1.

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Figure 9-2. SD/MMC Controller External Interface Signals

Table 9-1. SD/MMC Signal Description

Pin Direction Description

cclk_out Output Clock signals for slave device
ccmd Duplex Duplex command/response lines
cdata Duplex Duplex data read/write lines
card_detect_n Input Card detection input line
card_write_prt Input Card write protection status input

9.4 Functional Description

9.4.1 SD/MMC Host Controller Architecture
The SD/MMC host controller consists of two main functional blocks, as shown in Figure 9-3:

• Bus Interface Unit (BIU): It provides APB interfaces for registers, data read and write operation by FIFO and
DMA.

• Card Interface Unit (CIU): It handles external memory card interface protocols. It also provides clock
control.

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Figure 9-3. SDIO Host Block Diagram

9.4.1.1 BIU
The BIU provides the access to registers and FIFO data through the Host Interface Unit (HIU). Additionally, it
provides FIFO access to independent data through a DMA interface. The host interface can be configured
as an APB interface. Figure 9-3 illustrates the internal components of the BIU. The BIU provides the following
functions:

• Host interface

• DMA interface

• Interrupt control

• Register access

• FIFO access

• Power/pull-up control and card detection

9.4.1.2 CIU
The CIU module implements the card-specific protocols. Within the CIU, the command path control unit and
data path control unit prompt the controller to interface with the command and data ports, respectively, of the
SD/MMC/CE-ATA cards. The CIU also provides clock control. Figure 9-3 illustrates the internal structure of the
CIU, which consists of the following primary functional blocks:

• Command path

• Data path

• SDIO interrupt control

• Clock control

• Mux/demux unit

9.4.2 Command Path

The command path performs the following functions:

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• Configures clock parameters

• Configures card command parameters

• Sends commands to card bus (ccmd_out line)

• Receives responses from card bus (ccmd_in line)

• Sends responses to BIU

• Drives the P-bit on the command line

The command path State Machine is shown in Figure 9-4.

Figure 9-4. Command Path State Machine

9.4.3 Data Path

The data path block pops FIFO data and transmits them on cdata_out during a write-data transfer, or it receives
data on cdata_in and pushes them into FIFO during a read-data transfer. The data path loads new data pa-
rameters, i.e., expected data, read/write data transfer, stream/block transfer, block size, byte count, card type,
timeout registers, etc., whenever a data transfer command is not in progress.

If the data_expected bit is set in the Command register, the new command is a data-transfer command and the
data path starts one of the following operations:

• Transmitting data if the read/write bit = 1

• Receiving data if read/write bit = 0

9.4.3.1 Data Transmit Operation

The data transmit state machine is illustrated in Figure 9-5. The module starts data transmission two clock
cycles after a response for the data-write command is received. This occurs even if the command path detects
a response error or a cyclic redundancy check (CRC) error in a response. If no response is received from the
card until the response timeout, no data are transmitted. Depending on the value of the transfer_mode bit in the
Command register, the data-transmit state machine adds data to the card’s data bus in a stream or in block(s).
The data transmit state machine is shown in Figure 9-5.

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Figure 9-5. Data Transmit State Machine

9.4.3.2 Data Receive Operation

The data-receive state machine is illustrated in Figure 9-6. The module receives data two clock cycles after
the end bit of a data-read command, even if the command path detects a response error or a CRC error. If no
response is received from the card and a response timeout occurs, the BIU does not receive a signal about
the completion of the data transfer. If the command sent by the CIU is an illegal operation for the card, it would
prevent the card from starting a read-data transfer, and the BIU will not receive a signal about the completion of
the data transfer.

If no data are received by the data timeout, the data path signals a data timeout to the BIU, which marks an end
to the data transfer. Based on the value of the transfer_mode bit in the Command register, the data-receive
state machine gets data from the card’s data bus in a stream or block(s). The data receive state machine is
shown in Figure 9-6.

Figure 9-6. Data Receive State Machine

9.5 Software Restrictions for Proper CIU Operation

• Only one card at a time can be selected to execute a command or data transfer. For example, when data
are being transferred to or from a card, a new command must not be issued to another card. A new
command, however, can be issued to the same card, allowing it to read the device status or stop the
transfer.

• Only one command at a time can be issued for data transfers.

• During an open-ended card-write operation, if the card clock is stopped due to FIFO being empty, the

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software must fill FIFO with data first, and then start the card clock. Only then can it issue a stop/abort
command to the card.

• During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to resume
the suspended transfer, it must first reset FIFO, and then issue the resume command as if it were a new
data-transfer command.

• When issuing card reset commands (CMD0, CMD15 or CMD52_reset), while a card data transfer is in
progress, the software must set the stop_abort_cmd bit in the Command register, so that the CIU can
stop the data transfer after issuing the card reset command.

• When the data’s end bit error is set in the RINTSTS register, the CIU does not guarantee SDIO interrupts. In
such a case, the software ignores SDIO interrupts and issues a stop/abort command to the card, so that
the card stops sending read-data.

• If the card clock is stopped due to FIFO being full during a card read, the software will read at least two
FIFO locations to restart the card clock.

• Only one CE-ATA device at a time can be selected for a command or data transfer. For example, when
data are transferred from a CE-ATA device, a new command should not be sent to another CE-ATA device.

• If a CE-ATA device’s interrupts are enabled (nIEN=0), a new RW_BLK command should not be sent to the
same device if the execution of a RW_BLK command is already in progress (the RW_BLK command used
in this databook is the RW_MULTIPLE_BLOCK MMC command defined by the CE-ATA specifications). Only
the CCSD can be sent while waiting for the CCS.

• If, however, a CE-ATA device’s interrupts are disabled (nIEN=1), a new command can be issued to the same
device, allowing it to read status information.

• Open-ended transfers are not supported in CE-ATA devices.

• The send_auto_stop signal is not supported (software should not set the send_auto_stop bit) in CE-ATA
transfers.

After configuring the command start bit to 1, the values of the following registers cannot be changed before a
command has been issued:

• CMD - command

• CMDARG - command argument

• BYTCNT - byte count

• BLKSIZ - block size

• CLKDIV - clock divider

• CKLENA - clock enable

• CLKSRC - clock source

• TMOUT - timeout

• CTYPE - card type

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9.6 RAM for Receiving and Sending Data

The submodule RAM is a buffer area for sending and receiving data. It can be divided into two units: the one
is for sending data, and the other is for receiving data. The process of sending and receiving data can also
be achieved by the CPU and DMA for reading and writing. The latter method is described in detail in Section
9.8.

9.6.1 Transmit RAM Module

There are two ways to enable a write operation: DMA and CPU read/write.

If SDIO-sending is enabled, data can be written to the transferred RAM module by APB interface or DMA. Data
will be written from register EMAC_FIFO to the CPU, directly, by an APB interface.

9.6.2 Receive RAM Module

There are two ways to enable a read operation: DMA and CPU read/write.

When a subunit of the data path receives data, the subdata will be written onto the receive-RAM. Then, these
subdata can be read either with the APB or the DMA method at the reading end. Register EMAC_FIFO can be
read by the APB directly.

9.7 Descriptor Chain

Each linked list module consists of two parts: the linked list itself and a data buffer. In other words, each module
points to a unique data buffer and the linked list that follows the module. Figure 9-7 shows the descriptor
chain.

Figure 9-7. Descriptor Chain

9.8 The Structure of a Linked List

Each linked list consists of four words. As is shown below, Figure 9-8 demonstrates the linked list’s structure,
and Table 9-2, Table 9-3, Table 9-4, Table 9-5 provide the descriptions of linked lists.

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Figure 9-8. The Structure of a Linked List

The DES0 element contains control and status information.

Table 9-2. DES0

Bits Name Description

When set, this bit indicates that the descriptor is
owned by the DMAC. When reset, it indicates that
31 OWN
the descriptor is owned by the Host. The DMAC
clears this bit when it completes the data transfer.
These error bits indicate the status of the transition
to or from the card.
The following bits are also present in RINTSTS, which
indicates their digital logic OR gate.
• EBE: End Bit Error
30 CES (Card Error Summary) • RTO: Response Time out
• RCRC: Response CRC
• SBE: Start Bit Error
• DRTO: Data Read Timeout
• DCRC: Data CRC for Receive
• RE: Response Error

29:6 Reserved Reserved

When set, this bit indicates that the descriptor list
has reached its final descriptor. The DMAC then re-
5 ER (End of Ring)
turns to the base address of the list, creating a De-
scriptor Ring.
When set, this bit indicates that the second ad-
CH
4 dress in the descriptor is the Next Descriptor ad-
(Second Address Chained)
dress. When this bit is set, BS2 (DES1[25:13]) should
be all zeros.

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Bits Name Description

When set, this bit indicates that this descriptor con-
tains the first buffer of the data. If the size of the first
3 FD (First Descriptor)
buffer is 0, the Next Descriptor contains the begin-
ning of the data.
This bit is associated with the last block of a DMA
transfer. When set, the bit indicates that the buffers
pointed by this descriptor are the last buffers of the
2 LD (Last Descriptor) data. After this descriptor is completed, the remain-
ing byte count is 0. In other words, after the descrip-
tor with the LD bit set is completed, the remaining
byte count should be 0.
When set, this bit will prevent the setting of the TI/RI
DIC (Disable Interrupt
1 bit of the DMAC Status Register (IDSTS) for the data
on Completion)
that ends in the buffer pointed by this descriptor.
0 Reserved Reserved

The DES1 element contains the buffer size.

Table 9-3. DES1

Bits Name Description

31:26 Reserved Reserved
25:13 Reserved Reserved
Indicates the data buffer byte size, which must be a
multiple of four. In the case where the buffer size is
12:0 BS1 (Buffer 1 Size)
not a multiple of four, the resulting behavior is unde-
fined. This field should not be zero.

The DES2 element contains the address pointer to the data buffer.

Table 9-4. DES2

Bits Name Description

These bits indicate the physical address of the data
31:0 Buffer Address Pointer 1
buffer.

The DES3 element contains the address pointer to the next descriptor if the present descriptor is not the last
one in a chained descriptor structure.
Table 9-5. DES3

Bits Name Description

If the Second Address Chained (DES0[4]) bit is set,
then this address contains the pointer to the physical
31:0 Next Descriptor Address memory where the Next Descriptor is present.

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Bits Name Description

If this is not the last descriptor, then the Next De-
scriptor address pointer must be DES3[1:0] = 0.

9.9 Initialization
9.9.1 DMAC Initialization
The DMAC initialization should proceed as follows:

• Write to the DMAC Bus Mode Register (BMOD_REG) will set the Host bus’s access parameters.

• Write to the DMAC Interrupt Enable Register (IDINTEN) will mask any unnecessary interrupt causes.

• The software driver creates either the transmit or the receive descriptor list. Then, it writes to the DMAC
Descriptor List Base Address Register (DBADDR), providing the DMAC with the starting address of the list.

• The DMAC engine attempts to acquire descriptors from descriptor lists.

9.9.2 DMAC Transmission Initialization

The DMAC transmission occurs as follows:

1. The Host sets up the elements (DES0-DES3) for transmission, and sets the OWN bit (DES0[31]). The Host
also prepares the data buffer.

2. The Host programs the write-data command in the CMD register in BIU.

3. The Host also programs the required transmit threshold (TX_WMARK field in FIFOTH register).

4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMAC enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.

5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can
be done.

6. Subsequently, the DMAC engine waits for a DMA interface request (dw_dma_req) from BIU. This request
will be generated, based on the programmed transmit-threshold value. For the last bytes of data which
cannot be accessed using a burst, single transfers are performed on the AHB Master Interface.

7. The DMAC fetches the transmit data from the data buffer in the Host memory and transfers them to FIFO
for transmission to card.

8. When data span across multiple descriptors, the DMAC fetches the next descriptor and extends its op-
eration using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.

9. When data transmission is complete, the status information is updated in the IDSTS register by setting the
Transmit Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write transaction to DES0.

9.9.3 DMAC Reception Initialization

The DMAC reception occurs as follows:

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1. The Host sets up the element (DES0-DES3) for reception, and sets the OWN bit (DES0[31]).

2. The Host programs the read-data command in the CMD register in BIU.

3. Then, the Host programs the required level of the receive-threshold (RX_WMARK field in FIFOTH register).

4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMA enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.

5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can
be done.

6. The DMAC engine then waits for a DMA interface request (dw_dma_req) from BIU. This request will be
generated, based on the programmed receive-threshold value. For the last bytes of the data which cannot
be accessed using a burst, single transfers are performed on the AHB.

7. The DMAC fetches the data from FIFO and transfers them to the Host memory.

8. When data span across multiple descriptors, the DMAC will fetch the next descriptor and extend its op-
eration using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.

9. When data reception is complete, the status information is updated in the IDSTS register by setting
Receive-Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write-transaction to DES0.

9.10 SD/MMC Timing

Figure 9-9 shows the timing diagram for SD/MMC in high-speed (HS) mode. Table 9-6 lists the timing re-
quirements. These requirements are crucial for ensuring reliable and synchronized data communication in HS
mode.

tW(CKH) tW(CKL)

CK
tOV tOH
D, CMD
(output)
tISU tIH
D, CMD
(input)

Figure 9-9. SD/MMC Timing in HS Mode

Table 9-6. SD/MMC Timing Requirements

Symbol Parameter Conditions Min Typ Max Unit

tW (CKL) Clock Low Time fP P = 80 MHz 11.5 12.5 — ns
tW (CKH) Clock High Time fP P = 80 MHz 11.5 12.5 — ns

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tISU Input Setup Time in HS Mode fP P = 80 MHz 3.4 — — ns

tIH Input Hold Time in HS Mode fP P = 80 MHz 1.1 — — ns
tOV Output Valid Time in HS Mode fP P = 80 MHz — — 5.9 ns
tOH Output Hold Time in HS Mode fP P = 80 MHz 0.5 — — ns

Legend:

• fP P - Clock frequency in data transfer mode.

• tW (CKL) /tW (CKH) - Clock Low/High Time: tW (CKL) /tW (CKH) represents the time that the clock signal
(CK) should remain in the low or high state.

• tISU - Input Setup Time in HS Mode: tISU represents the setup time required for CMD and D (data lines)
inputs.

• tIH - Input Hold Time in HS Mode: tIH specifies the hold time required for CMD and D inputs.

• tOV - Output Valid Time in HS Mode: tOV defines the time it takes for the CMD and D outputs to be ready.

• tOH - Output Hold Time in HS Mode: tOH specifies the hold time required for the CMD and D outputs to
be valid.

• The timing of the CMD and D inputs and outputs are measured in relation to the clock signal CK.

9.11 Clock Phase Selection

If the setup time requirements for the input or output data signal are not met, users can specify the clock phase,
as shown in the figure below.

Figure 9-10. Clock Phase Selection

Please find detailed information on the clock phase selection register CLK_EDGE_SEL in Section Registers.

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9.12 Interrupt
Interrupts can be generated as a result of various events. The IDSTS register contains all the bits that might
cause an interrupt. The IDINTEN register contains an enable bit for each of the events that can cause an
interrupt.

There are two groups of summary interrupts, ”Normal” ones (bit8 NIS) and ”Abnormal” ones (bit9 AIS), as
outlined in the IDSTS register. Interrupts are cleared by writing 1 to the position of the corresponding bit. When
all the enabled interrupts within a group are cleared, the corresponding summary bit is also cleared. When both
summary bits are cleared, the interrupt signal dmac_intr_o is de-asserted (stops signalling).

Interrupts are not queued up, and if a new interrupt-event occurs before the driver has responded to it, no
additional interrupts are generated. For example, the Receive Interrupt IDSTS[1] indicates that one or more data
were transferred to the Host buffer.

An interrupt is generated only once for concurrent events. The driver must scan the IDSTS register for the
interrupt cause.

9.13 Register Summary

The addresses in this section are relative to the SD/MMC base address provided in Table 1-6 Peripheral Address
Mapping in Chapter 1 System and Memory.

Name Description Address Access

CTRL_REG Control register 0x0000 R/W
CLKDIV_REG Clock divider configuration register 0x0008 R/W
CLKSRC_REG Clock source selection register 0x000C R/W
CLKENA_REG Clock enable register 0x0010 R/W
TMOUT_REG Data and response timeout configuration register 0x0014 R/W
CTYPE_REG Card bus width configuration register 0x0018 R/W
BLKSIZ_REG Card data block size configuration register 0x001C R/W
BYTCNT_REG Data transfer length configuration register 0x0020 R/W
INTMASK_REG SDIO interrupt mask register 0x0024 R/W
CMDARG_REG Command argument data register 0x0028 R/W
CMD_REG Command and boot configuration register 0x002C R/W
RESP0_REG Response data register 0x0030 RO
RESP1_REG Long response data register 0x0034 RO
RESP2_REG Long response data register 0x0038 RO
RESP3_REG Long response data register 0x003C RO
MINTSTS_REG Masked interrupt status register 0x0040 RO
RINTSTS_REG Raw interrupt status register 0x0044 R/W
STATUS_REG SD/MMC status register 0x0048 RO
FIFOTH_REG FIFO configuration register 0x004C R/W
CDETECT_REG Card detect register 0x0050 RO
WRTPRT_REG Card write protection (WP) status register 0x0054 RO
TCBCNT_REG Transferred byte count register 0x005C RO
TBBCNT_REG Transferred byte count register 0x0060 RO
DEBNCE_REG Debounce filter time configuration register 0x0064 R/W
USRID_REG User ID (scratchpad) register 0x0068 R/W

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Name Description Address Access

RST_N_REG Card reset register 0x0078 R/W
BMOD_REG Burst mode transfer configuration register 0x0080 R/W
PLDMND_REG Poll demand configuration register 0x0084 WO
DBADDR_REG Descriptor base address register 0x0088 R/W
IDSTS_REG IDMAC status register 0x008C R/W
IDINTEN_REG IDMAC interrupt enable register 0x0090 R/W
DSCADDR_REG Host descriptor address pointer 0x0094 RO
BUFADDR_REG Host buffer address pointer register 0x0098 RO
CLK_EDGE_SEL Clock phase selection register 0x0800 R/W

9.14 Registers
SD/MMC controller registers can be accessed by the APB bus of the CPU.

The addresses in this section are relative to the SD/MMC base address provided in Table 1-6 Peripheral Address
Mapping in Chapter 1 System and Memory.

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Register 9.1. CTRL_REG (0x0000)

S
TU
D STA
CS T_
_C UP
SE RT_ SD OP RR

ET
NS
O C ST TE

ES
O
(re _W _R AT
AB D_C TO_ _IN

_R
AD RQ _D
se AI S
N U E

E
SE D_A VIC

ER
RE D_I AD

CO _R ET
RO T
DM rve LE
T

NT ESE
LL
N RE
)

d)

(re EN )

FI _R )
N DE

FO ES
se B
ed

ed

T_ d

A d
A
ve

IN ve
SE A_
rv

rv

r
se

se

se

AT
(re

(re

(re

CE
31 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 1 0x00 0 0 0 0 0 0 0 0 0 0 0 0 Reset

CEATA_DEVICE_INTERRUPT_STATUS Software should appropriately write to this bit after the power-
on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device’s interrupt is
usually disabled (nIEN = 1). If the host enables the CE-ATA device’s interrupt, then software
should set this bit. (R/W)

SEND_AUTO_STOP_CCSD Always set send_auto_stop_ccsd and send_ccsd bits together;

send_auto_stop_ccsd should not be set independently of send_ccsd. When set, SD/MMC
automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. Af-
ter sending this internally-generated STOP command, the Auto Command Done (ACD) bit in
RINTSTS is set and an interrupt is generated for the host, in case the ACD interrupt is not masked.
After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears
the send_auto_stop_ccsd bit. (R/W)

SEND_CCSD When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the
CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the
send_ccsd bit. It also sets the Command Done (CD) bit in the RINTSTS register, and generates
an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the
send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to
this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the
device has signalled CCS. (R/W)

ABORT_READ_DATA After a suspend-command is issued during a read-operation, software polls

the card to find when the suspend-event occurred. Once the suspend-event has occurred,
software sets the bit which will reset the data state machine that is waiting for the next block of
data. This bit is automatically cleared once the data state machine is reset to idle. (R/W)

SEND_IRQ_RESPONSE Bit automatically clears once response is sent. To wait for MMC card inter-
rupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime,
if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC
command state-machine sends CMD40 response on bus and returns to idle state. (R/W)

Continued on the next page...

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Register 9.1. CTRL_REG (0x0000)

Continued from the previous page...

READ_WAIT For sending read-wait to SDIO cards. (R/W)

INT_ENABLE Global interrupt enable/disable bit. 0: Disable; 1: Enable. (R/W)

DMA_RESET To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two
AHB clocks. (R/W)

FIFO_RESET To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion
of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. (R/W)

CONTROLLER_RESET To reset controller, firmware should set this bit. This bit is auto-cleared after
two AHB and two cclk_in clock cycles. (R/W)

Register 9.2. CLKDIV_REG (0x0008)

0
2
3

R1
R

ER

ER
DE

DE
ID

D
VI

VI

VI
V
DI

DI

DI

DI
K_

K_

K_

K_
CL

CL

CL

CL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

CLK_DIVIDER3 Clock divider-3 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER2 Clock divider-2 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER1 Clock divider-1 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER0 Clock divider-0 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

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Register 9.3. CLKSRC_REG (0x000C)

G
RE
)
ed

C_
rv

R
KS
se
(re

CL
31 4 3 0

0x000000 0x0 Reset

CLKSRC_REG Clock divider source for two SD cards is supported. Each card has two bits assigned
to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps
and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.
00 : Clock divider 0;
01 : Clock divider 1;
10 : Clock divider 2;
11 : Clock divider 3.
In MMC-Ver3.3-only controller, only one clock divider is supported. The cclk_out is always from
clock divider 0, and this register is not implemented. (R/W)

Register 9.4. CLKENA_REG (0x0010)

L
BE
NA
)
ed

_E
rv

LK
se

CC
(re

31 2 1 0

0x00000 0x00000 Reset

CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported.
0: Clock disabled;
1: Clock enabled.
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W)

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Register 9.5. TMOUT_REG (0x0014)

UT
EO
M
UT

I
_T
EO

SE
M

ON
I
_T

SP
TA
DA

RE
31 8 7 0

0x0FFFFFF 0x040 Reset

DATA_TIMEOUT Value for card data read timeout. This value is also used for data starvation by
host timeout. The timeout counter is started only after the card clock is stopped. This value is
specified in number of card output clocks, i.e. cclk_out of the selected card.
NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this
case, read data timeout interrupt needs to be disabled. (R/W)

RESPONSE_TIMEOUT Response timeout value. Value is specified in terms of number of card output
clocks, i.e., cclk_out. (R/W)

Register 9.6. CTYPE_REG (0x0018)

8

4
TH

TH
ID

ID
)

)
ed

ed
W

W
rv

rv
D_

D_
se

se
R

R
(re

(re
CA

CA
31 18 17 16 15 2 1 0

0x00000 0x00000 0x00000 0x00000 Reset

CARD_WIDTH8 One bit per card indicates if card is in 8-bit mode.

0: Non 8-bit mode;
1: 8-bit mode.
Bit[17:16] correspond to card[1:0] respectively. (R/W)

CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode.
0: 1-bit mode;
1: 4-bit mode.
Bit[1:0] correspond to card[1:0] respectively. Only NUM_CARDS*2 number of bits are imple-
mented. (R/W)

Register 9.7. BLKSIZ_REG (0x001C)

ZE
)

SI
ed

K_
rv

OC
se
(re

BL

31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00200 Reset

BLOCK_SIZE Block size. (R/W)

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Register 9.8. BYTCNT_REG (0x0020)

31 0

0x000000200 Reset

BYTCNT_REG Number of bytes to be transferred, should be an integral multiple of Block Size for
block transfers. For data transfers of undefined byte lengths, byte count should be set to 0.
When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command
to terminate data transfer. (R/W)

Register 9.9. INTMASK_REG (0x0024)

K
AS
_M
)

K
ed

NT

AS
rv

_I

M
se

IO

T_
(re

SD

IN
31 18 17 16 15 0

0x00000 0x00000 0x00000 Reset

SDIO_INT_MASK SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an
interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0. (R/W)

INT_MASK These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value
of 1 enables the interrupt. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation-by-host timeout/Volt_switch_int
Bit 9 (DRTO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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Register 9.10. CMDARG_REG (0x0028)

31 0

0x000000000 Reset

CMDARG_REG Value indicates command argument to be passed to the card. (R/W)

Register 9.11. CMD_REG (0x002C)

Y
NL
_O
RS

E
ET
TE

_E GT RC
DA D/W _M OP PL
IS

SE EN E_C
ND RV _C ION
CK ICE
EG

A ER ST M

XP H
T
RE NSF TO_ _CO
TR _A DAT MD

EC
_R
LO EV

CH _E ITE DE
SE _P RT AT

ON E_L NS
RE PON ESP D
DA EA ED

AI B LIZ
_C _D

TA R O

S R TE
SP S O
A U A
BE
UP D_C ECT

RE K_ EC
TE TA

W P_A TIA

X
US rve D

UM
(re rve E

DE
T O
se CM

(re _HO )

(re rve )
se d )

(re rve )
CC rve )
RE _EX )

EC P
E d

se d
se L
se d

se d
S d
A P

O NI

X
_N
(re rve

IN
ST _I
(re T_

D_
RD

ND
AR

CM
CA

SE
ST

31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0

0 0 1 0 0 0 0 0 0 0 0 0x00 0 0 0 0 0 0 0 0 0 0 0x00 Reset

START_CMD Start command. Once command is served by the CIU, this bit is automatically cleared.
When this bit is set, host should not attempt to write to any command registers. If a write is
attempted, hardware lock error is set in raw interrupt register. Once command is sent and a
response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt
Register. (R/W)

USE_HOLE Use Hold Register. (R/W) 0: CMD and DATA sent to card bypassing HOLD Register; 1:
CMD and DATA sent to card through the HOLD Register.

CCS_EXPECTED Expected Command Completion Signal (CCS) configuration. (R/W)

0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command
does not expect CCS from device.
1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command
completion signal from CE-ATA device.
If the command expects Command Completion Signal (CCS) from the CE-ATA device, the soft-
ware should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register
and generates interrupt to host if Data Transfer Over interrupt is not masked.

READ_CEATA_DEVICE Read access flag. (R/W)

0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device
1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
Software should set this bit to indicate that CE-ATA device is being accessed for read transfer.
This bit is used to disable read data timeout indication while performing CE-ATA read transfers.
Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not
indicate read data timeout while waiting for data from CE-ATA device. (R/W)

Continued on the next page...

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Register 9.11. CMD_REG (0x002C)

Continued from the previous page...

UPDATE_CLOCK_REGISTERS_ONLY (R/W)
0: Normal command sequence.
1: Do not send commands, just update clock register value into card clock domain
Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.
Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This
is provided in order to change clock frequency or stop clock without having to send command
to cards.
During normal command sequence, when update_clock_registers_only = 0, following control
registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT.
CIU uses new register values for new command sequence to card(s). When bit is set, there are
no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.

CARD_NUMBER Card number in use. Represents physical slot number of card being accessed. In
MMC-Ver3.3-only mode, up to two cards are supported. In SD-only mode, up to two cards are
supported. (R/W)

SEND_INITIALIZATION (R/W)
0: Do not send initialization sequence (80 clocks of 1) before sending this command.
1: Send initialization sequence before sending this command.
After power on, 80 clocks must be sent to card for initialization before sending any commands
to card. Bit should be set while sending first command to card so that controller will initialize
clocks before sending command to card.

STOP_ABORT_CMD (R/W)
0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-
number currently selected or not in data-transfer mode, then bit should be set to 0.
1: Stop or abort command intended to stop current data transfer in progress. When open-ended
or predefined data transfer is in progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of CIU can return correctly to
idle state.

WAIT_PRVDATA_COMPLETE (R/W)
0: Send command at once, even if previous data transfer has not completed;
1: Wait for previous data transfer to complete before sending Command.
The wait_prvdata_complete = 0 option is typically used to query status of card during data trans-
fer or to stop current data transfer. card_number should be same as in previous command.

SEND_AUTO_STOP (R/W)
0: No stop command is sent at the end of data transfer;
1: Send stop command at the end of data transfer.

Continued on the next page...

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Register 9.11. CMD_REG (0x002C)

Continued from the previous page ...

TRANSFER_MODE (R/W)
0: Block data transfer command;
1: Stream data transfer command. Don’t care if no data expected.

READ/WRITE (R/W)
0: Read from card;
1: Write to card.
Don’t care if no data is expected from card.

DATA_EXPECTED (R/W)
0: No data transfer expected.
1: Data transfer expected.

CHECK_RESPONSE_CRC (R/W)
0: Do not check;
1: Check response CRC.
Some of command responses do not return valid CRC bits. Software should disable CRC checks
for those commands in order to disable CRC checking by controller.

RESPONSE_LENGTH (R/W)
0: Short response expected from card;
1: Long response expected from card.

RESPONSE_EXPECT (R/W)
0: No response expected from card;
1: Response expected from card.

CMD_INDEX Command index. (R/W)

Register 9.12. RESP0_REG (0x0030)

31 0

0x000000000 Reset

RESP0_REG Bit[31:0] of response. (RO)

Register 9.13. RESP1_REG (0x0034)

31 0

0x000000000 Reset

RESP1_REG Bit[63:32] of long response. (RO)

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Register 9.14. RESP2_REG (0x0038)

31 0

0x000000000 Reset

RESP2_REG Bit[95:64] of long response. (RO)

Register 9.15. RESP3_REG (0x003C)

31 0

0x000000000 Reset

RESP3_REG Bit[127:96] of long response. (RO)

Register 9.16. MINTSTS_REG (0x0040)

SK
_M

SK
PT

_M
RU
ER

US
)
ed

NT

AT
rv

ST
_I
se

IO

T_
(re

SD

IN
31 18 17 16 15 0

0 0x0 0x00000 Reset

SDIO_INTERRUPT_MSK Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond
to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding
sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). (RO)

INT_STATUS_MSK Interrupt enabled only if corresponding bit in interrupt mask register is set. (RO)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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Register 9.17. RINTSTS_REG (0x0044)

AW
_R

AW
PT
RU

_R
ER

US
)
ed

NT

AT
rv

ST
_I
se

IO

T_
(re

SD

IN
31 18 17 16 15 0

0x00000 0x0 0x00000 Reset

SDIO_INTERRUPT_RAW Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to
card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0
has no effect. (R/W)
0: No SDIO interrupt from card;
1: SDIO interrupt from card.
In MMC-Ver3.3-only mode, these bits are always 0. Bits are logged regardless of interrupt-mask
status. (R/W)

INT_STATUS_RAW Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
are logged regardless of interrupt mask status. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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Register 9.18. STATUS_REG (0x0048)

S
TE
SY

K
ER RK
TA
BU

AR
_S

AT A
X

_3 Y C_

M
W RM
E

M
S
ND

TA US M

TU

FS

X_ TE
DA _B TE_
T

_I

FI _TX TY
TA

D_

_R WA
UN

SE

FI _EM L
se d)

P
_S
TA TA

FO L
ed

AN

FO _
O

FI _FU
ON
(re rve

DA _S
_C
rv

M
SP
se

M
TA
FO

FO

FO
CO
(re

DA
RE
FI

FI
31 30 29 17 16 11 10 9 8 7 4 3 2 1 0

0 0 0x000 0x00 1 1 1 0x01 0 1 1 0 Reset

FIFO_COUNT FIFO count, number of filled locations in FIFO. (RO)

RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. (RO)

DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. (RO)

DATA_BUSY Inverted version of raw selected card_data[0]. (RO)

0: Card data not busy;
1: Card data busy.

DATA_3_STATUS Raw selected card_data[3], checks whether card is present. (RO)

0: card not present;
1: card present.

COMMAND_FSM_STATES Command FSM states. (RO)

0: Idle
1: Send init sequence
2: Send cmd start bit
3: Send cmd tx bit
4: Send cmd index + arg
5: Send cmd crc7
6: Send cmd end bit
7: Receive resp start bit
8: Receive resp IRQ response
9: Receive resp tx bit
10: Receive resp cmd idx
11: Receive resp data
12: Receive resp crc7
13: Receive resp end bit
14: Cmd path wait NCC
15: Wait, cmd-to-response turnaround

FIFO_FULL FIFO is full status. (RO)

FIFO_EMPTY FIFO is empty status. (RO)

FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. (RO)

FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. (RO)

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Register 9.19. FIFOTH_REG (0x004C)

IZE
_S
ON
I
CT
SA
AN
TR
E_
PL
TI

K
UL
d)

d)
AR

AR
ed
ve

ve
M

M
rv
A_
r

r
_W

_W
se

se

se
DM
(re

(re

(re
RX

TX
31 30 28 27 26 16 15 12 11 0

0 0x0 0 x x x x x x x x x x x 0 0 0 0 0x0000 Reset

DMA_MULTIPLE_TRANSACTION_SIZE Burst size of multiple transaction, should be programmed

same as DMA controller multiple-transaction-size SRC/DEST_MSIZE. 000: 1-byte transfer; 001:
4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte
transfer; 110: 128-byte transfer; 111: 256-byte transfer. (R/W)

RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count
reaches greater than this number (FIFO_RX_WATERMARK), DMA/FIFO request is raised. During
end of packet, request is generated regardless of threshold programming in order to complete
any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled,
then interrupt is generated instead of DMA request.During end of packet, interrupt is not gen-
erated if threshold programming is larger than any remaining data. It is responsibility of host to
read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet,
even if remaining bytes are less than threshold, DMA request does single transfers to flush out
any remaining bytes before Data Transfer Done interrupt is set. (R/W)

TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count
is less than or equal to this number (FIFO_TX_WATERMARK), DMA/FIFO request is raised. If In-
terrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,
regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR)
interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet,
on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not be-
fore FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA
mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles
until required bytes are transferred. (R/W)

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Register 9.20. CDETECT_REG (0x0050)

_N
CT
TE
)
ed

DE
rv

D_
se

R
(re

CA
31 2 1 0

0x0 0x0 Reset

CARD_DETECT_N Value on card_detect_n input ports (1 bit per card), read-only bits.0 represents
presence of card. Only NUM_CARDS number of bits are implemented. (RO)

Register 9.21. WRTPRT_REG (0x0054)

T
EC
OT
)

PR
ed

_
rv

TE
se

RI
(re

W
31 2 1 0

0x0 0x0 Reset

WRITE_PROTECT Value on card_write_prt input ports (1 bit per card).1 represents write protection.
Only NUM_CARDS number of bits are implemented. (RO)

Register 9.22. TCBCNT_REG (0x005C)

31 0

0x000000000 Reset

TCBCNT_REG Number of bytes transferred by CIU unit to card. (RO)

Register 9.23. TBBCNT_REG (0x0060)

31 0

0x000000000 Reset

TBBCNT_REG Number of bytes transferred between Host/DMA memory and BIU FIFO. (RO)

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Register 9.24. DEBNCE_REG (0x0064)

NT
OU
_C
CE
)
ed

UN
rv

BO
se
(re

DE
31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic. The typical de-
bounce time is 5 ~ 25 ms to prevent the card instability when the card is inserted or removed.
(R/W)

Register 9.25. USRID_REG (0x0068)

31 0

0x000000000 Reset

USRID_REG User identification register, value set by user. Default reset value can be picked by
user while configuring core before synthesis. Can also be used as a scratchpad register by user.
(R/W)

Register 9.26. RST_N_REG (0x0078)

ET
ES
_R
)

RD
ed

CA
rv
se

T_
(re

RS
31 2 1 0

0 0x1 Reset

RST_CARD_RESET Hardware reset.1: Active mode; 0: Reset. These bits cause the cards to enter
pre-idle state, which requires them to be re-initialized. CARD_RESET[0] should be set to 1’b0 to
reset card0, CARD_RESET[1] should be set to 1’b0 to reset card1.The number of bits implemented
is restricted to NUM_CARDS. (R/W)

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Register 9.27. BMOD_REG (0x0080)

R
BL

W
)

)
E

OD FB
ed

ed
_D
_P

_S
BM D_
rv

rv
OD

OD
se

se

O
BM

BM

BM
(re

(re
31 11 10 8 7 6 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x00 0 0 Reset

BMOD_PBL Programmable Burst Length. These bits indicate the maximum number of beats to be
performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL
each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64,
128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value,
write the required value to FIFOTH register. This is an encode value as follows:
000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-
byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer.
PBL is a read-only value and is applicable only for data access, it does not apply to descriptor
access. (R/W)

BMOD_DE IDMAC Enable. When set, the IDMAC is enabled. (R/W)

BMOD_FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers
or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal
burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. (R/W)

BMOD_SWR Software Reset. When set, the DMA Controller resets all its internal registers. It is
automatically cleared after one clock cycle. (R/W)

Register 9.28. PLDMND_REG (0x0080)

31 0

0x000000000 Reset

PLDMND_REG Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend
state. The host needs to write any value into this register for the IDMAC FSM to resume normal
descriptor fetch operation. This is a write only register, PD bit is write-only. (WO)

Register 9.29. DBADDR_REG (0x0088)

31 0

0x000000000 Reset

DBADDR_REG Start of Descriptor List. Contains the base address of the First Descriptor. The LSB
bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may
be treated as read-only. (R/W)

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Register 9.30. IDSTS_REG (0x008C)

E
OD
_C
M

(re S_ S
BE

ID S_ E
(re NIS
)

S_ S

ID S_ )
s e DU

ST FB
ST CE
FS
ed

ed

ST d
ST AI

ST RI
TI
F

ID rve
S_

S_

ID S_

ID S_

S_
rv

rv
se

se
ST

ST

ST

ST
(re

ID

ID

ID

ID
31 17 16 13 12 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 0x0 0 0 0 0 0 0 0 0 0 0 Reset

IDSTS_FSM DMAC FSM present state: (RO)

0: DMA_IDLE; 1: DMA_SUSPEND; 2: DESC_RD; 3: DESC_CHK; 4: DMA_RD_REQ_WAIT
5: DMA_WR_REQ_WAIT; 6: DMA_RD; 7: DMA_WR; 8: DESC_CLOSE.

IDSTS_FBE_CODE Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. (RO)
3b001: Host Abort received during transmission;
3b010: Host Abort received during reception;
Others: Reserved.

IDSTS_AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt,
IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this
bit. (R/W)

IDSTS_NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt,
IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this
bit. (R/W)

IDSTS_CES Card Error Summary. Indicates the status of the transaction to/from the card, also
present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error, RTO :
Response Timeout/Boot Ack Timeout, RCRC : Response CRC, SBE : Start Bit Error, DRTO : Data
Read Timeout/BDS timeout, DCRC : Data CRC for Receive, RE : Response Error.
Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES
bit. If the CES bit is enabled, then the IDMAC aborts on a response error. (R/W)

IDSTS_DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to
OWN bit = 0 (DES0[31] =0). Writing 1 clears this bit. (R/W)

IDSTS_FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this
bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. (R/W)

IDSTS_RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1
clears this bit. (R/W)

IDSTS_TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1
clears this bit. (R/W)

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Register 9.31. IDINTEN_REG (0x0090)

(re TEN CES

ID TEN FBE
ID rve DU
I
TE AI

TE RI
TI
(re N_N
)

ID TEN )
ed

ed

IN d
IN _

IN _
se _

IN _
IN _
N_
ID TEN

ID TEN
rv

rv
se

se
N

IN
(re

I
ID

ID
31 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

IDINTEN_AI Abnormal Interrupt Summary Enable. (R/W)

When set, an abnormal interrupt is enabled. This bit enables the following bits:
IDINTEN[2]: Fatal Bus Error Interrupt;
IDINTEN[4]: DU Interrupt.

IDINTEN_NI Normal Interrupt Summary Enable. (R/W)

When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit
enables the following bits:
IDINTEN[0]: Transmit Interrupt;
IDINTEN[1]: Receive Interrupt.

IDINTEN_CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt sum-
mary. (R/W)

IDINTEN_DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
Enable, the DU interrupt is enabled. (R/W)

IDINTEN_FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. (R/W)

IDINTEN_RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
Interrupt is enabled. When reset, Receive Interrupt is disabled. (R/W)

IDINTEN_TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
Interrupt is enabled. When reset, Transmit Interrupt is disabled. (R/W)

Register 9.32. DSCADDR_REG (0x0094)

31 0

0x000000000 Reset

DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared
on reset. This register points to the start address of the current descriptor read by the IDMAC.
(RO)

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Register 9.33. BUFADDR_REG (0x0098)

31 0

0x000000000 Reset

BUFADDR_REG Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
reset. This register points to the current Data Buffer Address being accessed by the IDMAC.
(RO)

Register 9.34. CLK_EDGE_SEL (0x0800)

EL
L

E
SE

_S

S
V_
F_

DR
SA
L
_N

_S
L
E_

E_

E_
E

GE

GE
DG

DG

DG

DG
ED

ED
)

_E

_E

_E

_E
ed

N_

N_
IN

IN

IN

IN
rv

I
LK

LK

LK

LK

LK

LK
se

CC

CC

CC

CC

CC

CC
(re

31 21 20 17 16 13 12 9 8 6 5 3 2 0

0x000 0x1 0x0 0x1 0x0 0x0 0x0 Reset

CCLKIN_EDGE_N This value should be equal to CCLKIN_EDGE_L. (R/W)

CCLKIN_EDGE_L The low level of the divider clock. The value should be larger than
CCLKIN_EDGE_H. (R/W)

CCLKIN_EDGE_H The high level of the divider clock. The value should be smaller than
CCLKIN_EDGE_L. (R/W)

CCLKIN_EDGE_SLF_SEL It is used to select the clock phase of the internal signal from phase90,
phase180, or phase270. (R/W)

CCLKIN_EDGE_SAM_SEL It is used to select the clock phase of the input signal from phase90,
phase180, or phase270. (R/W)

CCLKIN_EDGE_DRV_SEL It is used to select the clock phase of the output signal from phase90,
phase180, or phase270. (R/W)

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10 Ethernet Media Access Controller (MAC)

10.1 Overview
Features of Ethernet

By using the external Ethernet PHY (physical layer), ESP32 can send and receive data via Ethernet MAC (Media
Access Controller) according to the IEEE 802.3 standard, as Figure 10-1 shows. Ethernet is currently the most
commonly used network protocol that controls how data is transmitted over local- and wide-area networks,
abbreviated as LAN and WAN, respectively.

Figure 10-1. Ethernet MAC Functionality Overview

ESP32 MAC Ethernet complies with the following criteria:

• IEEE 802.3-2002 for Ethernet MAC

• Two industry-standard interfaces conforming with IEEE 802.3-2002: Media-Independent Interface (MII)
and Reduced Media-Independent Interface (RMII).

Features of MAC Layer

• Support for a data transmission rate of 10 Mbit/s or 100 Mbit/s through an external PHY interface

• Communication with an external Fast Ethernet PHY through IEEE 802.3-compliant MII and RMII interfaces

• Support for:

– Carrier Sense Multiple Access / Collision Detection (CSMA/CD) protocol in half-duplex mode

– IEEE 802.3x flow control in full-duplex mode

– operations in full-duplex mode, forwarding the received pause-control frame to the user application

– backpressure flow control in half-duplex mode

– If the flow control input signal disappears during a full-duplex operation, a pause frame with zero
pause time value is automatically transmitted.

• The Preamble and the Start Frame Delimiter (SFD) are inserted in the Transmit path, and deleted in the
Receive path.

• Cyclic Redundancy Check (CRC) and Pad can be controlled on a per-frame basis.

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• The Pad is generated automatically, if data is below the minimum frame length.

• Programmable frame length supporting jumbo frames of up to 16 KB

• Programmable Inter-frame Gap (IFG) (40-96 bit times in steps of 8)

• Support for a variety of flexible address filtering modes:

– Up to eight 48-bit perfect address filters to mask each byte

– Up to eight 48-bit SA address comparison checks to mask each byte

– All multicast address frames can be transmitted

– All frames in mixed mode can be transmitted without being filtered for network monitoring

– A status report is attached each time all incoming packets are transmitted and filtered

• Returning a 32-bit status for transmission and reception of packets respectively

• Separate transmission, reception, and control interfaces for the application

• Use of the Management Data Input/Output (MDIO) interface to configure and manage PHY devices

• Support for the offloading of received IPv4 and TCP packets encapsulated by an Ethernet frame in the
reception function

• Support for checking IPv4 header checksums, as well as TCP, UDP, or ICMP (Internet Control Message
Protocol) checksums encapsulated in IPv4/IPv6 packets in the enhanced reception function

• Two sets of FIFOs: one 2 KB Tx FIFO with programmable threshold and one 2 KB Rx FIFO with configurable
threshold (64 bytes by default)

• When Rx FIFO stores multiple frames, the Receive Status Vector is inserted into the Rx FIFO after trans-
mitting an EOF (end of frame), so that the Rx FIFO does not need to store the Receive Status of these
frames.

• In store-and-forward mode, all error frames can be filtered during reception, but not forwarded to the
application.

• Under-sized good frames can be forwarded.

• Support for data statistics by generating pulses for lost or corrupted frames in the Rx FIFO due to an
overflow

• Support for store-and-forward mechanism when transmitting data to the MAC core

• Automatic re-transmission of collided frames during transmission (subject to certain conditions, see sec-
tion 10.2.1.2)

• Discarding frames in cases of late collisions, excessive collisions, excessive deferrals, and under-run con-
ditions

• The Tx FIFO is flushed by software control.

• Calculating the IPv4 header checksum, as well as the TCP, UDP, or ICMP checksum, and then inserting
them into frames transmitted in store-and-forward mode.

Ethernet Block Diagram

Figure 10-2 shows the block diagram of the Ethernet.

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Figure 10-2. Ethernet Block Diagram

Ethernet MAC consists of the MAC-layer configuration register module and three layers: EMAC_CORE (MAC Core
Layer), EMAC_MTL (MAC Transition Layer), and EMAC_DMA (Direct Memory Access). Each of these three layers
has two directions: Tx and Rx. They are connected to the system through the Advanced High-Performance Bus
(AHB) and the Advanced Peripheral Bus (APB) on the chip. Off the chip, they communicate with the external
PHY through the MII and RMII interfaces to establish an Ethernet connection.

10.2 EMAC_CORE
The MAC supports many interfaces with the PHY chip. The PHY interface can be selected only once after reset.
The MAC communicates with the application side (DMA side), using the MAC Transmit Interface (MTI), MAC
Receive Interface (MRI) and the MAC Control Interface (MCI).

10.2.1 Transmit Operation

A transmit operation is initiated when the MTL Application pushes in data at the time a response signal is as-
serted. When the SOF (start of frame) signal is detected, the MAC accepts the data and begins transmitting
to the RMII or MII. The time required to transmit the frame data to the RMII or MII, after the application initiates
transmission, varies, depending on delay factors like IFG delay, time to transmit Preamble or SFD (Start Frame
Delimiter), and any back-off delays in half-duplex mode. Until then, the MAC does not accept the data received
from MTL by de-asserting the ready signal.

After the EOF (end of frame) is transmitted to the MAC, the MAC completes the normal transmission and yields
the Transmit Status to the MTL. If a normal collision (in half-duplex mode) occurs during transmission, the MAC
makes valid the Transmit Status in the MTL. It then accepts and drops all further data until the next SOF is
received. The MTL block should retransmit the same frame from SOF upon observing a retry request (in the
Status) from the MAC.

The MAC issues an underflow status if the MTL is not able to provide the data continuously during transmission.
During the normal transmission of a frame from MTL, if the MAC receives an SOF without getting an EOF for the
previous frame, it ignores the SOF and considers the new frame as a continuation of the previous one.

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10.2.1.1 Transmit Flow Control

In full-duplex mode, when the Transmit Flow Control Enable bit (TFE bit in the Flow Control Register) is set to 1,
the MAC will generate and send a pause frame, as needed. The pause frame is added and transmitted together
with the calculated CRC. The generation of pause frames can be initiated in two ways.

When the application sets the Flow Control Busy bit (FCB bit in the Flow Control Register) to 1, or when the Rx
FIFO is full, a pause frame is transmitted.

• If an application has requested flow control by setting the FCB bit in the Flow Control Register to 1, the MAC
will generate and send a single pause frame. The pause time value in the generated frame is the pause
time value programmed in the Flow Control Register. To extend or end the pause time before the time
specified in the previously transmitted pause frame, the application program must configure the pause
time value in the Flow Control Register to the appropriate value and, then, request another pause frame
transmission.

• If the application has requested flow control when the Rx FIFO is full, the MAC will generate and transmit a
pause frame. The value of the pause time of the generated frame is the pause time value programmed in
the Flow Control Register. If the Rx FIFO remains full during the configurable interval, which is determined
by the Pause Low Threshold bit (PLT) in the Flow Control Register before the pause time expires, a second
pause frame will be transmitted. As long as the Rx FIFO remains full, the process repeats itself. If the FIFO
is no longer full before the sample time, the MAC will send a pause frame with zero pause time, indicating
to the remote end that the Rx buffer is ready to receive the new data frame.

10.2.1.2 Retransmission During a Collision

In half-duplex mode, a collision may occur on the MAC line interface when frames are transmitted to the MAC.
The MAC may even give a status to indicate a retry before the end of the frame is received. The retransmission
is then enabled and the frame is popped out from the FIFO. When more than 96 bytes are transmitted to the
MAC core, the FIFO controller frees the space in the FIFO, allowing the DMA to push more data into FIFO. This
means that data cannot be retransmitted after the threshold is exceeded or when the MAC core indicates that
a late collision has occurred.

The MAC transmitter may abort the transmission of a frame because of collision, Tx FIFO underflow, loss of
carrier, jabber timeout, no carrier, excessive deferral, and late collision. When frame transmission is aborted
because of collision, the MAC requests retransmission of the frame.

10.2.2 Receive Operation

A receive operation is initiated when the MAC detects an SFD on the RMII or MII. The MAC strips the Preamble
and SFD before processing the frame. The header fields are checked for the filtering and the FCS (Frame Check
Sequence) field used to verify the CRC for the frame. The received frame is stored in a shallow buffer until the
address filtering is performed. The frame is dropped in the MAC if it fails the address filtering.

The frame received by the MAC will be pushed into the Rx FIFO. Once the FIFO status exceeds the Receive
Threshold, configured by the Receive Threshold Control (RTC) bit in the Operation Mode register, the DMA can
initiate a preconfigured burst transmission to the AHB interface.

In the default pass-through mode, when the FIFO receives a complete packet or 64 bytes configured by the
RTC bit in the Operation Mode Register, the data pops up and its availability is notified to the DMA. After the DMA
initiates the transmission to the AHB interface, the data transmission continues from the FIFO until the complete

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packet is transmitted. Upon completing transmitting the EOF, the status word will pop up and be transmitted to
the DMA controller.

In the Rx FIFO Store-and-Forward mode (configured through the RSF or Receive Store and Forward bit in the
Operation Mode Register), only the valid frames are read and forwarded to the application. In the passthrough
mode, error frames are not discarded because the error status is received at the end of the frame. The start of
frame will have been read from the FIFO at that point.

10.2.2.1 Reception Protocol

After the receive module receives the packets, the Preamble and SFD of the received frames are removed.
When the SFD is detected, the MAC starts sending Ethernet frame data to the Rx FIFO, starting at the first byte
(destination address) following the SFD.

If the received frame length/type is less than 0x600 and the automatic CRC/Pad removal option is programmed
for the MAC, the MAC will send frame data to the Rx FIFO (the amount of data does not exceed the number
specified in the length/type field). Then MAC begins discarding the remaining section, including the FCS field.
If the frame length/type is greater than, or equal to, 0x600, the MAC will send all received Ethernet frame data
to the Rx FIFO, regardless of the programmed value of the automatic CRC removal option. By default, the MAC
watchdog timer is enabled, meaning that frames, including DA, SA, LT, data, pad and FCS, which exceed 2048
bytes, are cut off. This function can be disabled by programming the Watchdog Disable (WD) bit in the MAC
Configuration Register. However, even if the watchdog timer is disabled, frames longer than 16 KB will be cut
off and the watchdog timeout status will be given.

10.2.2.2 Receive Frame Controller

If the RA (Receive All) bit in the MAC Frame Filter Register is reset, the MAC will filter frames based on the
destination and source addresses. If the application decides not to receive any bad frames, such as runt
frames and CRC error frames, another level of filtering is needed. When a frame fails the filtering, the frame is
discarded and is not transmitted to the application. When the filter parameters are changed dynamically, if a
frame fails the DA and SA filterings, the remaining part of the frame is discarded and the Receive Status word is
updated immediately and, therefore, the zero frame length bit, CRC error bit, and runt frame error bit are set to
1. This indicates that the frame has failed the filtering.

10.2.2.3 Receive Flow Control

The MAC will detect the received pause frame and pause transmission of frames for a specified delay within
the received pause frame (in full-duplex mode only). The Pause Frame Detect Function can be enabled or
disabled by the RFCE (Receive Flow Control Enable) bit in the Flow Control Register. When receive flow control
is enabled, it starts monitoring whether the destination address of the received frame matches the multicast
address of the control frame (0x0180 C200 0001). If a match is detected (i.e. the destination address of the
received frame matches the destination address of the reserved control frame), the MAC will determine whether
to transmit the received control frame to the application, according to the PCF (Pass Control Frames) bit in the
Frame Filter Register.

The MAC will also decode the type, the opcode, and the pause timer field of the Receive Control Frame. If
the value of the status byte counter is 64 bits and there are no CRC errors, the MAC transmitter will halt the
transmission of any data frame. The duration of the pause is the decoded pause time value multiplied by the

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interval (which is 64 bytes for both 10 Mbit/s and 100 Mb/s modes). At the same time, if another pause frame
of zero pause time is detected, the MAC will reset the pause time to manage the new pause request.

If the type field (0x8808), the opcode (0x00001), and the byte length (64 bytes) of the received control frame
are not 0x8808, 0x00001, and 64 bytes, respectively, or if there is a CRC error, the MAC will not generate a
pause.

If a pause frame has a multicast destination address, the MAC filters the frame, according to the address match-
ing.

For pause frames with a unicast destination address, the MAC checks whether the DA matches the content of
the EMACADDR0 Register, and whether the Unicast Pause Frame Detect (UPFD) bit in the Flow Control Register
is set to 1. The Pass Control Frames (PCF) bits in the Frame Filter Register [7:6] control the filtering of frames
and addresses.

10.2.2.4 Reception of Multiple Frames

Since the status is available immediately after the data is received. Frames can be stored there, as long as the
FIFO is not full.

10.2.2.5 Error Handling

If the Rx FIFO is full before receiving the EOF data from the MAC, an overflow will be generated and the entire
frame will be discarded. In fact, status bit RDES0[11] will indicate that this frame is partial due to an overflow, and
that it should be discarded.

If the function that corresponds to the Flush Transmit FIFO (FTF) bit and the Forward Undersized Good Frames
(FUGF) bit in the Operation Mode Register is enabled, the Rx FIFO can filter error frames and runt frames.
If the receive FIFO is configured to operate in store-and-forward mode, all error frames will be filtered and
discarded.

In passthrough mode, if a frame’s status and length are available when reading a SOF from the Rx FIFO, the entire
error frame can be discarded. DMA can clear the error frame being read from the FIFO by enabling the Receive
Frame Clear bit. The data transmission to the application (DMA) will then stop, and the remaining frames will be
read internally and discarded. If FIFO is available, the transmission of the next frame will be initiated.

10.2.2.6 Receive Status Word

After receiving the Ethernet frames, the MAC outputs the receive status to the application. The detailed de-
scription of the receive status is the same as that which is configured by bit [31:0] in RDES0.

10.3 MAC Interrupt Controller

The MAC core can generate interrupts due to various events.

The interrupt register bits only indicate various interrupt events. To clear the interrupts, the corresponding status
register and other registers must be read. An Interrupt Status Register describes the events that prompt the MAC
core to generate interrupts. Each interrupt event can be prevented by setting the corresponding mask bit in
the Interrupt Mask Register to 1. For example, if bit3 of the interrupt register is set high, it indicates that a magic
packet or Wake-on-LAN frame has been received in Power-down mode. The PMT Control and Status register
must be read to clear this interrupt event.

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10.4 MAC Address Filtering

Address filtering will check the destination and source addresses of all received frames and report the address
filtering status accordingly. For example, filtered frames can be identified either as multicast or broadcast.The
address check, then, is based on the parameters selected by the application (Frame Filter Registers).

Physical (MAC) addresses are used for address checking during address filtering.

10.4.1 Unicast Destination Address Filtering

The MAC supports up to 8 MAC addresses for perfect filtering of unicast addresses. If a perfect filtering is
selected (by resetting bit[1] in the Frame Filter Register), the MAC compares all 48 bits of the received unicast
address with the programmed MAC address to determine if there is a match. By default, EMACADDR0 is always
enabled, and the other addresses (EMACADDR0 ~ EMACADDR7) are selected by a separate enable bit. When
the individual bytes of the other addresses (EMACADDR0 ~ EMACADDR7) are compared with the DA bytes
received, the latter can be masked by setting the corresponding Mask Byte Control bit in the register to 1. This
facilitates the DA group address filtering.

10.4.2 Multicast Destination Address Filtering

The MAC can be programmed to pass all multicast frames by setting the Pass All Multicast (PAM) bit in the Frame
Filter Register to 1. If the PAM bit is reset, the MAC will filter multicast addresses, according to Bit[2] in the Frame
Filter Register.

In perfect filtering mode, the multicast address is compared with the programmed MAC Destination Address
Registers (EMACADDR0 ~ EMACADDR7). Group address filtering is also supported.

10.4.3 Broadcast Address Filtering

The MAC does not filter any broadcast frames in the default mode. However, if the MAC is programmed to reject
all broadcast frames, which can happen by setting the Disable Broadcast Frames (DBF) bit in the Frame Filter
Register to 1, all broadcast frames will be discarded.

10.4.4 Unicast Source Address Filtering

The MAC may also perform a perfect filtering based on the source address field of the received frame. By default,
the Address Filtering Module (AFM) compares the Source Address (SA) field with the values programmed in the
SA register. By setting Bit[30] in the SA register to 1, the MAC Address Register (EMACADDR0 - EMACADDR7)
can be configured to contain SA, instead of Destination Address (DA), for filtering. Group filtering with SA is also
supported. If the Source Address Filter (SAF) enable bit in the Frame Filter Register is set to 1, the MAC discards
frames that do not pass the SA filtering. Otherwise, the result of SA filtering is given as a status bit in the Receive
Status word (Please refer to Table 10-9).

When the SAF enable bit is set to 1, the result of the SA filtering and DA filtering is AND’ed to determine whether
or not to forward the frame. Any frame that fails to pass will be discarded. Frames need to pass both filterings
in order to be forwarded to the application.

10.4.5 Inverse Filtering Operation

For both destination address (DA) and source address (SA) filtering, you can invert the results matched through
the filtering at the final output. The inverse filtering of DA and SA are controlled by the DAIF and SAIF bits,
respectively, in the Frame Filter Register. The DAIF bit applies to both unicast and multicast DA frames. When
DAIF is set to 1, the result of unicast or multicast destination address filtering will be inverted. Similarly, when the
SAIF bit is set to 1, the result of unicast SA filtering is reversed.

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The following two tables summarize the destination address and source address filtering, based on the type of
the frames received.

Table 10-1. Destination Address Filtering

Frame Type PM PF DAIF PAM DB DA Filter Result

1 X X X X Pass
Broadcast 0 X X X 0 Pass
0 X X X 1 Fail
1 X X X X All frames pass.
0 X 0 X X Pass when results of perfect/group filtering match.
Unicast 0 X 1 X X Fail when results of perfect/group filtering match.
0 1 0 X X Pass when results of perfect/group filtering match.
0 1 1 X X Fail when results of perfect/group filtering match.
1 X X X X All frames pass.
X X X 1 X All frames pass.
Pass when results of perfect/group filtering match and
0 X 0 0 X
pause control frame is discarded, if PCF = 0x.
Pass when results of perfect/group filtering match and
Multicast 0 1 0 0 X
pause control frame is discarded, if PCF = 0x.
Fail when results of perfect/group filtering match and
0 X 1 0 X
pause control frame is discarded, if PCF = 0x.
Fail when results of perfect/group filtering match and
0 1 1 0 X
pause control frame is discarded, if PCF = 0x.

The filtering parameters in the MAC Frame Filter Register described in Table 10-1 are as follows.

Parameter name: Parameter setting:

PM: Pass All Multicast 1: Set
PF: Perfect Filter 0: Cleared
DAIF: Destination Address Inverse Filtering
PAM: Pass All Multicast
DB: Disable Broadcast Frames

Table 10-2. Source Address Filtering

Frame Type PM SAIF SAF Source Address Filter Operation

1 X X Pass all frames
Pass when results of perfect/group filtering match. Frames not passed
0 0 0
are not discarded.
Fail when results of perfect/group filtering match. Frames not passed
0 1 0
Unicast are not discarded.
Pass when results of perfect/group filtering match. Frames not passed
0 0 1
are discarded.
Fail when results of perfect/group filtering match. Frames not passed
0 1 1
are discarded.

The filtering parameters in the MAC Frame Filter Register described in Table 10-2 are as follows.

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Parameter name: Parameter setting:

PM: Pass All Multicast 1: Set
SAF: Source Address Filtering 0: Cleared
SAIF: Source Address Inverse Filtering X: Don’t care

10.4.6 Good Transmitted Frames and Received Frames

A frame successfully transmitted is considered a ”good frame”. In other words, a transmitted frame is considered
to be good, if the frame transmission is not aborted due to the following errors:

• Jabber timeout

• No carrier or loss of carrier

• Late collision

• Frame underflow

• Excessive deferral

• Excessive collision

The received frames are considered ”good frames”, if there are not any of the following errors:

• CRC error

• Runt frames (frames shorter than 64 bytes)

• Alignment error (in 10/100 Mbps modes only)

• Length error (non-type frames only)

• Frame size over the maximum size (for non-type frames over the maximum frame size only)�

• MII_RXER input error

The maximum frame size depends on the frame type:

• The maximum size of untagged frames = 1518 bytes

• The maximum size of VLAN frames = 1522 bytes

10.5 EMAC_MTL (MAC Transaction Layer)

The MAC Transaction Layer provides FIFO memory to buffer and regulates the frames between the application
system memory and the MAC. It also enables the data to be transmitted between the application clock domain
and the MAC clock domains. The MTL layer has two data paths, namely the Transmit path and the Receive
path. The data path for both directions is 32-bit wide and operates with a simple FIFO protocol.

10.6 PHY Interface

The DMA and the Host driver communicate through two data structures:

• Control and Status Registers (CSR)

• Descriptor lists and data buffers

For details please refer to Register Summary and Linked List Descriptors.

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10.6.1 MII (Media Independent Interface)

Media Independent Interface (MII) defines the interconnection between MAC sublayers and PHYs at the data
transmission rate of 10 Mbit/s and 100 Mbit/s.

10.6.1.1 Interface Signals Between MII and PHY

Interface signals between MII and PHY are shown in Figure 10-3.

Figure 10-3. MII Interface

MII Interface Signal Description:

• MII_TX_CLK: TX clock signal. This signal provides the reference timing for TX data transmission. The
frequencies are divided into two types: 2.5 MHz at a data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.

• MII_TXD[3:0]: Transmit data signal in groups of four, syn-driven by the MAC sub-layer, and valid only
when the MII_TX_EN signal is valid. MII_TXD[0] is the lowest significant bit and MII_TXD[3] is the highest
significant bit. When the signal MII_TX_EN is pulled low, sending data does not have any effect on the
PHY.

• MII_TX_EN: Transmit data enable signal. This signal indicates that the MAC is currently sending nibbles
(4 bits) for the MII. This signal must be synchronized with the first nibble of the header (MII_TX_CLK) and
must be synchronized when all nibbles to be transmitted are sent to the MII.

• MII_RX_CLK: RX clock signal. This signal provides the reference timing for RX data transmission. The
frequencies are divided into two types: 2.5 MHz at the data transmission rate of 10 Mbit/s, and 25 MHz
at 100 Mbit/s.

• MII_RXD[3:0]: Receive data signal in groups of four, syn-driven by the PHY, and valid only when MII_RX_DV
signal is valid. MII_RXD[0] is the lowest significant bit and MII_RXD[3] is the highest significant bit. When
MII_RX_DV is disabled and MII_RX_ER is enabled, the specific MII_RXD[3:0] value represents specific
information from the PHY.

• MII_RX_DV: Receive data valid signal. This signal indicates that the PHY is currently receiving the recov-
ered and decoded nibble that will be transmitted to the MII. This signal must be synchronized with the first
nibble of the recovered frame (MII_RX_CLK) and remain synchronized till the last nibble of the recovered

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frame. This signal must be disabled before the first clock cycle following the last nibble. In order to re-
ceive the frame correctly, the MII_RX_DV signal must cover the frame to be received over the time range,
starting no later than when the SFD field appears.

• MII_CRS: Carrier sense signal. When the transmitting or receiving medium is in the non-idle state, the
signal is enabled by the PHY. When the transmitting or receiving medium is in the idle state, the signal
is disabled by the PHY. The PHY must ensure that the MII_CRS signal remains valid under conflicting
conditions. This signal does not need to be synchronized with the TX and RX clocks. In full-duplex mode,
this signal is insignificant.

• MII_COL: Collision detection signal. After a collision is detected on the medium, the PHY must immediately
enable the collision detection signal, and the collision detection signal must remain active as long as a
condition for collision exists. This signal does not need to be synchronized with the TX and RX clocks. In
full-duplex mode, this signal is meaningless.

• MII_RX_ER: Receive error signal. The signal must remain for one or more cycles (MII_RX_CLK) to indicate
to the MAC sublayer that an error has been detected somewhere in the frame.

• MDIO and MDC: Management Data Input/Output and Management Data Clock. The two signals constitute
a serial bus defined for the Ethernet family of IEEE 802.3 standards, used to transfer control and data
information to the PHY, see section Station Management Agent (SMA) Interface.

10.6.1.2 MII Clock

In MII mode, there are two directions of clock, Tx and Rx clocks in the interface between MII and the PHY.
MII_TX_CLK is used to synchronize the TX data, and MII_RX_CLK is used to synchronize the RX data. The
MII_RX_CLK clock is provided by the PHY. The MII_TX_CLK is provided by the chip’s internal PLL or external
crystal oscillator. For details regarding Figure 10-4, please refer to the clock-related registers in Register Sum-
mary.

Figure 10-4. MII Clock

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10.6.2 RMII (Reduced Media-Independent Interface)

RMII interface signals are shown in figure 10-5.

Figure 10-5. RMII Interface

10.6.2.1 RMII Interface Signal Description

The Reduced Media-Independent Interface (RMII) specification reduces the number of pins between the mi-
crocontroller’s external peripherals and the external PHY at a data transmission rate of 10 Mbit/s or 100 Mbit/s.
According to the IEEE 802.3u standard, MII includes 16 pins that contain data and control signals. The RMII
specification reduces 62.5% of the pins to the number of seven.

RMII has the following features:

• Support for an operating rate of 10 Mbit/s or 100 Mbit/s

• The reference clock frequency must be 50 MHz.

• The same reference clock must be provided to the MAC and the external Ethernet PHY. The PHY provides
independent 2-bit-wide TX and RX data paths.

• Note: If Wi-Fi and Ethernet are used simultaneously, the RMII clock cannot be generated by the internal
APLL clock, as it would result in clock instability. In this case, please use an external PHY or external clock
source to provide the reference clock.

10.6.2.2 RMII Clock

The configuration of the RMII clock is as figure 10-6 shows.

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Figure 10-6. RMII Clock

10.6.3 Station Management Agent (SMA) Interface

As Figure 10-4 shows, the MAC uses MDC and MDIO signals to transfer control and data information to the
PHY. The maximum clock frequency is 2.5 MHz. The clock is generated from the application clock by a clock
divider. The PHY transmits register data during a write/read operation through the MDIO. This signal is driven
synchronously to the MDC clock.

Please refer to Register Summary for details about the EMII Address Register and the EMII Data Register.

10.6.4 RMII Timing

This section describes the RMII timing specifications.

Figure 10-7. RMII Timing - Receiving Data

Table 10-3. Timing Parameters - Receiving Data

Timing Parameters Description Min Typ Max Unit

tCY C Clock cycle 20 20 20 ns
tSU Setup time 4 – – ns
tH Hold time 1 – – ns
tID Input delay 3 5 8 ns

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Figure 10-8. RMII Timing – Transmitting Data

Table 10-4. Timing Parameters – Transmitting Data

Timing Parameters Description Min Typ Max Unit

tCY C Clock cycle 20 20 20 ns
tSU Setup time 4 – – ns
tH Hold time 1 – – ns
tOD Output delay 6 9 12 ns

10.7 Ethernet DMA Features

The DMA has independent Transmit and Receive engines, and a CSR (Control and Status Registers) space. The
Transmit engine transfers data from the system memory to the device port (MTL), while the Receive engine
transmits data from the device port to the system memory. The controller uses descriptors to efficiently move
data from source to destination with minimal Host CPU intervention. The DMA is designed for packet-oriented
data transmission, such as frames in Ethernet. The controller can be programmed to interrupt the Host CPU for
normal situations, such as the completion of frame transmission or reception, or when errors occur.

10.8 Linked List Descriptors

This section shows the structure of the linked lists and the descriptors. Every linked list consists of eight
words.

10.8.1 Transmit Descriptors

The structure of the transmitter linked lists is shown in Figure 10-9. Table 10-5 to Table 10-8 show the description
of the linked lists.
31 0
Reserved

Reserved
OWN

Ctrl/status Status
TDES0 Ctrl[30:26] Ctrl[24:18] Status[16:7] [6:3] [2:0]
Ctrl
TDES1 [31:29] Reserved Transmit Buffer Size[12:0]

TDES2 Buffer Address [31:0]

TDES3 Next Descriptor Address[31:0]

TDES4 Reserved

TDES5 Reserved

TDES6 Reserved

TDES7 Reserved

Figure 10-9. Transmit Descriptor

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Table 10-5. Transmit Descriptor 0 (TDES0)

Bits Name Description

When set, this bit indicates that the descriptor is owned by the
DMA. When this bit is reset, it indicates that the descriptor is
owned by the Host. The DMA clears this bit, either when it com-
pletes the frame transmission or when the buffers allocated to the
[31] OWN: Own Bit
descriptor are empty. The ownership bit of the First Descriptor of
the frame should be set after all subsequent descriptors belong-
ing to the same frame have been set. This avoids a possible race
condition between fetching a descriptor and the driver setting an
ownership bit.
When set, this bit sets the Transmit Interrupt (Register 5[0]) after
[30] IC: Interrupt on Completion the present frame has been transmitted. This bit is valid only when
the last segment bit (TDES0[29]) is set.
When set, this bit indicates that the buffer contains the last seg-
[29] LS: Last Segment ment of the frame. When this bit is set, the TBS1 or TBS2 field in
TDES1 should have a non-zero value.
When set, this bit indicates that the buffer contains the first seg-
[28] FS: First Segment
ment of a frame.
When this bit is set, the MAC does not append a cyclic redun-
[27] DC: Disable CRC dancy check (CRC) to the end of the transmitted frame. This is
valid only when the first segment (TDES0[28]) is set.
When set, the MAC does not automatically add padding to a frame
shorter than 64 bytes. When this bit is reset, the DMA automati-
[26] DP: Disable Pad cally adds padding and CRC to a frame shorter than 64 bytes, and
the CRC field is added despite the state of the DC (TDES0[27])
bit. This is valid only when the first segment (TDES0[28]) is set.
[25] Reserved Reserved
When set, the MAC replaces the last four bytes of the transmitted
packet with recalculated CRC bytes. The host should ensure that
CRCR: CRC Replacement the CRC bytes are present in the frame being transmitted from the
[24]
Control Transmit Buffer. This bit is valid when the First Segment control
bit (TDES0[28]) is set. In addition, CRC replacement is done only
when Bit TDES0[27] is set to 1.

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Bits Name Description

These bits control the checksum calculation and insertion. The
following list describes the bit encoding:
• 2’b00: Checksum insertion is disabled.
• 2’b01: Only IP header checksum calculation and insertion
are enabled.
• 2’b10: IP header checksum and payload checksum calcu-
CIC: Checksum Insertion
[23:22] lation and insertion are enabled, but pseudo-header check-
Control
sum is not calculated in hardware.
• 2’b11: IP Header checksum and payload checksum calcula-
tion and insertion are enabled, and pseudo-header check-
sum is calculated in hardware.
This field is valid when the First Segment control bit (TDES0[28])
is set.
When set, this bit indicates that the descriptor list reached its fi-
[21] TER: Transmit End of Ring nal descriptor. The DMA returns to the base address of the list,
creating a Descriptor Ring.
When set, this bit indicates that the second address in the de-
scriptor is the Next Descriptor address, rather than the second
TCH: Second Address
[20] buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a
Chained
“don’t care” value. TDES0[21] takes precedence over TDES0[20].
This bit should be set to 1.
When set, these bits request the MAC to perform VLAN tagging or
untagging before transmitting the frames. If the frame is modified
for VLAN tags, the MAC automatically recalculates and replaces
the CRC bytes. The following list describes the values of these
bits:
• 2’b00: Do not add a VLAN tag.
VLIC: VLAN Insertion
[19:18] • 2’b01: Remove the VLAN tag from the frames before trans-
Control
mission. This option should be used only with the VLAN
frames.
• 2’b10: Insert a VLAN tag with the tag value programmed in
VLAN Tag Inclusion or Replacement Register.
• 2’b1: Replace the VLAN tag in frames with the Tag value pro-
grammed in VLAN Tag Inclusion or Replacement Register.
This option should be used only with the VLAN frames.
[17] Reserved Reserved

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Bits Name Description

When set, this bit indicates that the MAC transmitter detected
an error in the IP datagram header. The transmitter checks the
header length in the IPv4 packet against the number of header
bytes received from the application, and indicates an error status
if there is a mismatch. For IPv6 frames, a header error is reported
[16] IHE: IP Header Error
if the main header length is not 40 bytes. Furthermore, the Ether-
net Length/Type field value for an IPv4 or IPv6 frame must match
the IP header version received with the packet. For IPv4 frames,
an error status is also indicated if the Header Length field has a
value less than 0x5.
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
[15] ES: Error Summary • TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error
When set, this bit indicates the MAC transmitter has experienced
[14] JT: Jabber Timeout a jabber timeout. This bit is only set when EMACCONFIG_REG’s
bit EMACJABBER is not set.
When set, this bit indicates that the DMA or MTL flushed the frame
[13] FF: Frame Flushed
because of a software Flush command given by the CPU.

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Bits Name Description

When set, this bit indicates that MAC transmitter detected an error
in the TCP, UDP, or ICMP IP datagram payload.
The transmitter checks the payload length received in the IPv4
[12] IPE: IP Payload Error
or IPv6 header against the actual number of TCP, UDP, or ICMP
packet bytes received from the application, and issues an error
status in case of a mismatch.
When set, this bit indicates that a loss of carrier occurred during
frame transmission (that is, the MII_CRS signal was inactive for
[11] LOC: Loss of Carrier one or more transmit clock periods during frame transmission).
This is valid only for the frames transmitted without collision when
the MAC operates in the half-duplex mode.
When set, this bit indicates that the Carrier Sense signal from the
[10] NC: No Carrier
PHY was not asserted during transmission.
When set, this bit indicates that frame transmission is aborted be-
cause of a collision occurring after the collision window (64 byte-
[9] LC: Late Collision times including Preamble in MII mode, and 512 byte-times includ-
ing Preamble and Carrier Extension). This bit is not valid if the
Underflow Error bit is set.
When set, this bit indicates that the transmission was aborted after
16 successive collisions while attempting to transmit the current
[8] EC: Excessive Collision frame. If bit EMACRETRY of EMACCONFIG_REG is set, this bit is
set after the first collision, and the transmission of the frame is
aborted.
When set, this bit indicates that the transmitted frame is a VLAN-
[7] VF: VLAN Frame
type frame.
These status bits indicate the number of collisions that occurred
before the frame was transmitted. This count is not valid when
[6:3] Ctrl/status
the Excessive Collisions bit (TDES0[8]) is set. The core updates
this status field only in the half-duplex mode.
When set, this bit indicates that the transmission has ended be-
cause of excessive deferral of over 24,288 bit times (if Jumbo
[2] ED: Excessive Deferral
Frame is enabled) if bit EMACDEFERRAL of EMACCONFIG_REG is
set high.
When set, this bit indicates that the MAC aborted the frame be-
cause the data arrived late from the Host memory. Underflow Er-
ror indicates that the DMA encountered an empty transmit buffer
[1] UF: Underflow Error while transmitting the frame. The transmission process enters the
Suspended state and sets both Bit[5] in Transmit Underflow Reg-
ister (Status Register) and Bit[0] in Transmit Interrupt Register (Sta-
tus Register).
When set, this bit indicates that the MAC defers before transmis-
[0] DB: Deferred Bit sion because of the presence of a carrier. This bit is valid only in
the half-duplex mode.

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Table 10-6. Transmit Descriptor 1 (TDES1)

Bits Name Description

These bits request the MAC to add or replace the Source Address
field in the Ethernet frame with the value given in the MAC Address
0 register. If the Source Address field is modified in a frame, the
MAC automatically recalculates and replaces the CRC bytes. The
Bit[31] specifies the MAC Address Register value (1 or 0) that is
used for Source Address insertion or replacement. The following
list describes the values of Bits[30:29]:
• 2’b00: Do not include the source address.
[31:29] SAIC: SA Insertion Control
• 2’b01: Include or insert the source address. For reliable
transmission, the application must provide frames without
source addresses.
• 2’b10: Replace the source address. For reliable transmis-
sion, the application must provide frames with source ad-
dresses.
• 2’b11: Reserved
These bits are valid when the First Segment control bit
(TDES0[28]) is set.
[28:16] Reserved Reserved
[15:13] Reserved Reserved
TBS1: Transmit Buffer 1 These bits indicate the data buffer byte size in bytes. If this field
[12:0]
Size is 0, the DMA ignores this buffer and uses Buffer 2 or the next
descriptor.

Table 10-7. Transmit Descriptor 2 (TDES2)

Bits Name Description

[31:0] Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1.

Table 10-8. Transmit Descriptor 3 (TDES3)

Bits Name Description

This address contains the pointer to the physical memory where
[31:0] Next Descriptor Address
the Next Descriptor is present.

10.8.2 Receive Descriptors

The structure of the receiver linked lists is shown in Figure 10-10. Table 10-9 to Table 10-13 provide the description
of the linked lists.

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31 0

OWN
RDES0 Status[30:0]
Ctrl

Res
Ctrl
RDES1 Reserved[30:16] [15:14] Receive Buffer 1 Size[12:0]

RDES2 Buffer1 Address [31:0]

RDES3 Next Descriptor Address[31:0]

RDES4 Extended Status[31:0]

RDES5 Reserved

RDES6 Reserved

RDES7 Reserved

Figure 10-10. Receive Descriptor

Table 10-9. Receive Descriptor 0 (RDES0)

Bits Name Description

When set, this bit indicates that the descriptor is owned by the
DMA of the DWC_gmac. When this bit is reset, it indicates that the
[31] OWN: Own Bit descriptor is owned by the Host. The DMA clears this bit either
when it completes the frame reception or when the buffers that
are associated with this descriptor are full.
AFM: Destination Address When set, this bit indicates a frame that failed in the DA Filter in
[30]
Filter Fail the MAC.
These bits indicate the byte length of the received frame that was
transmitted to host memory. This field is valid when Last Descrip-
tor (RDES0[8]) is set and either the Descriptor Error (RDES0[14])
[29:16] FL: Frame Length or Overflow Error bits is reset. The frame length also includes the
two bytes appended to the Ethernet frame when IP checksum
calculation (Type 1) is enabled and the received frame is not a
MAC control frame.
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
[15] ES: Error Summary
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
When set, this bit indicates a frame truncation caused by a frame
that does not fit within the current descriptor buffers, and that the
[14] DE: Descriptor Error
DMA does not own the Next Descriptor. The frame is truncated.
This field is valid only when the Last Descriptor (RDES0[8]) is set.

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Bits Name Description

SAF: Source Address Filter When set, this bit indicates that the SA field of frame failed the SA
[13]
Fail Filter in the MAC.
When set, this bit indicates that the actual length of the frame
[12] LE: Length Error received and that the Length/Type field does not match. This bit
is valid only when the Frame Type (RDES0[5]) bit is reset.
When set, this bit indicates that the received frame was damaged
[11] OE: Overflow Error
because of buffer overflow in MTL.
When set, this bit indicates that the frame to which this descriptor
is pointing is a VLAN frame tagged by the MAC. The VLAN tag-
[10] VLAN: VLAN Tag
ging depends on checking the VLAN fields of the received frame
based on the Register (VLAN Tag Register) settings.
When set, this bit indicates that this descriptor contains the first
buffer of the frame. If the size of the first buffer is 0, the second
[9] FS: First Descriptor buffer contains the beginning of the frame. If the size of the sec-
ond buffer is also 0, the next Descriptor contains the beginning
of the frame.
When set, this bit indicates that the buffers pointed to by this de-
[8] LS: Last Descriptor
scriptor are the last buffers of the frame.
When IP Checksum Engine (Type 1) is selected, this bit, if set,
indicates one of the following:
• The 16-bit IPv4 header checksum calculated by the core did
not match the received checksum bytes.
• The header checksum checking is bypassed for non-IPv4
frames.
Otherwise, this bit, when set, indicates the Giant Frame Status.
IP Checksum Error (Type1),
[7] Giant frames are larger than 1,518 bytes (or 1,522 bytes for VLAN or
or Giant Frame
2,000 bytes when Bit[27] of the MAC Configuration register is set),
normal frames and larger-than-9,018-byte (9,022-byte for VLAN)
frames when Jumbo Frame processing is enabled.
When set, this bit indicates that a late collision has occurred while
[6] LC: Late Collision
receiving the frame in the half-duplex mode.
When set, this bit indicates that the Receive Frame is an Ethernet-
type frame (the LT field is greater than, or equal to, 1,536). When
[5] FT: Frame Type
this bit is reset, it indicates that the received frame is an IEEE 802.3
frame. This bit is not valid for Runt frames which are less than 14
bytes.
When set, this bit indicates that the Receive Watchdog Timer has
RWT: Receive
[4] expired while receiving the current frame and the current frame is
Watchdog Timeout
truncated after the Watchdog Timeout.
When set, this bit indicates that the MII_RXER signal is asserted
[3] RE: Receive Error
while MII_RXDV is asserted during frame reception.
When set, this bit indicates that the received frame has a non-
[2] DE: Dribble Bit Error integer multiple of bytes (odd nibbles). This bit is valid only in the
MII Mode.

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Bits Name Description

When set, this bit indicates that a Cyclic Redundancy Check (CRC)
[1] CE: CRC Error Error occurred on the received frame. This field is valid only when
the Last Descriptor (RDES0[8]) is set.
When the IP Checksum Offload (Type 2) is present, this bit, when
set, indicates that the extended status is available in descriptor
word 4 (RDES4). This is valid only when the Last Descriptor bit
(RDES0[8]) is set. This bit is invalid when Bit 30 is set.
When IP Checksum Offload (Type 2) is present, this bit is set even
when the IP Checksum Offload engine bypasses the processing
Extended Status Available/
[0] of the received frame. The bypassing may be because of a non-IP
Rx MAC Address
frame or an IP frame with a non-TCP/UDP/ICMP payload.
When the IPC Full Offload is not selected, this bit indicates an
Rx MAC Address status. When set, this bit indicates that the Rx
MAC Address registers value (1 to 15) matched the frame’s DA field.
When reset, this bit indicates that the Rx MAC Address Register 0
value matched the DA field.

Table 10-10. Receive Descriptor 1 (RDES1)

Bits Name Description

When set, this bit prevents setting the Status Register’s RI bit
(CSR5[6]) for the received frame that ends in the buffer indicated
[31] Ctrl
by this descriptor. This, in turn, disables the assertion of the in-
terrupt to Host because of the RI for that frame.
[30:29] Reserved Reserved
[28:16] Reserved Reserved
When set, this bit indicates that the descriptor list reached its fi-
[15] RER: Receive End of Ring nal descriptor. The DMA returns to the base address of the list,
creating a Descriptor Ring.
When set, this bit indicates that the second address in the de-
RCH: Second Address scriptor is the Next Descriptor address rather than the second
[14]
Chained buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a
“don’t care” value. RDES1[15] takes precedence over RDES1[14].
[13] Reserved Reserved
Indicates the first data buffer size in bytes. The buffer size must
be a multiple of 4, even if the value of RDES2 (buffer1 address
RBS1: Receive Buffer 1 pointer) is not aligned to bus width. When the buffer size is not
[12:0]
Size a multiple of 4, the resulting behavior is undefined. If this field
is 0, the DMA ignores this buffer and uses Buffer 2 or the next
descriptor depending on the value of RCH (Bit[14]).

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Table 10-11. Receive Descriptor 2 (RDES2)

Bits Name Description

[31:0] Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1.

Table 10-12. Receive Descriptor 3 (RDES3)

Bits Name Description

This address contains the pointer to the physical memory where
[31:0] Next Descriptor Address
the Next Descriptor is present.

Table 10-13. Receive Descriptor 4 (RDES4)

Bits Name Description

[31:28] Reserved Reserved
[27:26] Reserved Reserved
[25] Reserved Reserved
[24] Reserved Reserved
[23:21] Reserved Reserved
[20:18] Reserved Reserved
[17] Reserved Reserved
[16] Reserved Reserved
[15] Reserved Reserved
[14] Reserved Reserved
[13] Reserved Reserved
[12] Reserved Reserved
These bits are encoded to give the type of the message received.
• 3’b0000: Reserved
• 3’b0001: SYNC (all clock types)
• 3’b0010: Follow_Up (all clock types)
• 3’b0011: Delay_Req (all clock types)
• 3’b0100: Delay_Resp (all clock types)
• 3’b0101: Pdelay_Req (in peer-to-peer transparent clock)
[11:8] Message Type
• 3’b0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 3’b0111: Pdelay_Resp_Follow_Up (in peer-to-peer transpar-
ent clock)
• 3’b1000: Announce
• 3’b1001: Management
• 3’b1010: Signaling
• 3’b1011-3’b1110: Reserved
• 3’b1111: Reserved
When set, this bit indicates that the received packet is an IPv6
[7] IPv6 Packet Received packet. This bit is updated only when Bit[10] (IPC) of Register
(MAC Configuration Register) is set.

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Bits Name Description

When set, this bit indicates that the received packet is an IPv4
[6] IPv4 Packet Received packet. This bit is updated only when Bit[10] (IPC) of Register
(MAC Configuration Register) is set.
When set, this bit indicates that the checksum offload engine is
[5] IP Checksum Bypassed
bypassed.
When set, this bit indicates that the 16-bit IP payload checksum
(that is, the TCP, UDP, or ICMP checksum) that the core calculated
does not match the corresponding checksum field in the received
[4] IP Payload Error
segment. It is also set when the TCP, UDP, or ICMP segment
length does not match the payload length value in the IP Header
field. This bit is valid when either Bit 7 or Bit 6 is set.
When set, this bit indicates that either the 16-bit IPv4 header
checksum calculated by the core does not match the received
[3] IP Header Error
checksum bytes, or the IP datagram version is not consistent with
the Ethernet Type value. This bit is valid when either Bit[7] or Bit[6]
is set.
These bits indicate the type of payload encapsulated in the IP
datagram processed by the Receive Checksum Offload Engine
(COE). The COE also sets these bits to 2’b00 if it does not process
the IP datagram’s payload due to an IP header error or fragmented
IP.
[2:0] IP Payload Type
• 3’b000: Unknown or did not process IP payload
• 3’b001: UDP
• 3’b010: TCP
• 3’b011: ICMP
• 3’b1xx: Reserved
This bit is valid when either Bit[7] or Bit[6] is set.

10.9 Register Summary

Note that specific fields or bits of a given register may have different access attributes. Below is the list of all
attributes together with the abbreviations used in register descriptions.

• Read Only (RO)

• Write Only (WO)

• Read and Write (R/W)

• Read, Write, and Self Clear (R/W/SC)

• Read, Self Set, and Write Clear (R/SS/WC)

• Read, Write Set, and Self Clear (R/WS/SC)

• Read, Self Set, and Self Clear or Write Clear (R/SS/SC/WC)

• Read Only and Write Trigger (RO/WT)

• Read, Self Set, and Read Clear (R/SS/RC)

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• Read, Write, and Self Update (R/W/SU)

• Latched-low (LL)

• Latched-high (LH)

Name Description Address Access

DMA configuration and control registers
DMABUSMODE_REG Bus mode configuration 0x3FF69000 R/WS/SC
DMATXPOLLDEMAND_REG Pull demand for data transmit 0x3FF69004 RO/WT
DMARXPOLLDEMAND_REG Pull demand for data receive 0x3FF69008 RO/WT
Base address of the first receive de-
DMARXBASEADDR_REG 0x3FF6900C R/W
scriptor
Base address of the first transmit de-
DMATXBASEADDR_REG 0x3FF69010 R/W
scriptor
State of interrupts, errors and other
DMASTATUS_REG 0x3FF69014 R/SS/WC
events
Receive and Transmit operating modes
DMAOPERATION_MODE_REG 0x3FF69018 R/SS/WC
and command
DMAIN_EN_REG Enable / disable interrupts 0x3FF6901C R/W
Missed Frame and Buffer Overflow
DMAMISSEDFR_REG 0x3FF69020 R/W
Counter Register
DMARINTWDTIMER_REG Watchdog timer count on receive 0x3FF69024 R/W
DMATXCURRDESC_REG Pointer to current transmit descriptor 0x3FF69048 RO
DMARXCURRDESC_REG Pointer to current receive descriptor 0x3FF6904C RO
DMATXCURRADDR_BUF_REG Pointer to current transmit buffer 0x3FF69050 RO
DMARXCURRADDR_BUF_REG Pointer to current receive buffer 0x3FF69054 RO
MAC configuration and control registers
EMACCONFIG_REG MAC configuration 0x3FF6A000 R/W
EMACFF_REG Frame filter settings 0x3FF6A004 R/W
EMACGMIIADDR_REG PHY configuration access 0x3FF6A010 R/WS/SC
EMACMIIDATA_REG PHY data read write 0x3FF6A014 R/W
R/WS/SC(FCB)
EMACFC_REG frame flow control 0x3FF6A018
R/W(BPA)
EMACDEBUG_REG Status debugging bits 0x3FF6A024 RO
PMT_RWUFFR_REG Remote Wake-Up Frame Filter 0x3FF6A028 RO
PMT_CSR_REG PMT Control and Status 0x3FF6A02C RO
EMACLPI_CSR_REG LPI Control and Status 0x3FF6A030 RO
EMACLPITIMERSCONTROL_REG LPI Timers Control 0x3FF6A034 RO
EMACINTS_REG Interrupt status 0x3FF6A038 RO
EMACINTMASK_REG Interrupt mask 0x3FF6A03C R/W
Upper 16 bits of the first 6-byte MAC ad-
EMACADDR0HIGH_REG 0x3FF6A040 R/W
dress
Lower 32 bits of the first 6-byte MAC
EMACADDR0LOW_REG 0x3FF6A044 R/W
address

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Name Description Address Access

MAC address filtering and upper 16 bits
EMACADDR1HIGH_REG 0x3FF6A048 R/W
of the second 6-byte MAC address
Lower 32 bits of the second 6-byte
EMACADDR1LOW_REG 0x3FF6A04C R/W
MAC address
MAC address filtering and upper 16 bits
EMACADDR2HIGH_REG 0x3FF6A050 R/W
of the third 6-byte MAC address
Lower 32 bits of the third 6-byte MAC
EMACADDR2LOW_REG 0x3FF6A054 R/W
address
MAC address filtering and upper 16 bits
EMACADDR3HIGH_REG 0x3FF6A058 R/W
of the fourth 6-byte MAC address
Lower 32 bits of the fourth 6-byte MAC
EMACADDR3LOW_REG 0x3FF6A05C R/W
address
MAC address filtering and upper 16 bits
EMACADDR4HIGH_REG 0x3FF6A060 R/W
of the fifth 6-byte MAC address
Lower 32 bits of the fifth 6-byte MAC
EMACADDR4LOW_REG 0x3FF6A064 R/W
address
MAC address filtering and upper 16 bits
EMACADDR5HIGH_REG 0x3FF6A068 R/W
of the sixth 6-byte MAC address
Lower 32 bits of the sixth 6-byte MAC
EMACADDR5LOW_REG 0x3FF6A06C R/W
address
MAC address filtering and upper 16 bits
EMACADDR6HIGH_REG 0x3FF6A070 R/W
of the seventh 6-byte MAC address
Lower 32 bits of the seventh 6-byte
EMACADDR6LOW_REG 0x3FF6A074 R/W
MAC address
MAC address filtering and upper 16 bits
EMACADDR7HIGH_REG 0x3FF6A078 R/W
of the eighth 6-byte MAC address
Lower 32 bits of the eighth 6-byte MAC
EMACADDR7LOW_REG 0x3FF6A07C R/W
address
EMACWDOGTO_REG Watchdog timeout control 0x3FF6A0DC R/W
Clock configuration registers
EMAC_EX_CLKOUT_CONF_REG RMII clock divider setting 0x3FF69800 R/W
RMII clock half and whole divider set-
EMAC_EX_OSCCLK_CONF_REG 0x3FF69804 R/W
tings
Clock enable and external / internal
EMAC_EX_CLK_CTRL_REG 0x3FF69808 R/W
clock selection
PHY type and SRAM configuration registers
EMAC_EX_PHYINF_CONF_REG Selection of MII / RMII phy 0x3FF6980C R/W
EMAC_PD_SEL_REG Ethernet RAM power-down enable 0x3FF69810 R/W

10.10 Registers
The addresses in parenthesis besides register names are the register addresses relative to the EMAC base
address provided in Table 1-6 Peripheral Address Mapping in Chapter 1 System and Memory. The absolute
register addresses are listed in Section 10.9 Register Summary.

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Note: The value of all reset registers must be set to the reset value.

Register 10.1. DMABUSMODE_REG (0x0000)

EN
US 8_M LIB T
E_ O EA
A S

EN
_L

ZE

CH
LX DR R

L
SE DE

ST
RA ST
PB AD DBU

_L
PB

ST _S
PB

_S

IP
UR
R

O
P_
)

_R RB
SC
A_

PR BU
ed

K
A E

TI

_B

_S
X

SW _A
DE
M
rv

D_
DM MI

OG

SC
_D
se

A
I_

T_
A

XE

DM
DM
(re

DE
PR
RX

AL
FI
31 27 26 25 24 23 22 17 16 15 14 13 8 7 6 2 1 0

0 0 0 0 0 0 0 0 0 0x01 0 0x0 0x01 0 0x00 0 1 Reset

DMAMIXEDBURST When this bit is set high and the FB(FIXES_BURST) bit is low, the AHB master
interface starts all bursts of a length more than 16 with INCR (undefined burst), whereas it reverts
to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. (R/W)

DMAADDRALIBEA When this bit is set high and the FB bit is 1, the AHB interface generates all bursts
aligned to the start address LS bits. If the FB bit is 0, the first burst (accessing the start address
of data buffer) is not aligned, but subsequent bursts are aligned to the address. (R/W)

PBLX8_MODE When set high, this bit multiplies the programmed PBL(PROG_BURST_LEN) value
(Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
128, and 256 beats depending on the PBL value. (R/W)

USE_SEP_PBL When set high, this bit configures the Rx DMA to use the value configured in
Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When
reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines. (R/W)

RX_DMA_PBL This field indicates the maximum number of beats to be transferred in one Rx DMA
transaction. This is the maximum value that is used in a single block Read or Write.The Rx
DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts
a burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and
32. Any other value results in undefined behavior. This field is valid and applicable only when
USP(USE_SEP_PBL) is set high. (R/W)

FIXED_BURST This bit controls whether the AHB master interface performs fixed burst transfers or
not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of
the normal burst transfers. When reset, the AHB interface uses SINGLE and INCR burst transfer
operations. (R/W)

PRI_RATIO These bits control the priority ratio in the weighted round-robin arbitration between the
Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx
represented by each bit: (R/W)

• 2’b00 — 1: 1

• 2’b01 — 2: 0

• 2’b10 — 3: 1

• 2’b11 — 4: 1

Continued on the next page...

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Register 10.1. DMABUSMODE_REG (0x0000)

Continued from the previous page...

PROG_BURST_LEN These bits indicate the maximum number of beats to be transferred in one DMA
transaction. If the number of beats to be transferred is more than 32, then perform the following
steps: 1. Set the PBLx8 mode; 2. Set the PBL. (R/W)

ALT_DESC_SIZE When set, the size of the alternate descriptor increases to 32 bytes. (R/W)

DESC_SKIP_LEN This bit specifies the number of Word to skip between two unchained descriptors.
The address skipping starts from the end of current descriptor to the start of next descriptor.
When the DSL(DESC_SKIP_LEN) value is equal to zero, the descriptor table is taken as contigu-
ous by the DMA in Ring mode. (R/W)

DMA_ARB_SCH This bit specifies the arbitration scheme between the transmit and receive paths.
1’b0: weighted round-robin with RX: TX or TX: RX, priority specified in PR (bit[15:14]); 1’b1 Fixed
priority (Rx priority to Tx). (R/W)

SW_RST When this bit is set, the MAC DMA Controller resets the logic and all internal registers of
the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC
clock domains. Before reprogramming any register of the ETH_MAC, you should read a zero (0)
value in this bit. (R/WS/SC)

Register 10.2. DMATXPOLLDEMAND_REG (0x0004)

31 0

0x000000000 Reset

TRANS_POLL_DEMAND When these bits are written with any value, the DMA reads the current
descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that
descriptor is not available (owned by the Host), the transmission returns to the suspend state
and Bit[2] (TU) of Status Register is asserted. If the descriptor is available, the transmission
resumes. (RO/WT)

Register 10.3. DMARXPOLLDEMAND_REG (0x0008)

31 0

0x000000000 Reset

RECV_POLL_DEMAND When these bits are written with any value, the DMA reads the current de-
scriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is
not available (owned by the Host), the reception returns to the Suspended state and Bit[7] (RU)
of Status Register is asserted. If the descriptor is available, the Rx DMA returns to the active
state. (RO/WT)

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Register 10.4. DMARXBASEADDR_REG (0x000C)

31 0

0x000000000 Reset

START_RECV_LIST This field contains the base address of the first descriptor in the Receive De-
scriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only. (R/W)

Register 10.5. DMATXBASEADDR_REG (0x0010)

31 0

0x000000000 Reset

START_TRANS_LIST This field contains the base address of the first descriptor in the Transmit De-
scriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA. There-
fore, these LSB bits are read-only. (R/W)

Register 10.6. DMASTATUS_REG (0x0014)

IN _S AIL
T
E

P
IN

IL
AT

AN PR UN O
E

TO
S_ OC AV
TR V_IN _U OP
FA LY_R SU MM

TR NS_ UF_ _T
TR NS_ LO OW
VA
RE V_P T_T INT
R_
AT
ST

S_ T
TA E MM
T

A B ER
ST

C UF ST
A T NA
(re BU IN
ER
C_

F L
R T_ U

C D _
IN

AN JA W
C RO O

TR _O DF
RE _W NS
_
C_

RE V_B C_

TR S_ BB
EA IN _S
TS
T_

RO

L_ CV

T
_ )

CV UN
N_ NT
O

CV RA
(R ed)

EA ed)
(re PM
AC ed

BI
ed

PR

V
I
R_

S_

RE NS_
RE Y_T
EM erv

AB _
rv

rv

rv
_

RM
RO

AN

CV
se

se

se

RL
es

A
NO
(re

TR
ER

RE

31 30 29 28 27 26 25 23 22 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0x0 0x0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

EMAC_PMT_INT This bit indicates an interrupt event in the PMT module of the ETH_MAC. The
software must read the PMT Control and Status Register in the MAC to get the exact cause of
interrupt and clear its source to reset this bit to 1’b0. (RO)

Continued on the next page...

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