EE141-Fall 2010 Digital Integrated Circuits
Lecture 5 Overview of Semiconductor Memory
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Homework #2 due today Homework #3 due next Thursday Labs start tomorrow
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Class Material
Last lecture
Detailed Switch Model CMOS Gates Design Rules
Todays lecture
Overview of semiconductor memory
Reading (Chapter 12.1, 12.2.3, 12.3.1)
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Semiconductor Memory
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Why Memory?
Intel 45nm Core 2
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Semiconductor Memory Classification
Read-Write Memory Non-Volatile Read-Write Memory EPROM E PROM SRAM DRAM FIFO LIFO Shift Register CAM
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Read-Only Memory
Random Access
Non-Random Access
Mask-Programmed Programmable (PROM)
FLASH
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Random Access Memories (RAM)
STATIC (SRAM)
Data stored as long as supply is applied Larger (6 transistors/cell) Fast Differential (usually)
DYNAMIC (DRAM)
Periodic refresh required Smaller (1-3 transistors/cell) Slower Single Ended
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Random Access Chip Architecture
Conceptual: linear array
Each box holds some data But this does not lead to a nice layout shape Too long and skinny
Create a 2-D array
Decode Row and Column address to get data
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Basic Memory Array
CORE: - keep square within a 2:1 ratio - rows are word lines - columns are bit lines - data in and out on columns DECODERS: - needed to reduce total number of pins; N+M address lines for 2N+M bits of storage 220= 1Mb Ex: if N+M=20 MULTIPLEXING: - used to select one or more columns for input or output of data
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Basic Static Memory Element
If D is high, D_b will be driven low Which makes D stay high Positive feedback
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Positive Feedback: Bi-Stability
Vi 1 V o1 = V i 2 V o2
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V o1
o V
Vi2
V 5
V o2 = V i 1
2 i
V i1 A
1
V o2
V i 2 = V o1
o V 5 2 i
B V i 1 = V o2
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Writing into a Cross-Coupled Pair
Access transistor must be able to overpower the feedback
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Writing a 1
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Memory Cell
Complementary data values are written (read) from two sides
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SRAM Column
WL0
WL2
WL3
BL
BL_B
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SRAM Array Layout
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65nm SRAM
ST/Philips/Motorola
Access Transistor
Pull down
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Pull up
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Decoders
M bits S0 S1 S2 S0 A0 A1 M bits Word 0 Word 1 Word 2 Storage cell Word 0 Word 1 Word 2 Storage cell
wo r d s
SN 2 2 SN 2 1
A K2 1 Word N 2 2 Word N 2 1 K = log2N Input-Output (M bits)
De c o d e r
Word N 2 2 Word N 2 1
Input-Output (M bits) Decoder reduces the number of select signals
Intuitive architecture for N x M memory Too many select signals: N words == N select signals
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K = log2N
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Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
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Decoder Design Example
Look at decoder for 256x256 memory block (8KBytes)
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Problem Setup
Goal: Build fastest, lowest possible power decoder with static CMOS logic What we know
Basically need 256 AND gates, each one of them drives one word line
N=8
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Possible AND8
Build 8-input NAND gate using 2-input gates and inverters Is this the best we can do? Is this better than using fewer NAND4 gates?
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Possible Decoder
256 8-input AND gates
Each built out of tree of NAND gates and inverters
Need to drive a lot of capacitance (SRAM cells)
Whats the best way to do this?
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Next Lecture
Buffer delay optimization
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