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SYLLABUS: ENGG. DIGITAL ELEX
GATE-2019
ELECTRONICS AND COMMUNICATION ENGINEERING (EC)
Number systems; Combinatorial circuits: Boolean algebra, minimization of functions using Boolean
identities and Karnaugh map, logic gates and their static CMOS implementations, arithmetic circuits,
code converters, multiplexers, decoders and PLAs; Sequential circuits: latches and flip-flops, counters,
shift registers and finite state machines; Data converters: sample and hold circuits, ADCs and DACs;
Semiconductor memories: ROM, SRAM, DRAM; 8-bit microprocessor (8085): architecture,
programming, memory and I/O interfacing.
ELECTRICAL ENGINEERING (EE)
Combinational and Sequential logic circuits, Multiplexer, Demultiplexer, Schmitt trigger, Sample and
hold circuits, A/D and D/A converters, 8085Microprocessor: Architecture, Programming and
Interfacing.
IES-2019
ELECTRONICS AND TELECOMMUNICATION ENGINEERING
Transistor as a switching element; Boolean algebra, simplification of Boolean functions, Karnaguh map and
applications; IC Logic gates and their characteristics; IC logic families : DTL, TTL, ECL, NMOS, PMOS
and CMOS gates and their comparison; Combinational logic Circuits; Half adder, Full adder; Digital
comparator; Multiplexer Demulti-plexer; ROM an their applications. Flip flops. R-S, J-K, D and T flip-
flops; Different types of counters and registers Waveform generators. A/D and D/A converters.
Semiconductor memories.
ELECTRICAL ENGINEERING
Digital logic gate families, universal gates-combination circuits for arithmetic and logic operational,
equential logic circuits. Counters, registers, RAM and ROMs.
Table of Contents
1. Number System 1
1.1 (r)’s and (r-1)’s Comp. 1
1.2 Miscellaneous 4
2. Boolean Algebra 9
3. Logic GATES 24
4. Combinational Digital Circuits 40
4.1 Multiplexer 40
4.2 Adder 49
4.3 Decoder 53
4.4 Miscellaneous 55
5. Sequential Digital Circuits 59
5.1 Counter 59
5.2 Miscellaneous 74
6. Semiconductor Memories 90
7. Logic Gate Families 95
8. A/D & D/A Converters 111
9. MICROPROCESSOR 8085 PROGRAMMING & BASICS 122
10.MEMORIES & INTERFACING 134
Answers : 138
01
Number System
1.1 (r)’s and (r-1)’s Comp. AB [GATE -EC - 1987]
(5) The subtraction of a binary number Y from
AB [IES – EC – 1992] another binary number X, done by adding
(1) Which of the following number systems has the 2’s complement of Y to X, results in a
two 0’s? binary number without overflow. This
(A) Sign plus magnitude implies that the result is:
(B) 1’s complement (A) negative and is in normal form.
(C) 2’s complement (B) negative and is in 2’s complement
(D) None of the above form.
AC [IES – EC – 1993] (C) positive and is in normal form.
(2) When signed numbers are used in binary (D) positive and is in 2’s complement form.
arithmetic, then which one of the following
notations would have unique representation AA [GATE - IN - 2003]
for zero? (6) Two 4-bit 2’s complement numbers 1011
and 0110 are added. The result expressed in
(A) Sign- magnitude
4-bit 2’s complement notation is
(B) 1’s complements
(C) 2’s complements (A) 0001
(D) 9’s complements (B) 0010
AA [IES – EC – 1995] (C) 1101
(3) Two’s complement of a given 3 or more bit (D) cannot be expressed in 4-bit 2’s
binary number of non- zero magnitude is the complement
same as the original number if :
AC [GATE -EC - 2004]
(A) MSB is zero (7) 11001, 1001 and 111001 correspond to the
(B) LSB is zero 2’s complement representation of which one
of the following gets of number?
(C) MSB is one
(A) 25, 9 and 57 respectively
(D) LSB is one
(B) – 6, –6 and – 6 respectively
AD [IES – EE – 2005]
(4) Which of the following notations have two (C) –7, –7 and –7 respectively
representations of zero ? (D) –25, –9 and –57 respectively
1. 1's complement with radix of number
being 2 AD [GATE -EC - 1998]
(8) An equivalent 2’s complement
2. 7's complement with radix of number representation of the 2’s complement
being 8 number 1101 is
3. 9's complement with radix of number
(A) 110100 (B) 001101
being 10
4. 10's complement with radix of number (C) 110111 (D) 111101
being 10 AD [GATE -EC - 2002]
Select the correct answer using the code (9) 4-bit 2’s complement representation of a
given below. decimal number is 1000. The number is :
(A) 1, 2 and 4 (B) 1 and 3 (A) +8 (B) 0
(C) 2, 3 and 4 (D) 1, 2 and 3 (C) – 7 (D) – 8
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DIGITAL ELECTRONICS
AC [IES – EC – 2001] (C) copy the original byte to the less
(10) F's complement of (2BFD)hex is significant byte of the word and make
(A) E304 (B) D403 each bit of the more significant byte
equal to the most significant bit of the
(C) D402 (D) C403 original byte.
AD [IES – EC – 2002] (D) copy the original byte to the less
(11) A number is expressed in binary two’s significant byte as well as the more
complement as 10011. Its decimal significant byte of the word.
equivalent value is AC [GATE - IN - 2011]
(A) 19 (B) 13 (16) The result of (45)10 (45)16 expressed in bit
(C) – 19 (D) – 13 2’s complement representation is
(A) 011000 (B) 100111
AA [IES – EC – 2005]
(12) The number of 1's in 8-bits representation of (C) 101000 (D) 101001
- 127 in 2's complement form is m and that AA [GATE – EC – 2004]
in 1's complement form is n. What is the (17) The range of signed decimal numbers that
value of m:n ? can be represented by 6-bit 1’s complement
(A) 2 : 1 (B) 1 : 2 number is
(C) 3 : 1 (D) 1.02 (A) – 31 to + 31 (B) – 63 to +63
(C) – 64 to +63 (D) – 32 to +31
AA [IES – EC – 2004]
(13) How many 1's are present in the binary AC [GATE – EC – 2007]
representation (18) X = 01110 and Y = 11001 are two 5-bit
(4 4096) (9 256) (7 16) 5 binary numbers represented in two’s
complement format. The sum of X and Y
(A) 8 (B) 9 represented in two’s complement format
(C) 10 (D) 11 using 6 bits is
(A) 100111 (B) 001000
AD [GATE - IN - 2006] (C) 000111 (D) 101001
(14) A number N is stored in a 4-bit 2’s
complement representation as AB [GATE – EC – 2008]
a3 a2 a1 a0 (19) Two number are represented in signed 2’s
complement from as
It is copied into a 6-bit register and after a P = 11101101 and Q = 11100110
few operations the final bit pattern is If Q is subtract from P, the value obtained in
a3 a3 a2 a1 a0 1 signed 2’s complement form is :
(A) 100000111 (B) 00000111
The value of the bit pattern in 2’s (C) 11111001 (D) 111111001
compliment representation is given terms of
the original number is N as AC [GATE - IN - 1999]
(20) A number in 4-bit two’s complement
(A) 32 a3 2N 1
representation is X3 X 2 X1 X 0 . This number
(B) 32 a3 2 N 1 when stored using 8 – bits will be :
(C) 2 N 1 (A) 0000X 3 X 2 X1 X 0
(D) 2 N 1 (B) 1111X 3 X 2 X 1 X 0
AC [GATE – EC – 1997] (C) X 3 X 3 X 3 X 3 X 3 X 2 X 1 X 0
(15) A signed integer has been stored in a byte
(D) X 3 X 3 X 3 X 3 X 3 X 2 X1 X 0
using the 2’s complement format. We wish
to store the same integer in a 16 bit word. AC [GATE -EC - 1998]
We should (21) Two 2’s complement numbers having sign
(A) copy the original byte to the less bits x and y are added and the sign bit of the
significant byte of the word and fill the result is z. Then, the occurrence of overflow
more significant byte with zeros. is indicated by the Boolean function.
(B) copy the original byte to the more (A) xyz (B) x y z
significant byte of the word and fill the
less significant byte with zeros. (C) x y z x y z (D) xy yz zx
Page 2 TARGATE EDUCATION GATE-( EC /EE)
Topic 01 - Number System
AB[GATE-EC-2008]
(22) The two numbers represented in signed 2's
complement form are
P = 11101101 and Q = 11100110. If Q is
subtracted from P, the value obtained in
signed 2's complement form is
(A) 100000111
(B) 00000111
(C) 11111001
(D) 111111001
AB[GATE-EC-2001]
(23) The 2’s complements representation of -17
is
(A) 101110 (B) 101111
(C) 111110 (D) 110001
AC [GATE – IN – 2018]
(24) The representation of the decimal number
(27.625)10 in base-2 number system is
(A) 11011.110 (B) 11101.101
(C) 11011.101 (D) 10111.110
**********
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DIGITAL ELECTRONICS
1.2 Miscellaneous Codes:
A B C D
AD [GATE-EE-2014]
(1) Which of the following is an invalid state in (A) 3 2 4 1
an 8-4-2-1 Binary Coded Decimal counter (B) 2 3 1 4
(A) 1 0 0 0 (B) 1 0 0 1 (C) 1 2 3 4
(C) 0 0 1 1 (D) 1 1 0 0 (D) 3 1 2 4
AD[GATE-EC-2006] AC [IES – EE – 1992]
(2) A new Binary Coded Pentary (BCP) number (7) Which of the following hexagonal sum is
system is proposed in which every digit of a equivalent to hexadecimal A8H?
base-5 number is represented by its
corresponding 3-bit binary code. For (A) 2CH + 4FH
example, the base-5 number 24 will be
(B) 5EH + 1AH
represented by its BCP code 010100. In this
numbering system, the BCP code (C) 3BH + 6DH
100010011001 corresponds to the following
number in base-5 system (D) 5AH + 2CH
(A) 423 (B) 1324 AB [IES – EE – 1992]
(C) 2201 (D) 4231 (8) Match List - I with List - II and select the
correct answer by using the codes given
AA[GATE-IN-2004] below the lists:
(3) 7EH and 5FH are XORed. The output is
multiplied by 10H. The result is : List-I List-II
(Octal) (Binary)
(A) 0210H (B) 7E5FH
A. 75 1. 010110
(C) 5F7EH (D) 2100H
B. 65 2. 110101
AD[GATE-EC-2004] C. 37 3. 111101
(4) A digital system is required to amplify a
binary-enclosed audio signal. The user D. 26 4. 011111
should be able to control the gain of the Codes:
amplifier from a minimum to a maximum in
100 increments. The minimum number of A B C D
bits required to encode, in straight binary, is (A) 3 1 4 2
(A) 8 (B) 6 (B) 3 2 4 1
(C) 1 2 3 4
(C) 5 (D) 7
(D) 4 1 2 3
A3.9to4.1 [GATE – EC – 2014]
(5) The number of bytes required to represent AA [IES – EE – 1995]
the decimal number 1856357 in packed (9) Match List I with List II and select the
BCD (Binary coded decimal) form is -------- correct answer using the codes given below
--. the lists:
AC [IES – EE – 1992] List I List II
(6) Match List-I with List-II and select the
correct answer by using the Codes given (Binary) (Decimal)
below the lists: A. 10101010 1. 128
List - I List - II B. 11110000 2. 240
(Hexadecimal) (Octal) C. 10001000 3. 170
A. 68 1. 150 D. 10000000 4. 136
B. 8C 2. 214 Codes:
C. 4F 3. 117 A B C D
(A) 3 2 4 1
D. 5D 4. 135
(B) 2 3 1 4
Page 4 TARGATE EDUCATION GATE-( EC /EE)
Topic 01 - Number System
(C) 2 4 1 3 AB [IES – EE – 2003]
(D) 3 1 2 4 (16) The binary representation 100110 is
numerically equivalent to the
AD [IES – EE – 1995] 1. Decimal representation 46
(10) The decimal equivalent of the hexadecimal
number (BAD)16 is 2. Octal representation 46
(A) 111013 (B) 5929 3. Hexadecimal representation 26
(C) 3416 (D) 2989 4. Excess-3 representation 13
Select the correct answer using the codes
AD [GATE -EC -2003]
given below:
(11) The circuit shown in the figure converts
(A) 1 and 2 (B) 2 and 3
(C) 1 and 3 (D) 2 and 4
AB [IES – EE – 2004]
(17) What are the values respectively of R1 and
R2 in the expression
(235)R1 = (565)10 = (1065)R2?
(A) 8, 16 (B) 16, 8
(A) BCD to Binary code
(C) 6, 16 (D) 12, 8
(B) Binary to excess-3code
(C) Excess-3 to Gray code AA [IES – EC – 1991]
(D) Gray to Binary code. (18) Which of the following is incorrect?
AB [IES – EE – 1998] (A) 11100 2 – 1000012 001012
(12) Which one of the following is a non-valid
(B) 15E 16 350 10
BCD code?
(A) 0111 1001 (B) 0101 1011 (C) 8110 1010001 2
(C) 0100 1000 (D) 0100 1001
(D) 37.4 8 011111.100 2
AD [IES – EE – 1999]
(13) A four-bit BCD (DCBA) for numeral 9 can AB [IES – EC – 1991]
be decoded most economically by the logic (19) Consider the bit pattern 01010001. Which of
operation the following has Hamming distance of
(A) AD (B) ABD exactly 2 from these patterns?
(C) ACD (D) ABCD (A) 01010000 (B) 01010010
AB [GATE -EC - 1990] (C) 01010011 (D) 01010110
(14) The minimal function that can detect a
AC [IES – EC – 1992]
“divisible by 3”8421 BCD code digit
(20) If two numbers in excess – 3 code are added
(representation is D8 D4 D2 D1 ) is given by:
and the result is less than 9,then to get
(A) D8 D1 D4 D2 D8 D2 D1 equivalent binary
(B) D8 D1 D4 D2 D1 D4 D2 D1 (A) 0011 is subtracted
D8 D4 D2 D1 (B) 0011 is added
(C) 0110 is subtracted
(C) D8 D1 D4 D2 D8 D4 D2 D1
(D) 0110 is added
(D) D4 D2 D1 D4 D2 D1 D8 D4 D2 D1
AA [IES – EC – 1992]
AD [IES – EE – 2002] (21) A 7 bit Hamming code (Even parity checker)
(15) The decimal equivalent of hexadecimal 0001001 for a BCD digit is known to have
number 2 A 0 F is : error. The BCD encoded digit is
(A) 17670 (B) 17607 (A) 9 (B) 5
(C) 17067 (D) 10767 (C) 3 (D) 0
www.targate.org Page 5
DIGITAL ELECTRONICS
AB [IES – EC – 1993] 3 512 7 64 5 8 3 is
(22) The logic circuit given below converts a
(A) 8 (B) 9
Gray code Y1 Y2 Y3 into
(C) 10 (D) 12
AC [IES – EC – 2005]
(27) A Gray code is a/an
(A) Binary weighted Code
(B) Arithmetic code
(A) Excess – 3 code (C) Code which exhibits a single bit change
between two successive codes
(B) Binary code
(D) Alphanumeric code
(C) BCD code
AD [IES – EC – 2005/2014]
(D) Hamming code
(28) Given (135) baseX (144) baseX (323)baseX .
AA [IES – EC – 1995] What is the value of base x ?
(23) In hexadecimal system, 7716 – 3B16 is
equal to (A) 5 (B) 3
(A) 3C00 (B) 6016 (C) 12 (D) 6
(C) 3C16 (D) 7316 AD [IES – EC – 2006]
(29) What is the Gray code word for the binary
AB [IES – EC – 1998] 101011 ?
(24) Match List – I with List – II and select the
correct answer using the codes given below (A) 101011 (B) 110101
the Lists (C) 011111 (D) 111110
List – I AB [IES – EC – 2006]
(A) 45 (30) Which of the following subtraction
(B) 90 operations results in F16 ?
(C) 180 1. (BA)16–(AB)16
(D) 210 2. (BA)16–(CB)16
List – II 3. (CB)16–(BC)16
1. 1 0 1 1 0 1 0 0 Select the correct answer using the code
given below:
2. 1 1 0 1 0 0 1 0
3. 0 1 0 1 1 0 1 0 (A) Only 1 and 2
4. 0 0 1 0 1 1 0 1 (B) Only 1 and 3
5. 1 0 1 0 1 0 0 0 (C) Only 2 and 3
Codes : (D) 1, 2 and 3
A B C D AC [IES – EC – 2008]
(A) 3 4 5 2 (31) (24)8 is expressed in Gray code as which one
of the following ?
(B) 4 3 1 2
(A) 11000 (B) 10100
(C) 4 3 5 2
(C) 11110 (D) 11111
(D) 3 4 2 1
AA [IES – EC – 2010]
AB [IES – EC – 2000] (32) The hexadecimal representation of 6578 is :
(25) The decimal equivalent of the number
(11C)17 is (A) 1 AF H (B) D 78 H
(A) 183 (B) 318 (C) D 71 H (D) 32 F H
(C) 268 (D) 269 AD [IES – EC – 2011]
(33) If 73x (in base x number system) is equal to
AB [IES – EC – 2001] 54y (in base y number system), the possible
(26) The number of digit 1 present in the binary values of x and y are :
representation of
Page 6 TARGATE EDUCATION GATE-( EC /EE)
Topic 01 - Number System
(A) 8 and 16 (B) 10 and 12 AD [GATE -EC - 2002]
(C) 9 and 13 (D) 8 and 11 (42) Which of the following represent 'E316'?
AA [IES – EC – 2012] (A) (CE)16 + (A2)16
(34) If (11X1Y)8 = (12C9)16 then the value X and (B) (1BC)16 – (DE)16
Y are
(C) (2BC)16 – (1DE)16
(A) 3 and 1 (B) 5 and 7
(D) (200)16–(11D)16
(C) 7 and 5 (D) 1 and 5
AD [GATE -EC - 2007]
AB [GATE - IN - 1999] (43) What is the addition of (–64)10 and (80)16 ?
(35) For a shaft encoder, the most appropriate 2 –
bit code is (A) (–16)10
(A) 11,10,01,00 (B) 11,10,00,01
(B) (16)10
(C) 01,10,11,00 (D) 01,00,11,10
(C) (1100000)2
AB [GATE - IN - 2011]
(36) The base of the number system for the (D) (01000000)2
addition operation 24 + 14 = 41 to be true is
AA [GATE -EC - 2005]
(A) 8 (B) 7 (44) If (2.3)base4 (1.2)base4 (Y)base4 ; What is the
(C) 6 (D) 5 value of Y ?
AC [GATE - IN - 1992] (A) 10.1 (B) 10.01
(37) The most suitable coding scheme for coding
(C) 10.2 (D) 1.02
the successive positions in an 8 position
digital shaft encoder is AC [IES – EC – 2012]
(45) Binary data is being represented in size of
(A) 00,001,010,011,100,101,110,111 byte and in 2’s complement form. The
(B) 00,010,100,110,001,011,101,111 number of 0’s present in representation of (-
127) DECIMAL IS
(C) 00,001,011,010,110,111,101,111
(A) 8 (B) 7
(D) 00,001,100,101,010,011,110,111
(C) 6 (D) 5
AB [GATE - EE - 2007]
AC [GATE - IN - 2006]
(38) The octal equivalent of the HEX number
(46) The binary representation of the decimal
AB.CD is
number 1.375 is
(A) 253.314 (B) 253.632
(C) 526.314 (D) 526.632 (A) 1.111 (B) 1.010
AD [IES – EC – 2015] (C) 1.011 (D) 1.001
(39) Given (125)R = (203)5 the value of radix R
AB [GATE – EC – 1993]
will be
(47) 2’s complement representation of a 16-bit
(A) 16 (B) 10 number (one sign bit and 15 magnitude bits)
if FFFF. Its magnitude in decimal
(C) 8 (D) 6 representation is :
AC [IES – EC – 1992]
(A) 0 (B) 1
(40) Which of the following is error correcting
code? (C) 32,767 (D) 65,535
(A) EBCDIC (B) GRAY AC [IES -EC - 2006]
(C) Hamming (D) ASCII (48) The greatest negative number which can be
stored in a computer that has 8 – bit word
AD [GATE -EC - 2000] length and uses 2 complement arithmetic is
(41) (FE35)16 XOR (CB15)16 is equal to
(A) -256 (B) -255
(A) (3320)16 (B) (FE35)16
(C) (FE50)16 (D) (3520)16
(C) -128 (D) -127
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DIGITAL ELECTRONICS
AB [GATE -EC - 2002]
(49) In signed magnitude representation, the
binary equivalent of 22.5625 is (the bit
before comma represents the sign)
(A) 0, 10110.1011
(B) 0, 10110.1001
(C) 1, 10101.1001
(D) 1, 10110.1001
AD [GATE -EC - 2007]
(50) Which one of the following is the correct
sequence of the numbers represented in the
series given below ?
(2)3, (10)4, (11)5, (14)6, (22)7, ….
(A) 2, 3, 4, 5, 6 …
(B) 2, 4, 6, 8, 10, ….
(C) 2, 4, 6, 10, 12, …
(D) 2, 4, 6, 10, 16, ….
AB [GATE – EC – 2005]
(51) Decimal 43 in Hexadecimal and BCD
number system is respectively.
(A) B2, 0100 0011
(B) 2B, 0100 0011
(C) 2B, 0011 0100
(D) B2, 0100 0100
-------0000-------
Page 8 TARGATE EDUCATION GATE-( EC /EE)
02
Boolean Algebra
AD [GATE – EC – 2014] AD [GATE -EC - 2007]
(1) For an n-variable Boolean function the (5) The Boolean expression
maximum number of prime implicants is Y ABCD ABC D ABCD ABC D
(A) 2 (n – 1) (B) n2 can be minimized to
(C) 2n (D) 2(n - 1)
(A) Y ABCD ABC ACD
AD [IES – EC – 2007]
(2) Consider the following statements : (B) Y ABCD BC D ABCD
1. Minimization using Karnaugh map may (C) Y ABC D BCD ABCD
not provide unique solution.
(D) Y ABC D BCD ABC D
2. Redundant grouping in Karnaugh map
may result in non-minimized solution. AA[GATE-EC-2015]
(6) The Boolean expression
3. Don't care states if used in Karnaugh
map for minimization, the minimal F( X ,Y , Z ) XYZ XYZ XYZ XYZ
solution is not obtained.
Converted into canonical product of sum
Which of the statements given above are (POS) form is :
correct ?
(A) ( X Y Z )( X Y Z )
(A) 1, 2 and 3
(B) 2 and 3 only ( X Y Z )( X Y Z )
(C) 1 and 3 only (B) ( X Y Z )( X Y Z )
(D) 1 and 2 only
( X Y Z )( X Y Z )
AB[GATE-IN-2003]
(3) The Karnaugh map for a four variable (C) ( X Y Z )( X Y Z )
Boolean function is given in below figure.
The correct Boolean sum of product is ( X Y Z )( X Y Z )
(D) ( X Y Z )( X Y Z )
( X Y Z )( X Y Z )
AB[GATE-EC-2015]
(7) A function of Boolean variables, X, Y and Z
is expressed in terms of the main-terms as
(A) PQRS+QS F(X, Y, Z) = (1, 2, 5, 6, 7)
Which one of the product of sums given
(B) PQRS+QS below is equal to the function F(X, Y, Z)?
(C) PQR +QS (A) ( X Y Z ) ( X Y Z )
(D) PQRS+Q (X Y Z )
ATRUE [GATE-IN-1994] (B) ( X Y Z ) ( X Y Z )
(4) Any Boolean function can be realized using
only NAND gates. (True/False) ( X Y Z)
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DIGITAL ELECTRONICS
4. To reduce the expression for making it
(C) ( X Y Z ) ( X Y Z ) feasible for hardware implementation.
(X Y Z) ( X Y Z )
Select the correct answer from the codes
(X Y Z) given below:
(D)
(X Y Z ) ( X Y Z) (A) 1 only (B) 2 only 3
(X Y Z ) ( X Y Z) (C) 3 only (D) 3 and 4
X Y Z AC [IES – EC – 1992]
(13) The expression for shaded area shown below
AD [GATE -EC - 2003] is :
(8) The number of distinct Boolean expressions
of 4 variables is
(A) 16 (B) 256
(C) 1024 (D) 65536
AB [GATE -EC - 1990]
(9) The number of Boolean functions that can be (A) A B + B C
generated by n variables is equal to:
(B) ABC ABC
n
(A) 2n (B) 22
(C) ABC ABC ABC
(C) 2n1 (D) 2n
(D) None of the above
AD [GATE-EE-2014]
(10) A state diagram of a logic gate which AA [IES – EE – 1995]
exhibits a delay in the output is shown in the (14) The switching circuit given in the figure can
figure, where X is the don’t care condition, be expressed in binary logic notation as
and Q is the output representing the state.
(A) L = (A + B) (C + D) E
The logic gate represented by the state (B) L = AB + CD + E
diagram is
(C) L = E + (A + B) (C + D)
(A) XOR (B) OR
(D) L = (AB + CD) E
(C) AND (D) NAND
AA [IES – EC – 1995]
AD [IES – EC – 1998] (15) What Boolean function does the following
(11) While obtaining minimal sum of products circuit represent?
expression
(A) All don’t cares are ignored
(B) All don’t cares are treated as logic ones
(C) All don’t cares are treated as logic zeros
(D) Only such don’t cares that aid
minimization are treated as logic ones
(A) A[ F ( B C ).( D E )]
AB [IES – EC – 2009]
(12) What are the ultimate purposes of (B) A[ F ( B C ). DE ]
minimizing logic expressions?
(C) A[ F ( BC DE )]
1. To get a small size expression.
(D) A[ F ( B C ) ( D E )]
2. To reduce the number of variables in
the given expression. AD
(16) The minimum Boolean for the following
3. To implement the function of the logic circuit is
expression with least hardware.
Page 10 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
(C)
(D)
(A) AB+AC+BC (B) A+BC
(C)A+B (D) A+B+C AA [GATE - IN - 2011]
AD [IES – EE – 2011] (20) For the Boolean expression
(17) The Boolean expression for the shaded area f abc a b c abc abc ab c, the
in the Venn diagram shown is: minimized product of Sum (POS) expression
is
(A) f (b c ).(a c )
(B) f (b c ).(a c )
(A) A B C (C) f (b c).(a c)
(B) AB A BC (D) f c abc
(C) ABC ABC AA [GATE - IN - 2008]
(21) The minimum sum of product form of the
(D) AB ABC Boolean expression
AB [IES – EC – 1996] Y P Q R S PQ R S PQ R S
(18) The Boolean expression for the shaded area PQ R S P Q RS P Q RS is
in the given Venn diagram is :
(A) Y PQ QS
(B) Y PQ QRS
(C) Y PQ QRS
(A) AB + BC + CA (D) Y Q S PQR
(B) AB C A BC A BC AA [IES – EC – 2010]
(22) The standard SOP expression for Boolean
(C) ABC A B C expression AB AC BC is
(D) A B C AB C (A) ABC ABC ABC ABC
AA [IES – EC – 1998] (B) ABC ABC ABC
(19) The Venn diagram representing the Boolean
expression A+ ( A .B) is (C) ABC ABC ABC
(D) ABC ABC ABC
(A) AD [IES – EC – 1999]
(23) Y = f (A, B) = M 0, 1, 2, 3 represent
(M is Max terms)
(A) NOR gate
(B) (B) NAND gate
(C) OR gate
(D) A situation where output is independent
of input.
www.targate.org Page 11
DIGITAL ELECTRONICS
AA [IES – EE – 1994] Y (0, 2,3, 4)
(24) There are four Boolean variables x1, x2 , x3
and x4. The following functions are defined AA [GATE – EE – 2015]
on sets of them : (28) f(A, B, C, D) = M(0, 1, 3, 4, 5, 7, 9,11,
12, 13, 14, 15) is an maxterm representation
f ( x3 , x2 , x1 ) (345) of a Boolean function f(A, B, C, D) where A
is the MSB and D is the LSB. The
g ( x4 , x3 , x2 ) (1,6,7)
equivalent minimized representation of this
h ( x4 , x3 , x2 , x1 ) fg . function is
Then h( ( x4 , x3 , x2 , x1 ) ) is (A) (A C D)(A B D)
(A) Zero (B) ACD ABD
(B) (3,12,13) (C) ACD ABCD ABCD
(C) (3,4,5,1,6,7) (D) (B C D)(A B C D)
(D) (3,12,15) (A B C D)
AA [GATE –EC/ EE - 2012] AA [IES – EC – 2007]
(25) In the sum of products function (29) When the Boolean function
f ( X , Y , Z ) (2,3, 4,5) , the prime F ( X 1 , X 2 , X 3 ) (0,1, 2, 3)
implicants are
(4,5,6,7)
(A) X Y X Y
is minimized, what does one get?
(B) X Y X Y Z X Y Z (A) 1 (B) 0
(C) X Y Z X Y Z X Y (C) X 1 (D) X 3
(D) X Y Z X Y Z XY Z XYZ AC [GATE - IN - 2006]
(30) Min – term(sum of products) expression for
AA [GATE - EE - 2014] a Boolean function is given as follows.
(26) The SOP (sum of products) form of a F ( A, B , C ) m (0,1, 2, 3, 5, 6) b
Boolean function is Σ(0,1,3,7,11), where
inputs are A,B,C,D (A is MSB, and D is Where A is the MSB and C is the LSB. The
LSB). The equivalent minimized expression minimized expression for the function is
of the function is (A) A ( B C )
(A) (B C)( A C)( A B)(C D) (B) ( A B ) C
(C) A ( B C )
(B) (B C)( A C)( A C)(C D)
(D) ABC
(C) (B C)( A C)( A C)(C D)
AB [GATE –EE/IN - 2012]
(D) (B C)( A B)( A B)(C D) (31) The output Y of a 2-bit comparator is logic 1
whenever the 2-bit input A is greater than
AB [GATE -EC - 2008] the 2-bit input B. The number of
(27) The Boolean functions can be expressed in combinations for which the output is logic 1,
canonical SOP (sum of products) and POS is :
(product of sums) form. For the function,
(A) 4 (B) 6
Y A BC
. , which are such two forms?
(C) 8 (D) 10
(A) Y (1, 2, 6, 7) and Y (0, 2, 4)
AD
(B) Y (1, 4, 5, 6, 7) and (32) According to De Morgan's second thermo
Y (0, 2, 3) (A) A NAND gate is always complimentary
to an AND gate
(C) Y (1, 2, 5, 6, 7) and Y (0,1, 3)
(B) A NAND gate equivalent to a bubbled
(D) Y (1, 2, 4, 5, 6, 7) and NAND gate
Page 12 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
(C) A NAND gate is equivalent to a bubbled AB [IES – EC – 1998]
AND gate (39) How many min terms (excluding redundant
terms) do the minimal switching function?
(D) A NAND gate is equivalent to a bubbled
OR gate. f (v, w, x, y, z) x yz Originally have?
AC (A) 16 (B) 20
(33) The minimum number of NAND gates
required to implement EXOR is equal to (C) 24 (D) 32
(A) Zero (B) 1 AC [GATE -EC - 2001]
(40) Which one of the following is equivalent to
(C) 4 (D) 7 the Boolean expression Y AB BC CA ?
AD (A) AB BC CA
(34) The function
F ABC ABC ABC ABC ; (B) (A B)(B C)(A C)
can be reduced to which one of the (C) (A B)(B C)(C A)
following?
(A) F = A (B) F = AB (D) (A B) (B C)(C A)
(C) F = ABC (D) F = B
AC
AD (41) Boolean function F ( x, y ) ( x z )( y z ) is
(35) The expression equal to which one of the following
( X Y )( X Y )( X Y ) expressions?
is equivalent to (A) ( x y)( y z)
(A) X Y (B) XY (B) ( x z )( y z)
(C) X Y (D) XY (C) ( x y)( x z )
AC (D) ( x y)( x z )
(36) What is Boolean expression for a gating
network that will have output 0 only, when AC [GATE -EC - 2009]
X = 1, Y = 1, Z = 1; X = 0, Y = 0, Z = 0 X = (42) Which of the following Boolean algebra
1, Y = 0, Z = 0? rules is correct?
(A) XYZ XYZ XYZ (A) A. A 1
(B) ( XYZ )( X Y Z )( X Y Z ) (B) A AB A B
(C) A A B A B
(C) ( X Y Z ) ( X Y Z )
(D) A( A B) B
( X Y Z )
AB [GATE - IN - 1998]
(D) XY Z XYZ XYZ (43) The minimal sum of products form of f =
AC [IES – EC – 1991]
ABCD ABC BCD ABC is :
(37) The operation x y represents (A) AC BD (B) AC CD
(A) x – y (B) xy xy (C) AC BD (D) AB CD
(C) xy x y (D) x y AA [GATE -EC - 2012]
(44) The correct expression is :
AD [GATE -EC - 2002]
(38) With 4 Boolean variables, how many (A) AB AB AB ( A B )
Boolean expressions can be formed?
(A) 16 (B) AB AB AB( A B)
(B) 256 (C) AB AB AB( A B )
(C) 1024 (1K)
(D) AB AB AB ( A B )
(D) 64K (64 1024)
www.targate.org Page 13
DIGITAL ELECTRONICS
AC [GATE – EE/EC - 2013] Consider the Boolean function F (w, x, y, z)
(45) A bulb in a staircase has two switches, one = wy + xy + wxyz wxy xz x y z which
switch being at the ground floor and the
one of the following is the complete set of
other one at the first floor. The bulb can be
essential prime implicants?
turned ON and also can be turned OFF by
anyone of the switches irrespective of the (A) w, y , xz , x z (B) w, y, xz
state of the other switch. The logic of
switching of the bulb resembles (C) y, x y z (D) y, xz , xz
(A) An AND gate
AD
(B) An OR gate (49) Four logical expressions are given below :
(C) An XOR gate
1. A. B .C . D . E . F .G . H
(D) A NAND gate
2. AB .CD . EF .G H
AC [GATE -EC - 2011]
(46) Match List-I with List-II and select the 3. A B C D E F G H
correct answer using the code given below
the lists : 4. ( A B )(C D)( E F )(G H )
List I List II Two of these expressions are equal. They are
A. AND gate 1. Boolean complementation (A) 1 and 2 (B) 3 and 4
B. OR gate 2. Boolean addition (C) 1 and 3 (D) 2 and 4
C. Not gate 3. Boolean multiplication
AC
Codes: (50) What is the simplified form of the Boolean
expression
A B C
(A) 3 1 2 T ( X Y )( X Y )( X Y )?
(B) 1 2 3 (A) X Y (B) X Y
(C) 3 2 1
(C) XY (D) X Y
(D) 1 3 2
AC [IES – EC – 1991]
AA [GATE - EE - 2015]
(47) Consider the following Sum of products (51) The terms AB+AC+B C reduce to
expression, F. (A) AB + CA (B) AC + BC
F ABC AB C ABC ABC ABC (C) AC + B C (D) AB + BC
The equivalent Product of Sums expression
AC [GATE -EC - 2005]
is
(52) Which one of the following is the dual form
(A) F (A B C)(A B C) of the Boolean Identity?
(A B C) A B A C ( A C )( A B)?
(B) F (A B C)(A B C) (A) AB AC AC AB
(A B C) (B) ( A B) ( A C ) ( A C )( A B)
(C) F (A B C)(A B C) (C) ( A B)( A C) AC AB
(A B C) (D) AB AC AB AC BC
(D) F (A B C)(A B C) AB [GATE -EC - 2006]
(53) If A and B are Boolean variables, then what
(A B C)
is (A B) (A B) equal to ?
AD [GATE – EC – 2014]
(A) B (B) A
(48) The simplified Boolean expression from the
K-MAP (C) A+B (D) AB
Page 14 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
AA [IES -EC - 2008] AD [GATE -EC - 2004]
(54) Which one of the following statements is not (58) A Boolean function f of two variables x and
correct? y is defined as follows :
(A) X XY X f(0, 0) = f(0, 1) = f(1, 1) = 1; f(1, 0) = 0
(B) X ( X Y ) XY Assuming complements of x and y are not
available, a minimum cost solution for
(C) XY X Y X realizing f using only 2-input NOR gates and
(D) ZX Z XY ZX ZY 2-input OR gates (each having unit cost)
would have a total cost of
AC [IES -EC - 2012]
(A) 1 unit (B) 4 unit
(55) The Boolean equation
(C) 3 unit (D) 2 unit
X [( A B)( B C)]B cab be simplified
to AA[IES -EC - 2006]
(59) The Boolean expression for the truth table
(A) X AB (B) X AB
shown is :
(C) X AB (D) X AB A B C F
0 0 0 0
Common Data for the Next Two Questions
0 0 1 0
The following Karnaugh map represents a function 0 1 0 0
F, 0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
(A) B( A C )( A C )
AB [GATE - EE - 2010]
(B) B( A C )( A C )
(56) A minimized form of the function F is
(A) F X Y YZ (C) B( A C )( A C )
(B) F XY YZ
(D) B( A C )( A C )
(C) F XY Y Z
AD [GATE – EC – 2014]
(D) F XY Y Z
(60) The digital logic shown in the figure satisfies
AD [GATE - EE -2010 ] the given state diagram when Q1 is
(57) Which of the following circuits is a connected to input A of the XOR gate.
realization of the above function F ? Suppose the XOR gate is replaced an by an
XNOR gate. Which one of the following
(A)
options preserves the state diagram?
(B)
(C)
(D)
www.targate.org Page 15
DIGITAL ELECTRONICS
Suppose the XOR gate is replaced by an (C) 2 3 4 1
XNOR gate. Which one of the following
(D) 3 2 1 4
options preserves the state diagram?
(A) Input A is connected to Q2 AC [IES – EE – 2001]
(65) In Boolean Algebra, if F = (A + B) ( A C ),
(B) Input A is connected to Q2
then
(C) Input A is connected to Q1 and S is
complemented (A) F AB AC
(D) Input A is connected to Q1 (B) F AB AB
AB [GATE – EC – 2015] (C) F AC AB
(61) A 3 input majority gate is defined by the
(D) F AA AB
logic function M(a, b, c) = ab + bc + ca.
Which one of the following gates is AD [IES – EE – 2003]
represented by the function (66) The simplified form of a logic function
M M(a, b, c)M a, b, c , c ? Y ( AB)( AB ) is :
(A) 3-Input NAND gate (A) A + B (B) A B
(B) 3-Input XOR gate (C) A B (D) A B A B
(C) 3-Input NOR gate AC [IES – EE – 2003]
(67) The reduced form of the Boolean expression
(D) 3-Input XNOR gate
A[ B C ( AB AC )] is :
AB [IES – EC – 2006]
(62) What is the Boolean expression A B (A) A B (B) AB
equivalent to ?
(C) AB (D) AB B C
(A) AB A B (B) A B A B
AD [IES – EE – 2005]
(C) B (D) A (68) Which of the following statements is
correct?
AA [GATE – EC – 2014]
(63) The Boolean expression (A) X X Y X
X Y X Y XY X simplifi (B) X ( X Y ) XY
es to (C) X X Y XY
(A) X (B) Y (D) ZX Z XY ZX ZY
(C) XY (D) X + Y
AD [IES – EE – 2005]
AA [IES – EE – 1995] (69) The Boolean expression Y Z X Z X Y is
(64) Match List I with List II and select the logically equivalent to
correct answer using the codes given below
(A) YZ X
the lists :
List I List II (B) YZX X Y Z
(Boolean identity) (Boolean expression) (C) YZ XZ XY
A. Y .(Y Z ) 1. Y (D) X Y Z X Y Z XY Z X Y Z
B. Y X . Z 2. (Y X )(Y Z ) AC [IES – EE – 2008]
(70) Match List-I with List-II and select the
C. Y Z 3. Y Z ZY
correct answer using the code given the
D. X Y . Z 4. (X +Y )(X +Z ) Lists:
Codes: List – I
A B C D (Expression-I)
(A) 1 2 3 4 A. ABC + AB C + ABC
(B) 2 3 1 4 B. A B C A B C BC
Page 16 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
C. A B C A B C ABC ABC X Y Z
0 0 1
D. AB AB ABC 0 1 0
List-II 1 0 1
(Expression-II) 1 1 0
1. A BC (A) ( X Y )( X Y )
2. A( B C )
(B) ( X Y )( X Y )
3. BC (C) ( X )( X Y )
4. AB BC AC (D) None of the above
Codes:
AC [IES – EC – 1992]
A B C D
(75) What is dual of X XY X Y
(A) 2 1 4 3
(B) 4 3 2 1 (A) X+Y=XY
(C) 2 3 4 1 (B) X XY XY
(D) 4 1 2 3 (C) X ( X Y ) XY
AA [IES – EE – 2008]
(D) X ( X Y ) X Y
(71) The Boolean expression A.B A.B is
logically equivalent to which of the AA [IES – EC – 1993]
following? (76) The number of switching functions of 3
variables is
1. ( A B ).( A B ) (A) 8 (B) 64
2. ( A B ).( A B ) (C) 128 (D) 256
AA&B [IES – EC – 1997]
3. ( A B ).( A B )
(77) In a digital system, there are three inputs A,
B and C. The output should be high when at
4. ( A.B ).( A.B ) least two inputs are high. The Boolean
Select the correct answer using the code expression for the output is :
given below : (A) AB+BC+AC
(A) 1 and 2 only (B) 2 and 3 only (B) ABC ABC ACB ABC
(C) 1 and 3 only (D) None of these (C) ABC ABC ACB
AD [IES – EC – 1991] (D) AB BC AC
(72) If X, Y and Z are Boolean variables, then the
AA [IES – EC – 1998]
expression
(78) The complements of the Boolean expression
X(X+XY) Z(X+Y+Z) is equal to
AB ( BC AC ) is :
(A) X XY (B) X Y Z (A) ( A B ) ( B C )( A C )
(C) XYZ (D) XZ
(B) ( A.B ) ( BC )( AC )
AD [IES – EC – 1992]
(73) What is dual of A + [B+ (AC)] +D (C) ( A B ).( B C )( A C )
(A) A+ [B (A+C)] +D (D) ( A B).( B C)( A C )
(B) A [B+AC] D AA [IES – EC – 1999]
(79) The Boolean theorem
(C) A+ [B (A+C)] D
AB AC BC AB AC Corresponds
(D) A [B (A+C)] D to
AB [IES – EC – 1992] (A) ( A B).( A C).(B C)
(74) The product – of – sum expression for given
truth table is ( A B).( A C )
www.targate.org Page 17
DIGITAL ELECTRONICS
(B) AB AC BC AB BC (A) Z A.B.C A.B.C A.B .C
(C) AB AC BC AB BC A.B.C
(D) ( A B).( A C ).(B C) (B) Z A.B.C A.B .C A.B .C A.B .C
AB AC (C) Z A.B .C A.B .C A.B .C
AC [IES – EC – 2002] A.B.C
(80) Consider the Boolean expression
(D) Z A.B.C A.B.C A.B .C
X ABCD ABCD ABCD AC BD
A.B.C
The simplified form of X is
AC [IES – EC – 2005]
(A) C D (B) BC
(85) AB AC (A C)(A B)
(C) CD (D) BC Which one of the following is the dual form
AB [IES – EC – 2003] of the Boolean identity given above.
(81) Match List I with List II and select the (A) AB AC AC AB
correct answer using the codes given below (B) (A B)(A C) (A C)(A B)
the Lists :
(C) (A B)(A C) AC AB
List I List II
(D) AB AC AB AC BC
A. A B 0 1. A B
AD [IES – EC – 2006]
B. A B 0 2. A = B (86) What does the Boolean expression
AD ABCD ACD AB A B on
minimization result into ?
C. A. B 0 3. A = 1 OR B = 1
(A) A + D (B) AD A
D. A B 1 4. A = 1 OR B = 0 (C) AD (D) A D
Codes: AC [IES – EC – 2008]
A B C D (87) The Boolean function A + BC is a reduced
(A) 3 2 1 4 form of which one of the following?
(B) 2 3 4 1 (A) AB + BC
(C) 3 2 4 1
(D) 2 3 1 4 (B) A B A B C
AC [IES – EC – 2003] (C) ( A B ).( A C )
(82) The Boolean expression (D) None of these
(A B)(A C)(B C) simplifies to AB [IES – EC – 2010]
(88) The Boolean expression
(A) (A B)C (B) (A B)C
A B C A B C A B C ABC
(C) (A B)C (D) (A B)C
reduces to :
AA [IES – EC – 2003] (A) A (B) B
(83) The minimum number of NAND gates
required to implement the Boolean junction (C) C (D) A+B+C
A AB ABC is equal to AD [IES – EC – 2010]
(A) Zero (B) 1 (89) The complement of the expression
(C) 4 (D) 7 Y ABC ABC ABC ABC is
AC [IES – EC – 2004] (A) ( A B )( A C )
(84) A, B and C are three Boolean variables. (B) ( A B )( A C )
Which one of the following Boolean
expressions cannot be minimized any (C) ( A B )( A C )
further?
(D) ( A B )( A C )
Page 18 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
AB [IES – EC – 2011] The high and the low levels of the output of
(90) If the Boolean expression PQ QR PR is the digital circuit are 5V and 0V,
respectively. Which one of the following
minimized, the expression becomes
figures shows the correct variation of the
(A) P Q QR (B) P Q PR average value of the output voltage of τ for
0 t (T / 2) ?
(C) QR PR (D) P Q QR PR
AB [IES – EC – 2012]
(91) Simplified form of the logic expression
( A B C )( A B C )( A B C ) (A)
(A) AB C (B) A BC
(C) A (D) AB C
AB [GATE - IN - 1994]
(92) The Boolean expression A B C is equal
to
(B)
(A) A B C (B) A.B .C
(C) A B C (D) A.( B C )
AA [GATE - IN - 2000]
(93) The expression X A B is equivalent to
(A) A B (B) AB A (C)
(C) A B (D) AB
AD [GATE - IN - 2004]
(94) The simplest form of the Boolean expression
ABC D ABC D AB C D ABCD is
(D)
(A) AD (B) BC
(C) A B (D) AB
AC [GATE - IN - 2007]
(95) Two square waves of equal period T, but AB [GATE - EE - 2003]
with a time delay τ are applied to a digital (96) The Boolean expression
circuit whose truth table is shown in the X Y Z XY Z XY Z X Y Z XYZ can
following figure. be simplified to
(A) X Z X Z YZ
(B) XZ Y Z Y Z
(C) X Y YZ XZ
(D) XY Y Z X Z
AA [GATE - EE - 2004]
(97) The simplified form of the Boolean
expression
Y = ( A.BC D )( A.D B.C.) can be
written as
(A) A. D B .C . D
(B) AD B .C .D
(C) ( A D)( B.C D)
(D) A. D BC .D .
www.targate.org Page 19
DIGITAL ELECTRONICS
AD [GATE -EC - 1999] Y ABCD ABC D ABCD ABC D
(98) The Logical expression y A AB is (A) Y ABCD ABC ACD
equivalent to
(B) Y ABC D BC D ABC D
(A) y = AB (B) y = AB
(C) Y ABC D BCD ABCD
(C) y A B (D) y A B
(D) Y ABC D BCD ABC D
AB [GATE -EC - 2007]
AD [GATE -EC - 2009]
(99) The Boolean function Y = AB + CD is to be
(104) If X = 1 in the logic equation
realized using only 2-input NAND gates.
The minimum number of gates required is [ X Z{Y (Z XY )}]{X Z ( X Y )} 1,
(A) 2 (B) 3 then
(C) 4 (D) 5 (A) Y = Z (B) Y = Z
(C) Z = 1 (D) Z = 0
AA [GATE -EC - 1999]
(100) The minimized form of the logical AC [GATE -EC - 2000]
expression (105) Karnaugh map is used to
( A B C A BC A B C AB C) is (A) Minimize the number of flip flops in a
digital circuit.
(A) A C B C A B (B) Minimize the number of gates only in a
digital circuit
(B) A C BC A B (C) Minimize the number of gates and fan in
of a digital circuit
(C) A C BC A B (D) Design gates
(D) A C BC A B AA [GATE – EC – 2005]
(106) The number of product terms in the
AA [GATE -EC - 2003] minimized sum-of-product expression
(101) If the functions W, X, Y and Z are as obtained through the following k-map is
follows (where, “d” denotes don’t care states)
W R PQ RS
X PQ R S P Q R S P Q R S
Y RS PR P Q P Q (A) 2 (B) 3
(C) 4 (D) 5
Z R S PQ P Q R P QS
AC [IES – EC – 1997]
(A) W Z , X Z
(107) Consider the Karnaugh Map given below
(B) W Z , X Y The function represented by this map can be
(C) W Y simplified to the minimal form as
(D) W Y Z
AD [GATE -EC - 2004]
(102) The Boolean expression AC + BC is
equivalent to
(A) A C + B C + AC
(A) X1 X 2 X 4 X 2 X 4 X 1 X 3
(B) BC AC BC A C B
(B) X 1 X 2 X 4 X 2 X 4 X 1 X 2 X 3 X 4
(C) AC BC BC ABC
(C) X 2 X 4 X 2 X 4 X 1 X 3
(D) ABC ABC ABC ABC
(D) X 1 X 2 X 4 X 1 X 2 X 3 X 4
AD [GATE -EC -2007 ]
(103) The Boolean expression X1 X 2
Page 20 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
AA AB [IES – EE – 2010]
(108) map given in the figure is (112)
For a function F, the Karnaugh map is
shown above. Then minimal representation
of F is
(A) AC AD ABC (A) AB C (B) C AB
(B) AB AD ABC (C) A B C (D) A BC
(C) AC ACD ABC BCD AA [IES – EC – 2002]
(113) The minimized expression for the given K
(D) AB CD AD map(A: don’t care) is :
AB [IES – EC – 2007]
(109) By inspecting the Karnaugh map plot of the
switching function
F ( X 1 X 2 X 3 ) (1, 3, 6, 7)
One can say that the redundant prime
implicant is
(A) X1. X 3 (B) X 2 X 3 (A) A BC (B) B AC
(C) X 1 . X 2 (D) X 3 (C) C AB (D) A B C
AA [GATE -EC - 1998] AB [IES – EC – 2005]
(110) The K-map for a Boolean function is shown (114) What is the minimized logic expression
in figure. The number of essential prime corresponding to the given Karnaugh Map?
implicants for this function is :
(A) 4 (B) 5 (A) x z
(C) 6 (D) 8
(B) w x y w y z w y z w x y
AD [IES – EC – 1996]
(111) The Minimized expression for the given K- (C) w x y w y z w y z w x y
Map is (X: don’t care)
(D) xz w y z w x y w x y w y z
AD[GATE-IN-2007]
(115) A logic circuit implements the Boolean
function F X Y X Y Z . It is found that
the input combination X = Y = 1 can never
(A) CB BD CD occur. Taking this into account, a simplified
(B) AB C B B C expression for F is given by
(A) X Y.Z (B) X + Z
(C) C B AC B C
(C) X – Z (D) Y X.Z
(D) CB BD C B
www.targate.org Page 21
DIGITAL ELECTRONICS
S4AD [GATE–S4–EC–2016] (A) AB ABC ABC
(116) The logic functionality realized by the
circuit shown below is : (B) AC AB ABC
(C) AC AB ABC
(D) ABC AC ABC
AD [GATE–S1–EE–2017]
(122) The output expression for the Karnaugh map
shown below is
(A) OR (B) XOR
(C) NAND (D) AND
S4AA [GATE–S4–EC–2016]
(117) The minimum number of 2-input NAND
gates required to implement a 2-input XOR
gate is :
(A) 4 (B) 5
(C) 6 (D) 7 (A) BD BCD
S8AB [GATE–S8–EE–2016] (B) BD AB
(118) The output expression for the Karnaugh map (C) BD ABC
shown below is :
(D) BD ABC
AC [GATE – EC – 2018]
(123) A function F(A, B, C) defined by three
Boolean variables A, B and C when
expressed as sum of products is given by
(A) A B (B) A C F A B C A B C A B C
(C) A C (D) A C where, A , B , and C are the complements of
the respective variables. The product of
S4AB [GATE–S4–IN–2016] sums (POS) form of the function F is
(119) In the digital circuit given below, F is
(A) F ( A B C ) ( A B C ) ( A B C )
(B) F ( A B C ) ( A B C ) ( A B C )
(C) F ( A B C ) ( A B C ) ( A B C )
( A B C ) ( A B C )
(D) F ( A B C ) ( A B C ) ( A B C )
(A) XY + YZ (B) XY + YZ ( A B C ) ( A B C )
(C) XY + YZ (D) XZ+Y
AB [GATE – EE – 2018]
AA [GATE–S1–EE–2017] (124) Digital input signals , , with as the
(120) The Boolean expression AB AC BC MSB and as the LSB are used to realize
simplifies to the Boolean function F m0 m2
(A) BC AC (B) AB AC B m3 m5 m7 , where m i denotes the i th
(C) AB AC (D) AB + BC minterm. In addition, has a don’t care for
m1 . The simplified expression for is given
AB [GATE–S1–EC–2017] by
(121) Which one of the following gives the
simplified sum of products expression for (A) AC BC AC
the Boolean function
(B) A C
F m0 m2 m3 m5 where m0 , m2 , m3
and m5 are minterms corresponding to the (C) C A
inputs A, B and C with A as the MSB and C (D) AC BC AC
as the LSB?
Page 22 TARGATE EDUCATION GATE-( EC /EE)
Topic 02 - Boolean Algebra
AB [GATE – IN – 2018]
(125) The product of sum expression of a Boolean
function F(A, B, C) of three variables is
given by
F ( A, B, C ) ( A B C ) ( A B C )
(A B C) (A B C)
The canonical sum of product expression of
F(A, B, C) is given by
(A) ABC ABC ABC ABC
(B) ABC ABC ABC ABC
(C) ABC ABC ABC ABC
(D) ABC ABC ABC ABC
AB [GATE-EE-2019]
(126) The output expression for the Karnaugh map
shown below is :
(A) QR S (B) QR S
(C) QR S (D) QR S
A256 [GATE-IN-2019]
(127) The total number of Boolean functions with
distinct truth-tables that can be defined over
3 Boolean variables is _____ .
-------0000-------
www.targate.org Page 23
03
Logic GATES
AB&D [IES – EE – 1992] AA [IES – EC – 2001]
(1) Which of the following statement is true? (5) In the negative logic system,
(A) IC's area always linear (A) The more negative of the two logic
levels represents a logic '1' state.
(B) Digital circuits are linear circuits
(C) AND gate is a logic circuit whose (B) The more negative of the two logic
output is equal to its highest input levels represents a logic '0' state.
(D) In a four - input AND circuit, all input (C) All input and output voltage levels are
must be UP for the output to be UP. negative.
AA-ii,B-iv,C-iii,D-i [GATE - IN - 1995] (D) The output is always complement of the
(2) This question contains 4 sub-sections of intended logic function.
matching the pairs. Indicate the answer as AA [GATE – EC – 2014]
follows : (6) The output F in the digital logic circuit
If A and B are the inputs to a logic gate, then shown in the figure is
match the logic with its output
(a) NAND (i) AB
(b) NOR (ii) AB
(c) XNOR (iii) AB AB
(d) AND (iv) A B
(A) F XYZ X Y Z
AA [IES – EE – 2012] (B) F XY Z XY Z
(3) Statement (I) : XOR gate is not a universal
gate (C) F X Y Z XYZ
Statement (II) : It is not possible to realize (D) F X YZ XYZ
any Boolean function using XOR gates only
AC [GATE-EE-2014]
(A) Both (I) and (II) is true and R is the (7) Which of the following logic circuits is a
correct explanation of A realization of the function F whose
(B) Both (I) and (II) is true but R is NOT Karnaugh map is shown in figure
the correct explanation of A
(C) (I) is true but (II) is false
(D) (I) is false but (II) is true
AB [IES – EC – 1995]
(4) Which one of the following sets of gates are
best suited for parity checking and party (A)
generation?
(A) AND, OR, NOT gates
(B) X – OR, X – NOR gates
(B)
(C) NAND gates
(D) NOR gates
Page 24 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
(A) XY YX
(C) (B) (X Y)XY
(C) (XY)XY
(D) XY XY X Y
(D) AA [GATE - EE – 2004/IES – EE - 2010]
(11) The digital circuit using two inverters shown
in Fig. will act as
AA [GATE – EC – 2015]
(8) In the figure shown, the output Y is required
to be Y AB CD . The gates G1 and G2 (A) A bistable multi-vibrator
must be, respectively,
(B) An astable multi-vibrator
(C) A Monostable multi-vibrator
(D) An oscillator
AD[GATE-EC-2001]
(A) NOR, OR (12) In the figure, the LED
(B) OR, NAND
(C) NAND, OR
(D) AND, NAND
AC [GATE – EC – 2015]
(9) A universal logic gate can implement any
Boolean function by connecting sufficient
number of them appropriately. Three gates (A) emits light when both S1 and S 2 are
are shown. closed.
(B) emits light when both S1 and S 2 are
open.
(C) emits light when only of S1 and S 2 is
closed.
(D) does not emit light, irrespective of the
switch positions.
AC[GATE-EC-2015]
(13) In the circuit shown, diodes D1 ,D2 and D3
Which one of the following statements is are ideal, and the inputs E1 , E 2 and E3 are '0
TRUE?
V' for logic '0' and '10V' for logic '1'. What
(A) Gate 1 is a universal gate. logic gate does the circuit represent?
(B) Gate 2 is a universal gate.
(C) Gate 3 is a universal gate.
(D) None of the gates shown is a universal
gate
AA [GATE – IN – 2015]
(10) The logic evaluated by the circuit at the
output is
(A) 3 input OR gate
(B) 3 input NOR gate
(C) 3 input AND gate
(D) 3 input XOR gate
www.targate.org Page 25
DIGITAL ELECTRONICS
A*[GATE-IN-1998] (A) ( AB AB)C
(14) For the logic circuit shown in figure write
the expression for X, Y and Z. (B) ( AB AB)C
(C) ABC
(D) A B C
AB [IES – EE – 1998]
(18) The output X of the circuit shown in the
figure will be
AB [IES – EC – 2006/2010]
(15) The circuit given in the figure is to be used
to implement the function Z = f(A,B) =
A B .What values should be selected for I
and J?
(A) AB (B) AB
(C) AB (D) AB
AC [IES – EE – 1999]
(19) Which one of the gate labelled 1, 2, 3 and 4
in the network shown in the figure is
(A) I = 0, J = B (B) I = 1, J = B redundant?
(C) I = B, J = 1 (D) I = B , J = 0
AA [IES – EE – 1996]
(16) Which of the following is the truth table of
the given logic circuit ?
(A) 1 (B) 2
(C) 3 (D) 4
AB [IES – EE – 2000]
(20) The circuit shown in the given figure is
(A) (B
(C) (D)
AD [GATE – IN – 1995]
(17) A combinational circuit has input A, B and
C and its Karnaugh Map is a as shown. The (A) an AND gate (B) an OR gate
output of the circuit is given by (C) a XOR gate (D) a NAND gate
AB [IES – EE – 2002]
(21) The Boolean expression for the output Y in
the logic circuit is
Page 26 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
(A) A B C (B) A B C A B C D
(A) 3 1 4 2
(C) A B C (D) A B C (B) 2 1 4 3
AA [IES – EE – 2009] (C) 3 4 1 3
(22) Which one of the following is the correct (D) 2 4 1 3
output ( f ) of the below circuit?
AD [IES – EE – 2011]
(25) For logic circuit shown, the required inputs
A, B and C to make the output X = 1 are,
respectively,
(A) ( a b )( c d )
(B) ( a b )( c d )
(C) ( a b )( c d ) (A) 1, 0 and 1 (B) 0, 0 and 1
(C) 1, 1 and 1 (D) 0, 1 and 1
(D) ( a b )( a d )
AD [IES – EC – 2000]
AA [IES – EE – 2010] (26) The circuit shown in figure realizes the
(23) The circuit shown below generates the function
function of
(A) ( A B C )( DE )
(A) x y (B) 0 (B) ( A ( B C )( DE )
(C) x y yx yx (D) x. y (C) ( A B C )( DE )
AD [IES – EE – 2010]
(D) ( A B C )( DE )
(24) Match List I with List II and select the
correct answer using the code given below AA [IES – EC – 1991]
the lists : (27) The Boolean function F=AB+CD+E can be
List-I realized as
(A)
A.
B.
C.
(B)
D.
List-II
1. AB
2. AB (C)
3. A + B
4. A B
Codes :
www.targate.org Page 27
DIGITAL ELECTRONICS
(D)
AA [IES – EC – 1992]
(28) The minimized version for the logic circuit
shown in the figure is:
(A)
(B)
AA [IES – EC – 1995]
(31) The output Y for the logic circuit shown in
(C) the given figure is
(D)
AA [IES – EC – 1992/1993/1996/2000]
(29) Which of the following is a coincidence
logic circuit?
(A) (A) AB (B) A B
(C) AB (D) A B
AD [IES – EC – 1995]
(B) (32) The logic circuit shown in the given figure
can be minimized to
(C)
(A)
(B)
(D)
(C)
AB [IES – EC – 1994] (D)
(30) The output (X) wave form for the below
combination circuit for the inputs at A and B AB [IES – EC – 1996]
(waveform shown in the figure) will be. (33) The minimized logic circuit for the circuit
shown in fig. is
Page 28 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
AD [IES – EC – 1998]
(A) (37) The circuit shown in Fig. is equivalent to
(B)
(C)
(D)
AB [IES – EC – 1996] (A)
(34) In the figure shown X2, X1, X0 will be 1’s
complement of A2 A1 A0 if
(B)
(C)
(A) Y = 0
(B) Y =1 (D)
(C) Y A0 A1 A2
(D) Y=A0 = A1 = A2 AA [IES – EC – 1998]
AA [IES – EC – 1996] (38) The output Y of the circuit shown in the
(35) The circuit shown in the following figure figure is
realizes the function
(A) (A+B) C+DE
(B) AB+C (D+E)
(A) ( A B )C DE (C) (A+B) C+D+E
(D) (AB+C) DE
(B) ( A B )C D E
AD [IES – EC – 1999]
(C) AB C DE (39) The given figure shows a NAND gate with
(D) AB C ( D E ) input waveforms A and B.
AC [IES – EC – 2003/2007] The correct output waveform X of the gate
(36) The circuit shown in the figure is is :
functionally equivalent to
(A) NOR gate
(B) OR gate
(C) EX-OR gate
(D) NAND gate
www.targate.org Page 29
DIGITAL ELECTRONICS
AC [IES – EC – 1999] AC [IES – EC – 2001]
(40) The input waveform Vi and the output (43) The circuit shown in the given figure is :
waveform V0 of a Schmitt NAND are shown
in the given figures. The duty cycle of the
output waveform will be.
(A) An adder circuit
(B) A subtractor circuit
(C) A comparator circuit
(D) A parity generator circuit
AC [IES – EC – 2002]
(44) Consider the following circuits (Assume all
(A) 100% (B) 85.5% gates to have a finite propagation delay)
(C) 72.2% (D) 25%
Which of these circuits generate a periodic
AA [IES – EC – 2000] square wave output?
(41) Which one of the following figures
represents the coincidence logic?
1.
(A)
(B) 2.
(C)
3.
(D)
4.
AA [IES – EC – 2000]
(42) The logic operations of two combinational
circuits given in figure – I and figure - II are
(A) 1 and 2
(B) 3 and 4
(C) 2, 3 and 4
(D) 1, 2, 3 and 4
AB [IES – EC – 2007]
(45) For the logic circuit given below, what is the
(A) Entirely different (B) identical simplified Boolean function?
(C) Complementary (D) Dual
Page 30 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
(C) 2, 3 and 5 only
(D) 2 and 4 only
AB [IES – EC – 2011]
(49) Consider the following gate network:
(A) X = AB + C
(B) X = BC + A
(C) X = AB + AC
(D) X = AC + B
AA [IES – EC – 2007]
(46) The black box in the figure below, consists Which one of the following gates is
of a minimum complexity circuit that uses redundant?
only AND, OR and NOT gates.
(A) Gate No.1 (B) Gate No. 2
(C) Gate No. 3 (D) Gate No. 4
AB [GATE - IN - 1992]
(50) In the digital circuit shown below, the output
The function f ( X , Y , Z ) 1 whenever X , Y
f is found to be logic 1 when A is logic ‘0’.
are different and 0 otherwise. In addition the The values of B and C are
3 inputs X , Y , Z are never all the same
value.
Which one of the following equations leads
to the correct design for the minimum
complexity circuit?
(A) X 'Y XY '
(A) B = 1, C = 0
(B) X YZ '
(C) X 'Y ' Z XY ' Z (B) B = 0, C = 0 or 1
(D) XY Y ' Z Z ' (C) B = 1, C = 1
(D) Indeterminate
AA [IES – EC – 2010]
(47) The output X of the below logic circuit is AA [GATE - EE - 1996]
(51) The Boolean expression for the output of the
logic circuit shown in figure is
(A) AB CD EF (A) Y A B AB C
(B) AB CD EF (B) Y A B AB C
(C) ( A. B).(C D ).( E F )
(C) Y A B AB C
(D) A B . C D . E F (D) Y A B A B C
AD [IES – EC – 2011]
AB [GATE - EE - 1999]
(48) Which of the following are universal gates ?
1. AND (52) The logic function f = x. y x. y is the
2. NAND same as
3. OR (A) f ( x y )( x y )
4. NOR
5. NOT
(B) f x y ( x y)
(A) 1, 2, 3, 4 and 5
(C) f x. y . x. y
(B) 1, 3 and 4 only (D) None of (A), (B), (C)
www.targate.org Page 31
DIGITAL ELECTRONICS
AB [GATE - EE - 2002] (A) S is always with zero or odd
(53) For the circuit shown in Fig. the Boolean (B) S is always either zero or even
expression for the output Y in terms of
inputs P, Q, R and S is (C) S = 1 only if the sum of A, B, C and D
is even
(D) S = 1 only if the sum of A, B, C and D
is odd
AD [GATE – EE/EC – 2001/1994]
(57) The output of a logic gate is 1 when all its
inputs are at logic 0. The gate is either
(A) A NAND or an EX – OR gate
(A) P Q R S
(B) AN OR an EX – OR gate
(B) P Q R S
(C) AN AND of an EX – OR gate
(C) ( P Q )( R S ) (D) A NOR or an EX – NOR gate
(D) ( P Q )( R S )
AC [IES – EC –2004/ 2007/2011/2012]
AD [GATE - EE - 2004] (58) Assume that only x and y logic inputs are
(54) A digital circuit which compares two available, and their complements x and y
numbers A3 A2 A1 A0 , B3 B2 B1B0 is shown in are not available. What is the minimum
Fig. To get output Y = 0, choose one pair of number of 2-input NAND gates required to
correct input numbers implement x y ?
(A) 2 (B) 3
(C) 4 (D) 5
AD [IES – EC – 2011]
(59) The logic function;
Out = ab bc ca
defines:
1. The output of a 3-inputs XOR gate
2. The output of a 3-inputs majority gate
3. The sum output of a full adder
(A) 1010, 1010 (B) 0101, 0101
4. The carry output of a full adder
(C) 0010, 0010 (D) 1010, 1011
(A) 1 and 2 (B) 2 and 3
AD [GATE - EE - 2005] (C) 3 and 4 (D) 2 and 4
(55) In the figure, as long as X 1 1 and
A BC [GATE -EC - 1993]
X 2 1, the output Q remains (60) Boolean expression for the output of XNOR
(equivalence) logic gate with inputs A and B
is :
(A) A B A B
(A) at 1 (B) at 0 (B) AB AB
(C) at its initial value (D) unstable (C) ( A B)( A B)
AB [GATE - EE - 2007]
(56) A, B C and D are input, and Y is the output (D) ( A B)( A B)
bit in the XOR gate circuit of the figure
below. Which of the following statements AC [GATE -EC - 2001]
about the sum S of A, B, C, D and Y is (61) For the ring oscillator shown in the figure,
correct? the propagation delay of each inverter is 100
pico sec. What is the fundamental frequency
of the oscillator output?
Page 32 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
(A) 10 MHZ (B) 100 MHZ propagation delay per gate is __________ n
(C) 1 GHZ (D) 2GHZ. sec.
AB [GATE -EC - 1988] AA [GATE -EC - 1997]
(62) For the circuit shown below the output F is (68) The output of the logic gate in figure is
given by
(A) 0 (B) 1
(C) A (D) A
(A) F = 1 (B) F = 0 AB [GATE -EC - 1997]
(C) F = X (D) F = X (69) The Boolean function A + BC is a reduced
form of
AD [GATE -EC - 2006]
(63) The point p in the following figure is stuck – (A) AB BC
at 1. The output f will be (B) ( A B ).( A C )
(C) AB ABC
(D) ( A C ).B
(A) ABC (B) A AB [GATE -EC - 2002]
(70) If the input to the digital circuit (in the
(C) ABC (D) A
figure) consisting of a cascade of 20 XOR-
AB [GATE -EC - 1988] gates is X then the output Y is equal to
(64) Minimum number of 2-input NAND gates
required to implement he function.
F = ( X Y )(Z W ) is :
(A) 0 (B) 1
(A) 3 (B) 4
(C) 5 (D) 6 (C) X (D) X
AB, D [GATE -EC - 1989] AD [GATE -EC - 2010]
(65) Indicate which of the following logic gates (71) Match the logic gates in column A with their
can be used to realize all possible equivalents in column B.
combinational Logic functions:
(A) OR gates only
(B) NAND gates only
(C) EX-OR gates only
(D) NOR gates only
AB [GATE -EC - 1993]
(66) For the logic circuit shown in Figure, the (A) P-2, Q-4, R-1, S-3
output is equal to (B) P-4, Q-2, R-1, S-3
(C) P-2, Q-4, R-3, S-1
(D) P-4, Q-2, R-3, S-1
AD[GATE -EC - 2010]
(72) For the output F to be 1 in the logic circuit
shown, the input combination should be
(A) ABC (B) A B C
(C) AB BC A C (D) AB BC
A100nsec [GATE -EC - 1994]
(67) A ring oscillator consisting of 5 inverters is (A) A = 1, B = 1, C = 0
running at a frequency of 1.0 MHz. The (B) A = 1, B = 0, C = 0
www.targate.org Page 33
DIGITAL ELECTRONICS
(C) A = 0, B = 1, C = 0
(D) A = 0, B = 0, C = 1 (D)
AB [GATE -EC - 2011]
(73) The output Y in the circuit below is always
“1” when AA
(76) Consider the following statements:
1. A NAND gate is equivalent to an OR
gate with its inputs inverted
2. A NOR gate is equivalent to an AND
(A) two or more of the inputs P, Q, R are gate with its inputs inverted
“0”
3. A NAND gate is equivalent to an OR
(B) two or more of the inputs P, Q, R are
gate with its output inverted
“1”
(C) any odd number of the inputs P, Q, R is 4. A NOR gate is equivalent to an AND
“0” gate with its output inverted
(D) any odd number of the inputs P, Q, R is Which if these statements are correct?
“1” (A) 1and 2 (B) 2 and 3
AC [GATE -EC - 2000] (C) 3 and 4 (D) 1 and 4
(74) For the logic circuit shown in the figure, the
simplified Boolean expression for the output AB [IES - EE - 2003]
Y is (77) The AND function can be realized by using
only n number of NOR gates. What is n
equal to?
(A) 2 (B) 3
(C) 4 (D) 5
AA [GATE -EC - 2014]
(A) A + B + C (B) A (78) In the circuit shown in the figure, if c = 0,
(C) 0 (D) C the expression for Y is
AB [GATE -EC - 2002]
(75) The gates G1 and G2 in the figure have
propagation delays of 10n sec and 20n sec
respectively. If the input Vi makes an abrupt
change from logic 0 to 1 at time t = t 0 , then
the output waveform V0 is :
(A) Y AB AB
(B) Y A B
(C) Y A B
(D) Y AB
A40 [GATE - EC - 2015]
(A) (79) All the logic gates shown in the figure have
a propagation delay of 20 ns. Let A = C = 0
and B =1 until time t = 0. At t = 0, all the
inputs flip (i.e, A = C = 1 and B = 0) and
remain in that state. For t > 0, output Z =1
(B)
for a duration (in ns) of
(C)
AD [GATE - IN - 2015]
(80) Consider the logic circuit with input signal
TEST shown in the figure. All gates in the
figure shown have identical non-zero delay.
Page 34 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
The signal TEST which was at logic LOW is AD [IES -EC - 1993]
switched to logic HIGH. The output (86) Which one of the following is equivalent to
AND – OR realization?
(A) NAND – NOR realization
(A) stays HIGH throughout (B) NOR – NOR realization
(C) NOR – NAND realization
(B) stays LOW throughout
(D) NAND – NAND realization
(C) pulses from LOW to HIGH to LOW
AC [IES -EC - 1996]
(D) pulses from HIGH to LOW to HIGH (87) A three - input NAND gate is to be used as
AC [GATE - EE - 2009] an inverter. Which one of the following
(81) The complete set of only those Logic Gates measures will achieve better results?
designated as Universal gates is (A) The two inputs not used are kept open
(B) The two inputs not used are connected
(A) NOT, OR and AND Gates to ground (O level)
(B) XNOR, NOR and NAND Gates (C) The two inputs not used are connected
(C) NOR and NAND Gates to logic (1 level)
(D) None of the above
(D) XOR, NOR and NAND Gates
AC [IES -EC - 1997]
AC [IES – EC – 1998] (88) The output X of the logic circuit shown in
(82) The output of an EX-OR gate with A and B the figure is
as inputs will be
(A) AB AB (B) ( A B)( A B)
(C) ( A B) AB (D) A B AB
AD [IES -EC - 2008]
(83) In the given circuit, the output Y equals (A) A + BC (B) BC
which one of the following? (C) AB (D) AB + C
AB [IES -EC - 1999]
(89) The output Y of the given circuit is
(A) 1 (B) zero
(A) A B (C) X (D) X
(B) AB AB
AD[GATE - EC- 2000]
(C) AB (D) A B
(90) Consider the following logic circuit :
AC [IES -EC - 1992]
(84) The open collector wired circuit shown
below functions as
What is the required input condition (A,B,C)
to make the output X = 1, for the given logic
(A) EX-NOR (B) AND circuit?
(A) 1,0,1 (B) 0,0,1
(C) EX-OR (D) NOR
(C) 1,1,1 (D) 0,1,1
AA [IES -EC - 1993]
AA
(85) The gate whose output is LOW if and only if
(91) The open collector output of two 2-input
all the inputs are HIGH, is
NAND gates are connected to a common
(A) NAND (B) NOR pull-up resistor. If inputs of the gates are A,
B and C, D respectively, then output is equal
(C) OR (D) AND to
www.targate.org Page 35
DIGITAL ELECTRONICS
(A) A.B . C.D
(B) A.B C.D (A) AND gate
(C) A.B C.D (B) OR gate
(D) A.B.C.D (C) NAND gate
AD [IES - EE - 2002] (D) NOR gate
(92) Consider the following: AD [IES -EC - 1997]
Any combinational circuit can be built using (96) When two gates with open collector outputs
are tied together as shown in the figure, the
1. NAND gates
output obtained will be
2. NOR gates
3. EX – OR gates
4. Multiplexers
Which of these are correct?
(A) 1, 2 and 3
(A) A B C D
(B) 1, 3 and 4
(C) 2, 3 and 4 (B) A B C D
(D) 1, 2 and 4 (C) ( A B ) (C D)
AD [GATE - IN - 2015]
(93) In the circuit shown, the switch is (D) ( A B ) (C D )
momentarily closed and then opened. AD
Assuming the logic gates to have equal non- (97) The logic function;
zero delay, at steady state, the logic states of
X and Y are Out = ab bc ca
defines:
1. The output of a 3-inputs XOR gate
2. The output of a 3-inputs majority gate
3. The sum output of a full adder
4. The carry output of a full adder
(A) X is latched, Y toggles continuously (A) 1 and 2 (B) 2 and 3
(B) X and Y are both latched (C) 3 and 4 (D) 2 and 4
(C) Y is latched, X toggles continuously AB
(98) The function (A B) is to be realized using
(D) X and Y both toggle continuously
only 2 input NAND gates. The minimum
AA [IES -EC - 2009] number of 2 – input NAND gates required
(94) Which of the following are universal gates? for such a realization is
1. NAND (A) 3 (B) 4
2. NOR (C) 5 (D) 6
3. XOR AA
(99) The minimum number of NAND gates
Select the correct answer from the codes
required to implement the Boolean function
given below:
A AB ABC is equal to
(A) 1 and 2 only
(A) Zero (B) 1
(B) 1 and 3 only
(C) 4 (D) 7
(C) 2 and 3 only
AA [GATE – EC – 1998]
(D) 1, 2 and 3
(100) For the identity AB AC BC AB AC,
AD [IES -EC - 1993] the dual form is :
(95) The negative logic AND gate shown in the
given figure is equivalent of a positive logic
Page 36 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
(A) ( A B)( A C )(B C ) ( A B) AC [IES -EC - 2006]
(104) The Boolean expression
( A C) Y(A, B, C) = A + BC
is to be realized using 2-input gates of only
(B) ( A B)( A C )(B C ) ( A B) one type. What is the minimum number of
gates required for the realization?
( A C) (A) 1 (B) 2
(C) 3 (D) 4 or more
(C) ( A B)( A C )(B C ) ( A B)
AC [IES -EC - 2002]
(105) How is inversion achieved using EX-OR
( A C)
gate?
(D) A B A C B C A B A C (A) Giving input signal to the two input
lines of the gate tied together
AD [GATE – EC – 2008] (B) Giving input to one input line and logic
(101) Which of the following Boolean expressions
zero to the other line
correctly represents the relation between P,
Q, R and M 1 ? (C) Giving input to one input line and logic
one to the other line
(D) Inversion cannot be achieved using EX-
OR gate
AA[GATE-EE-2011]
(106) The output Y of the logic circuit given
(A) M 1 ( P OR Q ) XOR R below is
(B) M 1 ( P AND Q ) XOR R
(C) M 1 ( P NOR Q ) XOR R (A) 1 (B) 0
(C) x (D) x
(D) M 1 ( P XOR Q ) XOR R
S8AD [GATE–S8–EE–2016]
AC(GATE-EC-1998)
(107) The Boolean expression
(102) The minimum number of 2-input NAND
gates required to implement the Boolean (a b c d ) (b c ) simplifies to
function Z = A B C, assuming that A, B and
C are available, is (A) 1 (B) a, b
(A) two (B) three (C) a, b (D) 0
(C) five (D) six AC [GATE–S4–IN–2016]
AA [GATE – EC – 1998] (108) The Boolean expression
(103) In below figure, A = 1 and B = 1. The input XY X Y Z is equivalent to
B is now replaced by a sequence 101010
........ the outputs x and y will be (A) XYZ X Y Z
(B) X Y Z XYZ
(C) (X + Z )(Y+Z)
(D) X Z Y Z
(A) fixed at 0 and 1, respectively
S4AB [GATE–S4–EC–2016]
(B) x = 1010 ------- while y = 0101 ---- (109) Following is the K-map of a Boolean
function of five variables P, Q, R, S and X.
(C) x = 1010 ------- and y = 1010 -------
The minimum sum-of-product (SOP)
(D) fixed at 1 and 0, respectively expression for the function is :
www.targate.org Page 37
DIGITAL ELECTRONICS
(A) Q R (B) PQ R
(C) Q R (D) P Q R
A8 [GATE – EC – 2018]
(113) The logic gates shown in the digital circuit
below use strong pull-down nMOS
transistors for LOW logic level at the
outputs. When the pull-downs are off, high-
value resistors set the output logic levels to
HIGH (i.e. the pull-ups are weak). Note that
some nodes are intentionally shorted to
implement “wired logic”. Such shorted
nodes will be HIGH only if the outputs of all
(A) PQSX PQSX QRSX QRSX the gates whose outputs are shorted are
(B) QSX QSX HIGH.
(C) QSX QSX
(D) QS QS
S1AC [GATE–S1–EC–2016]
(110) The output of the combinational circuit
given below is :
The number of distinct values of X 3 X 2 X 1 X 0
(out of the 16 possible values) that give
Y 1 is _______.
AD [GATE – EE – 2018]
(114) In the logic circuit shown in the figure, Y is
given by
(A) A+B+C (B) A(B+C)
(C) B(C+A) (D) C(A+B)
AC [GATE – IN – 2017]
(111) A and B are the logical inputs and X is the
logical shown in the figure. The output X is (A) Y = ABCD
related to A and B by (B) Y = (A + B)(C + D)
(C) Y = A + B + C + D
(D) Y = AB + CD
AA [GATE – IN – 2018]
(115) The Boolean function F(X, Y) realized by the
given circuit is
(A) X AB BA (B) X AB BA
(C) X AB AB (D) X AB BA
(A) X Y X Y (B) X Y X Y
AC [GATE–S2–EE–2017]
(112) For a 3-input logic circuit shown, the output
(C) X Y (D) X Y
Z can be expressed as
Page 38 TARGATE EDUCATION GATE-( EC /EE)
Topic 03 - Logic Gates
AA [GATE-EE-2019]
(116) In the circuit shown below, X and Y are
digital inputs, and Z is a digital output. The
equivalent circuit is a
(A) XOR gate (B) NOR gate
(C) XNOR gate (D) NAND gate
-------0000-------
www.targate.org Page 39
04
Combinational Digital
Circuits
4.1 Multiplexer AA [GATE – EC – 2014]
(4) If X and Y are inputs and the Difference (D
AD [GATE – EC – 2014] = X - Y) and the Borrow (B) are the outputs,
(1) Consider the multiplexer based logic circuit which one of the following diagrams
shown in the figure. Which one of the implements a half subtractor?
following Boolean functions is realized by
the circuit?
(A)
(A) F W S 1 S 2
(B) F WS1 WS2 S1S2
(C) F W S1 S2
(D) F W S1 S2
(B)
AD [IES -EC - 2006]
(2) What is the number of selector lines required
in a single input n-output de-multiplexer?
(A) 2 (B) n
(C) 2 n (D) log 2 n
AC [GATE – EC – 2014]
(3) In the circuit shown, W and Y are MSBs of
the control inputs. The output F is given by (C)
(A) F W X W X Y Z (D)
(B) F W X W X Y Z
(C) F W X Y W X Y
(D) F W X Y Z
www.targate.org Page 40
Topic 04 - Combinational Digital Circuits
AC [GATE – EC – 2014] (C) D, 1, D, 1, 1, 1, D , D
(5) An 8-to-1 multiplexer is used to implement
a logical function Y as shown in the figure. (D) D , 0, D , 0, 0, 0 D, D
The output Y is given by
AC [GATE -EC - 2003]
(8) Without any additional circuitry, an 8:1
MUX can be used to obtain
(A) some but not all Boolean Functions of 3
variables
(B) all functions of 3 variables but none of
4 variables
(C) all functions of 3 variables and some
but not all of 4 variables
(D) all functions of 4 variables
(A) Y ABC ACD AA [GATE -EC -2010 ]
(9) In the following circuit, X is given by
(B) Y ABC ABD
(C) Y ABC ACD
(D) Y ABD ABC
AB [GATE – EE – 2015]
(6) In the 4 1 multiplexer, the output F is
given by F A B . Find the required input
I 3 I 2 I1 I 0 (A) X ABC ABC ABC ABC
(B) X ABC ABC ABC ABC
(C) X AB BC AC
(D) X AB BC AC
AA [IES – EC – 1998]
(10) The function ‘F’ implemented by the
multiplexer chip shown in the figure is :
(A) 1010 (B) 0110
(C) 1000 (D) 1110
AB [GATE – EE – 2015]
(7) A Boolean function f (A,B,C,D) =
(1,5,12,15) is to be implemented using an 8
× 1 multiplexer (A is MSB). The inputs (A) A (B) B
ABC are connected to the select inputs S2 S1
S0 of the multiplexer respectively. (C) AB (D) AB AB
AD [GATE -EC - 2010]
(11) The Boolean function realized by the logic
circuit shown is
Which one of the following options gives the
correct inputs to pins 0,1,2,3,4,5,6,7 in order
? (A) F m(0,1,3,5,9,10,14)
(A) D, 0, D, 0, 0, 0, D , D (B) F m(2,3,5,7,8,12,13)
(B) D , 1, D , 1, 1, 1, D, D
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DIGITAL ELECTRONICS
(C) F m(1, 2,4,5,11,14,15) 2. A decoder is a combinational logic
circuit that converts binary information
(D) F m(2,3,5,7,8,9,12) from ‘n’ input lines to a maximum of
2n distinct elements at the output.
AB [IES – EC – 2004] 3. The Boolean expression for the output
(12) Consider the following circuit: difference ‘D’ from a full subtractor is
exactly the same as the output sum ‘S’
from a full adder.
Which of the above statements is/are
correct?
(A) 2 and 4 only (B) 4 only
(C) 1 and 3 only (D) 1, 2 and 3
In the given TTL circuit, S2 and S0 are select AB [GATE - IN - 1995]
lines and X7 to X0 are LBSs. What is the (16) The combinatorial circuit shown in Figure.
output Y? employs a 4 to 1 multiplexer. The output Q
of the circuit is
(A) Indeterminate
(B) A B
(C) A B
(D) C B A
AC [IES – EC – 2008/2013]
(13) A digital multiplexer can be used for which
of the following?
1. Parallel to serial conversion
2. Many-to-one switch
(A) A B C (B) A B C
3. To generate memory chip select
4. For code conversion (C) A B C (D) A B C
Select the correct answer using the code AC [GATE - IN - 2001]
given below: (17) In the logic circuit shown in Fig. the output x
(A) 1, 3 and 4 is
(B) 2, 3 and 4
(C) 1 and 2 only
(D) 2 and 3 only
AA [IES – EC – 2009]
(14) Consider a multiplexer with X and Y as data
inputs and Z as control input. Z = 0 selects (A) A B BC C A
input X and Z = 1 selects input Y. What are
(B) A B C
the connections required to realize the 2-
variable Boolean function f T R, (C) AB BC CA
without using any additional hardware?
(D) AB BC C A
(A) R to X, 1 to Y, T to Z
(B) T to X, R to Y, T to Z AC [GATE - IN - 2003]
(18) A 2-to 1 digital multiplexer having a
(C) T to X, R to Y, 0 to Z switching delay of 1 µs is connected as
(D) R to X, 0 to Y, T to Z shown in Fig. The output of the multiplexer
is tied to its own select input S. The inputs
AC [IES – EC – 2010] which gets selected when S = 0 is tied to 1
(15) Consider the following statements: and the input that that go is selected when S
1. A multiplexer is analogous to a rotary = 1 is tied to 0. The output V0 will be
switch.
Page 42 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
(A) C ( A B) (B) C ( A B )
(C) C AB (D) C AB
AA [GATE - IN - 2008]
(21) The output F of the multiplexer circuit
shown below expressed in terms of the input
P, Q and R is
(A) 0
(B) 1
(C) pulse train of frequency 0.5 MHz
(D) pulse train of frequency 1.0 MHz
AC [GATE - IN - 2005]
(19) The cell of a field programmable Gate array
is shown in the figure. It has three 2-to-1 – (A) F P Q R
multiplexers with their select lines
G0 , G1 , G2 and 4 digital signal input lines (B) F PQ QR RP
I0 , I1, I 2 and I3 ,. The logical function that (C) F ( P Q ) R
relates the output O to the select and signal
input lines is (D) F ( P Q ) R
A [GATE - EE - 1999]
(22) The logic function F = AC+ABD+ACD is to
be realized using an 8 to 1 multiplexer
shown in the figure, using A, C and D as
control inputs.
(A) G 0 G 1I 2 G 0G1 I 3 G 2 G1 I 0
G 2G1 I1
(B) G 0 I 2 G 0 G1 G 2 I 0 G 2G1 I 1
G0
(C) G 0 G 2 I 0 G0 G 2 I1 G2 G 1 I 2 (A) Indicate the inputs to be applied at the
terminals 0 to 7.
G2G1I3
(B) Can the function be realize using a 4 to
(D) G2 G1 I 2 G 2 G 1 I 3 G2 G 0 I 0 1 multiplexer?
G0 G 2 I1 State YES or NO.
AC [GATE - IN - 2006] AA [GATE -EC - 2005]
(20) A combinational circuit using a 8-to-1 (23) The Boolean function f implemented in the
multiplexer is shown in the following figure. figure using two input multiplexers is :
The minimized expression for the output (Z)
is :
(A) ABC ABC
(B) ABC A BC
(C) ABC ABC
(D) ABC ABC
www.targate.org Page 43
DIGITAL ELECTRONICS
AC [GATE -EC - 2004]
(24) The minimum number of 2 to 1 multiplexers
required to realize a 4 to 1 multiplexer is
(A) 1 (B) 2
(A) HI for A and B is LO
(C) 3 (D) 4
(B) Independent of A and B
AA [GATE -EC - 2008]
(25) For the circuit shown in the following (C) LO for A and B is Hi
I 0 I 3 are inputs to the 4:1 multiplexer. (D) Hi for A or B is LO
R(MSB) and S are control bits
AB [IES -EC - 2004]
(29) Which one of the following statements is not
correct?
(A) An 8 input MUX can be used to
implement any 4 variable function
(B) A 3 line to 8 line DEMUX can be used
to implement any 4 variable function
The output Z can be represented by
(C) A 64 input MUX can be built nine 8
(A) PQ PQS QRS input MUXs
(D) A 6 line to 64 line DEMUX can be
(B) PQ PQR PQS built using nine 3 line to 8 line
DEMUXs
(C) PQR PQR PQRS QRS
AD [IES – EC – 1997]
(D) PQR PQRS PQRS QRS (30) The output ‘F’ of the multiplexer circuit
shown in the figure will be
AA [GATE -EC - 2009]
(26) What are the minimum number of 2-to-1
multiplexers required to generate a 2-input
AND gate and a 2-input EX-OR gate if the
complements of the inputs are not available
?
(A) 1 and 2 (B) 1 and 3
(C) 1 and 1 (D) 2 and 2 (A) AB BC CA BC
AA [IES – EC – 1991] (B) A B C
(27) In the figure shown (C) A B
X1 HIGH X2 HIGH
(D) ABC ABC ABC ABC
X3 HIGH X4 LOW
AB [IES – EC – 1999]
(31) Assertion (A): A de – multiplexer can be
used as a decoder.
Reason (R): A de – multiplexer is built by
using AND gates only
(A) Both A and R is true and R is the
correct explanation of A
S1 and S0 are control inputs (B) Both A and R is true but R is NOT the
This multiplexer is equivalent to correct explanation of A
(A) NAND gate (C) A is true but R is false
(B) AND gate (D) A is false but R is true
(C) OR gate
AA [IES – EC – 2005]
(D) EXNOR gate
(32) What is the output f ( x, y ) of the
AB [IES – EC – 1991] multiplexer resulting from the input logical
(28) How is the operation dependent on A and B? values?
Page 44 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
Reason (R) : In a combinational circuit, the
current output depends on the previous
outputs also.
Codes:
(A) Both A and R are true and R is the
correct explanation of A.
(B) Both A and R are true but R is not the
correct explanation of A
(A) An EXOR gate (C) A is true but R is false
(B) A NOR gate (D) A is false but R is true
(C) An NAND gate AB [GATE - EE - 2001]
(D) A NAND gate (36) The output f of the 4-to-1 MUX shown in
fig. is
AA [GATE – EE – 2006]
(33) A 4 1 MUX is used to implement a 3-input
Boolean function is as shown below. The
Boolean function F(A, B, C) implemented is
(A) xy + x (B) x+ y
(C) x+ y (D) xy + x
(A) F ( A, B , C ) (1, 2, 4, 6) AC [GATE - EE - 2003]
(37) Figure shows a 4 to 1 MUX to be used to
(B) F ( A, B , C ) (1, 2, 6) implement the sum S of a 1-bit full adder
with input bits P and Q and the carry input
(C) F ( A, B , C ) (2, 4, 5, 6)
Cin . Which of the following combinations
(D) F ( A, B , C ) (1, 5, 6) of inputs to I 0 , I1 , I 2 and I3 of the MUX will
AB [GATE - IN - 2007] realize the sum S?
(34) A MUX circuit shown in the figure below
implements a logic function F1. the correct
expression for F1 is
(A) I 0 I1 C in ; I 2 I 3 C in
(A) X Y Z
(B) X Y Z (B) I 0 I 1 C in ; I 2 I 3 C in
(C) I 0 I 3 C in ; I1 I 2 C in
(C) X Y Z (D) X Y Z
(D) I 0 I 3 C in ; I1 I 2 C in
AC [IES – EE – 1995]
AD [GATE -EC - 2011]
(35) Assertion (A) : A digital multiplexer can
(38) The logic function implemented by the
also be used to implement combinational
circuit below is (ground implies a logic “0”)
logic functions.
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DIGITAL ELECTRONICS
3. Converts parallel data into serial data
4. Is a combinational circuit
Which of these statements are correct?
(A) 1, 2 and 4 (B) 2, 3 and 4
(C) 1, 3 and 4 (D) 1, 2 and 3
AD [IES -EC - 2007]
(42) When two 16-input multiplexers drive a 2-
input MUX, what is the result?
(A) 2-input MUX
(A) F = AND (P, Q) (B) 4-input MUX
(B) F = OR (P, Q) (C) 16-input MUX
(C) F = XNOR (P, Q) (D) 32-input MUX
(D) F = XOR (P, Q) AD [IES -EC - 1996]
AB [GATE -EC - 2001] (43) A 4-input multiplexer can be used to
(39) In the TTL circuit in the figure, S2 and S0 are implement
select lines and X 7 and X 0 are input lines. (A) Four combinational functions of 2-
S0 and X 0 are LSB’s. What is the output Y ? variables each
(B) Two combinational functions of 4-
variables each
(C) One combinational function of 4-
variables
(D) One combinational function of 3-
variables
AC [IES -EC - 2000]
(44) Which one of the following can be used as
(A) Indeterminate parallel to serial converter ?
(B) A B (A) Decoder
(C) A B (B) Digital counter
(C) Multiplexer
(D) C A B C A B
(D) De-multiplexer.
AB [GATE -EC - 1992]
(40) The logic realized by the circuit shown in S3AA [GATE–S3–EC–2016]
figure is (45) A 4:1 multiplexer is to be used for
generating the output carry of a full adder. A
and B are the bits to be added while in is
the input carry and out is the output carry.
A and B are to be used as the select bits with
A being the more significant select bit.
(A) F A C (B) F A C
(C) F B C (D) F B C
AC [IES -EC - 2000]
(41) Consider the following statements A Which one of the following statements
Multiplexer correctly describes the choice of signals to
1. Selects one of the several inputs and be connected to the inputs I0, I1, I2 and I3 so
transmits it to a single output that the output is Cout ?
2. Routes the data from a single input to (A) I0 =0, I1=Cin, I2 =Cin and I3=1
one of many output (B) I0=1, I1 =Cin, I2=Cin and I3=1
Page 46 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
(C) I0=Cin, I1=0, I2=1 and I3=Cin
(D) I0=0, I1=Cin, I2=1 and I3=Cin
S4A6.0:6.0 [GATE–S4–EC–2016]
(46) For the circuit shown in the figure, the
delays of NOR gates, multiplexers and
inverters are 2 ns, 1.5 ns and 1 ns,
respectively. If all the inputs P, Q, R, S and
T are applied at the same time instant, the
maximum propagation delay (in ns) of the
circuit is _______
(A) 2-to-1 multiplexer
(B) 4-to-1 multiplexer
(C) 7-to-1 multiplexer
(D) 6-to-1 multiplexer
AB [GATE–S2–EC–2017]
(50) Consider the circuit shown in the figure.
S6AD [GATE–S6–EE–2016]
(47) Consider the following circuit which uses a
2-to-1 multiplexer as shown in the figure
below. The Boolean expression for output F
in terms of A and B is :
The Boolean expression F implemented by
(A) A B (B) A B the circuit is
(C) A + B (D) A B (A) X Y Z X Y Y Z
S4AA [GATE–S4–IN–2016] (B) X Y Z X Z Y Z
(48) A 4 to 1 multiplexer to realize a Boolean
function F (X, Y, Z) is shown in the figure (C) X Y Z X Y Y Z
below. The inputs Y and Z are connected to
the selectors of the MUX (Y is more (D) X Y Z X Z Y Z
significant). The canonical sum-of-product
AC [GATE – EC – 2018]
expression for F ( X, Y, Z ) is
(51) A four-variable Boolean function is realized
using 4 1 multiplexers as shown in the
figure.
(A) m (2,3, 4, 7) (B) m (1, 3, 5, 7)
(C) m (0, 2, 4, 6) (D) m(2,3,5,6)
S1AB [GATE–S1–EC–2016]
(49) The functionality implemented by the circuit
below is : The minimized expression for F(U,V,W, X)
is
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DIGITAL ELECTRONICS
(A) (UV UV )W
(B) (UV UV )(W X W X )
(C) (UV UV )W
(D) (UV UV )W X W X )
**********
Page 48 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
4.2 Adder (B) Having three inputs used to add two
binary digits. It produces their sum and
AB [IES – EE – 1995] carries as outputs
(1) The logic circuit given in the figure
(C) Used in the least significant position
represents a
when adding two binary digits with no
carry – in to consider. If produces their
sum and carry as outputs
(D) Having two inputs and two output.
AC [IES -EC - 1996]
(A) Full adder (5) Which one of the following statements is
(B) Half adder correct?
(C) Half subtractor (A) In serial adder, if d and D, respectively,
are the full adder and flip – flop delay,
(D) Boolean multiplier then the time required to perform n bit
AC[GATE-IN-2004] addition is [n(d+D)]
(2) In the circuit of figure A, B, C are the inputs (B) Maximum delay in n bit parallel adder is
and P,Q are the two outputs. The circuit is a ‘nd’ where d is delay of full adder
(C) If d is the delay of two – level circuit,
and then the total delay of a carry look
ahead adder is only 3d.
(D) none of the above
AA [IES – EE – 1997]
(6) In a half - adder having two inputs A and B
and two outputs, (S and C are the Sum and
carry output bits respectively) , the Boolean
expressions for S and C in terms of A and B
(A) half adder where P is the sum and Q is is
the carry
(A) S AB A.B; C A.B
(B) half adder where P is the carry and Q is
the sum (B) S AB AB; C A B
(C) full adder where P is the sum and Q is
the carry (C) S A.B AB; C A B
(D) full adder where P is the carry and Q is (D) S A A.B; C A B
the sum
AB [GATE -EC - 1997]
AD [GATE - IN - 2005] (7) A 2-bit binary multiplier can be
(3) Not withstanding over flow, the addition the implemented using
subtraction of K-bit signed binary numbers
can be realized using One K-bit full adder (A) 2 input ANDs only
and (B) 2 input XORs and 4-input AND gates
(A) 2 – input AND gates only.
(B) 2 – input NOR gates (C) Two (2) input NORs and one XNOR
gate.
(C) 2 – input OR gates
(D) XOR gates and shift registers.
(D) 2 – input XOR gates
AC [GATE -EC - 2014]
AB [IES -EC - 2000] (8) In a half-subtractor circuit with X and Y
(4) Which one of the following statements input the Borrow (M) and difference (N = X
correctly defines the full adder? - Y) are given by
(A) Having two inputs used to add two (A) M X Y , N XY
binary digits. It produces their sum and
carries as input (B) M XY , N X Y
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DIGITAL ELECTRONICS
(C) M XY , N X Y (4)
(D) M XY , N X Y
AA [IES -EC - 1994]
(9) A combinational circuit is one in which the Codes :
output depends on the
A B C D
(A) Input combination at that time
(A) 2 3 1 4
(B) Input combination and the previous
output (B) 2 3 4 1
(C) Input combination at the time and the (C) 3 2 4 1
previous input combination (D) 3 2 1 4
(D) Present output and the previous outputs AA [IES – EC – 1993]
AC [GATE -EC - 1999] (12) A carry look ahead adder is frequency used
(10) For a binary half-subtractor having two for addition because it
inputs A and B, the correct sets of logical (A) Is faster
expressions for the outputs D ( = A minus B)
(B) Is more accurate
and X ( = borrow) are
(C) Used fewer gates
(A) D AB AB, X AB
(D) Costs less
(B) D AB AB, X AB
AB [IES -EC - 2003]
(C) D AB AB, X AB (13) The addition of two binary variables A and
B results into a SUM and a carry output.
(D) D AB AB, X AB Consider the following expressions for the
SUM and CARRY outputs:
AC [IES – EE – 2008]
(11) Match List -I (function/ circuit) with List -II 1. SUM = A.B A.B
(circuit realization) and select the correct
2. SUM = A.B A.B
answer using the codes given below the
Lists: 3. CARRY = A.B
List - I 4. CARRY = A + B
A. D - flip flop Which of these expressions are correct?
(A) 1 and 3 (B) 2 and 3
B. T - flip flop
(C) 2 and 4 (D) 1 and 4
C. Exclusive OR
AC [GATE - IN - 2005]
D. Half adder (14) A combinational logics circuit has three
List - II inputs A, B and C and one output Y. The
output Y = 1 when at least two inputs are 1.
(1) Otherwise, Y = 0. in its minimized SOP
realization, the maximum number of two
input terms is
(A) 1 (B) 2
(C) 3 (D) 4
(2) AD [IES – EC – 1994]
(15) A full – adder can be implemented with half
– address and OR gates. A 4 – bit parallel
full adder without any initial carry requires
(A) 8 half – address, 4 OR gates
(3)
(B) Three bit parity checker
(C) 7 half – address, 4 – OR gates
(D) 7 half – address, 3 OR gates
Page 50 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
AB [IES – EC – 1994] AC [IES – EC – 2005]
(16) Which one of the following will give the (21) Which one of the following statements is not
sum of full adder as output? correct?
(A) Three input majority circuit (A) A full adder can be constructed using
(B) Three bit parity checker two half-adders and an OR gate.
(C) Three bit comparator (B) Two Four bit parallel adders can be
cascaded to construct 8-bit parallel
(D) Three bit counter adder.
AC [IES – EC – 1997] (C) Ripple carry adder has addition time
(17) A full – adder can be made out of independent of the number of bits.
(A) Two half – address (D) Carry lock ahead is used to speed up
(B) Two half – address and a NOT gate the parallel addition.
(C) Two half – address and an OR gate AC [IES – EC – 2007]
(22) Consider the following statements:
(D) Two half – address and an AND gate
For 3 input variables a, b, c; a Boolean
AB [IES – EC – 1998] function y ab bc ca represents
(18) The circuit shown in the given is a
1. a 3-input majority gate
2. a 3-input majority gate
3. Carry output of a full adder
4. Product circuit for a , b and c
Which of the above statements are correct?
(A) Full adder (A) 1 and 4 only
(B) Full subtractor (B) 2 and 3 only
(C) Shift register (C) 1 and 3 only
(D) Decade counter (D) 3 and 4 only
AB [IES – EC – 2000] AD [IES – EC – 2009]
(19) The half – adder circuit in the given figure (23) Which of the following circuits come under
has inputs AB = 11 the class of combinational logic circuits?
1. Full adder
2. Full subtractor
3. Half adder
4. J-K flip-flop
The logic level of P and Q outputs will be : 5. Counter
(A) P = 0 and Q = 0 Select the correct answer from the codes
given below:
(B) P = 0 and Q = 1
(C) P = 1 and Q = 0 (A) 1 only (B) 3 and 4
(D) P = 1 and Q = 1 (C) 4 and 5 (D) 1, 2 and 3
AA [IES – EC – 2005] A50.0 [GATE–S2–EC–2017]
(20) A 1-bit full adder takes 20ns to generate (24) Figure I shows a 4-bit ripple carry adder
carry-out bit and 40ns for the sum bit. What realize using full adders and Figure II shows
is the maximum rate of addition per second the circuit of a full-adder (FA). The
when four 1-bit full address are cascade? propagation delay of the XOR, AND and
OR gates in Figure II are 20 ns, 15 ns and 10
(A) 10 7 (B) 1.25 10 7 ns, respectively. Assume all the inputs to the
(C) 6.25 10 6 (D) 10 5 4-bit adder are initially reset to 0.
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DIGITAL ELECTRONICS
At t = 0, the inptus to the 4-bit adder are
changed to X 3 X 2 X1 X 0 = 1100,
Y3Y2Y1Y0 0100 and Z 0 1 . The output of
the ripple carry adder will be stable at t (in
ns) = ______.
A4 [GATE-IN-2019]
(25) The figure below shows that ith full-adder
block of a binary adder circuit. Ci is the
input carry and Ci+1 is the output carry of the
circuit. Assuming that each logic gate has a
delay of 2 nanosecond, with no additional
time delay due to the interconnecting wires.
If the inputs Ai, Bi are available and stable
throughout the carry propagation, the
maximum time taken for an input Ci to
produce a steady-state output Ci+1 is _____
nanosecond.
**********
Page 52 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
4.3 Decoder (A) Decoder
(B) de-multiplexer
AD [GATE – EC – 2015]
(1) A 1-to-8 demultiplexer with data input Din, (C) Multiplexer
address inputs S0, S1, S2 (with S0 as the LSB) (D) Encoder
and Y0 to Y7 as the eight demultiplexed AD [IES -EC - 2010]
outputs, is to be designed using two 2-to-4 (5) With which decoder it is possible to obtain
decoders (with enable input E and address many code conversions ?
inputs A0 and A1) as shown in the figure. (A) 2 line to 4 line
Din, S0, S1 and S2 are to be connected to
(B) 3 line to 8 line
P,Q,R and S , but not necessarily in this
order. The respective input connections to (C) Not possible with any decoder
P,Q,R and S terminals should be : (D) 4 line to 16 line decoder
AC [IES – EC – 2005]
(6) Consider the following statements:
A 4:16 decoder can be constructed (with
enable input) by
1. Using four 2:4 decoders (each with an
enable input) only.
2. Using five 2:4 decoders (each with an
enable input) only.
3. Using two 3:8 decoders (each with an
enable input) only.
(A) S 2 , D in ,S 0 ,S1 (B) S1 , D in ,S0 ,S 2
4. Using two 3:8 decoders (each with an
(C) D in ,S0 ,S1 ,S 2 (D) D in ,S2 ,S 0 , S1 enable input) and an inverter.
AB[IES – EE – 2002] Which of the statements given above is/are
(2) A 3-to-8 decoder is shown below: correct ?
(A) 1 only (B) 1 only
(C) 2 and 4 (D) None
AA [GATE - EE - 2008]
(7) A 3 line to 8 line decoder, with active low
outputs, is used to implement a 3-variable
Boolean function as shown in the figure:
The simplified form of Boolean function
F(A, B, C) implemented in ‘Product of Sum’
All the output lines of the chip will be high, form will be
when all the inputs 1, 2 and 3
(A) Are high; and G1, G2 are low
(B) Are high; and G1 is low, G2 is high
(C) Are low; and G1 is low, G2 is high
(D) Are high; and G1 is high, G2 is low
AB [IES – EC – 2001]
(3) The number of 4-line-to-16-line decoders
required to make an 8-line-to-256-line.
(A) ( x z ). x y z .( y z )
decoder is
(B) ( x z ). x y z .( y z )
(A) 16 (B) 17
(C) 32 (D) 64 (C) x y z . x y z . x y z .
AA [IES -EC - 1999] (x y z)
(4) A system accepts an M-bit word and
establishes the state '1' on one and only one
(D) x y z . x y z . x y z .
of 2M output line is called
(x y z)
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DIGITAL ELECTRONICS
S1AMTA [GATE–S1–EC–2016]
(8) Identify the circuit below.
(A) Binary to Gray code converter
(B) Binary to XS3 converter
(C) Gray to Binary converter
(D) XS3 to Binary converter
*********
Page 54 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
4.4 Miscellaneous A B C
(A) 1 2 3
AC [GATE - IN - 2003] (B) 2 3 1
(1) The logic circuit of Fig. is a
(C) 3 1 2
(D) 1 2 2
A* [GATE-IN-1997]
(5) Design the logic system shown in figure, to
(A) Half adder (B) XOR satisfy the truth table given, using minimum
(C) Equality detector (D) Full adder number of gates.
AA [GATE - IN - 2010]
(2) The logic gate circuit shown in the adjoining
figure realizes the function
AC [IES – EC – 1995/1997]
(6) The circuits shown in the given figure is
(A) XOR (B) XNOR
(C) Half adder (D) Full adder
AC [IES – EE – 1998]
(3) For the diode matrix shown in the figure the
output Y1 will be
(A) An adder circuit
(B) A subtractor circuit
(C) A comparator circuit
(D) A parity generator circuit
AA [GATE - EE - 1995]
(7) For a flip-flop formed from two NAND
gates as shown in figure. The unusable state
corresponds to
(A) X 0 X 2 (B) X 1 X 3
(C) X 1 X 3 (D) X 0 X 3
AC [IES – EC – 1992]
(4) Match List – I with List – II and select the
correct answer by using the codes given (A) X = 0, Y = 0
below the lists
(B) X = 0, Y = 1
List – I (C) X = 1, Y = 0
A. Multiplexer (D) X = 1, Y =
B. Shift – Register AA [IES – EC – 2002]
C. Encoder (8) Consider the following digital circuits :
List – II 1. Multiplexers
1. Sequential memory 2. Read Only Memories
2. Converts decimal number to binary 3. D-latch
3. Data selector 4. Circuit as shown
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DIGITAL ELECTRONICS
(A) Y A B AB C
(B) Y A B AB C
Which of these come under the class of (C) Y A B C
combinational circuits?
(D) Y AB C
(A) 1 and 2
AD [GATE - IN - 2009]
(B) 3 and 4
(12) The minimal sum-of-products expression for
(C) 1, 2 and 3 the logic function f represented by the given
Karnaugh map is :
(D) 1, 2, 3 and 4
AA [IES – EC – 2005]
(9) Which one of the following functions is
realized by the circuit shown above?
(A) QS P RS PQR PRS PQ R
(A) ( A B)C DE
(B) QS PRS PQR P RS PQR
(B) ( A B )C D E
(C) AB C DE
(C) PR S P Q R P RS PQR
(D) AB C ( D E ) (D) P R S PQR PRS PQ R
AA [GATE – EC – 2005] AD [GATE - IN - 2007]
(10) What is the Boolean expression for the truth (13) Let X = X 1 X 0 and Y Y1Y0 be unsigned 2-
table shown below?
bit numbers. The function F = 1 if X Y
A B C F and F = 0 otherwise. The minimized sum of
0 0 0 0 products expression for F is :
0 0 1 0 (A) Y1 .Y0 X 0 .Y0 X 1 . X 0 .Y 1
0 1 0 0
0 1 1 1 (B) X 0 .Y 1 Y1 Y 0 X 1 X 0
1 0 0 0
(C) Y1 . X 1 Y0 . X 1 . X 0 Y1 .Y0 . X 0
1 0 1 0
1 1 0 1 (D) X 1 .Y 1 X 0 .Y 0 .Y 1 X 0 . X 1 .Y 0
1 1 1 0
AA [GATE - EE - 2000]
(A) B ( A C )( A C ) (14) The minimal product-of-sums function
described by the K-map given in Fig.
(B) B ( A C )( A C )
(C) B ( A C )( A C )
(D) B ( A C )( A C )
AA [IES – EC – 2010]
(11) The Boolean expression for the output of the
below logic circuit is (A) AC (B) A C
(C) A+C (D) AC
AB[GATE-EC-1995]
(15) The output of the circuit shown in figure is
equal to
Page 56 TARGATE EDUCATION GATE-( EC /EE)
Topic 04 - Combinational Digital Circuits
Consider
(i) push button pressed/not pressed in
equivalent to logic 1/0 respectively,
(ii) a segment glowing/not glowing in the
display is equivalent to logic 1/0
respectively
(A) 0 AB[GATE-EC-2009]
(17) If segments a to g are considered as
(B) 1
functions of P1 and P2 , then which of the
(C) AB+AB following is correct?
(D) (A B) (A B) (A) g = P1 P2 , d c e
AB[GATE-EC-2003] (B) g = P1 P2 , d c e
(16) The circuit shown in the figure has 4 boxes (C) g = P1 P2 , e b c
each described by inputs P, Q, R and outputs
Y, Z with (D) g = P1 P2 , e b c
Y PQ R
AD[GATE-EC-2009]
Z RQ PR QP (18) What are the minimum numbers of NOT
gates and 2-input OR gates required to
design the logic of the driver for this 7-
segment display?
(A) 3 NOT and 4 OR
(B) 2 NOT and 4 OR
(C) 1 NOT and 3 OR
(D) 2 NOT and 3 OR
The circuit acts as a
AC [GATE–S2–EC–2017]
(A) 4 bit adder giving P + Q (19) A programmable logic array (PLA) is shown
(B) 4 bit subtractor giving P – Q in the figure.
(C) 4 bit subtractor giving Q – P
(D) 4 bit adder giving P + Q + R
Statement for Linked Answer Question for Next
Two Questions :
Two products are sold from a vending machine,
which has two push buttons P1 and P2 . When a
button is pressed, the price of the corresponding
product is displayed in a 7-segment display.
If no buttons are pressed, '0' is displayed,
signifying 'Rs. 0'
If only P1 is pressed, '2' is displayed, signifying
'Rs.2'
The Boolean function F implemented is
If only P2 is pressed, '5' is displayed, signifying
'Rs.5' (A) PQ R PQ R PQ R
If both P1 and P2 are pressed, 'E' is displayed, (B) ( P Q R) ( P Q R)
signifying 'Error'
The names of the segments in the 7-segment ( P Q R )
display, and the glow of the display for '0', '2', '5'
and 'E' are shown below (C) P Q R PQ R PQ R
(D) ( P Q R) ( P Q R)
( P Q R )
www.targate.org Page 57
DIGITAL ELECTRONICS
AA [GATE – EC – 2018]
(20) A 2 2 ROM array is built with the help of
diodes as shown in the circuit below. Here
W0 and W1 are signals that select the word
lines and B0 and B1 are signals that are
output of the sense amps based on the stored
data corresponding to the bit lines during the
read operation.
B0 B1
W0 D00 D01
W1 D10 D 11
Bits stored in the ROM Array
During the read operation, the selected word
line goes high and the other word line is in a
high impedance state. As per the
implementation shown in the circuit diagram
above, what are the bits corresponding to Dij
(where i = 0 or 1 and j = 0 or 1) stored in the
ROM?
1 0 0 1
(A) (B)
0 1 1 0
1 0 1 1
(C) (D)
1 0 0 0
AB [GATE-IN-2019]
(21) X X 1 X 0 and Y Y1Y0 are 2–bit binary
numbers. The Boolean function S that
satisfies the condition “If X > Y, then S = 1” ,
in its minimized form, is
(A) X 1Y1 X 0Y0
(B) X 1Y1 X 0Y0Y1 X 0Y0 X 1
(C) X 1Y1 X 0Y0
(D) X 1Y1 X 0Y0Y1 X 0Y0 X 1
-------0000-------
Page 58 TARGATE EDUCATION GATE-( EC /EE)
05
Sequential Digital Circuits
5.1 Counter AA[GATE-IN-2007]
(3) The pulse width T of an asynchronous pulse
AD [GATE-EC/EE/IN-2012] is measured by a counter with an edge-
(1) The state transition diagram for the logic triggered clock of known frequency fc as
circuit shown is : shown in the figure below :
The pulse width to be measured is applied to
the Enable pin of the counter. The counter
counts while the Enable is high and is held
reset to zero otherwise. The counter output is
latched by the negative edge of the Enable
signal. The measured pulse width is taken to
(A) be N times the clock period, where N is the
count reached at the end of a count cycle.
Assuming no overflow, the measurement
error will be limited to x% of T if
100
(A) T
xf c
(B)
100
(B) T
xfc
200
(C) T
xf c
(C)
200
(D) T
xf c
AC [GATE – EC – 2014]
(4) In the circuit shown choose the correct
(D) timing diagram of the output (y) from the
A62-63 [GATE – EC – 2014] given wave forms W1 , W2 , W3 and W4 .
(2) Five JK flip flops are cascaded to form the
circuit shown in figure clock pulses at a
frequency of 1 MHz are applied as shown
the frequency (in KHz) of the waveform at
Q 3 is ----------
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DIGITAL ELECTRONICS
A6 [GATE – EC – 2015]
(8) A mod-n counter using a synchronous binary
up-counter with synchronous clear input is
shown in the figure. The value of n is ____ .
AC [GATE – EC2 – 2015]
(9) The figure shows a binary counter with
(A) W1 (B) W2 synchronous clear input. With the decoding
logic show, the counter works as a
(C) W3 (D) W4
AD [GATE – EC – 2014]
(5) The outputs of the two flip-flops Q1, Q2 in
the figure shown are initialized to 0, 0. The
sequence generated at Q1 upon application of
clock signal is
(A) mod - 2 counter
(B) mod - 4 counter
(C) mod - 5 counter
(D) mod - 6 counter
(A) 01110... (B) 01010....
AA [GATE – EC3 – 2015]
(C) 00110.... (D) 01100.....
(10) The circuit shown consists of J-K flip-flops,
AD [GATE – EC – 2014] each with an active low asynchronous reset
(6) The circuit shown in the figure is a ( R d input). The counter corresponding to
this circuit is
(A) Toggle Flip Flop (A) a modulo-5 binary up counter
(B) JK Flip Flop (B) a modulo-6 binary down counter
(C) SR Latch (C) a modulo-5 binary down counter
(D) Master-Slave D Flip Flop (D) a modulo-6 binary up counter
A194.9to195.1 [GATE – EC – 2014] AD [GATE – EC3 – 2015]
(7) A 16-bit ripple adder is realized using 16 (11) A three bit pseudo random number generator
identical full adders (FA) as shown in the is shown. Initially the value of output Y =
figure. The carry-propagation of delay of Y2Y1Y0 is set to 111. The value of output Y
each FA is 12 ns and the sum propagation after three clock cycles is
delay of each FA is 15 ns. Worst case delay
(in ns) of this 16-bit adder will be----------.
Page 60 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) 000 (B) 001 (C) Ripple counter
(C) 010 (D) 100 (D) Sequence detector
A6 [GATE – EE – 2015] AC [IES – EE – 2010]
(12) The figure shows a digital circuit (16) Which of the following counter results in
constructed using negative edge triggered J – least delay?
K flip flops. Assume a starting state of Q2 Q1 (A) Ring counter
Q0 = 000. This state Q2 Q1 Q0 = 000 will
repeat after _____ number of cycles of the (B) Ripple counter
clock CLK. (C) Synchronous counter
(D) Asynchronous counter
AB&D [IES – EE – 2012]
(17) A divide-by-6 counter is obtained using
(A) 6-bit ripple counter
(B) 6-bit ring counter
AB [GATE – EE – 2015]
(13) In the following sequential circuit, the initial (C) 3-bit ripple counter
state (before the first clock pulse) of the (D) 3-bit twisted - ring counter
circuit is Q1Q 0 00 . The state (Q1Q 0 ) ,
Q1Q0 = 00. The state (Q1Q0), immediately AD [IES – EC – 1992]
after the 333rd clock pulse is : (18) Which type of counter is shown in the
figure?
(A) Synchronous (B) Johnson
(A) 00 (B) 01
(C) Ring (D) None
(C) 10 (D) 11
AB [IES – EC – 1992]
AC [IES – EE – 1997] (19) The circuit shown below is
(14) The circuit schematic shown in the
following figure represents a 4-bit
(A) 2:1 scalar (B) 4:1 scalar
(A) Static shift register
(C) Up – down counter (D) None
(B) Dynamic shift register
AC [IES – EC – 1994]
(C) Asynchronous counter (20) A divide – by – 78 counter can be realized
(D) Synchronous counter by using
AA [IES – EE – 2010] (A) 6 no’s of mod – 13 counters
(15) Circuit shown in the fig. below is a : (B) 13 no’s of mod – 6 counters
(C) One mod – 13 counter followed by one
mod – 6 counters
(D) 13 no’s of mod – 13 counters
AA [IES – EC – 1994]
(21) A 4 – bit synchronous counter uses flip flop
with propagation delay time of 15ns each.
(A) Shift register
The maximum possible time required for
(B) Binary counter change of state will be
www.targate.org Page 61
DIGITAL ELECTRONICS
(A) 15 ns (B) 30 ns AC [IES – EC – 2003]
(C) 45 ns (D) 60 ns (27) The number of unused states in a 4-bit
Johnson counter is
AC [IES – EC – 1994] (A) 2 (B) 4
(22) The block diagram shown in the given figure
represents (C) 8 (D) 12
AC [IES – EC – 2003]
(28) Match List-I with List II and select the
correct answer using the codes given below
the Lists :
List I List II
(Digital Circuit) (Circuit Type)
(A) Modulo – 3 ripple counter A. BCD to 7- 1. Sequential
(B) Modulo – 5 ripple counter segment circuit
Decoder
(C) Modulo – 7 ripple counter
B. 4-to-1 2. Combinational
(D) Modulo – 7 synchronous counter Multiplexer circuit
AD [IES – EC – 1997] C. 4-bit Shift 3. Neither
(23) A 4 – bit binary ripple counter uses flip – Register sequential nor
flops with a propagation delay time of 25 ns combinational
each. The maximum possible time required circuit
for change of state will be D. BCD Counter
(A) 25ns (B) 50ns Codes:
(C) 75 ns (D) 100ns A B C D
(A) 2 1 2 1
AC [IES – EC – 1997]
(24) The schematic shown in the figure (B) 3 2 1 3
represents a (C) 2 2 1 1
(D) 3 1 2 3
AA [IES – EC – 2005]
(29) 12 MHz clock frequency is applied to a
cascaded counter of modulus-3 counter,
modulus-4 counter and modulus-5 counter.
What are the lowest output frequency and
the overall modulus, respectively?
(A) Divide by seven counters (A) 200 kHz, 60 (B) 1 MHz, 60
(B) Divide by five counters (C) 3 MHz, 12 (D) 4 MHz, 12
(C) Binary coded decimal counters
(D) Divide by twelve counters AA [IES – EC – 2005]
(30) The circuit given below is that of a
AC [IES – EC – 1999]
(25) Symmetrical square wave of time period
100µ s can be obtained from square wave of
time period 10 µ s by using a
(A) Divided by – 5 circuits
(B) Divided by 2 circuit (A) Mod – 5 Counter
(C) Divided by – 5 circuit followed by a
(B) Mod-6 Counter
divided by – 2 circuit
(D) BCD counters (C) Mod-7 Counter
(D) Mod-8 Counter
AA [IES – EC – 2000]
(26) A ring counter consisting of Five flip flops AD [IES – EC – 2006]
will have (31) Match List I with List II and select the
(A) 5 states (B) 10 states correct answer using the code given below
(C) 32 states (D) infinite states the Lists:
Page 62 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
List I List II (A) 00,01,10,11,00 ..............
(Circuit) (Application) (B) 00,01,10,00,01 ...............
A. Ripple up 1. Division (C) 00,01,11,00,01 ...............
counter (D) 00,10,11,00,10 .............
B. Synchronous 2. Multiplication AA [GATE – EC – 1993]
down counter
(35) A pulse train with a frequency of 1 MHz is
C. Shift left 3. To create delay counted using a mod – 1024 ripple counter
register built with J – K flip flops. For proper
D. Shift right 4. Transient states operation of the counter the maximum
register permissible propagation delay per flip flop
stage is
Codes:
(A) 100 ns (B) 50 ns
A B C D
(C) 20 ns (D) 10 ns
(A) 2 3 4 1
(B) 4 1 2 3 AB [IES – EC – 2012]
(C) 2 1 4 3 (36) The highest speed counter is
(D) 4 3 2 1 (A) Asynchronous counter
(B) Synchronous counter
AD [IES – EC – 2009]
(32) Which of the following circuits come under (C) Ripple counters
the class of sequential logic circuits? (D) Ring counter
1. Full adder
AA [GATE - IN - 1998]
2. Full subtractor
(37) The minimum number of flip – flops needed
3. Half adder to make mod – 2 counter is
4. J-K flip-flop
(A) 1 (B) 2
5. Counter
Select the correct answer from the codes (C) 3 (D) 4
given below:
AC [GATE - IN -2003 ]
(A) 1 and 2 (B) 2 and 3 (38) The square wave C1 shown in Fig. is given
(C) 3 and 4 (D) 4 and 5 to the clock input of a 4-bit binary up/down
AA [IES – EC – 2009] counter whose UP/ DN input if fed with the
(33) Which of the following measurements can pulse train Pu . The counter is a negative
be done using a counter? edge triggered one. The counter starts with
1. Pulse duration 0000 and will reach 0000 again at the
2. Interval between two pulses
3. Amplitude of the pulse
4. Rise time of a pulse
Select the correct answer from the codes
given below:
(A) 1 and 2 (B) 2 and 3 (A) 15th clock pulse
(C) 1 and 4 (D) 2 and 4
(B) 16th clock pulse
AB [GATE – EC – 2007] (C) 44th clock pulse
(34) For the circuit shown below the counter state
(Q1 Q0) follows the sequence (D) 48th clock pulse
AB [GATE - IN - 2005]
(39) For the digital counter shown in the figure
with output Q0 , Q1 , Q2 ....., where Q0
indicates the LSB of the count value, the
correct statement when the switch Sw is
closed is
www.targate.org Page 63
DIGITAL ELECTRONICS
AC [GATE - IN - 2008]
(42) The above circuit is a
(A) Mod-8 Counter
(B) Mod-9 Counter
(C) Mod-10 Counter
(D) Mod-11 Counter
(A) Counter outputs are both even and odd AD [GATE - IN - 2011]
numbers (43) The circuit below show an up/down counter
working with a decode and a flip – flop.
(B) Counter outputs are only odd numbers Preset and clear of the flip-flop are
(C) Counter outputs are only even numbers asynchronous active – low inputs.
(D) Counter stops counting
AA [GATE - IN -2006 ]
(40) Given that the initial state (Q1Q0 ) is the
counting sequence of the counter shown in
the following figure is, Q1Q 0
Assuming that the initial value of counter
(A) 00 – 11 – 01 – 10 - 00
output ( Q2 Q1Q0 ) as zero, the counter outputs
in decimal for 12 clock cycles are
(B) 00 – 01 – 11 – 10 - 00
(A) 0,1,2,3,4,4,3,2,1,1,2,3,4
(C) 00 – 11 – 10 – 01 - 00 (B) 0,1,2,3,4,5,0,1,2,3,4,5,0
(C) 0,1,2,3,4,5,5,,4,3,2,1,0,1
(D) 00 – 10 – 01 – 11 - 00 (D) 0,1,2,3,4,5,4,3,2,1,0,1,2
Statement for Linked Answer Questions for
Next Two Questions : AC [GATE - EE - 2005/IES - EE - 2009]
(44) The digital circuit shown in the figure works
Consider the counter circuit shown below: as a
(A) JK flip-flop
(B) Clocked RS flip-flop
(C) T flip-flop
(D) Ring counter
AA [GATE - IN - 2008]
(41) In the above figure, Y can be expressed as AC [GATE - EE - 2011]
(45) A two-bit counter circuit is shown is shown
(A) Q3 (Q2 Q1 ) below
(B) Q3 Q2 Q1
(C) Q 3 ( Q 2 Q1 )
(D) Q3 Q 2 Q1
Page 64 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
If the state QAQB of the counter at the clock AC [GATE -EC - 2001]
(49) The digital block in the figure is realized
time tn is ‘10’ then the state QAQB of the
using two positive edge triggered D flip –
counter at tn 3 (after three clock cycles) flops. Assume that for t t0 , Q1 Q2 0.
will be The circuit in the digital block is given by
(A) 00 (B) 01
(C) 10 (D) 11
AB [GATE -EC - 2005]
(46) The given figure shows a ripple counter
using positive edge triggered flip-flops. If (A)
the present state of the counter is
Q2 Q1Q0 011, then its next state ( Q 2 Q1Q 0 )
will be
(B)
(C)
(A) 010 (B) 100
(C) 111 (D) 101
(D)
AB [GATE -EC - 2004]
(47) Choose the correct one from among the
AB [GATE -EC - 2003]
alternatives A, B, C, D after matching an
(50) A 4 bit ripple counter and a 4 bit
item from Group 1 with the most appropriate
synchronous counter are made using flip-
item in Group2.
flops having a propagation delay of 10 ns
Group 1 Group 2 each. If the worst case delay in the ripple
P. Shift register 1. Frequency division counter and the synchronous counter be R
and S respectively, Then
Q. Counter 2. Addressing in
memory chips (A) R = 10ns, S = 40ns
R. Decoder 3. Serial to parallel (B) R = 40ns, S = 10ns
data conversion (C) R = 10ns, S = 30ns
(A) P-3, Q-2, R-1 (D) R = 30ns, S = 10ns
(B) P-3, Q-1, R-2 AC [GATE -EC - 2004]
(C) P-2, Q-1, R-3 (51) In the modulo-6 ripple counter shown in the
figure, the output of the 2-input gate is used
(D) P-1, Q-3, R-2
to clear J-K flipflops. The 2-input gate is
AD [GATE -EC - 1999]
(48) The ripple counter shown in the figure works
as a
(A) a NAND gate
(B) a NOR gate
(A) Mod-3 up counter (C) an OR gate
(B) Mod-5 up counter (D) an AND gate
(C) Mod-3 down counter AA [GATE -EC - 2006]
(52) Two D-flip-flops, as shown below, are to be
(D) Mod-5 down counter connected as a synchronous counter that
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DIGITAL ELECTRONICS
goes through the following Q1Q0 sequence
00 01 11 10 00 ........
The inputs D0 and D1 respectively should (A)
be connected as
(B)
(A) Q1 and Q 0
(B) Q0 and Q1
(C) Q1 Q0 and Q1 Q0
(D) Q1 Q0 and Q1 Q0
(C)
AA [GATE -EC - 2009]
(53) What are the counting states ( Q1 , Q 2 ) for the
counter shown in the figure below ?
(D)
(A) 11, 10, 00, 11, 10, .........
AD [IES – EE – 2003]
(B) 01, 1011, 00, 01 ......... (56) The three-stage Johnson Ring Counter as
(C) 00, 11, 01, 10, 00 ......... shown above is clocked at a constant
(D) 01, 10, 00, 01, 10 ......... frequency of fc from the starting state of
AD [GATE -EC - 2011] Q0Q1Q2 101 . The frequency of outputs
(54) Two D flip – flops are connected as a Q 0 Q1Q2 will be
synchronous counter that goes through the
following QB Q A sequence 00 11 01
10 00 ...
The connections to the input D A and D B
are
(A) D A QB , DB Q A
(B) D A Q A , DB Q B
(C) DA (QA Q B Q AQB ), DB QA (A) fc / 8 (B) fc / 6
(D) D A (Q AQB Q A Q B ), DB Q B (C) fc / 3 (D) fc / 2
AA [GATE -EC - 2011] AC [IES – EE – 1999]
(55) The output of a 3-stage Johnson (twisted – (57) The counter shown in the figure has initially
ring) counter is fed to a digital – to – analog Q2Q1Q0 = 000. The status of Q2Q1Q0 after the
(D/A) converter as shown in the figure first pulse is :
below. Assume all states of the counter to be
unset initially. The waveform which
represents the D/A converter output V0 is :
(A) 001 (B) 010
(C) 100 (D) 101
AC [GATE – EC – 1995]
(58) An R-S latch is
Page 66 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) Combinatorial circuit (A) 0 (B) 1
(B) Synchronous sequential circuit. (C) Qn (D) Q n
(C) One bit memory element
AA [IES – EC – 2012]
(D) One clock delay element. (64) If both inputs of S-R NAND latch are low,
AD [GATE – EC – 2003] the output will be
(59) A 0 to 6 counter consists of 3 flipflops and a (A) Unpredictable
combination circuit of 2 input gate(s). (B) Toggle
The combination circuit consists of (C) Reset
(A) one AND gate (D) Remain same
(B) one OR gate AB [IES -EC – 2004/2009]
(C) one AND gate and one OR gate (65) Consider the following statements regarding
registers and latches:
(D) two AND gates
1. Registers are made of edge-triggered
Statement for Linked Answer Questions for FFs, whereas latches are made from
Next Two Questions : level-triggered FFs.
Consider the circuit shown in the following figure. 2. Registers are temporary storage devices
whereas latches are not.
3. A latch employs cross- coupled
feedback connections.
4. A register stores a binary word whereas
a latch does not.
Which of the above statements is/are
correct?
(A) 1 and 2 (B) 1 and 3
(C) 2 and 3 (D) 3 and 4
AD [GATE – EC – 2007] AD [IES -EC - 2009]
(60) The correct input/output relationship (66) Which of the following flip-flop is used as a
between Y and ( X 1 , X 2 ) is latch?
(A) Y X 1 X 2 (A) J K flip-flop
(B) R S flip-flop
(B) Y X 1 X 2
(C) T flip-flop
(C) Y X 1 X 2 (D) D flip-flop
(D) Y X 1 X 2 AA [IES -EC – 2004/2009]
(67) Consider the following statements:
AB [GATE – EC – 2007]
(61) The D flip-flop are initialized to For a master-slave J-K flip-flop,
Q1Q2 Q3 000 . After 1 clock cycle, Q1Q 2 Q3 1. The toggle frequency is the maximum
clock frequency at which the flip-flop
is equal to
will toggle reliably.
(A) 011 (B) 010
2. The data input must precede the clock
(C) 100 (D) 101 triggering edge transition time by some
AB [GATE - IN - 1994] minimum time.
(62) The minimum number of flip – flop required 3. The data input must remain fixed for a
to design a MOD – 10 counter is : given time after, the clock triggering
(A) 3 (B) 10 edge transition time for reliable
(C) 4 (D) 5 operation.
4. Propagation delay time is equal to the
AB rise time and fall time of the data.
(63) The output Qn 1 of a J-K flip – flop for the Which of the above statements is/are
input J = 1, K = 1 is : correct?
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DIGITAL ELECTRONICS
(A) 1, 2 and 3 (B) 1 and 2 only AC,D [IES -EC - 1992]
(C) 2 and 3 only (D) 3 and 4 only (73) The difference between sequential and
combinational circuits is that
AB [IES -EC – 1999/2007/2014] (A) Combinational circuits store bits
(68) A 1 ms pulse can be converted into a 10 ms
(B) Combinational circuits have memory
pulse by using which one of the following?
(C) Sequential circuits store bits
(A) An astable multivibrator
(D) Sequential circuits have memory
(B) A monostable multivibrator
AC
(C) A bistable multivibrator
(74) Which of the following statements are
(D) A J-K flip-flop correct?
AA [IES -EC - 2006] 1. A flip – flop is used to store 1 – bit of
(69) Which one of the following equations information
satisfies the JK flip-flop truth table? 2. Race – around condition occurs in a J-
K flip flop to store 2 – bits of
(A) Qn 1 J n Qn K n Qn
information
(B) Qn 1 J n Qn K n Qn 3. Master – slave configuration is used in
flip flop to store 2 bits of information
(C) Qn 1 J n Qn K n Qn
4. A transparent latch consists of a D –
(D) Qn 1 J n Qn K n Qn type flip flop
Select the correct answer using the codes
AA,B [IES -EC - 1999] given below
(70) In a negative edge triggered J – K flip flop, (A) 1, 2 and 3 (B) 1, 3 and 4
in order to have the output Q state 0, 0 and 1
in the next three successive clock pulses, the (C) 1, 2 and 4 (D) 2, 3 and 4
J – K input states required would be AC [IES – EE – 2010]
respectively (75) In how many different modes a universal
(A) 00, 00 and 10 shift register operates?
(B) 00, 01 and 11 (A) 2 (B) 3
(C) 00, 10 and 11 (C) 4 (D) 5
(D) 01, 10 and 11 AC [IES – EE – 2007]
(76) The reduced state table of a sequential
AA [IES -EC – 2000/2009/2014]
machine has 7 rows. What is the minimum
(71) Consider the following statements
number of flip-flops needed to implement
1. Race around condition occurs in a JK the machine?
flip – flop when both the inputs are one
(A) 0 (B) 2
2. A flip – flop is used to store one bit of
(C) 3 (D) 7
information
3. A transparent latch consists of a D-type AA
flip flop (77) For a JK flip-flop, Qn is output at time step
t n . Which of the following Boolean
4. Master – slave configuration is used in
flip – flops to store two bits of expressions represents Qn 1 ?
information (A) J n Q n K n Q n
Which of these statements are correct? (B) J n Q n K n Q n
(A) 1, 2 and 3 (B) 1, 3 and 4
(C) J n Qn K n Q n
(C) 1, 2 and 4 (D) 2, 3 and 4
(D) J n Qn K n Q n
AD [IES – EC – 2010]
(72) The Q output of a J-K FLIP – FLOP is ‘I’ AB [IES -EC - 1994]
the output does not change when a clock – (78) A synchronous sequential circuit is to be
pulse is applied. The inputs J and K will be designed which will produce an output '1'
respectively (where ‘x’ don’t care state) when previous and present input represent
(A) 0 and x (B) x and 0 an even number, with present input being
least significant bit. The minimum number
(C) 1 and 0 (D) 0 and 0 of states of the machine will be :
Page 68 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) 2 (B) 3 AC [IES – EC – 2011]
(C) 4 (D) 5 (83) An eight-bit binary ripple UP counter with a
modulus of 256 is holding the count
AB [IES -EC - 1998] 01111111. What will be the count after 135
(79) If a mod-6 counter is constructed using 3- clock pulses?
flip - flop, the counter will skip (A) 0000 0101
(A) 4 counter
(B) 1111 1001
(B) 3 counter
(C) 0000 0110
(C) 2 counter
(D) None of the counts (D) 0000 0111
AA [IES – EE – 2005] AA [IES -EC - 2000]
(80) In a ripple counter, the stage whose output (84) Assertion (A): A ring counter is preferred
has a frequency equal to 1/8th that of the over a binary sequential counter
clock signal applied to the first stage, also Reason (R): The decoding logic is simple
has an output periodicity equal to 1/8th that for a ring counter
of the output signal obtained from the last (A) Both A and R is true and R is the
stage. The counter is correct explanation of A
(A) Modulo-8 (B) Modulo-6 (B) Both A and R is true but R is NOT the
(C) Modulo-64 (D) Modulo-16 correct explanation of A
AC [GATE – EE – 2000] (C) A is true but R is false
(81) A dual-slope analog-to-digital converter uses (D) A is false but R is true
an N-bit counter. When the input signal Va AB [IES – EE – 2010]
is being integrated, the counter is allowed to (85) A shift register with the serial output
count up to a value: connected back to the serial input is a
(A) Equal to 2N 2 (A) Feedback shift register
N
(B) Equal to 2 1 (B) Shift register counter
(C) Proportional to Va (C) Universal shift register
(D) Inversely proportional to Va
(D) Serial to parallel converter
AB [IES – EC – 2012] AB [IES – EE – 2012]
(82) Match List I with List II select the correct (86) To operate correctly, starting a ring counter
answer using the code given below the lists : requires
List I (A) Clearing all the flip-flops
(A) 555 (B) Presetting one filp-flop and clearing all
(B) 74173 other
(C) 74163 (C) Clearing one flip-flop and presenting
all other
(D) 8097
(D) Presetting all the flip-flops
List II
AD [IES – EE – 2012]
1. Microcontroller
(87) For a bi-directional synchronous counter
2. Register
(A) Each flip-flop divides the frequency of
3. Timer its clock input by 2
4. Counter (B) Each flip - flop output is used as the
Code : clock input to the next flip - flop
A B C D (C) No decoding logic is required
(A) 3 4 2 1 (D) Each flip-flop is clocked at the same
time
(B) 1 4 2 3
(C) 3 2 4 1 AD [IES -EC - 1999]
(88) The initial state MOD – 16 down counter is
(D) 1 2 4 3 0110. After 37 clock pulses, the state of the
counter will be
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DIGITAL ELECTRONICS
(A) 1011 (B) 0110 (C) A bi stable multi vibrator
(C) 0101 (D) 0001 (D) A J-K flips – flop
AA [IES -EC - 2004] AC [GATE -EC - 1990]
(89) The total number of 1’s in a 15-bit shift (95) A 4 bit modulo-16 ripple counter uses JK
register is to be counted by clocking into a flip-flops. If the propagation delay of each
counter which is present to 0. The counter FF is 50ns, the maximum clock frequency
must have which one of the following. that can be used is equal to:
(A) 4-bits (B) 5-bits (A) 20 MHz (B) 10 MHz
(C) 16-bits (D) 6-bits (C) 5 MHz (D) 4 MHz
AC [IES -EC - 2003] AC[GATE-IN-2002]
(90) Minimum number of J-K flip-flops needed (96) The 14-bit timer is loaded with the counter
to construct a BCD counter is value of 07DOH. The timer input is
(A) 2 (B) 3 connected to a clock with a frequency of 800
KHz. The timer is programmed to produce a
(C) 4 (D) 5 continuous signature wave output. The
AC [IES – EC – 2011] frequency of the square wave output is
(91) A 4-bit ripple counter consisting of flip-flops (A) 400 kHz (B) 800 kHz
that each has a propagation delay of 12ns
from clock to Q output. For the counter to (C) 400 Hz (D) 2000 kHz
recycle from 1111 to 0000, it takes a total of AC[GATE-IN-2003]
(A) 12ns (B) 24ns (97) The clock frequency of a timer-counter is 10
(C) 48ns (D) 26ns MHz. The timer-counter is used in the
period mode and the input to the timer-
AD [GATE - IN - 1995]
counter is a square wave of frequency 2 kHz.
(92) A 4-bit synchronous counter with a series
The display of the timer-counter will show a
carry, uses flip – flop and AND gates,
value
having a propagation delay of 30 ns and 10
ns respectively. The maximum time interval (A) 200 (B) 2000
required between two successive clock (C) 5000 (D) 50000
pulses for reliable operation of the counter is
(A) 10 ns (B) 30 ns AA[GATE-IN-2009]
(98) The figure below shows a 3-bit ripple
(C) 40 ns (D) 50 ns
counter, with Q 2 as the MSB, the flip-flop
AA [GATE - IN - 2002/IES - EE - 2008] are rising-edge triggered. The counting
(93) Consider the following statements in direction is
Johnson counter:
1. A MOD-6 Johnson counter requires 3
FFs.
2. Johnson counter requires decoding
gates. (A) always down
3. To decode each count, one logic gate is
used. Each gate requires only two (B) always up
inputs regardless of the number of FFs. (C) up or down depending on the initial
Which of the statements given above are state of Q0 only
correct? (D) up or down depending on the initial
(A) 1 and 2 only states of Q 2 ,Q1 and Q 0
(B) 2 and 3 only
AC[GATE-IN-2014]
(C) 1 and 3 only
(99) Frequency of an analog periodic signal in the
(D) 1, 2 and 3 range of 5kHz-10kHz is to be measured with
AB [IES -EC - 1995] a resolution of 100Hz by measuring its
(94) A 1 m sec pulse can be converted into a 10 period with a counter. Assuming negligible
m sec pulse by using signal and transition delays the minimum
clock frequency and minimum number of
(A) An astable multi vibrator bits in the counter needed, respectively, are:
(B) A mono stable multi vibrator
Page 70 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) 1 MHz, 10-bits (B) 1 MHz, 10-bits
(C) 1 MHz, 8-bits (D) 10MHz, 8-bits
AC[GATE-EE-2014]
(100) A cascade of three identical modulo-5
counters has an overall modulus of
(A) 5 (B) 25
(C) 125 (D) 625
A*[GATE-IN-2002]
(101) A counter timer has a basic clock of 16
If the clock (Clk) frequency is 1 GHz, then
MHz. The count value displayed is in error
the counter behaves as a
by 1 count. The frequency at which the error
in the displayed value is the same whether (A) mod-5 counter
the counter-time is used in the frequency (B) mod-6 counter
mode of operation or period mode of
operation is (C) mod-7 counter
(A) 15 MHz (B) 10 MHz (D) mod-8 counter
(C) 8 MHz (D) 4 MHz S4AB [GATE–S4–IN–2016]
S1AA [GATE–S1–EC–2016] (104) A synchronous counter using two J - K flip
(102) The block diagram of a frequency flops that goes through the sequence of
states:
synthesizer consisting of a Phase Locked
Loop (PLL) and a divide-by-N counter Q1Q2=00→1→ 01→ 11→ 00….. is
(comprising 2 , 4, 8, 16 outputs) is required. To achieve this, the inputs to the
sketched below. The synthesizer is excited flip flops are
with a 5 kHz signal (Input 1). The free-
running frequency of the PLL is set to 20
kHz. Assume that the commutator switch
makes contacts repeatedly in the order 1-2-
3-4.
(A) J 1 Q 2 , K 1 0; J 2 Q1' , K 2 Q1
(B) J 1 1, K 1 1; J 2 Q1 , K 2 Q1
(C) J 1 Q 2 , K 1 Q 2' ; J 2 1, K 2 1
(D) J 1 Q 21 , K 1 Q 2 ; J 2 Q1 , K 2 Q1'
S3AC [GATE–S3–EC–2016]
(105) The state transition diagram for a finite state
machine with states A, B and C, and binary
inputs X, Y and Z, is shown in the figure.
The corresponding frequencies synthesized
are:
(A) 10 kHz, 20 kHz, 40 kHz, 80 kHz
(B) 20 kHz, 40 kHz, 80 kHz, 160 kHz
(C) 80 kHz, 40 kHz, 20 kHz, 10 kHz
(D) 160 kHz, 80 kHz, 40 kHz, 20 kHz
S4AD [GATE–S4–EC–2016]
(103) For the circuit shown in the figure, the delay
of the bubbled NAND gate is 2 ns and that
of the counter is assumed to be zero. Which one of the following statements is
correct?
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DIGITAL ELECTRONICS
(A) Transitions from State A are (D) It cannot be reliably used as a
ambiguously defined. frequency divider due to disjoint
(B) Transitions from State B are internal cycles.
ambiguously defined. A10 [GATE – IN – 2018]
(C) Transitions from State C are (108) For the 3-bit binary counter shown in the
ambiguously defined. figure, the output increments at every
positive transition in the clock (CLK).
(D) All of the state transitions are defined Assume ideal diodes and the starting state of
unambiguously.
the counter as 000. If output high is 1 V and
AD [GATE–S1–EC–2017] output low is 0 V, the current I (in mA)
(106) A finite state machine (FSM) is flowing through the 50 resistor during
implemented using the D flip-flops A and B, the 5th clock cycle is (up to one decimal
and logic gates, as shown in the figure place) ______.
below. The four possible states of the FSM
are QA QB 00, 01, 10, and 11
Assume that XIN is held at constant logic
level throughout the operation of the FSM.
When the FSM is initialized to the AC [GATE – IN – 2018]
QA QB 00 and clocked, after a few clock (109) A 2-bit synchronous counter using two J-K
cycles, it starts cycling through flip flops is shown. The expressions for the
inputs to the J-K flip flops are also shown in
(A) all of the four possible states if X IN 1 the figure. The output sequence of the
(B) three of the four possible states if counter starting from Q1Q2 00 is
XIN 0
(C) only two of the four possible states if
X IN 1
(D) only two of the four possible states if
XIN 0
AB [GATE – EE – 2018] (A) 00 11 10 01 00 ...
(107) Which one of the following statements is
true about the digital circuit shown in the (B) 00 01 10 11 00 ...
figure
(C) 00 01 11 10 00 ...
(D) 00 10 11 01 00 ...
A4 [GATE-EC-2019]
(110) In the circuit shown, the clock frequency,
i.e., the frequency of the CLK signal, is 12
kHz. The frequency of the signal at Q2 is
_____ kHz.
(A) It can be used for dividing the input
frequency by 3.
(B) It can be used for dividing the input
frequency by 5.
(C) It can be used for dividing the input
frequency by 7.
Page 72 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
AD [GATE-IN-2019]
(111) The circuit shown in the figure below uses
ideal positive edge-triggered synchronous J-
K flip flops with outputs X and Y. If the
initial state of the outputs is X = 0 and Y = 0
just before the arrival of the first clock pulse,
the state of the output just before the arrival
of the second clock pulse is :
(A) X = 0, Y = 0 (B) X = 0, Y = 1
(C) X = 1, Y = 0 (D) X = 1, Y = 1
*********
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DIGITAL ELECTRONICS
5.2 Miscellaneous (A) 0001 (B) 0011
(C) 0100 (D) 1100
AA [GATE – IN – 2015]
(1) For the circuit shown in the figure, the AB [GATE-EE-2014]
raising edge triggered D –flip flop with (4) A JK flip flop can be implemented by T flip-
asynchronous reset has a clock frequency of flops. Identify the correct implementation.
1 Hz . The NMOS transistor has an ON
(A)
resistance of 1000 and an OFF resistance
of infinity. The nature of the output
waveform is
(B)
(A)
(B)
(C)
(D) (C)
AD [GATE – EC3 – 2015]
(2) An SR latch is implemented using TTL gates
as shown in the figure. The set and reset
pulse inputs are provided using the push-
button switches. It is observed that the
circuit fails to work as desired. The SR latch
can be made functional by changing
(D)
(A) NOR gates to NAND gates
(B) inverts to buffers
(C) NOR gates to NAND gates and
inverters to buffers
(D) 5 V to ground
AB [IES – EE – 1996]
(3) For the digital circuit shown in the given AB [IES – EE – 1997]
figure, the output Q 3Q 2Q1Q 0 = 0001 initially. (5) To realize the given truth table from the
circuit shown in the figure, the input to J in
After a clock pulse appears, the output terms of A and B would have to be
Q 3Q 2Q1Q 0 will be
Page 74 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) S = 0 C0 0
(B) S = 0 C0 1
(C) S = 1 C0 0
(D) S = 1 C0 1
(A) AB (B) A AC [GATE -EC -2007 ]
(C) B (D) AB (8) The following binary values ware applied to
AB[GATE-IN-2015] the X and Y inputs of the NAND latch
(6) The number of clock cycles for the duration shown in the figure in the sequence indicated
of an input pulse is counted using a cascade below:
of N decade counters (DC 1 to DC N) as X 0, Y 1; X 0, Y 0; X 1, Y 1.
shown in the figure. If the clock frequency in
The corresponding stable P, Q outputs will
mega hertz is f, the resolution and range of
be
measurement of input pulse width, both in
s , are respectively,
(A) P = 1, Q = 0; P = 1, Q = 0; P=1, Q=0 or
p = 0, Q=1
(B) P = 1, Q = 0; P = 1, Q = 0; or P=0,
Q=1; P=1, Q=0
(C) P = 1, Q = 0; P = 1, Q = 1; P=1, Q=0;
or P=0, Q=1
(D) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
1 (2 N 1)
(A) and
f f AA [IES – EE – 2008]
(9) In the circuit shown in the figure, Q = 0,
1 (10 N 1) initially. What shall be the subsequent states
(B) and
f f of Q when clock pulses are given ?
10 N (10 N 1)
(C) and
f f
2N (2 N 1)
(D) and
f f
AD[GATE-EC-2006]
(A) 1, 0, 1, 0, ........
(7) For the circuit shown in the figure below,
two 4-bit parallel-in serial-out shift registers (B) 0, 0, 0, 0, .........
loaded with the data shown are used to feed
the data to a full adder. Initially, all the flip- (C) 1, 1, 1, 1, .........
flops are in clear state. After applying two (D) 0, 1, 0, 1, .........
clock pulses, the outputs of the full adder
should be AD [IES – EE – 2000]
(10) The states of a RS flip-flop are given in the
following table :
States R S Qn Qn+1
1 0 0 1 1
2 0 1 0 1
3 1 0 1 0
The mode of operation of states 1, 2 and 3
are respectively
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DIGITAL ELECTRONICS
(A) Indeterminate, set and reset What is the output of the combinational
logic circuit to the J input?
(B) Prohibited, set and hold
(A) AB (B) A
(C) Set, hold and reset
(C) B (D) AB
(D) Hold, set and reset
AA [IES – EE – 2010]
AD [IES – EE – 2003] (15) Assertion(A):
(11) T flip-flop can be made from a J-K flip-flop
by making D flip-flops are used to construct a buffer
registers.
(A) J = K (B) J = K = 1
Reason(R):
(C) J = 0, K = 1 (D) J = K=T
Buffer registers are used to store binary
AC [IES – EE – 2006] word temporarily.
(12) What is represented by the digital circuit
given below? AA [IES – EC – 1991]
(16) Find radix of the system shown in the figure
below
(A) An SR flip-flop with A = S and B = R
(B) A JK flip-flop with A = K and B = J (A) 2 (B) 4
(C) A JK flip-flop with A = J and B = K (C) 6 (D) 8
(D) An SR flip-flop with A = R and B = S AD [IES – EC – 1991]
(17) What will be the state of the output after the
AB [GATE – EE – 2002/IES - EE - 2007] third clock cycle?
(13) The frequency of the clock signal applied to
the rising edge triggered D flip-flop shown
in the above figures is 10 kHz. What is the
frequency of the signal available at Q?
QA QB
(A) LO LO
(A) 2.5 kHz (B) 5 kHz (B) HI LO
(C) 10 kHz (D) 20 kHz (C) LO HI
AB [IES – EE – 2008] (D) HI HI
(14) The following truth table has to be realized
with the circuit shown in the figure: AD [IES – EC – 1992]
(18) The race around condition exists in J – K
flips flop if
(A) J = 0; K =1
(B) J = 0; K = 1
A B Qn+1 (C) J = 0; J = 0
0 0 Qn (D) J = 1; K = 1
0 1 1
AA [IES – EC – 1992]
1 0 Qn (19) In a JK flip – flop, the output Qn is 1 and it
1 1 0 does not change when a clock pulse applied.
Page 76 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
The possible combination of Jn and Kn could 1. It must have at least six gates
be (x denotes don’t care) 2. It must have some feedback
(A) x and 0 (B) x and 1 3. Its output should depend on some past
(C) 0 and x (D) 1 and x value.
Codes :
AB [IES – EC – 1994]
(A) 1, 2 and 3 (B) 1 and 2
(20) Which one of the following circuits converts
an RS flip flop to T flip flop? (C) 2 and 3 (D) 1 and 3
(A) AA [IES – EC – 1995]
(24) Which one of the circuits given below
converts a JK F/F to a T F/F?
(A)
(B)
(B)
(C)
(C)
(D)
(D)
AB [IES – EC – 1994/2013]
(21) In a sequential circuits, the output at any AD [IES – EC – 1995]
instant of time depend (25) An input frequency of 12 KHz is applied to
(A) Only on the inputs present at that the J – K flips – flop arrangement shown in
instant of time the given figure. The resulting output
frequency will be
(B) On past output as well as present inputs
(C) Only on the past inputs
(D) Only on the past outputs
AA [IES – EC – 1995]
(22) Given A = 1, B=1, Qn = 0 and Pn =1 what
will be output Qn+1 and Pn+1 when the clock (A) 24 KHz (B) 12 KHz
input (CK) is applied? (C) 6 KHz (D) 3 KHz
AB [IES – EC – 1996/2007/2015]
(26) For the circuits shown in the given figure,
the frequency of the output Q will be.
(A) Qn 1 0, Pn 1 0
(B) Qn 1 0, Pn 1 1
(C) Qn 1 1, Pn 1 0
(A) Twice the input clock frequency
(D) Qn 1 1, Pn 1 1 (B) Half the input clock frequency
AC [IES – EC – 1995] (C) Same as the input clock frequency
(23) Which of the following characteristics are (D) Inverse of the propagation delay of the
necessary for sequential circuits? EF
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DIGITAL ELECTRONICS
AC [IES – EC – 1997]
(27) Shift register with associated waveform is
shown in the following figure: Which of
these is/are correct?
(A) 0000 (B) 0101
(C) 1010 (D) 1110
AD [GATE – EC – 1997]
(32) Consider the following J-K flip-flop :
In the given J-K flip-flop,
J Q and K = 1. Assume that the flip-flop
was initially cleared and then clocked for 6
(A) X1 alone (B) X2 alone pulses. What is the sequence at the Q
output?
(C) X3 alone (D) X1, X2 and X3
(A) 010000 (B) 011001
AA [IES – EC – 2000]
(C) 010010 (D) 010101
(28) A T- flip – flop function is obtained from a
JK flip – flop. If the flip – flop belongs to a AD [IES – EC – 2005]
TTL family, the connection needed at the (33) Match List-I (Type of flip-flop) with List-II
input must be (Symbol) and select the correct answer using
(A) J = K = 1 (B) J = K = 0 the code given below the lists :
(C) J = 1 and K = 0 (D) J = 0 and K = 1 List-I
AB [IES – EC – 2012] A. T flip-flop
(29) The characteristic equation of the T-flip-flop B. Level-triggered JK flip-flop
is given by
C. Leading edge-triggered JK flip-flop
(A) Q TQ TQ
D. Trailing edge-triggered JK flip-flop
(B) Q TQ QT
List II
(C) Q T Q 1.
(D) Q TQ
AC [IES – EC – 2003/2007]
(30) The characteristic equation for the next state
( Q n 1 ) of a J-K flip-flop is 2.
(A) Qn 1 JQn K Q n
(B) Qn 1 J Qn K Q n
(C) Qn 1 J Qn KQn 3.
(D) Qn 1 JQn K Qn
AC [GATE– EC – 1992]
(31) The initial contents of the 4-bit serial-in-
parallel-out, right shift, shift register as
shown in figure above are 0110. After 3 4.
clock pulses, he contents of the shift register
will be
Page 78 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
Codes : AD [IES – EC – 2009]
(38) Match List I with List II and select the
A B C D
correct answer using the code given below
(A) 1 2 3 4 the lists:
(B) 2 1 3 4 List I
(C) 1 2 4 3 (Application of Circuit)
1. Divider
(D) 2 1 4 3
2. Clips input voltage at two
AA [IES – EC – 2007] predetermined levels
(34) The characteristic equation of a flip-flop 3. Square wave generator
gives the next state QN 1 in terms of the 4. Narrow current pulse generator
present state QN and the inputs. Which one List II
of the following is the characteristic (Circuit Name)
equation of J-K flip-flop? 1. Astable multivibrator
(A) QN 1 J Q N KQN 2. Schmitt trigger
(B) QN 1 J KQN 3. Bistable multivibrator
4. Blocking oscillator
(C) QN 1 KQN JQN
Codes:
(D) QN 1 1 JQN
A B C D
AB [IES – EC – 2007] (A) 4 2 1 3
(35) For the circuit shown in the figure below, (B) 3 2 1 4
what is the frequency of the output Q?
(C) 4 1 2 3
(D) 3 1 2 4
AA,B [IES – EC – 2009]
(39) Which of the following conditions should be
satisfied to call an astable multivibrator
(A) Twice the input clock frequency circuit using discrete components as a digital
(B) half the input clock frequency circuit?
(C) Same as the input clock frequency 1. A flip-flop is always a digital circuit.
(D) Inverse of the propagation delay of the
2. Only when we assign 1 and 0 to the
FF
high and low levels of the output, a
AB [IES – EC – 2008] flip-flop is called a digital circuit.
(36) Assertion(A): 3. Only if the power supply voltage is
D-Flip-Flops are used as buffer register. maintained at +5V or -5V, it is called a
digital circuit.
Reason (R):
4. Only if it is in IC from, following the
D-Flip-Flops are free from “race-around”
technology of IC manufacture, it is
condition.
called a digital circuit.
AC [IES – EC – 2008] Select the correct answer from the codes
(37) The circuit is given below illustrates a given below:
typical application of the JK flip-flops. What
does this represent? (A) 1 only (B) 2 and 3
(C) 2 only (D) 3 and 4
AA [GATE-EC/EE/IN-2012]
(40) Consider the given circuit.
(A) A shift register
(B) A data storage device
(C) A frequency divider circuit
(D) A decoder circuit
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DIGITAL ELECTRONICS
In this circuit, the race around
(A) Does not occur
(B) Occurs when CLK = 0
(C) Occurs when CLK = 1 and A = B = 1
(A) 3 (B) 7
(D) Occurs when CLK = 1 and A = B = 0
(C) 11 (D) 15
AB [IES – EC – 2009]
AD [IES – EC – 2010]
(41) Which of the following capabilities are
(44) The J-K flip-flop shown below is initially
available in a Universal Shift Register?
rest, so that Q = 0. If a sequence of four
1. Shift left clock pulses is then applied, with the J and K
inputs as given in the figure, the resulting
2. Shift right sequence of values that appear at the output
3. Parallel load Q starting with its initial state, is given by
4. Serial add
Select the correct answer from the codes
given below:
(A) 2 and 4 only
(B) 1, 2 and 3 (A) 01011 (B) 01010
(C) 1, 2 and 4 (C) 00110 (D) 00101
(D) 1, 3 and 4 AD [GATE – EE – 2003]
AC [IES – EC – 2010] (45) An X-Y flip flop, whose characteristic table
(42) Analyze the sequential circuit shown above is given below is to be implemented using J-
in figure. Assuming that initial sequence K flip flop. This can be done by making
would lead to state 11? X Y Q n 1
0 0 1
0 1 Qn
1 0 Qn
1 1 0
(A) J X , K Y
(B) J X , K Y
(C) J Y , K X
(A) 1 – 1 (D) J Y , K X
(B) 1 – 0
AD [GATE - IN - 2004]
(C) 0 – 0 (46) The two NAND gates before the latch circuit
(D) State 11 is unreachable shown in Fig. are used to
AB [GATE – EE – 2003]
(43) The shift register shown in the given figure
is initially loaded with the bit pattern 1010.
Subsequently the shift register is clocked,
and with each clock pulse the pattern gets
shifted by one bit position to the right. With
each shifted by one bit position to the right.
With each shift, the bit at the serial input is (A) act as buffers
pushed to the left most position (msb). After (B) operate the latch faster
how many clock pulses will be content of
(C) avoid racinig problem
the shift register become 1010 again?
(D) invert the latching action
Page 80 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
AB [GATE - IN - 2008] AA [GATE - IN - 2004]
(47) The inverters in the ring oscillator circuit (51) In Fig. initially Q = A = B = 0. After three
shown below are identical. If the output clock triggers, the state of Q, A and B will
waveform has a frequency of 10 MHz, the be respectively
propagation delay of each inverter is
(A) 5ns (B) 10ns
(C) 20ns (D) 50ns
AC [GATE - IN - 2009]
(48) In the figure shown, the initial state of Q is
0. The output is observed after the (A) 110
application of each clock pulse. The output
sequence at Q is (B) 011
(C) 011
(D) 101
AC [GATE - IN - 2004]
(52) In the digital circuit shown in Fig. the flip
flops have set time of 5 ns and a worst case
(A) 0000.. (B) 1010... delay of 15 ns. The AND gate has a delay of
(C) 1111... (D) 1000... 5 ns. Maximum possible clock rate for the
circuit to operate faithfully is
AA [GATE - IN - 2001]
(49) In the circuit shown in Fig. when inputs A =
B = 0, the possible logic states of C and D
are
(A) 21 MHz (B) 2 MHz
(A) C = 0, D = 1 or C = 1, D = 0 (C) 25 MHz (D) 30 MHz
(B) C = 1, D = 1 or C = 0, D = 0 AB [GATE - IN - 2006]
(C) C = 1, D = 0 (53) All the logic gates in the circuit shown
below have finite propagation delay. The
(D) C = 0, D = 1 circuit can be used as a clock generator, if
AB [GATE - IN - 2003]
(50) The correct cyclic sequence of the outputs
(Q0 Q1 ) for the JK master – slave flip – flop
circuit shown in Fig. when the input clock is
applied is
(A) X = 0 (B) X = 1
(C) X = 0 or 1 (D) X = Y
AC [GATE - IN - 2007]
(54) A sequential circuit is shown in the figure
below. Let the state of the circuit be encoded
(A) 00, 01, 10, 11, 00, 01, .... as QAQB . The notation X Y implies
(B) 00, 10, 01, 00, 10, 01, .... that state Y is reachable from state X in a
finite number of clock transitions. Identify
(C) 00, 01, 10, 00, 01, 10, ...
the INCORRECT statement.
(D) None
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DIGITAL ELECTRONICS
(A) For Vi 2v, P 0
(A) 01 00 (B) For Vi 3v, P 0
(B) 11 01
(C) For Vi 0v , P 0 always
(C) 01 11
(D) For Vi 0v , P can be either 0 or 1.
(D) 01 10
AB [GATE - EE - 2005] AA [GATE -EC - 1987]
(55) Select the circuit which will produce the (57) A ripple counter using negative edge-
given output Q for the input signals X1 and triggered D-flip flops is shown in Fig. The
flip-flops are cleared to ‘0’ at the R input.
X 2 given in the figure. The feedback logic is to be designed to
obtain the count sequence shown in the same
figure. The correct feedback logic is:
(A)
(A) F Q2Q1 Q0 (B) F Q 2 Q1 Q 0
(C) F Q 2 Q1Q 0 (D) F Q 2 Q1 Q 0
(B) AC [GATE -EC - 1988]
(58) The circuit given below is a
(C)
(A) J-K Flip-flop
(B) Johnson’s counter.
(C) R-S latch
(D) (D) None of above
AFaster [GATE -EC - 1994]
(59) Synchronous counters are ________ than the
ripple counters.
AB [GATE -EC - 1987]
AD [GATE -EC - 1995]
(56) Choose the correct statements relating to the
(60) A switch-tail ring counter is made by using a
circuit of figure
single D flip-flop. The resulting circuit is a
Page 82 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
(A) SR flip-flop (B) JK flip-flop (A) S-R Flip-flop with inputs X = R and Y
(C) D flip-flop (D) T flip-flop =S
(B) S-R Flip-flop with inputs X = S and Y
AC [GATE -EC - 1998] =R
(61) Figure shows a mod-K counter, Here K is (C) J-K Flip-flop with inputs X = J and Y =
equal to K
(D) J-K Flip-flop with inputs X = K and Y
=J
AB [GATE -EC - 2000]
(65) In the figure, the J and K inputs of all the
four flipflops are made high. The frequency
of the signal at output Y is
(A) 1 (B) 2
(C) 3 (D) 4
AD [GATE -EC - 2010]
(62) Assuming that all flip-flops are in reset
(A) 0.833 KHz (B) 1.0 KHz
condition initially, the count sequence
observed at Q A in the circuit shown is (C) 0.91 KHz (D) 0.77 KHz
AB [GATE -EC - 2008]
(66) For each of the positive edge-triggered J-K
flip-flop used in the following figure, the
propagation delay is T
(A) 0010111.... (B) 0001011....
(C) 0101111.... (D) 0110100...
AA [GATE -EC - 2011]
(63) When the output Y in the circuit below is
“1”, it implies that data has
Which of the following waveforms correctly
(A) changed from “0” to “1” represents the output at Q1 ?
(B) changed from “1” to “0”
(C) changed in either direction
(A)
(D) not changed
AD [GATE -EC - 2000]
(64) A sequential circuit using D Flip-flop and
logic gates is shown in the figure, where X (B)
and Y are the inputs and Z is the output. The
circuit is :
(C)
(D)
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DIGITAL ELECTRONICS
AA [IES – EC – 1997] (A) 1s (B) 2s
(67) The output Qn of a J-K filp-flop is zero. It
changes to 1 when a clock pulse is applied. (C) 8s (D) 16s
The input Jn and Kn are respectively
AB
(A) 1 and X (B) 0 and X (74) Consider the following statements regarding
(C) X and 0 (D) X and 1 registers and latches:
1. Registers are made of edge-triggered
AA [IES - EE - 2008] FFs, whereas latches are made from
(68) A J.K flip-flop can be made from an S-R level-triggered FFs.
flip-flop by using two additional 2. Registers are temporary storage devices
(A) AND gates (B) OR gates whereas latches are not.
3. A latch employs cross- coupled
(C) NOT gates (D) NOR gates feedback connections.
AB [IES -EC - 1992] 4. A register stores a binary word whereas
(69) Which of the following is not a characteristic a latch does not.
of a flip flop? Which of the above statements is/are
correct?
(A) The flip – flop is a bi – stable device
with only two stable states (A) 1 only (B) 1 and 3
(C) 2 and 3 (D) 3 and 4
(B) The flip – flop has two input signals
AC
(C) The flip – flop has two output signals (75) Consider the following statements:
(D) The outputs are complement of each 1. A flip-flop is used to store 1-bit of
other information.
AB [IES -EC - 1992] 2. Race-around condition occurs in a J-K
(70) By placing an inverter between both inputs flip-flop when both the inputs are 1.
of an S-R filp-flop, the resulting filp - flop
3. Master-slave configuration is used in
becomes
flip-flops to store 2-bits of information.
(A) J-K filp-flop
4. A transparent latch consists of a D-type
(B) D- filp-flop flip-flop.
(C) T - flip-flop Which of the above statements is/are
(D) Master slave JK flip-flop correct?
AA (A) 1 only (B) 1, 3 and 4
(71) A 1 µ s pulse can be converted into a 1 ms (C) 1, 2 and 4 (D) 2 and 3 only
pulse by using
(A) A mono stable multivibrator AD
(76) Consider the following statements regarding
(B) An astable multivibrator registers and latches :
(C) A bi – stable multivibrator
1. Registers are temporary storage
(D) A J – K flip – flop devices, whereas latches are not.
AA [IES -EC - 2003] 2. A latch employs cross-coupled
(72) The output of a Moore sequential machine is feedback connections.
a function of
3. A register stores a binary word,
(A) All present states of the machine whereas a latch does not.
(B) All the inputs The correct statement(s) is/are
(C) A few combination of inputs and the
(A) 1 only (B) 2 only
present state
(D) All the combinations of inputs and the (C) 1 and 3 (D) 2 and 3
present state A0.5 [GATE - EE - 1995]
AC [IES -EC - 2001] (77) For a J-K flip-flop its J input is tied to its
(73) The 54/74164 chip is an 8-bit serial-input- own Q output and its K input is connected to
parallel-output shift register. The clock is its own Q output. If the flip-flop is fed with a
1MHz. The time needed to shift an 8-bit clock of frequency 1 MHz, its Q output
binary number into the chip is frequency will be ___________.
Page 84 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
AD [IES -EC - 1992] are Q1 1 , Q2 0 , the states after the
(78) Which of the following flip – flop cannot be arrival of the clock edge are Q1 …….,
converted to D – type (Delay) flip – flop
Q2 ………
(A) S – R flip flop
(B) J – K flip flop
(C) Master slave flip flop
(D) None of the above
AB [IES -EC - 1997]
(79) For the design of sequential circuits having
nine state MINIMUM number of memory
AD[GATE-IN-1994]
elements required is:
(84) The output Qn1 of a J-K flip-flop for the
(A) 3 (B) 4 input J=1, K=1 is
(C) 5 (D) 9 (A) 0 (B) 1
AC [IES -EC - 2002] (C) Qn (D) Qn
(80) A sequence detector is required to given a
logical output of 1 whenever the sequence A*[GATE-IN-1995]
1011 is detected in the incoming pulse (85) Figure shows a sequential circuit with four J-
stream. Minimum number of flip-flops K flip-flops. Generate a table of output
needed to build the sequence detector is : ( Q 3 Q 2 Q1Q 0 ) changes with each clock pulse.
Start with Q 3Q 2 Q1Q 0 0001 and complete a
(A) 4 (B) 3
full cycle.
(C) 2 (D) 1
AC [IES -EC - 2006]
(81) A master slave configuration consists of two
identical flip-flops connected in such a way
that the output of the master is input to the
slave.
Which one of the following is correct?
(A) Master is level triggered and slave is
edge triggered
(B) Master is edge triggered and slave is AB[GATE-IN-2013]
level triggered (86) The digital circuit shown below uses two
negative edge-triggered D-flip-flops.
(C) Master is positive edge triggered and Assuming initial condition of Q1 and Q 0 as
slave is negative edge triggered
zero, the output Q1 , Q0 of this circuit is
(D) Master is negative edge triggered and
salve is positive edge triggered
AC [GATE – EC – 2004]
(82) A master slave flip-flop has the
characteristic that
(A) change in the input immediately
effected in the output
(B) change in the output occurs when the
site of the master is affected
(C) change in the output occurs when the (A) 00, 01, 10, 11, 00 …
state of the slave is affected (B) 00, 01, 11, 10, 00 …
(D) both the master and the slave states are (C) 00, 11, 10, 01, 00 …
affected at the same time. (D) 00, 01, 11, 11, 00 …
A0, 1 [GATE-IN-1993] A*[GATE-EC-1991]
(83) A sequential circuit formed by two edge (87) An S-R FLIP-FLOP can be converted into a
triggered JK flip flops is shown in figure. If T FLIP-FLOP by connecting to ______ Q
the states before the arrival of a clock edge
and _______to Q .
www.targate.org Page 85
DIGITAL ELECTRONICS
AC[GATE-EC-2005]
(88) The present output Q n of an edge triggered
JK flip-flop is logic 0. If J = 1, then Q n+1
(A) cannot be determined
(B) will be logic 0
(C) will be logic 1
(D) will race around
AC[GATE-EC-2008]
(89) For the circuit shown in the figure, D has a
transition from 0 to 1 after CLK changes
from 1 to 0. Assume gate delays to be
negligible
Which of the following statements is true ?
(A) Q goes to 1 at the CLK transition and AA[GATE-EE-2008]
stays at 1. (92) The truth table of a monoshot shown in the
(B) Q goes to 0 at the CLK transition and figures is given in the table below :
stays at 0.
Two monoshots, one positive edge triggered
(C) Q goes to 1 at the CLK transition and and other negative edge triggered, are
goes to 0 when D goes to 1. connected shown in the figure. The pulse
(D) Q goes to 0 at the CLK transition and widths of the two monoshot outputs, Q1 and
goes to 1 when D goes to 1. Q2 are and TON1 and TON2 respectively.
AC[GATE-EC-2009]
(90) Refer to the NAND and NOR latches shown
in the figure. The inputs ( P1 , P2 ) for both the
latches are fist made (0, 1) and then, after a
few seconds, made (1, 1). The corresponding
stable outputs ( Q1 , Q 2 ) are
The frequency and the duty cycle of the
signal of Q1 will respectively be
(A) NAND: first (0, 1) then (0, 1) NOR: 1 TON1
(A) f ,D
first (1, 0) then (0, 0) TON1 TON2 TON1 TON2
(B) NAND: first (1, 0) then (0, 1) NOR:
first (1, 0) then (0, 0) 1 TON2
(C) NAND: first (1, 0) then (1, 0) NOR: (B) f ,D
TON1 TON2 TON1 TON2
first (1, 0) then (0, 0)
(D) NAND: first (1, 0) then (1, 1) NOR: 1 TON1
first (1, 0) then (0, 1) (C) f ,D
TON1 TON1 TON2
AB[GATE-EE-2004]
(91) The digital circuit shown in figure generates 1 TON1
a modified clock pulse at the output. Choose (D) f ,D
the correct output waveform from the TON2 TON1 TON2
options given below.
Page 86 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
AB[GATE-EE-2013]
(93) The clock frequency applied to the digital
circuit shown in figure below is 1 kHz. If the
initial state of the output Q of the flip-flop is
'0', then the frequency of the output The average power dissipated (in mW) in the
waveform Q in kHz is resistor is ________
S6AC [GATE–S6–EE–2016]
(96) The current state QA QB of a two JK flip-flop
system is 00. Assume that the clock rise-
time is much smaller than the delay of the
JK flip-flop. The next state of the system is
(A) 0.25 (B) 0.5
(C) 1 (D) 2
AC[GATE-EE-2014]
(94) Two monoshot multivibrators, one positive
edge triggered ( M1 ) and another negative
edge triggered ( M 2 ), are connected as
shown in figure.
(A) 00 (B) 01
(C) 11 (D) 10
AB [GATE – IN – 2017]
(97) The two inputs A and B are connected to an
The monoshot M1 and M 2 when triggered R-S latch via two AND gates as shown in
the figure. If A = 1 and (B = 0), the output
produce pulses of width T1 and T2
QQ is
respectively, where T1 >T2 . The steady state
output voltage V0 of the circuit is
(A)
(B)
(A) 00 (B) 10
(C) 01 (D) 11
A6 [GATE–S2–EE–2017]
(C) (98) For the synchronous sequential circuit
shown below, the output Z is zero for the
initial conditions QAQB QC Q 'A Q B' Q C' 100.
(D)
S3A1.45:1.55 [GATE–S3–EC–2016]
(95) Assume that all the digital gates in the
circuit shown in the figure are ideal, the
resistor = 10 Ω and the supply voltage is
5 . The D flip-flops D1 , D2, D3 , D4 and D5
are initialized with logic values 0,1,0,1 and
0, respectively. The clock has a 30% duty
cycle.
www.targate.org Page 87
DIGITAL ELECTRONICS
The minimum number of clock cycles after (A) X = ‘1’, Y = ‘1’
which the output z would again become zero (B) either X = ‘1’, Y = ‘0’ or X = ‘0’, Y =
is ___________ . ‘1’
(C) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y =
A4 [GATE–S2–EC–2017]
‘0’
(99) The state diagram of a finite state machine
(FSM) designed to detect an overlapping (D) X = ‘0’, Y = ‘0’
sequence of three bits is shown in the figure. A29.9-30.1 [GATE–S1–EC–2017]
The FSM has an input ‘In’ and an output (102) Consider the D-Latch shown in the figure,
‘Out’. The initial state of the FSM is S 0 . which is transparent when its clock input CK
is high and has zero propagation delay. In
the figure, the clock signal CLK1 has a 50%
duty cycle and CLK2 is a one-fifth period
delayed version of CLK1. The duty cycle at
the output of the latch in percentage is
_________.
If the input sequence is 10101101001101,
starting with the left-most bit, then the
number of times ‘Out’ will be 1 is _____.
A10 [GATE–S1–EC–2017]
(100) A 4-bit shift register circuit configured for
right-shift operation, i.e.
Din A,A B,B C,C D, is shown.
If the present state of the shift register is A0.82-0.86 [GATE – EC – 2018]
ABCD = 1101, the number of clock cycles (103) In the circuit shown below, a positive edge-
required to reach the state ABCD = 1111 is triggered D Flip-Flop is used for sampling
________ input data Din using clock . The XOR
gate outputs 3.3 volts for logic HIGH and 0
volts for logic LOW levels. The data bit and
clock periods are equal and the value of
T / TCK 0.15 , where the parameters
T and TC K are shown in the figure.
Assume that the Flip-Flop and the XOR gate
AB [GATE–S1–EC–2017]
are ideal.
(101) In the latch circuit shown, the NAND gates
havw non-zero, but unequal propagation
delays. The present input condition is: P = Q
= ‘0’. If the input condition is changed
simultaneously to P = Q = ‘1’, the outputs X
and Y are
Page 88 TARGATE EDUCATION GATE-( EC /EE)
Topic 05 - Sequential Digital Circuits
If the probability of input data bit ( Din ) AA [GATE-IN-2019]
transition in each clock period is 0.3, the (106) In the circuit below, the light dependent
average value (in volts, accurate to two resistor (LDR) receives light from the LED.
decimal places) of the voltage at node X, is The LDR has resistances of 5k and
_______. 500 under dark and illuminated
conditions, respectively. The LED is OFF at
A5 [GATE – EC – 2018]
(104) A traffic signal cycles from GREEN to time t 0 . At time t 0 s, the switch S1 is
YELLOW, YELLOW to RED and RED to closed for 1 ms and then kept open
GREEN. In each cycle, GREEN is turned on thereafter. Assuming zero propagation delay
for 70 seconds, YELLOW is turned on for 5 in the devices, the LED
seconds and the RED is turned on for 75
seconds. This traffic light has to be
implemented using a finite state machine
(FSM). The only input to this FSM is a clock
of 5 second period. The minimum number of
flip-flops required to implement this FSM is
_______.
AD [GATE-EC-2019]
(105) The state transition diagram for the circuit
shown is (A) turns ON when S1 is closed and
remains ON after S1 is opened
(B) turns ON when S1 is closed and turns
OFF after S1 is opened
(C) turns ON when S1 is closed and toggles
periodically from ON to OFF after S1 is
opened
(D) remains OFF when S1 is closed and
continues to remain OFF after S1 is
opened.
-------0000-------
(A)
(B)
(C)
(D)
www.targate.org Page 89
06
Semiconductor Memories
AB [GATE - EE - 2009] (A) 16 (B) 48
(1) The increasing order of speed of data access (C) 64 (D) 104
for the following devices is
AC [IES – EC – 1995]
(i) Cache Memory
(7) Match List – I with List – II and select the
(ii) CDROM correct answer using the codes given below
(iii) Dynamic RAM the lists.
(iv) Processor Registers List – I (Memories)
(v) Magnetic Tape A. Static PL memory
(A) (v), (ii), (iii), (iv), (i) B. CCD Memory
(B) (v), (ii), (iii), (i), (iv) C. ECL Memory
(C) (ii), (i), (iii), (iv), (v) D. GAL memory
(D) (v), (ii), (i), (iii), (iv) List – II (Particular characteristic)
1. Erasable programmable
AD [GATE -EC - 1994] 2. Ultra high speed
(2) A PLA can be 3. Stores large volume of data
(A) as a microprocessor 4. Does not need redressing
(B) as a dynamic memory 5. Non – Volatile
(C) to realize a sequential logic Codes :
(D) to realize a combinational logic. A B C D
AC [GATE -EC - 1994] (A) 4 3 2 1
(3) A dynamic RAM consists of (B) 4 2 3 1
(A) 6 transistors (C) 5 1 2 3
(B) 2 transistors and 2 capacitors (D) 3 5 2 1
(C) 1 transistor and 1 capacitor AB [IES – EC – 2000]
(D) 2 capacitors only (8) Which one of the following statements is
correct?
AB [GATE -EC - 1995]
(4) The minimum number of MOS transistors (A) RAM is a non-volatile memory
required to make a dynamic RAM cell is whereas ROM is a volatile memory
(A) 1 (B) 2 (B) RAM is a volatile memory whereas
ROM is non – volatile memory
(C) 3 (D) 4
(C) Both RAM and ROM data is not lost
AC [GATE -EC - 2001] when power is switched off
(5) An 8085 microprocessor based system uses
a 4k x 8bit RAM whose starting address is (D) Both RAM and ROM are non-volatile
AAOO H. The address of Last byte in this memories but in RAM data is lost when
power is switched off.
RAM is
(A) 0FFF H (B) 1000 H AC [IES – EC – 2001/2015]
(9) Four memory chips of 16 4 size have their
(C) B9FF H (D) BA00 H
address buses connected together. This
ANone [IES – EC – 1992] system will be of size
(6) The number of NAND gate required for two (A) 64 4 (B) 16 16
dimensional addressing of 256 x 8 bit ROM
using 8 to 1 selectors is (C) 32 8 (D) 256 1
Page 90 TARGATE EDUCATION GATE-( EC /EE)
Topic 06 - Semiconductor Memories
AC [IES – EC – 2002] (D) PLA contains a programmable ‘AND’
(10) A typical cell, for a dynamic RAM can be array and programmable ‘OR’ array
implemented by using how many MOS
transistors ? AA [IES – EC – 2006]
(13) A single ROM is used to design a
(A) Six (B) Five combinational circuit described by a truth
(C) One (D) two table. What is the number of address lines in
the ROM?
AC [IES – EC – 2005]
(11) Match List I (Programmable Logic Device) (A) Number of input variables in the truth
with List II (Function) and select the correct table
answer using the code given below the lists: (B) Number of output variables in the truth-
List I List II table
(Programmable (C) Number of input plus output variables
(Function) in the truth-table
Logic Device)
A. EPROM 1. AND-gate (D) Number of lines in the truth-table
programmable,
OR-gate AA [IES – EC – 2012]
permanently (14) Consider the following statements for a
hardwired DRAM.
B. PLA 2. Both AND and 1. Bit is stored as a charge.
OR gates
programmable 2. It is made of MOS transistors
C. GAL 3. AND-gate 3. Speed of DRAM is faster than
programmable, processors
OUTPUT
permanently 4. Each memory cell requires six
hardwired but transistors
may be taken Which of these statements are correct?
through
Register, or tri (A) 1 and 2 only
state gate (B) 2 and 3 only
programmable
D. PAL 4. AND-gate (C) 3 and 4 only
permanently (D) 1, 2, 3 and 4
hardwired,
OR-gate AD [GATE -EC - 2005]
programmable (15) What memory address range is NOT
represented by chip#1 and chip # 2 in the
figure. A0 to A15 in this figure are the
Codes:
address lines and CS means chip select.
A B C D
(A) 4 1 3 2
(B) 3 2 4 1
(C) 4 2 3 1
(D) 3 1 4 2
AC,D [GATE – EC – 1992]
(12) Which one of the following statements is
correct?
(A) PROM contains a programmable
‘AND’ array and a fixed ‘OR’ array
(B) PLA contains a fixed ‘AND’ array and
a programmable ‘OR’ array
(C) PROM contains a fixed ‘AND’ array
and a programmable ‘OR’ array (A) 0100 – 02FF
(B) 1500 – 16FF
www.targate.org Page 91
DIGITAL ELECTRONICS
(C) F900 – FAFF
(D) F800 – F9FF
AD [GATE -EC - 1999]
(16) If CS = A15 A14 A13 is used as the chip select
logic of a 4k RAM in an 8085 system, then
its memory range will be
(A) 3000H – 3FFFH
(B) 7000H – 7FFFH
(C) 5000H – 5FFFH and 6000H – 6FFFH
(D) 6000H – 6FFFH and 7000H – 7FFFH
AB [GATE -EC - 2002]
(17) If the input X 3 , X 2 , X 1 , X 0 to the ROM in the
(A) 1111 (B) 1011
figure as 8421 BCD numbers, then the
(C) 1000 (D) 0010
outputs Y3 , Y2 , Y1 , Y0 are
AB [GATE -EC - 2006]
(19) An I/O peripheral device shown in the figure
below is to be interfaced to an 8085
microprocessor. To select the I/O device in
the I/O address range D 4 H D 7 H , its chip
– select (CS ) should be connected to the
output of the decoder shown in the figure.
(A) Gray code numbers
(B) 2421 BCD numbers
(C) excess -3 code numbers
(D) None of the above
AC [GATE -EC - 2003]
(18) In the circuit shown in the figure. A is
parallel-in, parallel out 4 bit register, which
loads at the rising edge of the clock ‘C’. The
input lines are connected to a 4 bit bus, W. (A) output 7 (B) output 5
Its output acts as the input to a 16 4 ROM (C) output 2 (D) output 0
whose output is floating when the enable
input E is 0. A partial table of the contents of AA [IES – EC – 2000]
the ROM is as follows. (20) Match List – I (Memory elements) with List
– II (Properties) and select the correct
Address 0 2 4 6
answer using the codes given below the lists
Data 0011 1111 0100 1010 List – I
Address 8 10 11 14 A. Semiconductor memory
Data 1011 1000 0010 1000 B. Ferrite core memory
The clock to the register is shown, and the C. Magnetic tape memory
data on the W bus at time t1 is 0110. The List – II
total data on the bus at time t 2 is : 1. Destructive read out.
Page 92 TARGATE EDUCATION GATE-( EC /EE)
Topic 06 - Semiconductor Memories
2. Combinational logic AD [IES – EE – 1992]
3. Volatile. (26) Access in magnetic drum memory is
Codes : (A) Completely random
A B C (B) Sequential and cyclic
(A) 2 1 3 (C) A cyclic sequential
(B) 1 3 2 (D) Partly random and partly cyclic
(C) 3 2 1 sequential.
(D) 3 1 2 AC [IES – EE – 1992]
(27) Direct-memory-access channel facilitates
AB [IES – EC – 2004] data to move into and out of the system
(21) A ROM is to be used to implement a
“squarer” which outputs the square of a 4-bit (A) Without subroutine
number. What must be the size of the ROM? (B) With equal time delay
(A) 16 address lines and 16 data lines (C) Without programme intervention
(B) 4 address lines and 8 data lines (D) on first come first serve basis.
(C) 8 address lines and 8 data lines AC [IES – EE – 1992]
(D) 4 address lines and 16 data lines (28) 2,764 is 65,536-bit EPROM organized as
8,192 words of 8 bits each. It has
AA [IES – EC – 2011]
(22) The difference between PLA and ROM is (A) 1C address lines and 10 data lines
(A) PLA is sequential, ROM is (B) 12 address lines and 10 data lines
combinational
(C) 13 address lines and 8 data lines
(B) PLA is combinational, ROM is
sequential (D) 15 address lines and 12 data lines.
(C) PLA is economizes on the number of AB [IES – EE – 1992]
min–terms to implement Boolean (29) All to the following are non-volatile
functions memories EXCEPT
(D) PLA has fixed AND array, ROM has
fixed OR array. (A) ROM's
AD [IES – EE – 1992] (B) Semiconductor RAM
(23) PROM is (C) PROM's
(A) Permanent read only memory (D) EPROM's
(B) Polarized read only memory
AD [IES – EE – 1992]
(C) Positive read only memory (30) A Semiconductor Read-only-memory
(D) Programmable read only memory basically is
AA [IES – EE – 1992] (A) a sequential circuit with flip-flop
(24) The advantage of magnetic drum storage is (B) a sequential circuit with flip-flop and
(A) High access time gates
(B) Large size (C) a set of flip-flop memory elements
(D) a combinational logic circuit.
(C) Only read out is possible
(D) Low access time AA,D [IES – EE – 2012]
(31) In case of dynamic memory
AD [IES – EE – 1992] (A) Contents tend to decay over a period of
(25) As compared to MOS memories, bipolar time
memories have
(B) Contents are retained without
(A) Slower success time but are cheaper distortion
(B) Slower access time and are costly (C) Power consumption is low.
(C) Faster access time and are cheaper (D) The speed is low as compared to static
(D) Faster access time and are costly memory.
www.targate.org Page 93
DIGITAL ELECTRONICS
AC [IES – EE – 1993] AA [IES – EC – 2009/IES - EE- 1997]
(32) Programmable ROM has a decoder at the (37) A 3 8 decoder with two enable inputs is to
input and be used to address 8 blocks of memory.
(A) Both these blocks being fully What will be the size of each memory block
programmable when addressed from a sixteen bit bus with
two MSB's used to enable the decoder?
(B) Only the former block being
programmable (A) 2K (B) 4K
(C) Only the latter block being (C) 16K (D) 64K
programmable
AC [IES – EE – 1998]
(D) Both these blocks being partially
(38) Which one of the following is an example of
programmable
non- volatile memory?
AD [IES – EE – 1995] (A) Static RAM (B) Dynamic RAM
(33) In computer terminology 1 M Byte memory
means (C) ROM (D) Cache memory
(A) 1000000 bytes AB [IES – EE – 2012]
(B) 1000024 bytes (39) For a memory system, the cycle time is
(C) 1024000 bytes (A) Same as the access time
(D) 1048576 bytes (B) Larger than the access time
AC [IES – EE – 1996] (C) Shorter than the access time
(34) If the number of bits in input and output (D) Sub - multiple of the access time
codes is 4 and 8 respectively for a ROM.
Then the memory of this chip is equal to AD [IES – EE – 2012]
(40) Number of address lines necessary to
(A) 12 bits (B) 32 bits connect 8 k memory chip is :
(C) 128 bits (D) 256 bits (A) 10 (B) 11
AB [IES – EE – 1996] (C) 12 (D) 13
(35) A random-access R/W semiconductor
memory chip is organized into 128 words of AB[GATE-EC-2001]
8 bits each. A block diagram of the chip is (41) In the DRAM cell in the figure, the Vt of the
shown in the following figure: NMOSFET is 1V. For the following three
Ignoring power supply connections, the combinations of WL and BL voltages
minimum number of pin connections per (A) 5V; 3V; 7V (B) 4V; 3V; 4V
chip is (C) 5V; 5V; 5V (D) 4V; 4V; 4V
AA[GATE-EC-1996]
(42) Each cell of a static Random Access
Memory contains
(A) 6 MOS transistors
(B) 4 MOS transistors and 2 capacitors
(C) 2 MOS transistors and 4 capacitors
(D) 1 MOS transistor and 1 capacitor
AB [GATE–S2–EC–2017]
(A) 23 (B) 25 (43) In a DRAM,
(C) 26 (D) 138 (A) periodic refreshing is not required
AC [IES – EE – 1997] (B) information is stored in a capacitor
(36) The larger the RAM of a computer, the (C) information is stored in a latch
faster is its speed, since it eliminates
(D) both read and write operations can be
(A) Need for ROM performed simultaneously
(B) Need for external memory
(C) Frequency disk I/O s -------0000-------
(D) Need for a data – wide path
Page 94 TARGATE EDUCATION GATE-( EC /EE)
07
Logic Gate Families
AA [GATE-EC/EE/IN-2012]
(1) In the circuit shown
(A) V1 V2 VDD
(B) V1 V2 VEE
(C) V1 V DD and V2 V EE
(D) V1 V EE and V2 V DD
AB[GATE-IN-2005]
(A) Y A B C (B) Y ( A B)C (4) Identify the logic given in the figure
(C) Y ( A B ) C (D) Y AB C
AB [GATE-EC/EE/IN-2013]
(2) In the circuit shown below, Q1 has negligible
collector-to-emitter saturation voltage and
the diode drops negligible voltage across it
under forward bias. If Vcc is +5 V, X and Y
are digital signals with 0 V as logic 0 and
VCC as logic 1, than the Boolean expression
for Z is (A) NOR (B) NAND
(C) AND (D) OR
AB [GATE – EC – 2014]
(5) If WL is the word Line and BL the Bit Line,
and SRAM cell is shown in
(A)
(A) X Y (B) X Y
(C) X Y (D) XY
AD[GATE-IN-2003]
(3) For the CMOS analog switch shown in
figure, the positive supply is VDD and the (B)
negative supply is V EE . The input Vi is
bipolar. The switch will be ON and V0 will
be equal to Vi provided
www.targate.org Page 95
DIGITAL ELECTRONICS
(C)
(D)
(A) X1 X 2 (B) X1 X 2
(C) ( X 1 X 2 ) (D) ( X 1 X 2 )
AC [GATE - IN - 2007]
(9) A CMOS implementation of a logic gates is
AA [GATE – EC – 2014] shown in the following figure: The Boolean
(6) The output (Y) of the circuit shown in the logic function realized by the circuit is :
figure is
(A) AND (B) NAND
(C) NOR (D) OR
AA [IES – EE – 2003]
(A) A B C (B) A B.C A.C (10) The shown NMOS circuit is a gate of the
type
(C) A B C (D) A.B.C
AD [GATE-IN-2014]
(7) The figure is a logic circuit with inputs A
and B and output Y. Vss = + 5 V. The circuit
is of type
(A) NAND (B) NOR
(C) AND (D)EXCLUSIVE-OR
AD [IES – EC – 1999]
(11) The load resistance R L between X and Y in
the switch shown in Figure – I
(A) NOR (B) AND
(C) OR (D) NAND
AD [GATE– EE – 2009/IES - EE - 2009]
(8) If X1 and X2 are the inputs to the circuit as
shown in the figure, then what is the output
Q?
CANNOT be replaced
Page 96 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
(A) an NMOS inverter with enhancement
(A) (B) mode transistor as load
(B) an NMOS inverter with depletion mode
transistor as load
(C) a CMOS inverter
(D) a BJT inverter
(C) (D) AC[GATE-EC-2005]
(16) Both transistors T1 and T2 shown in figure,
have a threshold voltage of 1 Volts. The
device parameters K 1 and K 2 of T1 and T 2
are, respectively, 36 A/V 2 and 9 A/V 2 .
A*[GATE-EC-1991]
(12) In figure, the Boolean expression for the The output voltage V0 is
output in terms of inputs A, B and C when
the clock 'ck' is high, is given by
(A) 1 V (B) 2 V
(C) 3 V (D) 4 V
AA [IES – EC – 2005]
(17) In the circuit given below, both transistors
A*[GATE-EC-1994] have the approximate value of the highest
(13) In the output stage of a standard TTL, we possible output voltage Vout , if Vin can range
have a diode between the emitter of the pull- from 0 to VDD?
up transistor and the collector of the pull- (Assume 0 < VT < VDD)
down transistor. The purpose of this diode is
to isolate the output node from the power
supply VCC .
AC[GATE-EC-2002]
(14) The circuit in the figure has two CMOS
NOR-gates. This circuit function as a :
(A) VDD VT (B) VDD
(C) VT (D) 0
AA [GATE – EC – 1998]
(A) flip-flop (18) The threshold voltage for each transistor in
(B) Schmitt trigger the figure shown below is 2.0 V. What are
(C) monostable multi-vibrator the values of Vi for this circuit to work as an
(D) astable multi-vibrator inverter ?
AC[GATE-EC-2004]
(15) Given figure is the voltage transfer
characteristic of
(A) –5V and 0 V
(B) –5 V and 5 V
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DIGITAL ELECTRONICS
(C) 0 V and 5 V Statement for Linked Answer Questions for
Next Two Questions :
(D) –3 V and 3 V
In the following circuit, the comparator output is
AA-Q, B-R, C-S[GATE-EE-1998] logic "1" if V1 V 2 and is logic "0" otherwise. The
(19) Match the following :
D/A conversion is done as per the relation
Logic Function
3
A. X Y P. Sum VDAC 2 n 1 bn Volts, where b3 ( MSB ) , b2 , b1
n0
B. XY Q. NAND and b0 (LSB) are the counter outputs. The counter
C. XY R. Carry starts from the clear state.
S. NOR
AA[GATE-EE-2014]
(20) A 3-bit gray counter is used to control the
output of the multiplexer as shown in the
figure. The initial state of the counter is
000 2 . The output is pulled high. The output
of the circuit follows the sequence
AD[GATE-EC-2008]
(23) The stable reading of the LED displays is :
(A) 06 (B) 07
(C) 12 (D) 13
AB[GATE-EC-2008]
(24) The magnitude of the error between VDAC
and Vin at steady state in volts is
(A) I 0 ,1,1, I1 , I 3 ,1,1, I 2
(A) 0.2 (B) 0.3
(B) I 0 ,1, I1 ,1, I 2 ,1, I 3 ,1 (C) 0.5 (D) 1.0
(C) 1, I 0 ,1, I1 , I 2 ,1, I 3 ,1 A*[GATE-EC-2015]
(25) Consider a four bit D to A converter. The
(D) I 0 , I1 , I 2 , I 3 , I 0 , I1 , I 2 , I3 analog value corresponding to a digital
signals of values 0000 and 0001 are 0V and
AA[GATE-EE-2003] 0.0625V respectively. The analog value(in
(21) A memory system has a total of 8 memory Volts) corresponding to the digital signal
chips, each with 12 address lines and 4 data 1111 is _______.
lines. The total size of the memory system is AC [GATE - IN - 2004]
(A) 16 kbytes (B) 32 kbytes (26) In Fig. if the input C = 0 and D = 0, the
output Y can be made 0 by making
(C) 48 kbytes (D) 64 kbytes
A0.62-0.66[GATE-EE-2014]
(22) A hysteresis type TTL inverter is used to
realize an oscillator in the circuit shown in
the figure
(A) A = 0, B = 1
(B) A = 0, B = 0
(C) A = 1, B = 1
(D) A = 1, B = 0
AB [IES – EC – 1996]
If the lower and upper trigger level voltages (27) What is the output of the gate circuit shown
are 0.9 V and 1.7 V, the period (in ms), for in the above figure?
which output is LOW, is ____
Page 98 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
(A) P NOR Q (B) P NAND Q
(C) P OR Q (D) P AND Q
AD [IES – EE – 1992]
(31) Positive logic in a logic circuit is one in
which
(A) Logic 0 and 1 are represented by 0 and
positive voltage respectively
(B) Logic 0 and 1 are represented by Then
by negative and positive voltage
respectively
(C) Logic 0 voltage level is higher then
(A) ( A B )( C D )
logic 1 voltage level
(B) AB CD (D) Logic 0 voltage level is lower then
logic 1 voltage level.
(C) AB CD
AD [IES – EE – 1996]
(D) ( A B )( C D ) (32) Match List I with List II and select the
correct answer using the codes given below
AB [IES – EC – 1995] the lists:
(28) The circuit shown in the given figure is a
List I List II
(Name of Logic (Propagation
gate) delay)
A. DTL 1. 8 ns
B. TTL 2. 10 ns
C. ECL 3. 25 ns
(A) Positive logic OR circuit D. CMOS 4. 1 ns
(B) Negative logic OR circuit
Codes:
(C) Positive logic NAND circuit
(D) Negative logic NAND circuit A B C D
(A) 3 2 1 4
AB [GATE - IN - 2009]
(29) The diode in circuit shown an ideal. A (B) 4 3 2 1
voltage of 0 V represents logic 0 and +5 V (C) 3 2 4 1
represents logic 1. The logic function Z
realized by the circuit for logic inputs X and (D) 2 1 4 3
Y is
AD [IES – EE – 1998]
(33) The output 'F' of the circuit shown in the
given figure is :
(A) Z = X = Y (B) Z = XY
(C) Z X Y (D) Z = Z XY
AD [GATE -EC - 2008]
(30) The logic function implemented by the
following circuit at the terminal out is
(A) AB (B) AB
(C) AB AB (D) AB AB
AD [IES – EE – 2001]
(34) Match List I with List II and select the
correct answer:
www.targate.org Page 99
DIGITAL ELECTRONICS
List I (Type of gates) (A) Gain bandwidth product
A. ECL (B) (Propagation delay time) * (Power
B. TTL dissipation)
C. CMOS (C) (Fan – out) * (power dissipation)
(D) (Noise Margin) * (Power dissipation)
D. NMOS
List II (Values of propagation delay) AC [IES – EC – 1994]
1. 5 ns (38) The open collector of the gates are
connected together as shown in the given
2. 20 ns
figure. The logic expression for Y will be
3. 200 ns
4. 1 ns
Codes:
A B C D
(A) 1 4 3 2
(A) A B C D
(B) 4 1 3 2
(B) A B C D
(C) 1 4 2 3
(C) ( A B ) ( C D )
(D) 4 1 2 3
(D) AB CD
AA [IES – EC – 1996] AC [IES – EC – 1995]
(35) Match List-I with List-II and select the (39) The logic function performed by the circuit
correct answer using the code given below given in the figure is
the lists:
List I List II
(Semiconductor (Characteristic)
technology)
A. TTL 1. Maximum
power
consumption
B. ECL 2. Highest packing
density
X1, X2: inputs Y0: output
C. NMOS 3. Least power (A) Y0=X1X2 (B) Y0=X1+X2
consumption
(C) Y0 X 1 X 2 (D) Y0 X 1 X 2
D. CMOS 4. Saturated logic
AC [IES – EC – 1995]
(40) If the various logic families are arranged in
Codes: the ascending order of their fan – out
A B C D capabilities, the sequence will be
(A) 1 4 2 3 (A) TTL, ECL, IIL, CMOS
(B) 1 4 3 2 (B) ECL, TTL, IIL, CMOS
(C) 4 1 2 3 (C) IIL,TTL, ECL, CMOS
(D) 4 1 3 2 (D) TTL, ECL, CMOS, IIL
AA [IES – EE – 2012] AD [IES – EC – 1996]
(36) Statement (I) : ECL gate has the highest (41) Which one of the following logic functions
speed of operation. is implemented by the gates when their open
collector type outputs are tied together as
Statement (II) : The transistors in ECL
shown in the given figure?
gate operate in active region.
AB [IES – EC – 1994]
(37) The figure of merit of logic family is given
by
Page 100 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
(A) f = AB+C+D C. HTL 3. Current hogging
(B) f AB ( C D ) D. CMOS 4. NOR/OR output
(C) f AB ( C D ) 5. Totem-pole output
Codes:
(D) f AB C D
A B C D
AB [IES – EC – 1999] (A) 3 5 4 2
(42) The voltage levels of a negative logic system (B) 1 2 5 4
(A) Must necessarily be negative (C) 3 2 5 4
(D) 1 5 4 2
(B) May be negative or positive
(C) Must necessarily be positive AA [IES – EC – 2003]
(47) Assertion (A) :
(D) Must necessarily be 0V and – 5V
The switching speed of ECL gate is very
AA [IES – EC – 1999] high.
(43) Consider the following statements regarding
Reason(R) :
ICs:-
The devices in ECL gate operate in active
1. ECL has the least propagation delay.
region.
2. TTl has the largest fan – out
AA [IES – EC – 2003]
3. CMOS has the biggest noise margin (48) Assertion(A):
4. TTl has the lowest power consumption When transistor switches are to be used in an
Which of these statements are correct? application where speed is a premium, it is
(A) 1 and 3 (B) 2 and 4 better to reduce the storage time.
(C) 3 and 4 (D) 1 and 2 Reason(R):
It is comparatively easy to reduce storage
AB [IES – EC – 2001] time rather than the rise time and fall time of
(44) Assertion (A) : ECL gate has the highest a transistor switch.
speed of operation as compared to other
logic families. AC [IES – EC – 2004/2006/2007/2010]
Reason (R) : ECL gate dissipates more (49) Match List I with List II and select the
power. correct answer using the code given below
the lists:
AB [IES – EC – 2001] List I List II
(45) Consider the following logic families.
1. MOS A. HTL 1. High fan-out
2. DTL B. CMOS 2. Highest speed of
3. RTL operation
2
4. ECL C. I L 3. High noise immunity
The sequence of these logic families in the D. ECL 4. Lowest product of
order of their increasing noise margin is power and delay
(A) 3, 4, 1, 2 (B) 3, 4, 2, 1
(C) 4, 3, 1, 2 (D) 4, 3, 2, 1 Codes:
A B C D
AB [IES – EC – 2002]
(A) 3 4 1 2
(46) Match List I with List II and select the
correct answer using codes given below the (B) 2 1 4 3
lists: (C) 3 1 4 2
List I List II (D) 2 4 1 3
(Logic Gates) (Operation)
AB [IES – EC – 2007&2008]
A. TTL 1. More logical swing (50) Why does an I2L (Integrated Injection Logic)
B. ECL 2. Low power have higher density of integration than TTL?
dissipation
www.targate.org Page 101
DIGITAL ELECTRONICS
(A) It does not require transistors with high Codes:
current gain and hence they have
smaller geometry A B C
(B) It uses multi-collector transistors (A) 1 3 2
(C) It does not require isolation diffusion (B) 2 3 1
(D) It uses dynamic logic instead of static
logic (C) 1 2 3
AC [IES – EC – 2009] (D) 2 1 3
(51) Which of the following factors are
responsible to design IC logic gates to AA [IES – EC – 2011]
operate at a fixed supply voltage of 5 volts ? (55) Match List-I with List-II and select the
correct answer using the code given below
1. Low heating of IC logic gates. the lists:
2. Compatibility with other logic gates.
List I List II
3. Satisfactory and safe operation.
4. Standardization from IC manufacturing A. DCTL 1. Multiple collectors
point of view. B. ECL 2. Current hogging
Select the correct answer from the code C.
2
IL 3. High speed
given below :
(A) 1 only (B) 2 only Codes:
(C) 2 and 3 (D) 3 and 4 A B C
AC [IES – EC – 2009] (A) 2 3 1
(52) Which of the following statements is not (B) 1 3 2
correct ?
(C) 2 1 3
(A) Propagation delay is the time required
for a gate to change its state (D) 3 2 1
(B) Noise immunity is the amount of noise AC [GATE – EC – 1997]
which can be applied to the input of a (56) In standard TTL, the ‘Totem pole’ refers to:
gate without causing the gate to change
(A) Multi-emitter input stage
state
(B) The phase splitter
(C) Fan-in of a gate is always equal to fan-
out of the same gate (C) The output buffer
(D) Operating speed is the maximum (D) Open collector output stage
frequency at which digital data can be AD [IES – EC – 2012]
applied to a gate (57) For a transistor used as a switch, td is delay
AA [IES – EC – 2010] time, tr is rise time, ts is storage time and tf is
(53) Assertion(A) : fall time. Then turn-on time tON and turn-off
time tOFF are respectively
The TTL NAND gate in tristate output
(A) (td + ts) and (tr + tf)
configuration can be used for a bus
arrangement with more than one gate output (B) (td + ts) and (ts + tr)
connected to a common line. (C) (tr + ts) and (td + tf)
Reason(R): (D) (td + tr) and (ts + tf)
The tri state configuration has a control AA [GATE - IN - 1994]
input, which can the bus line. (58) The diode circuit shown in Fig. functions as
AB [IES – EC – 2011]
(54) Match List-I with List-II and select the
correct answer using the code given below
the lists:
List I List II
A. TTL 1. Low power consumption
B. ECL 2. High speed (A) AND gate (B) OR gate
(C) NAND gate (D) NOR gate
C. CMOS 3. Low propagation delay
Page 102 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
AA [GATE - IN - 2003]
(59) Introducing a Schottky diode between the
base and collector of the output transistor in
(A)
a TTL circuit
(A) Increases the speed of operation by
inhibiting saturation
(B) Decreases the speed of operation by
inhibiting saturation
(C) Increases the FAN OUT by enabling
(B)
saturation
(D) Increases the speed of operation by
enabling saturation
AA [GATE - EE - 1998]
(60) The open collector outputs of two inputs
NAND gates are connected to a common (C)
pull up resistor. If the input to the gates are
P, Q and R, S respectively, the output is
equal to
(A) PQ . RS (B) PQ RS
(C) PQ RS (D) PQRS (D)
AC [GATE - EE - 2006]
(61) A TTL NOT gate circuit is shown in figure.
Assuming VBE 0.7 v of both the
transistors, if Vi 3.0 V, then the states of A A BC [GATE -EC - 1991]
(63) The CMOS equivalent of the following n
the two transistors will be
MOS gate(figure) is_________
(draw the circuit).
(A) Q1 ON and Q2 OFF
(B) Q1 reverse ON and Q2 OFF
(C) Q1 reverse ON and Q2 ON
AD [GATE -EC - 1992]
(D) Q1 OFF and Q2 reverse ON
(64) Figure shows the circuit of a gate in the
AA [GATE - EE - 2010] Resistor Transistor Logic (RTL) family. The
(62) The TTL circuit shown in the figure is fed circuit represents a
with the waveform X (also shown.) All gates
have equal propagation delay of 10 ns. The
output Y of the circuit is
(A) NAND (B) AND
(C) NOR (D) OR
AB [GATE -EC - 1997]
(65) The inverter 74 AL S01 has the following
specifications:
www.targate.org Page 103
DIGITAL ELECTRONICS
I OH max 0.4 mA , AA [GATE -EC - 2004]
I OL max 8 mA, I1 H max 20 A, I IL max = (69) The figure shows the internal schematic of a
TTL AND-OR-INVERT (AOI) gate. For the
0 .1m A .
inputs shown in the figure, the output Y is :
The fan out based on the above will be
(A) 10 (B) 20
(C) 60 (D) 100
AC [GATE -EC - 1997]
(66) For the NMOS logic gate shown in figure,
the logic function implemented is :
(A) 0 (B) 1
(C) AB (D) AB
AC [GATE -EC - 2005]
(70) The transistors used in a portion of the TTL
gate shown in the figure have a 100.
The base-emitter voltage of is 0.7 for a
transistor in active region and 0.75 V for a
transistor in saturation. If the sink current I =
1mA and the output is at logic 0, then the
current IR will be equal to
(A) ABCDE
(B) ( AB C ).( D E )
(C) A.( B C ) D .E
(D) ( A B ).C D.E
AC [GATE -EC - 1997] (A) 0.65 mA (B) 0.70 mA
(67) The gate delay of an NMOS inverter is
dominated by charge time rather than (C) 0.75 mA (D) 1.00 mA
discharge time because
AC[GATE -EC - 2009]
(A) the driver transistor has a larger (71) The full forms of the abbreviations TTL and
threshold voltage than the load CMOS in reference to logic families are
transistor. (A) Triple Transistor Logic and chip Metal
(B) the driver transistor has larger leakage oxide semiconductor.
currents compared to the load (B) Tristate Transistor Logic and chip
transistor.
metal oxide semiconductor
(C) the load transistor has a smaller W/L (C) Transistor Logic and complementary
ratio compared to the driver transistor.
Metal oxide semiconductor
(D) none of the above
(D) Tristate Transistor Logic and
AD [GATE -EC - 1999] complementary Metal oxide silicon.
(68) Commercially available ECL gates use two AB [GATE -EC - 2003]
ground lines and one negative supply in
(72) The DTL, TTL, ECL and CMOS facility
order to
GATE of digital ICS are compared in the
(A) Reduce power dissipation following 4 columns
(B) increase fan-out (P) (Q) (R) (S)
(C) Reduce loading effect Fan is DTL DTL TTL CMOS
(D) eliminate the effect of power line minimum
glitches or the biasing circuit.
Page 104 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
Power TTL CMOS ECL DTL VOH is the minimum output high-level
consumption voltage
is Minimum
V O L is the maximum output high-level
Propagation CMOS ECL TTL TTL voltage
delay is
V IH is the minimum acceptable input high-
minimum
level voltage and
The correct column is : V IL is the maximum acceptable input low-
(A) P (B) Q level voltage,
(C) R (D) S The correct relationship is:
(A) VIH VOH VIL VOL
AB [GATE -EC - 2007]
(B) VOH VIH VIL VOL
(73) The circuit diagram of a standard TTL NOT
gate is shown in the figure. When (C) VIH VOH VOL VIL
V I 2.5 V , the modes of operation of the (D) VOH VIH VOL VIL
transistors will be :
AB [GATE – EC – 1998]
(76) The noise margin of a TTL gate is about
(A) 0.2 V (B) 0.4 V
(C) 0.6 V (D) 0.8 V
AB [GATE – EC – 1994]
(77) In standard TTL the ‘totem pole’ stage refers
to
(A) the multi-emitter input stage
(B) the phase splitter
(C) the output buffer
(D) open collector output stage.
(A) Q1: Reverse Q2: Normal
active active AB [GATE – EC – 1989]
Q3: Saturation Q4: Cut-off (78) A logic family has threshold voltage
VT 2V , minimum guaranteed output high
(B) Q1: Reverse Q2: Saturation voltage VOH 4V , minimum accepted input
active
high voltage V1 H 3V , maximum
Q3: Saturation Q4: Cut-off
guaranteed output low voltage VOL 1V , and
(C) Q1: Normal Q2: Cut-off
maximum accepted input low voltage
active
VIL 1.5V . Its noise margin is
Q3: Cut-off Q4: Saturation
(A) 2V (B) 1 V
(D) Q1: Saturatin Q2: Saturation
(C) 1.5 V (D) 0.5 V
Q3: Saturation Q4: Normal
active AB [GATE – EE – 1998]
(79) In standard TTL gates, the totem pole output
AB [GATE -EC - 2003] stage is primarily used to
(74) The output of the 74 series of TTL gates is
(A) Increase the noise margin of the gate
taken from a BJT in
(B) Decrease the output switching delay
(A) Totem pole and common collector
configuration (C) Facilitate a wired OR logic connection
(B) either totem pole or open collector (D) Increase the output impedance of the
configuration circuit
(C) common base configuration
AD [IES – EC – 2009]
(D) common collector configuration
(80) Which of the following output
AB [GATE – EC – 1987] configurations are available in a TTL gate?
(75) Given that for a logic family, 1. Open collector output
2. Totem-pole output
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DIGITAL ELECTRONICS
3. Tristate output AD [IES – EC – 1998]
Select the correct answer from the codes (86) TTL circuits with active pull – up are
given below: preferred because of their suitability for
(A) Wired – And Operation
(A) 1 only
(B) Bus operated system
(B) 1 and 2 only
(C) Wired logic operation
(C) 2 and 3 only (D) Reasonable dissipation and speed of
(D) 1, 2 and 3 operation
AA [IES – EC – 2011] AB [IES – EC – 1992]
(81) CMOS logic families are associated with : (87) The “ECL” has very high switching speed
1. Low power dissipation because the transistors are
2. High noise immunity (A) Switching between cut – off and
saturation regions
3. Low Fan-out
(B) Switching between cut – off and active
4. Comparatively high logic voltage swing regions
(A) 1, 2 and 4 only (C) Switching between active and
(B) 1, 2 and 3 only saturation regions
(C) 2, 3 and 4 only (D) Any of the above
(D) 1, 2, 3 and 4 AA [IES – EE – 2012]
(88) Pull-up resistor is needed for an open
AB
collector gate
(82) The figure of merit of a logic family is given
by (A) To provide VCC for the IC
(A) Gain bandwidth (B) To provide ground for the IC
(B) Propagation delay time power (C) To provide the HIGH voltage
dissipation (D) To provide the LOW voltage
(C) Fan-out propagation delay time
AA [IES – EE – 2003]
(D) Noise margin power dissipation (89) Consider the following statements in respect
AA [IES -EC - 2005] of ECL gate :
(83) Assertion (A) : 1. Its switching speed is high
2. It provides OR an NOR logic
The speed-power product is an important
operations
parameter for comparing various TTL series.
3. Its power dissipation is small as
Reason(R) : compared to other logic gates
A low value of speed-power product 4. Its logic levels are compatible with
indicates that a propagation delay can be other logic levels are compatible with
achieved without excessive power other logic family gates
dissipation and vice-versa.
Which of these statements are correct?
AB [IES -EC – 2000/2008] (A) 1 and 2 (B) 1, 2 and 3
(84) The figure of merit of a logic family is given (C) 1, 2 and 4 (D) 3 and 4
by the product of
AD [IES - EE - 1997]
(A) Gain and bandwidth (90) Assertion (A) : TTL and CMOS cannot be
(B) Propagation delay time and power normally used together.
dissipation
Reason (R) : TTL operates on a ( 5.25) V
(C) Fan-out and propagation delay time
regulated supply voltage and some mA,
(D) Noise margin and power dissipation while the CMOS operates on unregulated
AA [IES – EC – 1997] supply voltage of +3V to +15V and some
(85) In digital circuit, Scotty transistor preferred µA.
over normal transistor because their Codes :
(A) Lower propagation delay
(A) Both A and R are true and R is the
(B) Higher propagation delay correct explanation of A.
(C) Lower power dissipation
(B) Both A and R are true but R is not the
(D) Higher power dissipation correct explanation of A
Page 106 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
(C) A is true but R is false AA [GATE – IN – 1999]
(96) Indicate which one of the following
(D) A is false but R is true statements is correct:
AA [IES - EE - 1993] (A) Static RAM are faster than dynamic
(91) Assertion (A) : The emitter logic reduces RAMs
the transistor rise time and hence results in (B) RAMs cannot be used to realize Read
logic gates which switch very fast. Write Memory (RWM)
Reason (R) : In emitter - coupled logic, the (C) ROMs are not Random access Devices
transistors are maintained in unsaturated (D) RAMs are generally non-volatile.
condition.
AB [GATE – IN – 2004]
Codes: (97) The sink current of the TTL NAND gate
shown in Fig. is 16 mA and the input
(A) Both A and R are true and R is the
capacitance of the CMOS NAND gate is 10
correct explanation of A.
pF. The minimum pull-up time constant in
(B) Both A and R are true but R is not the ns for the CMOS gate with these
correct explanation of A specifications is
(C) A is true but R is false
(D) A is false but R is true
AC [IES – EE – 1992]
(92) While ___ is the fastest unsaturated logic
gate ___ has the excellent noise immunity ?
(A) ECL; TTL (B) TTL; ECL (A) 10.2 (B) 7.5
(C) ECl; HTL (D) RTL; DTL (C) 8.5 (D) 6.5
AC [GATE – EC – 1999] AB [IES – EC – 2012]
(93) A Darlington Emitter follower circuit is (98) In locations where the humidity is low, ICs
sometimes used in the output stage of a TTL based on one of the following technologies
gate in order to should be handled only after grounding the
(A) increase its I O L body. The technology is
(B) Reduce its I OH (A) TTL (B) CMOS
(C) Increase its speed of operation. (C) DTL (D) I2 L
(D) Reduce power Dissipation.
AB [IES – EC – 2009]
AA [GATE – EC – 1989] (99) Which one of the following logic families
(94) Among the digital IC-families – ECL, TTL can be operated using a supply voltage from
and CMOS:- 3 V to 15 V?
(A) ECL has the least propagation delay (A) TTL (B) ECL
(B) TTL has the largest fan-out
(C) TL has the lowest power consumption (C) PMOS (D) CMOS
(D) CMOS has the biggest noise margin AA [IES – EC – 2006]
A74LS & CMOS [GATE – EC – 1987] (100) Consider the following statements describing
(95) Fill in the blanks of the statements below the property of a complementary
concerning the following Logic Families: MOS(CMOS) inverter;
Standard TTL (74 XXLL), Low power TTL 1. It is a combination of an n-channel FET
(74 LXX) Low power schottky TTL and a p-channel FET.
(74LSXX), schottky TTL(74 SXX), Emitter 2. There is power dissipation when the
coupled Logic (ECL), CMOS input carries the logical 1 signal.
(A) Among the TTL Families, __________ 3. There is no power dissipation when the
family requires considerably less power input carries the logical 1 signal.
than the standard TTL(74XX) and also 4. There is power dissipation during
has comparable propagation delay. transition from 0 to 1 or from 1 to 0.
(B) Only the _____ family can operate over Which of the statements given above are
a wide range of power supply voltages correct ?
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DIGITAL ELECTRONICS
(A) 1,2 and 3 (B) 2, 3 and 4 2. Fan out ------ 40.
(C) 1, 3 and 4 (D) 1, 2 and 4 3. Worst case output current at low level
AA [IES – EC – 2006] IOL max-------- 16 mA
(101) Match List I with List Ii and select the 4. Direct compatibility with CMOS -------
correct answer using the code given below NOT possible
the Lists:
Select the correct answer using the codes
List I List II given below
(TTL Nos.) (Significance) Codes :
A. 74 LS 00 1. Low power/low (A) 1, 2, 3 and 4
speed
(B) 2 and 4
B. 74 H 00 2. High speed/high
power (C) 1, 2 and 3
(D) 1, 3 and 4
C. 74 00 3. Basic NAND Gate
D. 74 L 00 4. Low power AC [IES – EC – 1994]
Schottky (104) Match List – I with List – II and select the
correct answer, using the codes given below
Codes: the lists
A B C D List –I (Logic gate)
(A) 4 2 3 1 A. HTL
(B) 3 1 4 2 B. CMOS
C. I2L
(C) 4 1 3 2
D. ECL
(D) 3 2 4 1 List – II (Characteristic)
AA [IES -EC - 2002] 1. High Fan – out
(102) Match List I with List II select the correct 2. Highest speed of operation
answer using codes given below the lists: 3. High noise immunity
List I List II 4. Lowest product of power and delay
TTL Codes :
A. 1. Low propagation
delay A B C D
(A) 4 2 1 4
B. ECL 2. Low power
consumption (B) 1 3 2 3
(C) 3 1 4 2
C. MOS 3. Higher packing
(D) 3 4 1 2
density on Si
wafer AD [IES - EE - 1993]
D. CMOS 4. Saturated bipolar (105) Match List I (Logic circuit) with List II
logic (Property) and select the correct answer
using the codes given below the List:
5. High fan-out
List I List II
Codes: A. DTL 1. High voltage supply
A B C D B. TTL 2. High speed of
operation
(A) 4 1 3 2
C. NMOS 3. High packing
(B) 5 3 2 1 density
(C) 4 3 2 1 D. CMOS 4. High noise margin
Codes:
(D) 5 1 3 2
A B C D
AC [IES – EC – 1997] (A) 1 3 2 4
(103) Which of the following standard TTL
(B) 2 1 3 4
parameter pairs are correctly matched?
(C) 1 2 3 4
1. Worst case high voltage at the input VIH
(D) 2 3 4 1
min...... 2v.
Page 108 TARGATE EDUCATION GATE-( EC /EE)
Topic 07 - Logic Gate Families
AB [IES - EE - 1996] (A) XNOR
(106) If negative logic is used, the diode gate (B) XOR
shown in the given figure will represent
(C) NOR
(D) OR
AD [GATE – EC – 2018]
(110) The logic function f (X, Y) realized by the
given circuit is
(A) OR gate
(B) AND gate
(C) NOR gate
(D) NAND gate
AD [IES – EC – 1997]
(107) The schematic shown in the figure indicated
(A) NOR (B) AND
(A) CMOS NOR gate (C) NAND (D) XOR
(B) CMOS NAND gate
AA [GATE-EC-2019]
(C) CMOS AND gate (111) In the circuits shown the threshold voltage of
(D) CMOS transmission gate each nMOS transistor is 0.6 V. Ignoring the
effect of channel length modulation and
AA[GATE-IN-1994] body bias, the values of Vout1 and Vout2,
(108) The diode circuit shown in figure functions respectively, in volts, are
as
(A) AND gate (B) OR gate
(C) NAND gate (D) NOR gate
AMTA [GATE–S2–EC–2017]
(109) For the circuit shown in the figure. P and Q
are the inputs and Y is the output.
(A) 1.8 and 2.4 (B) 2.4 and 2.4
(C) 1.8 and 1.2 (D) 2.4 and 1.2
AA [GATE-EC-2019]
(112) In the circuit shown, A and B are the inputs
and F is the output. What is the functionality
of the circuit?
The logic implemented by the circuit is
www.targate.org Page 109
DIGITAL ELECTRONICS
(A) XNOR (B) SRAM Cell
(C) Latch (D) XOR
AA [GATE-EC-2019]
(113) In the circuit shown, what are the values of F
for EN = 0 and EN = 1, respectively?
(A) Hi-Z and D (B) 0 and D
(C) Hi-Z and D (D) 0 and 1
-------0000------
Page 110 TARGATE EDUCATION GATE-( EC /EE)
08
A/D & D/A Converters
(C) 100 ms (D) 120 ms
AC [GATE – IN – 2015]
(1) An ADC is interfaced with a microprocessor AC [GATE - IN - 2003]
as shown in the figure. All signals have been (4) If the input of 120 mV is corrupted by power
indicated with typical notations. Acquisition supply interference at 50 Hz having peak
of one new sample of the analog input signal amplitude of 3 mV, the worst-case error
by the microprocessor involves introduced by the interference in the reading
is
(A) 0% (B) 1%
(C) 3% (D) %
AB[GATE-IN-2009]
(5) The circuit is used at a sampling rate of 1
kHz, with an A/D converter having a
conversion time to 200 s . The opamp has
(A) one READ cycle only an input bias current of 10 nA. The
(B) one WRITE cycle only maximum hold error is
(C) one WRITE cycle followed by one (A) 1 mV (B) 2 mV
READ cycle
(C) 5 mV (D) 10 mV
(D) one READ cycle followed by one
WRITE cycle AA[GATE-IN-2014]
(6) An N-bit ADC has an analog reference
AC[GATE-IN-2002] voltage V. Assuming zero mean and uniform
(2) Majority of digital voltmeters are built with distribution of the quantization error, the
a dual slope ADC because quantization noise power will be :
(A) Dual slope ADCs are less complex than V2
other type of ADCs (A)
12(2 N 1)2
(B) Dual slope ADCs are faster than other
V2
types of ADCs (B)
12(2 N 1)
(C) Dual slope ADCs can be designed to be
insensitive to noise and interference V
(C)
12(2N 1)
(D) Dual slope ADCs provide BCD
outputs. V2
(D)
Common Data Questions for Next Two 12
Questions :
In a dual slope ADC, the reference voltage is 100 AA[GATE-IN-2014]
mV and the first integration period is set as 50 (7) The circuit in the figure represents a counter-
msec. The input resister of the integrator is 1 k based unipolar ADC. When SOC is asserted
and the integrating capacitor 0.047 F . the counter counts up and the DAC output
grows. When the DAC output exceeds the
AB [GATE - IN - 2003] input sample value, the comparator switches
(3) For an input voltage of 120mV, the second from logic 0 to logic 1, disabling the clock
integration (de-integration) period will be and enabling the output buffer by asserting
EOC. Assuming all components to be ideal,
(A) 50 ms (B) 60ms
Vref , DAC output and input to be positive,
www.targate.org Page 111
DIGITAL ELECTRONICS
the maximum error in conversion of the AC [IES – EE – 2003]
analog sample value is (12) An n-bit A/D converter is required to
convert an analog input in the range 0-5 V to
an accuracy of 10 mV. The value of n should
be
(A) 16 (B) 10
(C) 9 (D) 8
AB [IES – EC – 1991]
(13) The resolution for N bit system D/A
converter is
1 1
(A) (B)
2N 2 1N
(C) 2N - 1 (D) 2N
AB [IES – EC – 1993]
(14) Which one of the following is a D to A
(A) directly proportional to Vref conversion technique?
(B) inversely proportional to Vref (A) Successive approximation
(C) independent of Vref (B) Weighted resistor technique
(D) directly proportional to clock frequency (C) Dual slop technique
AA[GATE-EE-2015] (D) Single slope technique
(8) An 8-bit, unipolar Successive
Approximation Register type ADC is used to AA [IES – EC – 1994]
convert 3.5 V to digital equivalent output. (15) A 10 – bit D/A converter provides an analog
The reference voltage is +5V. The output of output which has a maximum value of 10.23
the ADC at the end of 3rd clock pulse after volts. The resolution is
the start of conversion, is (A) 10 mV (B) 20 mV
(A) 1010 0000 (B) 1000 0000 (C) 15 mV (D) 25 mV
(C) 0000 0001 (D) 0000 0011
AB [IES – EC – 1994]
AB [GATE – EC – 2014] (16) The disadvantage of a counter type A/D
(9) For a given sample and hold circuit if the converter as comparator type A/D converter
value of the hold capacitor is increased, then is that
(A) Droop rate decreases and acquisition (A) The resolution is low
time decreases (B) Longer conversion time is required
(B) Droop rate decreases and acquisition
(C) The circuitry is more complex
time increases
(D) Its stability is low
(C) Droop rate decreases and acquisition
time decreases AB [IES – EC – 1994]
(D) Droop rate decreases and acquisition (17) Flash ADC is
time increases (A) A serial ADC
AD [IES – EE – 1994] (B) A parallel ADC
(10) Number of comparators required to build a (C) Partly serial and partly parallel ADC
5-bit Analog to Digital Converted (ADC) is (D) Successive approximately ADC
(A) 5 (B) 11 AC [IES – EC – 1996]
(C) 21 (D) 31 (18) Consider the Analog to Digital converters
given below:
AB [IES – EE – 1999]
(11) The number of comparators needed in a 4-bit 1. Successive Approximation ADC
flash- type A/D converter is 2. Dual Ramp ADC
(A) 32 (B) 15 3. Counter method ADC
4. Simultaneous ADC
(C) 8 (D) 4
Page 112 TARGATE EDUCATION GATE-( EC /EE)
Topic 08 - A/D & D/A Converters
The correct sequence of the ascending order (A) 3.34375V (B) 6.0 V
in terms of conversion times of these ADC’s (C) 8.125V (D) 16s
is
(A) 3,2,4,1 (B) 2,3,4,1 AD [IES – EC – 2001]
(C) 4,1,3,2 (D) 3,2,1,4 (25) An 8-bit D/A converter has a full scale
output voltage of 20V. The output voltage
AB [IES – EC – 2010] when the input is 11011011, is
(19) A D/A converter has 5 V full scale output
(A) 160mV (B) 78mV
voltage and an accuracy of 0.2% . The
maximum error for any output voltage will (C) 20V (D) 17V
be AA [IES – EC – 2004/2009]
(A) 5 mV (B) 10 mV (26) Match List I with List II and select the
(C) 20 mV (D) 25 mV correct answer using the code given below
the lists:
AA [IES – EC – 1997] List I
(20) A 12 bit ADC is employed to converts an (Type of N-bit ADC)
analog voltage of zero to 10 volts. The
A. Flash Converter
resolution of the ADC is
B. Successive approximation
(A) 2.44 mV (B) 24.4 mV
C. Counter ramp
(C) 83.3 mV (D) 1.2 V D. Dual slope
AB [IES – EC – 1997] List II
(21) In a 4 – bit weighted – resistor D/A (Characteristics)
converter, the resister value corresponding to 1. Integrating Type
LSB is 16 KΩ. The resistor value 2. Fastest converter
corresponding to the MSB will be 3. Maximum conversion time = N bits
(A) 1 KΩ (B) 2 KΩ 4. Uses a DAC in its feedback path
(C) 4 KΩ (D) 16 KΩ Codes:
AC [IES – EC – 1998] A B C D
(22) The resolution of an – n – bit D/A converter (A) 2 3 4 1
with a maximum input of 5V is 5mV. The (B) 1 3 4 2
value of ‘n’ is (C) 2 4 3 1
(A) 8 (B) 9 (D) 1 4 3 2
(C) 10 (D) 11
AA [IES – EC – 2006]
AC [IES – EC – 1999] (27) Which one of the following D/A converters
(23) The output voltage V0 with respect to has the resolution of approx. 0.4% of its full
ground of the R-2R ladder network shown in scale range?
the given figure is (A) 8-bit (B) 10-bit
(C) 12-bit (D) 16-bit
AC [IES – EC – 2008]
(28) How many bits will a D/A converter use so
that its full-scale output voltage is 5V and its
resolution is at the most 10 mV?
(A) 5 (B) 7
(C) 9 (D) 11
AB [IES – EC – 2009]
(A) 1 V (B) 2 V (29) In which one of the following types of
(C) 3V (D) 4V analog to digital converters the conversion
time is practically independent of the
AC [IES – EC – 2001] amplitude of the analog signal?
(24) The output voltage of a 5-bit D/A binary
ladder that has a digital input of 11010 (A) The dual slope integrating type
(Assuming 0 = 0V and 1 = +10V) is (B) Successive approximation type
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DIGITAL ELECTRONICS
(C) Counter ramp type (A) 0.7 mA (B) 0.2 mA
(D) Tracking type (C) 0.1 mA (D) 1 mA
AD [IES – EC – 2011] AA [GATE - IN - 1997]
(30) Consider the following statements for an N - (36) A sample – and – hold circuit is normally
bit DACs : required before the following type of A/D
1. R – 2R ladder type is based on dual converter
slops integration. (A) Successive approximation
2. R – 2R requires resistors of large
spread in values (B) Flash (parallel) converter
3. R – 2R requires roughly 2N resistors. (C) Voltage – to – frequency converter
4. R - 2R requires roughly N Number of (D) Dual slope integrator.
resistors.
AB [GATE - IN - 1998]
Which of these statements are correct?
(37) Integrated output waveform for the dual
(A) 3 only (B) 1 only slope ADC is shown in Fig. The time T for
(C) 1 and 3 (D) 2 and 4 an 8 bit counter with 4 MHz clock will be
AD [IES – EC – 2012]
(31) An analog voltage of 3.41 V is converted
into 8 – bit digital form by an A/D converter
with a reference voltage of 5V. The digital
output is
(A) 1001001 (B) 11110001
(A) 0.032 ms (B) 0.064 ms
(C) 10110111 (D) 10101110
(C) 0.64 ms (D) 0.024 ms
AA [IES – EC – 2012]
(32) In which of the following type of A/D AA [GATE - IN - 1998]
converter does the conversion time almost (38) Percent resolution of an 8 bit D/A converter
double for every bit added to the device? is
(A) Counter type A/D converter (A) 0.39 (B) 0.78
(B) Tracking type A/D converter (C) 2.56 (D) None of these
(C) Single – slope integrating type A/D AB [GATE - IN - 2004]
converter (39) The number of comparators required in an 8-
(D) Successive approximation type A/D bit flash – type A/D converter is
converter (A) 256 (B) 255
AA [IES – EC – 2012] (C) (8+2) (D) 8
(33) A 12- bit ADC is operating with a 1 µs clock AB [GATE - IN - 2011]
period and total conversion time in seen to (40) Figure below shown a circuit of
be 14 µs. The ADC must be of implementing an 8-bit Digital – to – Analog
(A) Flash type converter (DAC) using two identical 4-bit
(B) Counting type DACs with equal reference voltages.
(C) Integrating type Assume that b0 represents LSB, b7 MSB and
(D) Successive approximately type the opamp is ideal. To obtain correct analog
values corresponding to an 8-bit DAC at the
AA [GATE - IN - 1996]
output V0. the value of resistor R is
(34) An 8 bit ADC outputs all 1’s when
Vin 1.275 volts. The quantization error is
(A) +5 mV (B) – 5 mV
(C) 10 mV (D) 2.5 mV
AB [GATE - IN - 1996]
(35) A 3-bit resistance ladder D/A (R-2R
network) has resistor values of R = 10 k
and 20 k VREF equals 8 volts. What is I out
for a digital input of 111?
Page 114 TARGATE EDUCATION GATE-( EC /EE)
Topic 08 - A/D & D/A Converters
(A) 0.25 k (B) 0.5 k AC [GATE – IN – 2006]
(45) What is the step size of the DAC?
(C) 1 k (D) 8 k
(A) 0.125 V (B) 0.525 V
AC [GATE - IN - 1999] (C) 0.625 V (D) 0.75 V
(41) The advantage of a dual slope converter over
successive approximation converter is that AB [GATE - IN - 2007]
the dual slope converter (46) The circuit shown in the figure below works
(A) Is faster as a 2-bit analog to digital converter for
0 Vin 3V .
(B) Eliminates error due to drift
(C) Can reduce the errors due to power
supply
(D) Does not require a stable voltage
reference
AD [GATE - IN - 1999]
(42) The conversion time of an 8-bits successive
approximation converter with a 1 MHz clock
is nearly
(A) 512 µS (B) 256 µS
(C) 128 µS (D) 8 µS
AB [GATE - IN - 2003]
(43) In a dual slope ADC, the reference voltage is
100 mV and the first integration period is set The MSB of the output Y1 , expressed as a
as 50 ms. The input resister of the integrator
Boolean function of the inputs X 1 X 2 X 3 is
is 100 k and the integrating capacitor
given by
0.047 F . For an input voltage of 120mV,
the second integration (de-integration) (A) X1 (B) X2
period will be (C) X3 (D) X1 + X2
(A) 50 ms (B) 60ms Common Data Questions for Next Three
(C) 100ms (D) 120ms Questions :
Common Data Questions for Next Two A data acquisition system (DAS) shown below
Questions : employs a successive approximation type 12-bit
ADC having a conversion time of 5s.
An R – 2R ladder type DAC is shown below. If a
switch status is 0, 0V is applied and if a switch
status is 1,5V is applied to the corresponding
terminal of the DAC.
AC [GATE - IN - 2008]
(47) The quantization error of the ADC is
(A) 0% (B) 0.012%
AB [GATE – IN – 2006] (C) 0.024% (D) 0.048%
(44) What is the output voltage (v0 ) for the
AD [GATE - IN - 2008]
switch status S 0 0, S1 1, S 2 1? (48) The system is used as a single channel DAS
5 15 with channel 1 selected as input to the ADC
(A) V (B) V which is in the continuous conversion mode,
4 4 for avoiding aliasing error, the cutoff
17.5 22.5 frequency fc of the filter in channel 1
(C) V (D) V
4 4 should be
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DIGITAL ELECTRONICS
(A) f c 100 kHz AB [GATE - EE - 1994]
(53) The number of comparisons carried out in a
(B) f c 100 kHz 4-bit flash-type A/D converter is
(A) 16 (B) 15
(C) 100kHz f c 200 kHz
(C) 4 (D) 3
(D) f c 200 kHz
AC [GATE - EE - 2001]
AC [GATE - IN - 2008] (54) Among the following four, the slowest ADC
(49) If the multiplexer is controlled such that the (analog-to-digital converter) is
channels are sequenced every 5 s as (A) Parallel-comparator (i.e., flash) type
1,2,1,3,1,4,1,2,1,3,1,4,1,............, the input (B) Successive approximation type
connected to channel 1 will be sampled at (C) Integrating type
the rate of the filter in channel 1 will be (D) Counting type
sampled at the rate of
AA [GATE - EE -2004 ]
(A) 25k samples/s (55) The voltage comparator shown in Fig. can be
(B) 50k samples/s used in the analog-to-digital conversion as
(C) 100k samples/s
(D) 200k samples/s
(A) a 1-bit quantizer
AA [GATE - IN - 2010]
(50) A 4-bit successive approximation type ADC (B) a 2-bit quantizer
has a full scale value of 15V. The sequence (C) a 4-bit quantizer
of the states, the SAR will traverse, for the (D) a 8-bit quantizer
conversation of an input of 8.15 V is
AB[GATE - EE - 2003]
(56) The simplified block diagram of a 10-bit
(A) A/D converter of dual slope integrator type
is shown in the Fig. The 10-bit counter at the
output is clocked by a 1 MHz. clock.
(B) Assuming negligible timing overhead for the
control logic, the maximum frequency of the
analog signal that can be converted using
(C) this A/D converter is approximately.
(D)
AC [GATE - IN - 2011]
(51) A4-bit successive approximation type of (A) 2 kHz (B) kHz
A/D converter has an input range of 0 to 15
volts. The output bit b1 next to the LSB has (C) 500 Hz (D) 250 Hz
a stuck at zero fault. The pair of input AC [GATE - EE - 2006]
voltages that produces the same output code (57) A student has made a-3 bit binary down
word is counter and connected to the R-2R ladder
type DAC [Gain = (-1 k /2R) as shown in
(A) 2V and 4V (B) 4V and 6V
figure to generate a staircase waveform. The
(C) 1V and 2V (D) 8V and 9V output achieved is different as shown in
figure. What could be the possible cause of
AD [IES – EC – 2006/GATE - EE -1993]
this error?
(52) A 10 bit A/D converter is used to digitize an
analog signal in the 0 to 5 V range. The
maximum peak to peak ripple voltage that
can be allowed in the D.C. supply voltage is
(A) Nearly 100mV
(B) Nearly 50Mv
(C) Nearly 25mV
(D) Nearly 5.0 mV
Page 116 TARGATE EDUCATION GATE-( EC /EE)
Topic 08 - A/D & D/A Converters
List – I
(A) Flash converter
(B) Dual slope converter
(C) Successive approximation
Converter
List – II
(1) requires a conversion time of the order
(A) The resistance values are incorrect
of a few seconds
(B) The counter is not working properly (2) requires a digital-to-analog converter
(C) The connection from the counter to (3) minimizes the effect of power supply
DAC is not proper interference.
(4) requires a very complex hardware.
(D) The R and 2R resistances are (5) is a tracking A/D converter.
interchanged
AB [GATE -EC - 1999]
AC [GATE -EC - 1990] (60) The resolution of a 4-bit counting ADC is
(58) Which of the resistance networks of figure 0.5 volts. For an analog input of 6.6 volts,
can be used as 3 bit R-2R ladder DAC. the digital output of the ADC will be
Assume V0 corresponds to LSB.
(A) 1011 (B) 1101
(C) 1100 (D) 1110
AB [GATE -EC - 2000]
(61) An 8-bit successive approximation analog to
(i)
digital converter has full scale reading of
2.55 V and its conversion time for an analog
input of 1 V is 20 s. The conversion time
for a 2V input will be
(A) 10 s (B) 20s
(C) 40s (D) 50s
AC [GATE -EC -2003 ]
(ii) (62) The minimum number of comparators
required to build an 8 bit flash ADC is
(A) 8 (B) 63
(C) 255 (D) 256
AB [GATE -EC - 2000]
(63) For the 4 bit DAC shown in the figure, the
output voltage V0 is :
(iii)
(A) Both (i) and (ii)
(B) Both (i) and (iii) (A) 10 V (B) 5 V
(C) Only (iii) (C) 4 V (D) 8 V
(D) Only (ii) AB [GATE -EC - 2006]
(64) A 4-bit D/A converter is connected to a free-
AA-4,B-3,C-2 [GATE -EC - 1995] running 3-bit up counter, as shown in the
(59) For an ADC, match the following: if following figure which of the following
waveforms will be observed at V 0 ?
www.targate.org Page 117
DIGITAL ELECTRONICS
(A) 31.25 A (B) 62.5 A
(C) 125 A (D) 250 A
AC
(68) The number of comparators in a 4-bit flash
ADC is
(A) 4 (B) 5
(C) 15 (D) 16
In the figure shown above, the ground has
been shown by the symbol AC [GATE – EE – 1994]
(69) The contents of the accumulator in an 8085
microprocessor is altered after the execution
(A) of the instruction.
(A) CMP C (B) CPI 3A
(C) ANI 5C (D) ORA A
(B) AD
(70) An 8-bit ADC, with 2’s compliment output,
has a nominal input range of -2V to +2V. It
(C) generates a digital code of 00H for an analog
input in the range -7.8125 mV to +7.815
mV. An input of -1.5 V will produce a
(D) digital output of
(A) 90 H (B) 96H
Statement for Linked Answer Questions for (C) 9 BH (D) A0H
Next Two Questions : AD [GATE –IN – 2006]
In the Digital-to-Analog converter circuit shown in (71) A single channel single acquisition system
the figure below, VR 10 V and R = 10 k . with 0-10 V range consists of a sample – and
– hold circuit with worst case drop rate of
100 V/ms and 10-bit ADC. The maximum
conversion time for the ADC is
(A) 49 m s (B) 0.49 ms
(C) 4.9 ms (D) 49 ms
A0.097[GATE-IN-1994]
(72) The percent resolution of a 10 bit D/A
converter is ............ .
AB[GATE -EC -2007] AC [GATE – IN – 1998]
(65) The current i is (73) The full scale input voltage to an ADC is
(A) 31.25A (B) 62.5A 10V. The resolution required is 5mV. The
minimum number of bits required for ADC
(C) 125 A (D) 250A is :
AC [GATE -EC - 2007] (A) 8 (B) 10
(66) The voltage V0 is (C) 11 (D) 12
(A) 0.781 v (B) 1.562 v AB
(C) 3.125 v (D) 6.250 v (74) An 8-bit 2’s complement representation of
an integer is FA(hex). Its decimal equivalent
AB is
(67) The current i is : (A) 10 (B) – 6
(C) +6 (D) +10
AA [IES – EC – 2012]
(75) Match List – I with List – II and select the
correct answer using the code given below
the lists
Page 118 TARGATE EDUCATION GATE-( EC /EE)
Topic 08 - A/D & D/A Converters
List – I AD
A. Flash converter ADC (79) In successive – approximation A/D
B. Successive approximation ADC converter, offset voltage equal to ½ LSB is
added t the D/A converter’s output. This is
C. Counter ramp ADC
done to
D. Dual slope ADC
List – II (A) Improver the speed of operation
1. Integrating type (B) Reduce the maximum quantization
2. Fast conversion error
3. Maximum conversion clock periods = (C) Increase the number of bits at the
number of bits output
4. Uses a DAC in its feedback path
Codes : (D) Increase the range of input voltage that
can be converted
A B C D
(A) 2 3 4 1 AB [IES – EC – 1999]
(B) 1 3 4 2 (80) Assertion (A): The output of an 8 – bit A to
(C) 2 4 3 1 D converter is 80H for an input of 2.5V
(D) 1 4 3 2 Reason(R): ADC has an output range of 00
to FFH for an input range of -5V to +5V
AA
(76) Dual-slope integration type Analog-to- (A) Both A and R is true and R is the correct
Digital converters provide : explanation of A
1. Higher speeds compared to all other (B) Both A and R is true but R is NOT the
types of A/D converters correct explanation of A
2. Very good accuracy without putting (C) A is true but R is false
extreme requirements on component (D) A is false but R is true
stability.
AB [IES – EC – 1991]
3. Good rejection of power supply hum. (81) For a D/A converter, the resolution required
4. Better resolution compared to all other is 50 mV and the total maximum output
types of A/D converters for the same voltage is 10V. The number of bits required
number of bits. is
(A) 2 and 3 only (A) 7 (B) 8
(B) 3 and 4 only (C) 9 (D) 200
(C) 4 and 1 only
AD [IES – EC – 1994]
(D) 1, 2, 3 and 4 (82) In a 4 – bit weighted resistor D/A converter,
the resistor value corresponding to LSB is 32
AA [IES – EC – 2008] KΩ. The resistor value corresponding to
(77) In order to build a 3 bit simultaneous A/D MSB will be
converter, what is the number of comparator
circuits required? (A) 32KΩ (B) 16KΩ
(A) 7 (B) 8 (C) 8KΩ (D) 4KΩ
(C) 15 (D) 16 AC [IES – EC – 2015]
AA [IES – EC – 2003] (83) A 4 – bit D/A converter gives an output
(78) A10-bit ADC with full-scale output voltage voltage of 4.5 V for an input code of 1001.
of 10.24V is designed to have a LSB/2 The output voltage for an input code of
accuracy. If the ADC is calibrated at 25 0 c 0110.
and the operating temperature ranges from (A) 1.5 V (B) 2.0V
00 c to 50 0 c , then the maximum net
(C) 3.0 V (D) 4.5 V
temperature coefficient of ADC should not
exceed. AD
0
(A) 200 V / C 0
(B) 400 V / C (84) For N-bit successive Approximation ADC’s,
other parameters such as clock frequency
0
(C) 600 V / C (D) 800 V / 0 C remaining constant, the conversion time is
proportional to
www.targate.org Page 119
DIGITAL ELECTRONICS
(A) N2 (B) N S6AB[GATE–S6–EE–2016]
(90) A temperature in the range of −40˚ C to 55˚
(C) log N (D) N C is to be measured with a resolution of 0.1˚
C. The minimum number of ADC bits
AA [GATE – EE – 1999] required to get a matching dynamic range of
(85) For a dual ADC type 3 ½ digit DVM, the
the temperature sensor is
reference voltage is 100mV and the first
integration time is set to 300ms. For some (A) 8
input voltage, the “deintegration” period is
(B) 10
370.2ms. The DVM will indicate(in mV).
(C) 12
(A) 123.4 (B) 199.9
(D) 14
(C) 100.0 (D) 1.414
S3AA [GATE–S3–EC–2016]
AB [GATE – EC – 1998] (91) In an N bit flash ADC, the analog voltage is
(86) The advantage of using a dual slope ADC in fed simultaneously to 2N − 1 comparators.
a digital voltmeter is that The output of the comparators is then
(A) its conversion time is small encoded to a binary format using digital
circuits. Assume that the analog voltage
(B) its accuracy is high source Vin (whose output is being converted
(C) it gives output in BCD format to digital format) has a source resistance of
75 Ω as shown in the circuit diagram below
(D) it does not require a comparator. and the input capacitance of each
comparator is 8 pF. The input must settle to
AA [GATE – EC – 2003]
an accuracy of 1/2 LSB even for a full scale
(87) The circuit shown in the figure is a 4 bit
input change for proper conversion. Assume
DAC
that the time taken by the thermometer to
The input bits 0 and 1 are represented by 0 binary encoder is negligible.
and 5v respectively. The OP-AMP is ideal,
but all the resistances and the 5V inputs have
a tolerance of 10%.
The specification (rounded to the nearest
multiple of 5%) for the tolerance of the DAC
is
If the flash ADC has 8 bit resolution, which
one of the following alternatives is closest to
(A) 35% (B) 20% the maximum sampling
(C) 10% rate ?
(D) 5%
(A) 1 megasamples per second
AC[GATE-EC-2000]
(88) The number of comparators in a 4-bit flash (B) 6 megasamples per second
ADC is
(C) 64 megasamples per second
(A) 4 (B) 5
(C) 15 (D) 16 (D) 256 megasamples per second
AC[GATE-EC-2002] S6AA [GATE–S6–EE–2016]
(89) The number of comparators required in a 3- (92) A 2-bit flash Analog to Digital Converter
bit comparator type ADC is (ADC) is given below. The input is 0 ≤ VIN
(A) 2 (B) 3 ≤ 3 Volts. The expression for the LSB of the
(C) 7 (D) 8 output B0 as a Boolean function of X2, X1,
and X0 is
Page 120 TARGATE EDUCATION GATE-( EC /EE)
Topic 08 - A/D & D/A Converters
(A) X 0 [ X 2 X 1 ]
(B) X 0 [ X 2 X 1 ]
(C) X 0 [ X 2 X 1 ]
(D) X 0 [ X 2 X 1 ]
AC [GATE – IN – 2018]
(93) The number of comparators required for
implementing an 8-bit flash analog-to-digital
converter is
(A) 8 (B) 128
(C) 255 (D) 256
AD [GATE-IN-2019]
(94) In the circuit shown below, assume that the
comparators are ideal and all components
have zero propagation delay. In one period
of the input signal Vin 6sin(t ) , the
fraction of the time for which the output
OUT is in logic state HIGH is
(A) 1/12 (B) 1/2
(C) 2/3 (D) 5/6
A64 [GATE-IN-2019]
(95) An 8-bit weighted resistor digital-to-analog
converter (DAC) has the smallest resistance
of 500 . The largest resistance has a value
__ k .
-------0000-------
www.targate.org Page 121
09
MICROPROCESSOR 8085
PROGRAMMING &
BASICS
(A) the microprocessor is deconnected from
AC[GATE-EC -1997] the system bus till the reset is pressed.
(1) In an 8085 p system, the RST instruction
will cause an interrupt (B) the microprocessor enters into a halt
state and the buses are tri-stated.
(A) Only if an interrupt service routine is
not being executed (C) the microprocessor halts execution of
the program and returns to monitor.
(B) Only if a bit in the interrupt mask is
made 0 (D) the microprocessor reloads the program
(C) Only if interrupts have been enabled by from the locations 0024 and 0025H.
an EI instruction AB[GATE-EE-1993]
(D) None of the above (6) Three devices A, B and C have to be
connected to a 8085 microprocessor. Device
AC[GATE-EC -2000] A has highest priority and device C has the
(2) The number of hardware interrupts (which lowest priority and device C has the lowest
require an external signal to interrupt) priority. In this context which of the
present in an 8085 microprocessor are statements are correct?
(A) 1 (B) 4 (A) A uses TRAP, B uses RST 5.5 and C
uses RST6.5.
(C) 5 (D) 13
(B) A uses RST 7.5, B uses RST 6.5 and C
AA[GATE-EC -2000] uses RST 5.5.
(3) In the 8085 microprocessor, the RST6 (C) A uses RST 5.5, B uses RST 6.5 and C
instruction transfers the program execution uses RST 7.5.
to the following location: (D) A uses RST 5.5, B uses RST 6.5 and C
(A) 30 H (B) 24 H uses TRAP.
(C) 48 H (D) 60 H A*[GATE-EE-1994]
(7) The stack pointer of a microprocessor is at
AD[GATE-EC -2009] A001. At the end of execution of following
(4) In a microprocessor, the service routine for a instruction, the value of stack pointer is
certain interrupt start from a fixed location ______.
of memory which cannot be externally set, PUSH PSW
but the interrupt can be delayed or rejected. XTHL
Such an PUSH D
(A) non-maskable and non-vectored JMP FC70H
(B) maskable and non-vectored
AC[GATE-EE-1995]
(C) non-maskable and vectored (8) In an 8085 microprocessor, after the
(D) maskable and vectored execution of XRA A instruction
AB[GATE-EE-1992] (A) the carry flag is set.
(5) If the HLT instruction of a 8085 (B) the accumulator contain FFH.
microprocessor is executed
Page 122 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
(C) the zero flag is set. List-I
(D) the accumulator contents are shifted left (a) ANA R
by one bit. (b) XRA R
AC[GATE-EE-1997] (c) CMP R
(9) In a microprocessor, the address of the next List-II
instruction to be executed, is stored in Contents of CY flag AC
(A) stack pointer ACC flag
(B) address latch
(C) program counter (P) unchanged may be unchanged
SET
(D) general purpose register
(Q) unchanged SET SET
AB[GATE-EE-2000] (R) unchanged SET RESET
(10) Which of the following is not a vectored
(S) may change RESET RESET
interrupt ?
(T) may change RESET SET
(A) TRAP (B) INTR
(C) RST 7.5 (D) RST 3 AC[GATE-EE-2003]
(14) The following program is written for an
AC[GATE-EE-2001] 8085 microprocessor to add two bytes
(11) An Intel 8085 processor is excuting the located at memory addresses 1FFE and
program given below : 1FFF
MVI A, 10 H LXI H, 1FFE
MOV B, M
MVI B, 10 H
INR L
Back: NOP MOV A, M
ADD B ADD B
RLC INR L
JNCBACK MOV M, A
XRA A
HLT
On completion of the execution of the
The number of times that the operation NOP program, the result of addition is found
will be executed is equal to (A) in the register A
(A) 1 (B) 2 (B) at the memory address 1000
(C) 3 (D) 4 (C) at the memory address 1F00
AD[GATE-EE-2002] (D) at the memory address 2000
(12) When a program is being executed in an
8085 microprocessor, its program counter AD[GATE-EE-2004]
contains (15) If the following program is executed in a
microprocessor, the number of instruction
(A) the number of instructions in the cycles it will take from START to HALT is :
current program that have already been
executed.
(B) the total number of instructions in the
program being executed.
(C) the memory address of the instruction
that is being currently executed.
(D) the memory address of the instruction (A) 4 (B) 8
that is to be executed next
(C) 13 (D) 16
Aa-T, b-S, c-P[GATE-EE-1996]
(13) In a 8085 microprocessor, the following AC[GATE-EE-2005]
instructions may results in change of (16) The 8085 assembly language instruction that
accumulator contents and change in status stores the content of H and L registers into
flags. Choose the correct match for each the memory locations 2050H and 2051 H,
instruction. respectively is
www.targate.org Page 123
DIGITAL ELECTRONICS
(A) SPHL 2050H (B) SPHL 2051H (A) PC = 2102 H, SP = 2700 H
(C) SHLD 2050H (D) STAX 2050H (B) PC = 2700 H, SP = 2700 H
AD[GATE-EE-2006] (C) PC = 2800 H, SP = 26FE H
(17) A software delay subroutine is written as (D) PC = 2A02 H, SP = 2702 H
given below :
AD[GATE-EE-2009]
DELAY : MVI H, 255D (20) In an 8085 microprocessor, the contents of
MVI L, 255D the Accumulator, after the following
instructions are executed will become
LOOP : DCR L
XRA A
JNZ LOOP MVIB F0H
DCR H SUB B
JNZ LOOP (A) 01 H (B) 0F H
How many times DCR L instruction will be (C) F0 H (D) 10 H
executed ?
A*[GATE-EC -1992]
(A) 255 (B) 510 (21) The following program is run on an 8085
microprocessor
(C) 65025 (D) 65279
Memory address is in HEX Instruction
AA[GATE-EE-2006]
(18) In an 8085 A microprocessor bases system, 2000 LXI SP, 1000
it is desired to increment the contents of
2003 PUSH H
memory location whose address is available
in (D, E) register pair and store the result in 2004 PUSH D
same location. The sequence of instruction
is : 2005 CALL 2050
(A) XCHG (B) XCHG 2008 POP H
INR M INX H 2009 HLT
(C) INX D (D) INR M
After the completion of the execution of the
XCHG XCHG program, program counter of the 8085
contains _______, and the stack pointer
AB[GATE-EE-2008] contains ______,
(19) The content of some of the memory location
in an 8085 A based system are given below AC[GATE-EC -1996]
Address Content (22) The following sequence of instructions are
executed by an 8085 microprocessor
. .
1000 LXI SP, 27FF
26FE 00
1003 CALL 1006
26FF 01
1006 POP H
2700 02
The contents of the stack pointer (SP) and
2701 03 the register pair on completion of execution
2702 04 of these instructions are,
(A) SP = 27FF, HL = 1003
. . . .
(B) SP = 27FD, HL = 1003
The content of stack (SP), program counter
(PC) and (H, L) are 2700 H, 2100 H and (C) SP = 27FF, HL = 1006
0000 H respectively. When the following (D) SP = 27FD, HL = 1006
sequence of instruction are executed
AD[GATE-EC -1997]
2100 H : DAD SP
(23) The following instructions have been
2101 H : PCHL executed by an 8085 p
the content of (SP) and (PC) at the end of ADDRESS INSTRUCTION
execution will be
(HEX)
Page 124 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
6010 LXI H, 8A79H (A) 3CFOH (B) 3CF8H
6013 MOV A, H (C) EFFDH (D) EFFFH
6014 ADD H Common Data Questions for Next Two
6015 DAA Questions :
6016 MOV H, A An 8085 assembly language program is given
below
6017 PCHL
Line 1: MVI A, B5H
From which address will the next instruction 2: MVI B, 0EH
be fetched?
3: XRI 69H
(A) 6019 (B) 0379 4: ADD B
(C) 6979 (D) None 5: ANI 9BH
AB[GATE-EC -2002] 6: CPI 9FH
(24) Consider the following assembly language 7: STA 3010H
program 8: HLT
MVI B, 87H
AB[GATE-EC -2007]
MOV A, B (26) The contents of the accumulator just after
START: JMP NEXT execution of the ADD instruction in line 4
will be
MVI B, 00H
(A) C3H (B) EAH
XRA B
(C) DCH (D) 69H
OUT PORT 1
HLT AC[GATE-EC -2007]
(27) After execution of line 7 of the program, the
NEXT: XRA B status of the CY and Z flags will be
JP START (A) CY = 0, Z = 0
OUT PORT 2 (B) CY = 0, Z = 1
HLT (C) CY = 1, Z = 0
The execution of the above program in an (D) CY = 1, Z = 1
8085 microprocessor will result in
AA[GATE-EC -2013]
(A) an output of 87H at PORT 1 (28) For 8085 microprocessor, the following
(B) an output of 87H at PORT 2 program is executed
(C) infinite looping of the program MVI A, 05H;
execution with accumulator data MVI B, 05H
remaining at 00H
PTR: ADD B;
(D) infinite looping of the program
execution with accumulator data DCR B;
alternating between 00H and 87H JNZ PTR;
AB[GATE-EC -2006] ADI 03H;
(25) Following is the segment of a 8085 assembly HLT;
language program
At the end of program, accumulator contains
LXI SP, EFFFH
(A) 17H (B) 20H
CALL 3000H
(C) 23H (D) 05H
3000H: LXI H, 3CF4H
AA[GATE-EC -2014]
PUSH PSW
(29) An 8085 microprocessor executes
SPHL “STA1234H” with starting address location
POP PSW 1FFEH (STA copies the contents of the
Accumulator to the 16-bit address location).
RET While the instruction is fetched and
On completion of RET execution, the executed, the sequence of values written at
contents of SP is the address pins A 15 A 8 us
www.targate.org Page 125
DIGITAL ELECTRONICS
(A) 1FH, 1FH, 20H, 12H AC[GATE-EC -1995]
(B) 1FH, FEH, 1FH, FFH, 12H (33) An ‘Assembler’ for a microprocessor is used
for
(C) 1FH, 1FH, 12H, 12H
(A) assembly of processors in a production
(D) 1FH, 1FH, 12H, 20H, 12H line.
AC[GATE-EC -2015] (B) creation of new programmes using
(30) Which one of the following 8085 different modules.
microprocessor programs correctly
calculates the product of two 8-bit numbers (C) translation of program from assembly
stored in registers B and C? language to machine language.
(A) MVI A, 00 H (D) translation of higher level language into
JNZ LOOP English text
CMP C AB[GATE-EC -1998]
LOOP DCR B (34) An I/O processor controls the flow of
HLT information between
(B) MVI, A, 00H (A) cache memory and I/O devices
CMP C (B) main memory and I/O devices
(C) two I/O devices
LOOP DCR B
(D) cache and main memories
HLT
(C) MVI, A, 00H AC[GATE-EC -1998]
(35) An instruction used to set the carry Flag in a
LOOP ADD C computer can be classified as
DCR B
(A) data transfer
JNZ LOOP
(B) arithematic
HLT (C) logical
(D) MVI A, 00H (D) program control
ADD C
AB[GATE-EC -2015]
LOOP INR B (36) In a 8085 microprocessor, the shift registers
HLT which store the result of an addition and the
overflow bit are, respectively
AA[GATE-EC -1988] (A) B and F (B) A and F
(31) In register index addressing mode is given
(C) H and F (D) A and C
by
(A) The index register value AA[GATE-EC -1989]
(37) In a microprocessor system, the stack is a
(B) The sum of the index register value and used for
the operand (A) storing the program return address
(C) The operand whenever a sub-routine jump
instruction is executed
(D) The difference of the index register (B) transmitting and receiving
value and the operand.
(C) storing all important CPU register
AD[GATE-EC -1993] contents whenever an interrupts is to be
(32) In a microcomputer, wait states are used to
(D) storing program instructions for
(A) Make the processor wait during a DMA interrupt service routines.
operation
AD[GATE-EC -1995]
(B) Make the processor wait during an (38) When a CPU is interrupt, it
interrupt processing (A) stops execution of instruction
(C) Make the processor wait during a (B) acknowledges interrupt and continues
power shut down (C) acknowledge interrupt and continues
(D) Interface slow peripherals to the (D) acknowledges interrupt and awaits for
processor the next instruction from the
interrupting device.
Page 126 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
AD[GATE-EC -1996] (B) Contents of location 9258 are compared
(39) The total number of memory accesses with the contents of the accumulator
involved (inclusive of the op-code fetch)
(C) Contents of location 9258 are
when an 8085 processor executes the
complemented and stored in location
instruction LDA 2003 is :
9258
(A) 1 (B) 2
(D) Contents of location 5892 are
(C) 3 (D) 4 complemented and stored in location
AA[GATE-EC -2000] 5892
(40) The contents of Register (B) and AD[GATE-EC -2004]
Accumulator (A) of 8085 microprocessor are (44) It is desired to multiply the numbers 0AH by
49 H and 3 AH respectively. The contents of 0BH and store the result in the accumulator.
A and the status of the carry flag (CY) and The numbers are available in registers B and
sign flag (S) after executing SUB B C respectively. A Part of 8085 program for
instructions are this purpose is given below:
(A) A = F1, CY = 1, S = 1 MVI A, 00H
(B) A = 0F, CY = 1, S = 1 Loop;--------------
(C) A = F0, CY = 0, S = 0 --------------------
(D) A = 1F, CY = 1, S = 1 --------------------
HLT END
AA[GATE-EC -2003]
The sequence of instructions to complete the
(41) In an 8085 microprocessor, the instruction
program would be
CMP B has been executed while the content
of the accumulator is less than that of (A) JNZ LOOP, ADD B, DCR C
register B. As a result (B) ADD B, JNZ LOOP, DCR C
(A) Carry flag will be set but Zero flag will (C) DCR C, JNZ LOOP, ADD B
be reset (D) ADD B, DCR C, JNZ LOOP
(B) Carry flag will be reset but Zero flag Common Data Questions for Next Two
will be set Questions :
(C) Both carry flag and Zero flag will be Consider an 8085 microprocessor system
reset AC[GATE-EC -2005]
(D) Both carry flag and Zero flag will be set (45) The following program starts at location
0100H
AB[GATE-EC -2004]
(42) The number of memory cycles required to LXI SP, 00FF
execute the following 8085 instructions LXI H, 0107
(I) LDA 3000 H MVI A, 20H
(II) LXI D, FOF1 H would be SUB M
(A) 2 for (I) and 2 for (II) The contents of the accumulator when the
(B) 4 for (I) and 3 for (II) program counter reaches 0109H is
(C) 3 for (I) and 3 for (II) (A) 20 H (B) 02 H
(D) 3 for (I) and 4 for (II) (C) 00 H (D) FFH
AC[GATE-EC -2004] AC[GATE-EC -2005]
(43) Consider a sequence of 8085 instructions (46) If in addition following code exists from
given below. 0109 onwards,
LXI H, 9258, MOV A, M, CMA, MOV M, ORI 40 H
A ADD M
Which one of the following is performed by What will be the result in the accumulator
this sequence? after the last instruction is executed?
(A) Contents of location 9258 are moved to (A) 40 H (B) 20 H
the accumulator (C) 60 H (D) 42 H
www.targate.org Page 127
DIGITAL ELECTRONICS
AC[GATE-EC -2010] ((SP)) (PC)
(47) For the 8085 assembly language program
given below, the content of the accumulator (B) (PC) Addr
after the execution of the program is : ((SP)) (PC)
3000 MVI A, 45 (SP) incremented
3002 MOV B, A
(C) (PC) Addr
3003 STC
(SP) incremented
3004 CMC
((SP)) (PC)
3005 RAR
3006 XRA B (D) ((SP)) (PC)
(SP) incremented
(A) 00H (B) 45H
(PC) Addr
(C) 67H (D) E7H
AC[GATE-EE-2011]
AC[GATE-EC -2011] (51) A portion of the main program to call a
(48) An 8085 assembly language program is subroutine SUB in an 8085 environment is
given below. Assume that the carry flag is given below :
initially unset. The content of the
accumulator after the execution of the :
program is : LXI D, DISP
MVI A, 07H LP : CALL SUB
RLC :
MOV B, A :
It is desired that control be returned to LP +
RLC
DISP + 3 when the RET instruction is
RLC executed in the subroutine. The set of
ADD B instructions that precede the RET instruction
in the subroutine are
RRC
(A) POP D (B) POP H
(A) 8CH (B) 64H
DAD H DAD D
(C) 23H (D) 15H
PUSH D INX H
AD[GATE-EC -2015]
INX H
(49) In an 8085 microprocessor, which one of the
following instructions changes the content of INX H
the accumulator ? PUSH H
(A) MOV B, M (B) PCHL
(C) POP H (D) XTHL
(C) RNZ (D) SBI BEH
DAD D INX D
AD[GATE-EE-2010]
(50) When a "CALL Addr" instruction is PUSH H INX D
executed, the CPU carries out the following INX D
sequential operations internally:
XTHL
Note :
AC[GATE-EE-2014]
(R) means content of register R (52) In 8085 A microprocessor, the operation
((R)) means content of memory location performed by the instruction LHLD 2100H is
pointed to by R (A) (H) 21H, (L) 00H
PC means Program Counter (B) (H) M(2100H), (L) M(2101H)
SP means Stack Pointer
(C) (H) M(2101H), (L) M(2100H)
(A) (SP) incremented
(D) (H) 00H, (L) 21H
(PC) Addr
Page 128 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
AFALSE[GATE-IN-1994] (A) immediately after HOLD goes low
(53) The contents of the STACK memory in a (B) immediately after HOLD goes high
microprocessor system are retrieved on first-
(C) after half-clock cycle after HLDS goes
in-first out basis.
low
A# [GATE-IN-1994] (D) after half-clock cycle after HlDA goes
(54) The program counter on a 8-bit high
microprocessor is always a 8-bit register.
AB[GATE-IN-2002]
Ans.: PC contains the address of next instruction (61) In an INTEL 8085 microprocessor the
to be fetched thus it is a 16-bit register. ADDRESS-DATA bus and the DATA bus
AC[GATE-IN-1997] are
(55) The stack pointer in a microprocessor is a (A) Non multiplexed
register containing (B) Multiplexed
(A) the address of the next operand (C) Duplicated
(B) the current size of the stack (D) Same as CONTROL bus
(C) the address of the top of the stack A*[GATE-IN-2002]
(D) the address for storing the result of (62) In an 8085 based system the subroutine
arithmetic operations TEST given below is called by another
program. When the processor returns from
AB[GATE-IN-1998] the subroutine TEST, the value in the
(56) Identify the software interrupt instruction in accumulator will be
8085 microprocessor
Test MOV A, #00H
(A) INT (B) RST 5
CALL TEST
(C) RST 7.5 (D) RST 6.5
TEST INR A
AC[GATE-IN-2000] RET
(57) For an 8085 microprocessor, the Stack
Pointer and Program Counter registers (A) 02 (B) 00
contain the number F000 and 2400 in Hex (C) FF (D) 20
respectively. The contents of the register
after execution of the instruction CALL AC[GATE-IN-2002]
E000 would be (63) Some of the pins of an 8085 CPU and their
functions are listed below. Identify the
(A) PC : F003 SP : 2400 correct answer that matches the pins to their
respective functions.
(B) PC : 2400 SP : 2400
Group-I
(C) PC : E000 SP : 2401
P. RST 7.5
(D) PC : E000 SP : 23FE
Q. H OLD
AC[GATE-IN-2001]
(58) An m-bit microprocessor has an m-bit R. IO/ M
S. ALE
(A) flag register
Group-II
(B) instruction register
1. Selects I/O or memory
(C) data counter
2. Demultiplexes the address and data bus
(D) program counter 3. Is a vectored interrupt
AA[GATE-IN-2001] 4. Facilitates direct memory access
(59) In 8085 microprocessor , CY flag may be set
5. Is a clock
by the instruction
6. Selects BCD mode of operation
(A) SUB (B) INX
(A) P-3, Q-2, R-1, S-4
(C) CMA (D) ANA
(B) P-4, Q-1, R-5, S-3
AB[GATE-IN-2001]
(60) Microprocessor 8085 regains control of the (C) P-3, Q-4, R-1, S-2
bus (D) P-2, Q-3, R-6, S-1
www.targate.org Page 129
DIGITAL ELECTRONICS
AD[GATE-IN-2003] AB[GATE-IN-2005]
(64) In an 8085 system containing 8 KB of ROM (68) In an 8085 microprocessor, which one of the
and 8 KB of RAM, the ROM is selected following is the correct sequence of the
when A15 is 0 and the RAM is selected machine cycles for the execution of the DCR
when A15 is 1. A13 and A14 are unused. The M instruction ?
CPU executes the following program (A) op-code fetch
Prog 1 MVI A, 00H (B) op-code fetch, memory read, memory
STA 8080H write
DCR A (C) op-code fetch, memory read
STA C080H
(D) op-code fetch, memory write, memory
RET write
The content of memory location 8080H after AD[GATE-IN-2005]
the execution of the return instruction is (69) A microprocessor has an instruction XOR
(A) FFH (B) FEH (r1 , r2 ) , which perform an Exclusive OR
(C) 01H (D) 00H operation of register r1, r2 and stores the
result in r1 . After the following instructions
AC[GATE-IN-2004]
(65) The vectored address corresponding to the are executed
software interrupt command RST7 in 8085 XOR (r2 , r1 )
Microprocessor is
(A) 0017H (B) 0027H XOR (r1 , r2 )
(C) 0038H (D) 0700H
XOR (r2 , r1 )
AD[GATE-IN-2004]
(66) The following 8085 instructions are Which one of the following is true ?
executed sequentially.
(A) Content of register r1 is half sum of r1
Prog : XRA A and r2
MOV L, A
(B) Content of register r2 is half sum of r1
MOV H, L and r2
INX H
(C) Content of registers r1 and r2 unaltered
DAD H
(D) Contents of registers r1 and r2 are
After execution, the content of HL register
pair is swapped
(A) 0000H (B) 0101H AA[GATE-IN-2005]
(70) In a 8085 Microprocessor the value of the
(C) 0001H (D) 0002H stack pointer (SP) is 2010H and that of DE
register pair is 1234H before the following
AA[GATE-IN-2005]
code is executed. The value of the DE
(67) The time period of a square wave in the
register pair after the following code is
audio frequency range is measured using an
executed is :
8085 Microprocessor by feeding the square
wave to one of the four interrupts, namely, LXI H, 0000H
RST 7.5, RST 6.5, RST 5.5, or INT. The
PUSH, H
algorithm used starts a timer at the beginning
of a time period, stops the time at the PUSH H
beginning of the next time period and reads
POP B
the time values for time measurement.
Which of the following interrupts should be DAD SP
selected for this applications? XCGH
(A) INTR (B) RST 5.5 (A) 200EH (B) 200CH
(C) RST 6.5 (D) RST 7.5 (C) 2010H (D) 1232H
Page 130 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
AA[GATE-IN-2006] AA[GATE-IN-2007]
(71) A memory mapped I/O device has an (74) 8-bit signed integers in 2's complement form
address of 00F0H. Which of the following are read into the accumulator of an 8085
8085 instructions output the content of the Microprocessor from an I/O port using the
accumulator to the I/O device? following assembly language program
segment with symbolic addresses.
(A) LXI, 00F0H
BEGIN: IN PORT
MOV M, A
(B) LXI H, 00F0H RAL
OUT M JNC BEGIN
(C) LXI H, 00F0H RAR
OUT F0H END: HLT
(D) LXI H, 00F0H This program
MOV A, M (A) halts upon reading a negative number
AC[GATE-IN-2006] (B) halts upon reading a positive number
(72) An 8085 assembly language program is (C) halts upon reading a zero
given as follows. The execution time of each
instruction is given against the instruction in (D) never halts
terms of T-state. AA[GATE-IN-2008]
Instruction T-states (75) A part of a program written for an 8085
microprocessor is shown below. When the
……………. ……………. program execution reaches LOOP2, the
MVI B, 0AH 7T value of register C will be
SUB A
LOOP: MVI C, 05H 7T C, A
DCR C 4T LOOP 1 : INR A
DCR B 4T DAA
JC LOOP 2
JNZLOOP 10T/7T
INR C
The execution time of the program in terms JNC LOOP 1
of T-states is
LOOP 2: NOP
(A) 247 T (B) 250 T
(A) 63 H (B) 64 H
(C) 254 T (D) 257 R
(C) 99 H (D) 100 H
AD[GATE-IN-2007]
(73) A snapshot of the address, data and control AA[GATE-EE-2014]
buses of an 8085 microprocessor executing a (76) In an 8085 microprocessor, the following
program is given below : program is executed.
Address location-instruction
Address 2020H
2000 H XRA A
Data 24H
2001 H MVI B, 04 H
IO/ M Logic High
2003 H MVI A, 03 H
Logic High 2005 H RAR
RD
2006 H DCR B
WR Logic Low 2007 H JNZ 2005
The assembly language instruction being 200 AH HLT
executed is : At the end of program, register A contains
(A) IN 24H (B) IN 20H (A) 60 H (B) 30 H
(C) OUT 24H (D) OUT 20H (C) 06 H (D) 03 H
www.targate.org Page 131
DIGITAL ELECTRONICS
AA[GATE-IN-2009] circuit produces a logic high output as long
(77) The following is an assembly language as the object is in front of the window, and
program for 8085 microprocessors: this output is used to interrupt the processor.
The duration of an object being in front of
Instruction
Address Mnemonic the window is in the range of 100 ms to 2 s.
Code
The processor takes 1 ms to process the
MVI A, input after an interrupt. The best choice of
1000H 3E, 06
06H interrupt for an error free counting is
1002H C6, 70 ADI 70H (A) RST 5.5 (B) RST 6.5
STA (C) RST 7.5 (D) INTR
1004H 32, 07, 10
1007H AB[GATE-EC-1993]
1007H AF XRA A (81) In a microprocessor, the register which holds
the address of the next instruction to be
1008H 76 HLT
fetched is
When this program halts, the accumulator (A) Accumulator
contains
(B) Program Counter
(A) 00H (B) 06H (C) Stack Pointer
(C) 70H (D) 76H (D) Instruction Register
AD[GATE-IN-2010] AC[GATE-EC-2008]
(78) The subroutine SBX given below is (82) An 8085 executes the following instructions
executed by an 8085 processor. The value in
the accumulator immediately after the 2710 LXI H, 30 A0H
execution of the subroutine will be 2713 DAD H
SBX MVI A, 99H 2714 PCHL
ADI 11H All addresses and constants are in Hex. Let
MOV C, A PC be the contents of the program counter
and HL be the contents of the HL register
RET pair just after executing PCHL
(A) 00H (B) 11H Which of the following statements is
(C) 99H (D) AAH correct?
(A) PC =2715H HL = 30A0H
AB[GATE-IN-2010]
(B) PC =30A0H HL = 2715H
(79) In an 8085 processor, the main program calls
the subroutine SUB1 given below. When the (C) PC =6140H HL = 6140H
program returns to the main program after (D) PC =6140H HL = 2715H
executing SUB1, the value in the
accumulator is AB[GATE-IN-2014]
(83) A microprocessor accepts external interrupts
Address Opcode level Mnemonic
(Ext INT) through a Programmable Interrupt
2000 3E, 00 SUB1: MVIA, 00H Controller as shown in the figure.
2002 CD, 05, 20 CALL SUB2
2005 3C SUB2: INR A
2006 C9 RET
Accumulator for A = 00H increases and
finally A = 14H
(A) 00 (B) 01
Assuming vectored interrupt, a correct
(C) 02 (D) 03 sequence of operations when a single
AD[GATE-IN-2011] external interrupt (Ext INT 1) is received
(80) The number of objects crossing a window will be
sequentially at variable speed is to be (A) Ext INT1 INTA Data Read
counted using an interrupt in the 8085 INT
microprocessor. The objects are sensed by
an optical source and a detector with (B) Ext INT1 INT INTA Data
associated signal conditioning circuit. The Read
Page 132 TARGATE EDUCATION GATE-( EC /EE)
Topic 09 - Microprocessor 8085 Programming & Basics
(C) Ext INT1 INT INTA addresses as 0008H, 0010H and 0018H. To
Address write execute a 32-byte long interrupt service
subroutine for Int1 starting at the address
(D) Ext INT1 INT Data Read ISS1, the location 0008H onwards should
Address write ideally contain
S4D [GATE–S4–EC–2016] (A) a CALL to ISS1
(84) In an 8085 microprocessor, the contents of (B) an unconditional JUMP to ISS1
the accumulator and the carry flag are A7 (in
hex) and 0, respectively. If the instruction (C) a conditional JUMP to ISS1
RLC is executed, then the contents of the (D) Only ISS1
accumulator (in hex) and the carry flag,
respectively, will be AC [GATE–S1–EC–2017]
(88) The clock frequency of an 8085
(A) 4E and 0 (B) 4E and 1
microprocessor is 5 MHz. If the time
(C) 4F and 0 (D) 4F and 1 required to execute an instruction is 1.4 s ,
S3AA [GATE–S3–EC–2016] then the number of T-states needed for
(85) An 8 Kbyte ROM with an active low Chip executing the instruction is
Select input (CS) is to be used in an 8085 (A) 1 (B) 6
microprocessor based system. The ROM (C) 7 (D) 8
should occupy the address range 1000H to
2FFFH. The address lines are designated as AB [GATE–S1–EC–2017]
A15 to A0 , where A15 is the most significant (89) The following FIVE instructions were
address bit. executed on an 8085 microprocessor.
Which one of the following logic MVI A, 33 H
expressions will generate the correct (CS)
MVI B, 78 H
signal for this ROM ?
ADD B
(A) A15 A14 ( A13 A12 A13 A12 )
CMA
(B) A15 A14 ( A13 A12 )
ANI 32 H
(C) A15 A14 ( A13 A12 A13 A12 )
The accumulator value immediately after the
(D) A15 A15 A13 A12 execution of the fifth instruction is
S1AC [GATE–S1–EC–2016] (A) 00H (B) 10H
(86) In an 8085 system, a PUSH operation (C) 11H (D) 32H
requires more clock cycles than a POP
operation. Which one of the following A279-282 [GATE – IN – 2018]
options is the correct reason for this? (90) A portion of an assembly language program
written for an 8-bit microprocessor is given
(A) For POP, the data transceivers remain below along with explanations. The code is
in the same direction as for instruction intended to introduce a software time delay.
fetch (memory to processor), whereas The processor is driven by a 5 MHz clock.
for PUSH their direction has to be The time delay (in s ) introduced by the
reversed.
program is_____.
(B) Memory write operations are slower
than memory read operations in an MVI B, 64H ; Move immediate the given
8085 based system. byte into register B. Takes 7
clock periods.
(C) The stack pointer needs to be pre-
decremented before writing registers in LOOP : DCR B ; Decrement register
a PUSH, whereas a POP operation uses B. Affects Flags. Takes 4
the address already in the stack pointer. clock periods.
(D) Order of registers has to be JNZ LOOP ; Jump to address with Label
interchanged for a PUSH operation, LOOP if zero flag is not set.
whereas POP uses their natural order. Takes 10 clock periods
when jump is performed and
AA OR B [GATE – IN – 2017] 7 clock periods when jump
(87) An 8-bit microcontroller with 16 address is not performed.
lines has 3 fixed interrupts i.e. Int 1, In2 and
Int3 with corresponding interrupt vector -------0000-------
www.targate.org Page 133
10
MEMORIES &
INTERFACING
A*[GATE-IN-1994] AC[GATE-IN-2001]
(1) In a 8-bit microprocessor with 16 address (5) In a microprocessor with 16 address and 12
lines, the range of signed integers that can be data lines, the maximum number of opcodes
processed is ……. is :
AA[GATE-IN-1999] (A) 26 (B) 28
(2) A computer has a memory space of 216 and (C) 212 (D) 216
word length of 24 bits. The memory chips
available have 10 address and 8 data lines. A*[GATE-IN-2002]
The number of chips required for the (6) A minimal microcomputer system is
computer memory space is constructed using INTEL 8085
microprocessor, an 8156 RAM and an 8355
(A) 192 (B) 256
ROM. The chip enable CE of 8355 are
(C) 512 (D) 1024 connected to address line A12 of 8085 the
address of port A of the 8156 chip is :
AC[GATE-IN-1999]
(3) The important feature of a microcontroller is (A) 21 H (B) 12 H
that it has on-chip (C) 11 H (D) 20 H
(A) math co-processor AD[GATE-EC -1988]
(B) program memory (7) For a microprocessor system using I/O-
(C) interface for I/O devices mapped the following statement(s) is NOT
(D) hardware multiplier true
(A) Memory space available is greater
AB[GATE-IN-2000]
(B) Not all data transfer instruction are
(4) Find the correct match among the following
available
pair in the context of an 8085
microprocessor (C) I/O and Memory address spaces are
distinct
A. DAA
(D) I/O address space is greater
B. LXI
A*[GATE-EC -2004]
C. RST (8) The 8255 Programmable Peripheral
D. JMP Interface is used as described below
1. Program control instruction (I) An A/D converter is interfaced to a
2. Data movement Instruction microprocessor through an 8255. The
conversion is initiated by a signal from
3. Interrupt instruction the 8255 on Port C. A signal on Port C
4. Arithmetic instruction causes data to be strobed into Port A
Codes : (II) Two computers exchange data using a
pair of 8255s. Port A works as a
(A) (A) - (i), (B) - (ii), (C) - (iii), (D) - (iv) bidirectional data port supported by
(B) (A) - (iv), (B) - (ii), (C) - (iii), (D) - (i) appropriate handshaking signals/
(C) (A) - (iv), (B) - (iii), (C) - (ii), (D) - (i) The appropriate modes of operation of the
(D) (A) - (ii), (B) - (iv), (C) - (iii), (D) - (i) 8255 for (I) and (II) would be
Page 134 TARGATE EDUCATION GATE-( EC /EE)
Topic 10 - Memories & Interfacing
(A) Mode 0 for (I) and Mode 1 for (II) AB[GATE-IN-2003]
(12) A ROM is interfaced to an 8085 CPU as
(B) Mode 1 for (I) and Mode 0 for (II) indicated in figure. The address range
(C) Mode 2 for (I) and Mode 0 for (II) occupied by the ROM is
(D) Mode 2 for (I) and Mode 1 for (II)
AD[GATE-EC -2014]
(9) For the 8085 microprocessor, the interfacing
circuit to input 8-bit digital data DI0 DI7
from an external device is shown in the
figure. The instruction for correct data
transfer is (A) 0000 - 0FFF
(B) 0000 - 1FFF
(C) 0000 - 2FFF
(D) 8000 - 9FFF
AC[GATE-IN-2005]
(13) An 8-bit microcontroller has an external
RAM is the memory map from 8000H to
9FFFH. The number of bytes this RAM can
store is
(A) 8193 (B) 8191
(C) 8192 (D) 8000
AB[GATE-IN-2008]
(A) MVI A, F8H (14) A 2K 8 bit RAM is interfaced to an 8-bit
(B) IN F8H microprocessor. If the address of the
memory location in the RAM is 0800H, the
(C) OUT F8H
address of the last memory location will be
(D) LDA F8F8H (A) 1000 H (B) 0FFFH
AA[GATE-EE-2002] (C) 4800H (D) 47FFH
(10) The logic circuit used to generate the active AB[GATE-IN-2010]
low chip select (CS) by an 8085 (15) An 8-bit DAC is interfaced with a
microprocessor to address a peripheral is microprocessor having 16 address lines
shown in figure. The peripheral will respond
( A 0 …. A15 ) as shown in the adjoining
to addresses in the figure.
figure. A possible valid address for this
DAC is :
(A) E000-EFFF
(B) 000E-FFFE
(C) 1000-FFFF
(A) 3000H (B) 4FFFH
(D) 0001-FFF1
(C) AFFFH (D) C000H
A*F800 to FFFFH[GATE-EE-1997]
(11) The range of addresses for which the AC[GATE-IN-2011]
memory chip shown in figure, will be (16) An 8K 8 bit RAM is interfaced to an 8085
selected is to microprocessor. In a fully decoded scheme if
the address of the last memory location of
this RAM is 4FFFH, the address of the first
memory location of the RAM will be
(A) 1000 H (B) 2000 H
(C) 3000 H (D) 4000 H
www.targate.org Page 135
DIGITAL ELECTRONICS
AC[GATE-EC -1988] (C) 50 H to AF H
(17) A 8-bit microprocessor has 16-bit address (D) 70 H to 73 H
bus A 0 A15 . The processor has a 1 kB
Byte memory chip as shown. The address AC[GATE-EC -2007]
range for the chip is (21) An 8255 chip is interfaced to an 8085
microprocessor system as an I/O mapped I/O
as shown in the figure. The address lines
A 0 and A1 of the 8085 are used by the 8255
chip to decode internally its three ports and
the Control register. The address lines
A 3 to A 7 as well as the IO / M signal are
used for address decoding. The range of
address for which the 8255 chip would get
(A) F00FH TO F40EH selected is
(B) F100 TO F4FFH
(C) F000H TO F3FFH
(D) F700H TO FAFFH
AB[GATE-EC -1988] (A) F8H - FBH
(18) A microprocessor with a 16-bit address bus
is used in a linear memory selection (B) F8H - FCH
configuration(i.e. Address bus lines are (C) F8H – FFH
directly used as chip selects of memory (D) F0H – F7H
chips) with 4 memory chips. The maximum
addressable memory space is A7 [GATE-EC-2015]
(22) A 16 kB (=16,384 bit) memory array is
(A) 64 k (B) 16 k
designed as a square with an aspect ratio of
(C) 8 k (D) 4 k one (number of rows is equal to the number
of columns). The minimum number of
AA,D[GATE-EC -1992]
address lines needed for the row decoder is
(19) In an 8085 microprocessor system with
_________ .
memory mapped I/O,
AD [GATE-EC-2013]
(A) I/O devices have 16-bit address
(23) There are four chips each of 1024 bytes
(B) I/O devices are accused using IN and connected to a 16 big address bus as shown
OUT instructions. in the figure below. RAMs 1, 2, 3 and 4
respectively are mapped to address
(C) there can be a maximum of 256 input
devices and 256 output devices
(D) arithmetic and logic operations can be
directly performed with the I/O data.
AA[GATE-EC -1997]
(20) The decoding circuit shown in Fig. has been
used to generate the active low chip select
signal for a microprocessor peripheral.(The
address lines are designated as A 0 to A 7 for
I – O addresses)
The peripheral will correspond to IO address
in the range
(A) 0C00H-0FFFH, 1C00H-1FFFH,
2C00H-2FFFH, 3C00H-3FFFH
(B) 1800H-1FFFH, 2800H-2FFFH, 3800H-
(A) 60 H to 63 H 3FFFH, 4800H-4FFFH
(B) A4 H to A7 H
Page 136 TARGATE EDUCATION GATE-( EC /EE)
Topic 10 - Memories & Interfacing
(C) 0500H-08FFH, 1500H-18FFH, 3500H- output of a 3 to 8 decoder with active low
38FFH, 5500H-58FFH outputs. S0, S1 , and S2 are the input lines to
the decoder, with S2 as the MSB. The
(D) 0800H-0BFFH, 1800H-1BFFH,
2800H-2BFFH, 3800H-3BFFH decoder has one active low EN1 and one
active high EN 2 enable lines as shown
AB[GATE-EC -2010] below. The address range(s) that gets
(24) In the circuit shown, the device connected to mapped onto this memory module is (are)
Y5 can have address in the range
(A) 3000H to 33FFH and E000H to E3FFH
(B) 1400H to 17FFH
(C) 5300H to 53FFH and A300H to A3FFH
(D) 5800H to 5BFFH and D800 H to DBFFH
(A) 2000 – 20 FF A512 [GATE-IN-2019]
(27) In a microprocessor with a 16 bit address
(B) 2D00 – 2DFF
bus, the most significant address lines A15
(C) 2E00 – 2EFF to A12 are used to select a 4096 word
(D) FD00 – FDFF memory unit, while lines A0 to A11 are used
to address a particular word in the memory
AB[GATE-EE-2014] unit. If the 3 least significant lines of the
(25) An output device is interfaced with 8-bit address bus A0 to A2 are short-circuited to
microprocessor 8085 A. The interfacing ground, the addressable number of words in
circuit is shown in figure. the memory unit is ______ .
-------0000-------
The interfacing circuit makes use of 3 Line
to 8 Line decoder having 3 enable lines
E1 , E 2 , E3 . The address of the device is
(A) 50H (B) 5000H
(C) A0H (D) A000H
S4AD [GATE–IN–2016]
(26) A 1 Kbyte memory module has to be
interfaced with an 8-bit microprocessor that
has 16 address lines. The address lines A0 to
A9 of the processor are connected to the
corresponding address lines of the memory
module. The active low chip select CS of
the memory module is connected to the y5
www.targate.org Page 137
DIGITAL ELECTRONICS
Answers :
01 - NUMBER SYSTEM
1.1 (R)’S AND (R-1)’S COMPLIMENT
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
B C A D B A C D D C D A A D C C
17. 18. 19. 20. 21. 22. 23. 24.
A C B C C B B C
1.2 Miscellaneous
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
D D A D * C C B A D D B D B D B
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
B A B C A B A B B B C D D B C A
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
D A B B C B D C D D D A C C B C
49. 50. 51.
B D B
5. 3.9-4.1
02 - BOOLEAN ALGEBRA
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
D D B * D A B D B D D B C A A D
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
D B A A A A D A A A B A A C B D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
C D D C C D B C C C B A C C A D
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
D C C C B A C B D D A D B B A A
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
C D C D D C A D D B C A A,B A A C
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96.
B C A C C D C B D B B B A D C B
97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112.
A D B A A D D D C A C A B A D B
113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127.
A B D D A B B A B D C B B B 256
4. TRUE
Page 138 TARGATE EDUCATION GATE-( EC /EE)
ANSWERS
03 - LOGIC GATES
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
B,D * A B A A C A C A A D C * B A
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
D B C B B A A D D D A A A B A D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
B B A C D A D C A A C C B A A D
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
B B A B B D D B D C D B,C C B D B
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
B,D B 100 A B B D D B C B A B A 40 D
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96.
C C D C A D C C B D A D D A D D
97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112.
D B A A D C A C C A D C B C C C
113. 114. 115. 116.
8 D A A
2. A-ii,B-iv,C-iii,D-i
14. AC AB BA
70. 100nsec
84. 40
04 – COMBINATIONAL DIGITAL CIRCUITS
4.1 – Multiplexer
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
D D C A C B B C A A D B C A C B
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
C C C C A * A C A A A B B D B A
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
A B C B C D B B C D D C A * D A
49. 50 51
B B C
46. 6.0
4.2 – Adder
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
B C D B C A B C A C C A B C D B
17. 18. 19. 20. 21. 22. 23. 24. 25.
C B B A C C D 50 4
www.targate.org Page 139
DIGITAL ELECTRONICS
4.3 – Decoder
1. 2. 3. 4. 5. 6. 7. 8.
D B B A D C A MTA
4.4 – Miscellaneous
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
C A C C * C A A A A A D D A B B
17. 18. 19. 20. 21.
B D C A B
05 – SEQUENTIAL DIGITAL CIRCUITS
5.1 – Counter
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
D * A C D D * * C A D 6 B C A C
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
B,D D B C A C D C C A C C A A D D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
A B A B A C B A A C D C C B B D
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
C B C A A D A D C C D D B B B A
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
B D A B A A,B A D C,D C C C A B B A
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96.
C B C A B B D D A C C D A B C D
97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111.
C A C C * A D B C D B 10 C 4 D
2. 62 - 63
7. 194.9to195.1
8. 6
5.2 – Miscellaneous
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
A D B B B B D C A D D C B B A A
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
D D A B B A C A D B C A B C C D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
D A B B C D A,B A B C B D D D B C
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
A B A C B C B B A C * D C D A D
Page 140 TARGATE EDUCATION GATE-( EC /EE)
ANSWERS
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
B B A A B B A A C B C D 0.5 D B C
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96.
C C 0,1 D * B * C C C B A B C * C
97. 98. 99. 100. 101. 102. 103. 104. 105. 106.
B 6 4 10 B * * 5 D A
48. TRUE
59. Faster
92. 0.5
95. 1.45-1.55
102. 29.9-30.1
103. 0.82-0.86
06 – SEMICONDUCTOR MEMORIES
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
B D C B C * C B C C C C,D A A D D
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
B C B A B A D A D D C C B D A,D C
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43.
D C B C A C B D B A B
6. None
07 – LOGIC GATE FAMILIES
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
A B D B B A D D C A D * * C C C
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
A A * A A * D B * C B B B D D D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
D
D A A B C C C D B A B B B A A
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
C B C C A B A C D A A A C A * D
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
B C C D A C C B B B B B B B B D
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96.
A B A B A D B A A D A C C A * A
97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112.
B B B A A A C C D B D A MTA D A A
113.
19. A-Q, B-R, C-S
22. 0.62-0.66
www.targate.org Page 141
DIGITAL ELECTRONICS
63. A BC
95. A : 74LS B: CMOS
08 – A/D & D/A CONVERTERS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
C C B C B A A A B D B C B B A B
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
B C B A B C C C D A A C B D D A
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
A A B A B A B B C D B B C B C D
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
C A C D B C A B C C * B B C B B
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
B C B C C D D * C B A A A A D B
81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95.
B D C D A B A C C B A A C D 64
59. A-4,B-3,C-2
72. 0.097
09 – MICROPROCESSOR 8085 PROGRAMMING & BASICS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
C C A D B B * C C B C D * C D C
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.
D A B D * C D B B B C A A C A D
33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48.
C B C B A D D A A B C D C C C C
49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.
D D C C * # C B C C A B B * C D
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80.
C D A B D A A C D A A A A D B D
81. 82. 83. 84. 85. 86. 87. 88. 89. 90.
B C B D A C * C B *
13. a-T, b-S, c-P
53. FALSE
87. A or B
90. 279-282
10 – MEMORIES & INTERFACING
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.
? A C B C ? D ? D A * B C B B C
17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27.
C B A,D A C 7 D B B D *
Page 142 TARGATE EDUCATION GATE-( EC /EE)
ANSWERS
11. F800 to FFFFH
27. 512
*** END OF THE BOOKLET ***
www.targate.org Page 143
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