Tutorial 8
CSE 112 Computer Organization
Q1. Qualitatively comparing performance
a) Two processors A and B are working on the same ISA. Frequency of processor A is
higher than frequency of processor B. For a given program, does it imply that processor
A always executes more instructions per second than processor B?
b) Two processors A and B are working on the same ISA. For a given program, if A
executes x Instructions per second, and B executes y instructions per second. If x > y,
does this imply processor A is faster than processor B?
Q2.
Your job is to evaluate the potential performance of two processors, each implementing a
different ISA. The evaluation is based on its performance on a particular benchmark. On the
processor implementing ISA A, the best compiled code for this benchmark performs at the rate
of 10 Instructions per Cycle. That processor has a 500 MHz clock. On the processor
implementing ISA B, the best compiled code for this benchmark performs at the rate of 2
Instructions Per Cycle. That processor has a 600 MHz clock.
a) What is the performance in Millions of Instructions per Second (MIPS) of the processor
implementing ISA A?
b) What is the performance in MIPS of the processor implementing ISA B?
c) Which one is the higher performance processor: A or B or Don’t Know. Briefly explain
your answer.
d) Suppose that the number of instructions of the benchmark compiled on ISA A is 1000.
Suppose that the number of instructions of the benchmark compiled on ISA B is 250.
Then, which is the higher-performing processor?
ISA conventions for Q3
All instructions follow the following conventions:
mnemonic destination source1 source2
mnemonic destination source
Q3. Pipeline Diagram (5 stages: Fetch, Decode, Execute, Memory, Writeback)
Draw the pipeline diagram for the following assembly programs. Assume that you have different
instructions and data memories.
a. add r1 r2 r3
add r4 r5 r6
add r7 r2 r3
add r8 r2 r5
b. mov r1, r3
add r3, r2, r4
add r5, r2, r4
mov r7, r8
Q4. Values Mismatch due to Hazard ()
Determine the value of register r3 and r5 for the following program, considering two execution
cases - one without pipeline and another with 5 stage pipeline . Assume the prgram with the 5
stage pipeline gets executed as shown in Table 1. Assume the initial register values to be equal
to the number (that is r1 = 1, r2 = 2, r3 = 3 and so on). .
add r1, r2, r3
add r3, r4, r1
add r5, r7, r3
Table 1
Instruction 1 2 3 4 5 6 7
Add r1, r2, r3 F D X M W
add r3, r4, r1 F D X M W
add r5, r7, r3 F D X M W
Do the values match? If no, what can be the possible reasons for mismatch ?
