Module -1 ML] =) ti cor QI | a | Demonsirats the postive and negative logic using AND gate + The binary signal at the inputs and outputs of any gate has tone of two values, except during transition. One signal valve represents logic 1 and the other logic 0. Choosing the high-level H to represent logic 1 defines a positive logic system. Choosing the low-level L to represent logic I defines a ive logic system. v The conversion from positive logic to negative logic and vice versa is essentially an operation that changes 1's to 0's and 0's to 1'sin both the inputs and the output of agate. Since this operation prodices the dual ct a function, the change of ll terminal from one polarity t the ‘other results in taking the dua ofthe function. The upshot i that all AND operations ae converted to OR operations (or raphic symbols) and vice versa —D | Find the POS expression for Flabed) = 112,358,10,13,14) + &1,67,11) 13] Cor and realize it using NOR gates. F(a,beed) = 112,3,5,8,10,13,14) + 4(1,6,7,11) Blue: (A + 0) Green: (A+ C) Orange : (C'+ 0) Brown: (8'+C +0) Purple: (A’ + B + D) Fs (A+) (A+C) (C+) (B+ C+D) (A'+ B+ D) (A45)(a4z) (Are+9)(A 4D) (A4Z) (c+ 8) (Bre rd) (A849) eed 5 (a5) +04 42) 4+C64D) 4+(B4c40) +(A 4640) AD Fae tepr Bent ABD 2 Rloted +7 (o+Bp) + AbdtGB) =azev cwo wae© | Simplify the Boolean function, Fw xyz) = S11 24,679.12 1] 13 | Cor map and Write the Ve am for realizing the minimize (FG2) 4 (@*9)4 peep eop tie(492) 4 (BEG) 1K 92) 4 (B%4) 4(B aH (4HD) 5 medwle code (F,0/4,9,2)7 fogut 19/4,9,2; ould f° assign $2 (4545 2) | ( (42450442) | (ow 426 (44959775 ow 5 or 444) | | (ow s>4 ~~ | tnd moduleOQ.2 | a | What is Binary logic? List out any 4 Laws of Logie S|] cor Binary logic is a system that uses only two digits, and 0, to represent the operation of binary logic gates.| Simplify the following Boolean function and find its SOP 10] 13 [Cor ) Fexy.2)= $041,856) + 23,7) i) Fwarcysz) = 5(5,6.7.12,14,15) + 4(13,9,11)F(x) 46204 (wr) eg)‘+ Ahardware description language (HDL) is a computer-based language that describes the hardware of digital systems ina textual form. — + Itresembles an ordinary computer programming language, such as C, but is specifically oriented to describing hardware structures and the behavior of logic circuits. + Itcan be used to represent logic diagrams, truth tables, Boolean expressions, and complex abstractions of the behavior of a digital system, + One way to view an HOL is to observe that it describes a relationship between signals that are the inputs to a circuit and the signals that are the outputs of the circuit. + For example, an HDL description of an AND gate describes how the logic value of the gate’s output. is determined by the logic values ofits inputs. + HDLs are used in several major steps in the design flow of an integrated circuit: design entry, {functional simulation or verification, logic synthesis, timing verification, and fault simulation. iD > ‘tout Inpat wre > and G1 (wt. A,B} Optional gate stance name . mode Single Cnc, 8.6.0.6) oe Rac G3 (6.0), Guiwh el‘Combinational Cireuits juential Circuits: Toe ouipaa theconbinatonal | Theutpu of he wequental spend only on the: cireuits lon both present perentpus ipasendeee “Th Tecdback pas not peseat | The ececk pts presen Tnibecomblrtonalcran | thesequental create Tn combinational creas, Tn the sequential crea tnorcementareset | neon Sementspan wat ole and rege, ro Thess ick sig heck gals aed pals equ “The combinational circuit i ere _simple to design. sequential circuit. Demullipleser Decoder, Full adder ‘encoder, Half adder, Magnitude comparator ‘Sequential Circuits: Registers, Flip Flops, Counters,Fi(A,6.c)2 Em 013-49) 14.00) 7 ABC S90N 9A BS 4 4100 4 AEE OWS +» ABe‘Qd | a [Define Encoder. Design « Four-inpat Priority Encoder 313 |co2ae S=A*B*Cin ee Cout=AB+BCin+ACin Tee | ccm module full_adder(input a, b, cin, output S, Cout); ofe{e]o | o assign S= ab cin; ofofi;31]o assign Cout = (a & b) | (b & cin) | (a & cin); of1fe, 1] o endmodule ofaf1] eo]. rfefe|1 0 rfefate [4 t[ife,e |. a rato: = : om es == _D=A*B* Bin Bout=A B+(A*B) Bin module full_subtractor(input a, b, Bin, output D, Bout); assign D=a%b*Bin; a & b) | (“a b) & Bin);Flip-Flop Characterii Tables (01 JK ip Fp 0) SAFIp Fp 2K Q(t 1) Operation SR QW) Opmaton Here are the characteristic equations + SR flip flop: net = 5+ an? © 9 Qu) Noctange 0 0 Qi) Noctange + Dfip lop: net = 0 He H rt r | H nae ‘+ IK flip flop: Qne1 = Q'n) + nk’ TL Gy Compleat Port Undies CLT (© OFip Fp (0) TFip op D a(t 1) Operation T__a(t+1) Operation o 0 Rewt o 20) Nochange ' set ' Bo Compleat‘Addressing modes are an aspect of the instruction set architecture in most central processing unit designs. ‘+ The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand of each instruction Immediate addressing mode Mov AL, 35H (move the Register mode MOV AK,CX (move the contents of CX register to AK register) Register Indirect mode MOV AX, [8X](move the contents of mesory location s addressed by the register BX to the register AX) Direct addressing/ Absolute addressing Mode 00 AL, [0321] //add the contents of offset address 0381 to AL Indirect addressing Mode MOV A, GAL (effective address is in the register) 12 35H into AL register)FA=LOC EA= [Ri] EA = {LOC} BA=(RI4X A= IR1+IR/) EAS (RJ +IR/L+X BA=IPCI+X EA= Ri Tocrement Ri Decrement Ri EA= (Ri)Memory Address Register (MAR) isa register in the CPU that stores the memory address from which data is fetched to the CPU registers. It can also store the address to which data i sent and stored via system bus. Program Counter (PC) isa register that manages the memory address of the instruction to be executed next Instruction Register (I) isa part of a CPU's control unit that holds the instruction that is being executed or decoded. Memory Data Register (MDR) is 2 register in a computer's CPU that stores data being transferred to and from immediate access storage. I's aso known as the Memory Buffer Register (MER) ‘Arithmetic Logie Unit (ALU) performs basic arithmetic and logical operations.CPU time = {nstuetion count CPL ‘Thins en ears tas the asc performance equation. ‘Clock rate "The prorat prc fore pcan propa it mach me ipo ote carta he inva abs of te parce N,S.ccK. To acer igh + The performance of a program depends on the algorithm, performance, he compact designer mest sek ways to reduce the vibe of T, which the language, the compiler, the architecture, and the actual Samara re Crh carte meee ed See Co aa called clock ck clack prod ck ecu voces tneeinctcone enactment icp Serer Sesser es | Foca to one cocky vaya te procer ‘We man canphasiae that N, 5, and R sre oot independent parameters, changing clock, which runs at a constant rate (exe any aes enor. Invodacing » enw foam: in te design of 8 proces WB. Cock period - The length of each clock cycle. lead to improved performance oly the vel ea ito reduce the va of TA wth o ¥ ee eer ee coiatencnter caren 'SPEC- System Performance Evaluation Corporation, is 8 non profit organization selects and publishes bench marks, 2 ee)TI fehl ng etep ll snenton In the program in Figure 2.10, the instruction Branch>0 LOOP (branch if greater than 0) isa conditional branch instruction that causes a branch to location LOOP if the result ofthe immediately preceding instruction, which is the decremented val in register Rl, is greater than zero. This means thatthe loop is repeat as long as there are entries i te list that are yet to be added to RO. At the ‘od of the nth passthrough the oop, the Decremeat instruction produces a value of zero, and, hence, branching does not occur. Instead, the Move instruction is fetched ‘and executed. It moves the final result from RO into memory location SUM.bb |The Registers RI and R2 has decimal values 1200 and 4600, Calculate the] 7 | 13 | CO3 effective address ofthe memory operand in each of the following instructions | ‘when they are exccuted in sequence, ) Load 20(R1), RS ii) Move #3000, RS Store RS, 30(R1,R2) iv) Add ~{R2), RS ¥) Subtract (RI)*, RS ‘Registers R1 and R2 of a computer contain the decimal values 1200 and 4600, we have to find effective address of ‘axiociated memory operand in each instruction: ‘oad 20(R1),RS : This means load 208R1 into RS. i= 1200, Ri + 20= 1220, 20 RS have 1220, CHective address of RS is 1220. ‘Move #13000,R5 : This means move value 3000 into RS. so effective address is part of the instruction whose value is 3000. Now RS = 3000 Store RS,30(R1,R2): This means 30+R1+R2 and store the result into RS ‘50 RS = 30+1200+4600 = $830, so now RS value is $830, the eHective address is 5830. ‘Add -{R2),RS : This means -1 from R2 value and store the result into RS.. So RS= 4600-1 = 4599, effective ‘address of RS is 4599. Its pre decrement addressing. Subtract (Ra}+,RS : This means effective address is contents of R150 EA Itis post increment addressing.=] =] | = Asingle bus structure is a computer architecture that uses a common bus to communicate between the processor, memory, and V0 devices. fone common bus is used to communicate between peripherals and microprocessors (Only one transfer ata time: The bus can only be used for one transfer at a time, so only two units can actively use the bus at any given time. {single bus structure is primarily ound in mini and microcomputers. (One significant advantage of using a one bus data path i its simplicity Single bus structure has disadvantages of limited speed since usually only two units can participate in a data transfer at any one time. This means that an arbitration system is required and that unis will be forced to walExplain VO operations involving keyboard and display device with a] 10 | L4 cos in buffer and echoes it b program that reads one line from keyboard, stores back to display. More LINER alae emery pit WAITK TeeB g0STATUS Tet SI Beak WAITK Wat fr tract ob enter More DATAINL Read dare WAITD Tobe #iSTATUS Tee SOUT Beweh=0 WARD Wa fr dapat cme edly Move RLDATAOUT. Seed dato pny Move RRO) ‘Stare arate and wae potter Compare #8D.Rt (Check Caringe Rear ean 0 WAITK 1a, et ater Qari Mowe #8ADATAOUT tere, ed Line Fe (Cal PROCESS Callentrtie to prom the the apt ine gem A A pogrn tt at on ne fom he yh, ein mcr be, diem bok eB daly “Toren he ta concept et conde ingle eampl of 10 operons oy nga kebourd anda dipy device in a compter ser The four eis show in Figure 43 ae ood nthe data ease operations. Regier STATUS conti tw ene fag, SIN and SOUT, which provide stats information forthe keyboard a the cipiay en, respectively. The two fags KIRQ an DIRQ his reper ae se in conection wih ire They snd the KEN and DEN bt ie fepiter CON ‘TROL, wil be dscused i Scce 42. Data fom te keyboard we ae aaah in he DATAIN reper, an data et 1 he ply ae stored i the DATAOU pet ‘The program in Figure 44 sa tha Figure 220. Ti pope eds 2 Iie of care oe your and stores tina emery ae sing a caine LUNE. Thesis aboute PROCESS wo proces teat ioe. Aseachcharcer ‘steak itis choad bck the spay Regier RD is eda oro the memory tude aea The cook of RO are spied ang he Asbicremeet ening made 1 tat saceste area retin ceemne Neny bon Bach rae ick ose ft the Carine Retr (CR) ara, which us the ASC coe OD he) It 2 Line Feed charac (ASC coe OA) scat mone the cane ae ine dow ce the Spey serine PROCESS ‘Sealed Oderwis. be progam bop tack 1 wai seater es fem Be tout,Dla chang iso method of iterrpt handing that ives connecting devices that can equest an iteupt ima seal manner The dees oe connected na Seal form, th he deve wih he Nghes pity placed ft flowed by ower pony Sees = | | i I ee eo fw 3) oman shown in Figure 4.84. The interrupt-request line INTR is common to all devices. The interrupt acknowledge line, INTA, is connected ina dasy-chain fashion, such thatthe INTA signal propagates serially through the devices. When several devices raise an interrupt request and the INTR line is activated, the processor responds by setting the INTA line to 1. This signal is received by device 1. Device 1 passes the signal on to device 2 only if it does not require any service. If device | has a pending request for inerrup,itblocks the INTA signal and proceeds to pat is identifying code on the data lines. Therefore, inthe daisy-chain arrangement, the device that is electrically closest to the processor has the highest priority. The second device along the chain has second highest priocity, and $0 on.=e Figen 42 Sequence ga ding an mas be ev a Figen 420 Fr 420 Asoc enqueue wig odyDisrated arbitration eas that al devices wating to we the bus vee espoiily in caying out the abiation process, without wing central aie. A ‘urge reba for drttedaturaon i lasted in Figure 2 Each dence ‘he brie stig «it detficacn member Wes coe ce mae devices rogue {he bes, they assert he Sat-Arbiran sgal and pace thei 4-6 ID numbers {oor ope collector ines, ARBD thowgh ARB. A wine i selected a rest of he ‘mtn among the gals tans over these Ines by all cotender. The 2 tomes that the code on the furs represent the request tha ta the highet 1D— & 4 sTe]s]s]~om, Moe Moe, Fagre 7A. Comacson ond anal signa regs MOE ‘i up of eat pio ron Man RI Te ston mee omnes ncn ne ax =) Ste opine nema tr he EC mp ney nt DR fe nee m-pe0H am pocerTfch word ef iafomatin fom mema.the roceuor hast spect the des of ‘teemar lcance wie hs nlorraton sre an! eur Read operat, Ths ‘gpl whether the information tobe fect represen insution a a progr x operand specified by a inaction. The proceortasfr the required aes the MAR, woe ouput is coneced othe abet ies fe merory bs. A th sane tine, the procera ie the contol nes of he memory but o inet tha Read opratn needed When the requ data recived rom th memory he see need in reper MDR, fo whe hey canbe treed oor ee i the proces. ‘Te connections fer repiter MDR risa ie Figure 74. has four cout signa: MOR, sed MOR, cool the coanecton 1 the teal as, aed MDRa td MPR cool the common 1 the eel but. The cca Fig 73 ‘easly modied ws povie be atonal connections A tee apa akin cane ‘set wth he memory bus iain conned be dapat Tt pat ee ‘wiea MDRag = 1. A second sae gu, conte’ by MOR canbe wed comact the ouput of te ip opto the memory bs.The pipelined processor in Figure 8.2 completes the processing of one instruction in each clock cycle, which means thatthe rate of instruction processing is four times that of sequential operation. The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages. However, this increase would be achieved only if pipelined operation as depicted in Figure 8.22 coald be sustained ‘without interruption throughout program execution. Unfortunately, tis isnot the case Fora variety of reasons, one ofthe pipeline stages may not be able to complete its processing task for a given instruction in the time alloted. For example, tage Ein the four-stage pipeline of Figure 8.2b is responsible for arithmetic and logic operations, and one clock cycle is assigned for this task. Although this may be suficient for ‘most operations, some operations, such as divide, may require more time to complete. Figure 8.3 shows an example in which the operation specified in instruction I; requires three cycles to complete, from cycle 4 through cycle 6. Thus, in cycles 5 and 6, the Write stage mast be told to do nothing, because it has no data to work with. Meanwhile, the information in buffer B2 mast remain intact until the Execute stage has completed its operation. This means that stage 2 and, in turn, stage 1 are blocked from accepting ‘new instructions because the information in B1 cannot be overwritten. Thus, steps D, and Fs must be postponed as shown.