Synchronous Counter Design

Several methods are available that follow arbitrary sequence.

Here we will learn one common method using JK flip-Flops.
In synchronous counters all the FF’s are clocked at the same
time.

Example (1)

Design a JK synchronous counter that has the

following sequence: 000,001,010,011,100 and
repeat. The undesired states 101,110 and 111 must
always go to 000 on the next clock pulse.
Design Procedure
Given a Counter sequence,
C B A
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
0 0 0
0 0 1
etc.
J-K Excitation Table

TRANSITION PRESENT NEXT

AT OUTPUT STATE STATE J K
Q(N) Q(N+1)
0 0 0 0 0 X
0 1 0 1 1 X
1 0 1 0 X 1
1 1 1 1 X 0
0 0 TRANSITION; FF’s Present status is 0 and it should remain in 0
when a clock pulse is applied. That can be either J=K=0 status or J=0,K=1.
That mean J=0 and K=0 or 1
That’s J=0 and K=X(don’t care)

0 1 TRANSITION: The present state is 0 and it has to change to 1.

This can happen either J=1 and K=0 or J=K=1.
That mean always J=1 and K=0 or1
J=1 and K=X( don’t care)

1 0 TRANSITION; The present state is 1 and it has to change to 0.

This can happen either J=0 and K=1 or J=K=1.
That mean always K=1 and J=0 or1
K=1 and J=X( don’t care)

1 1 TRANSITION; The present state is 1 and it has to change to 1.

This can happen either J=K=0 or J=1 and K=0.
That mean always K=0 and J can be either level
K=0 and J=X( don’t care) 6
STEP -1
Draw the state transition diagram showing all the possible states,
including those that are not part of the desired counting sequence
STEP -2
Use the state transition diagram to set up a table that lists all
PRESENT states and their NEXT states
Present state Next state
C B A C B A
1 0 0 0 0 0 1
2 0 0 1 0 1 0
3 0 1 0 0 1 1
4 0 1 1 1 0 0
5 1 0 0 0 0 0
6 1 0 1 0 0 0
7 1 1 0 0 0 0
8 1 1 1 0 0 0
STEP -3
Add a column to this table for each J and K input. For each PRESENT state,
indicate the level required at each J and K input in order to produce the transition
to the NEXT state.

Present state Next state

C B A C B A jC kC jB kB jA kA
1 0 0 0 0 0 1 0 X 0 X 1 X
2 0 0 1 0 1 0 0 X 1 X X 1
3 0 1 0 0 1 1 0 X X 0 1 X
4 0 1 1 1 0 0 1 X X 1 X 1
5 1 0 0 0 0 0 X 1 0 X 0 X
6 1 0 1 0 0 0 X 1 0 X X 1
7 1 1 0 0 0 0 X 1 X 1 0 X
8 1 1 1 0 0 0 X 1 X 1 X 1
STEP- 4
Design the logic expression to generate the level required at
each J and K, using K-maps.
A B
1 x x 1
Present state
C 0 x x 0
C B A jA kA
0 0 0 1 X jA= C
0 0 1 X 1 A B
0 1 0 1 X
0 1 1 X 1
1 0 0 0 X x 1 1 x
1 0 1 X 1
1 1 0 0 X C x 1 1 x
1 1 1 X 1
kA = 1 10
STEP- 4
…..cont.
A B
Present state 0 1 x x
C B A jB kB
0 0 0 0 X
C 0 0 x x
0 0 1 1 X
0 1 0 X 0 jB = AC
0 1 1 X 1 A B
1 0 0 0 X
1 0 1 0 X
1 1 0 X 1
x x 1 0
1 1 1 X 1
C x x 1 1
kB = A+C 11
STEP- 4
…..cont.
A B
Present state
C B A jC kC 0 0 1 0
0 0 0 0 X
0 0 1 0 X C 0 x x 0
0 1 0 0 X
0 1 1 1 X jC = AB
1 0 0 0 1 A B
1 0 1 X 1
1 1 0 0 1
1 1 1 X 1 x x x x
C 1 1 1 1
kC = 1 12
SETP -5
Finally to implement the final expressions.
 Sequential Circuit: Counter
◼ Example: 2-bit synchronous binary counter (using T flip-
flop or JK)

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 Sequential Circuit: Counter
Synchronous Counter (Parallel)
◼ Example: 3-bit synchronous binary counter (using T flip-
flop or JK) cont….
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◼ Example: 4-bit synchronous binary counter (using T flip-
flop or JK) cont….
Example: BCD Synchronous Counter ◼

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◼ Example: BCD Synchronous Counter

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 Synchronous Counter Design / Example (2)

? Design a JK synchronous counter that has the following

sequence:000,010,101,110 and repeat. The undesired
states 001,011,100 and 111 must always go to 000 on the next
clock pulse.
STEP -1 :State Transition Diagram

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 Synchronous Counter Design / Example (2) ….cont.

STEP- 2 : Table to list PRESENT and NEXT status

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 Synchronous Counter Design / Example (2) ….cont.

STEP- 3 : Table indicate the Level required at each J and K

inputs in order to produce the transition to the NEXT

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 Synchronous Counter Design / Example (2) ….cont.

STEP- 4 :Design the logic circuits to generate the levels

required at each J and K inputs

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 Synchronous Counter Design / Example (2) ….cont.

STEP- 5 :Simplify the SOP expression using K-maps

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Synchronous Counter Design / Example (2) ….cont.

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Synchronous Counter Design / Example (3)

? Design a JK synchronous counter that has the following

sequence:000,010,101,110 and repeat. For undesired
states their NEXT states can be DON’T CARES.
STEP -1 :State Transition Diagram

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 Synchronous Counter Design / Example (3) ….cont.

STEP- 2 : Table to list PRESENT and NEXT status

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 Synchronous Counter Design / Example (3) ….cont.

STEP- 3 : Table indicate the Level required at each J and K

inputs in order to produce the transition to the NEXT

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 Synchronous Counter Design / Example (3) ….cont.
STEP- 4 :Design the logic circuits to generate the levels
required at each J and K inputs

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Synchronous Counter Design / Example (3) ….cont.

STEP- 5 :Simplify the SOP expression using K-maps

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Synchronous Counter Design / Example (3) ….cont.

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Example -1:
To design a 3 bit counter (JK FF) with the
following count sequence 4,5,7,1,3. All
unwanted stages go to 4.
Example -2:
b) Design a synchronous random counter to
count in the following sequence: (0, 1, 3, 2, 6,
7, 5, 4, 0), using J-K flip-flop.

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